diff options
Diffstat (limited to 'include/dt-bindings')
421 files changed, 40793 insertions, 1525 deletions
diff --git a/include/dt-bindings/arm/coresight-cti-dt.h b/include/dt-bindings/arm/coresight-cti-dt.h new file mode 100644 index 000000000000..61e7bdf8ea6e --- /dev/null +++ b/include/dt-bindings/arm/coresight-cti-dt.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides constants for the defined trigger signal + * types on CoreSight CTI. + */ + +#ifndef _DT_BINDINGS_ARM_CORESIGHT_CTI_DT_H +#define _DT_BINDINGS_ARM_CORESIGHT_CTI_DT_H + +#define GEN_IO 0 +#define GEN_INTREQ 1 +#define GEN_INTACK 2 +#define GEN_HALTREQ 3 +#define GEN_RESTARTREQ 4 +#define PE_EDBGREQ 5 +#define PE_DBGRESTART 6 +#define PE_CTIIRQ 7 +#define PE_PMUIRQ 8 +#define PE_DBGTRIGGER 9 +#define ETM_EXTOUT 10 +#define ETM_EXTIN 11 +#define SNK_FULL 12 +#define SNK_ACQCOMP 13 +#define SNK_FLUSHCOMP 14 +#define SNK_FLUSHIN 15 +#define SNK_TRIGIN 16 +#define STM_ASYNCOUT 17 +#define STM_TOUT_SPTE 18 +#define STM_TOUT_SW 19 +#define STM_TOUT_HETE 20 +#define STM_HWEVENT 21 +#define ELA_TSTART 22 +#define ELA_TSTOP 23 +#define ELA_DBGREQ 24 +#define CTI_TRIG_MAX 25 + +#endif /*_DT_BINDINGS_ARM_CORESIGHT_CTI_DT_H */ diff --git a/include/dt-bindings/ata/ahci.h b/include/dt-bindings/ata/ahci.h new file mode 100644 index 000000000000..77997b35612c --- /dev/null +++ b/include/dt-bindings/ata/ahci.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause */ +/* + * This header provides constants for most AHCI bindings. + */ + +#ifndef _DT_BINDINGS_ATA_AHCI_H +#define _DT_BINDINGS_ATA_AHCI_H + +/* Host Bus Adapter generic platform capabilities */ +#define HBA_SSS (1 << 27) +#define HBA_SMPS (1 << 28) + +/* Host Bus Adapter port-specific platform capabilities */ +#define HBA_PORT_HPCP (1 << 18) +#define HBA_PORT_MPSP (1 << 19) +#define HBA_PORT_CPD (1 << 20) +#define HBA_PORT_ESP (1 << 21) +#define HBA_PORT_FBSCP (1 << 22) + +#endif diff --git a/include/dt-bindings/bus/moxtet.h b/include/dt-bindings/bus/moxtet.h index dc9345440ebe..10528de7b3ef 100644 --- a/include/dt-bindings/bus/moxtet.h +++ b/include/dt-bindings/bus/moxtet.h @@ -2,7 +2,7 @@ /* * Constant for device tree bindings for Turris Mox module configuration bus * - * Copyright (C) 2019 Marek Behun <marek.behun@nic.cz> + * Copyright (C) 2019 Marek Behún <kabel@kernel.org> */ #ifndef _DT_BINDINGS_BUS_MOXTET_H diff --git a/include/dt-bindings/bus/ti-sysc.h b/include/dt-bindings/bus/ti-sysc.h index babd08a1d226..76b07826ed05 100644 --- a/include/dt-bindings/bus/ti-sysc.h +++ b/include/dt-bindings/bus/ti-sysc.h @@ -18,6 +18,10 @@ #define SYSC_DRA7_MCAN_ENAWAKEUP (1 << 4) +/* PRUSS sysc found on AM33xx/AM43xx/AM57xx */ +#define SYSC_PRUSS_SUB_MWAIT (1 << 5) +#define SYSC_PRUSS_STANDBY_INIT (1 << 4) + /* SYSCONFIG STANDBYMODE/MIDLEMODE/SIDLEMODE supported by hardware */ #define SYSC_IDLE_FORCE 0 #define SYSC_IDLE_NO 1 diff --git a/include/dt-bindings/clock/actions,s500-cmu.h b/include/dt-bindings/clock/actions,s500-cmu.h index 030981cd2d56..a237eb26accb 100644 --- a/include/dt-bindings/clock/actions,s500-cmu.h +++ b/include/dt-bindings/clock/actions,s500-cmu.h @@ -72,7 +72,14 @@ #define CLK_NAND 52 #define CLK_ECC 53 #define CLK_RMII_REF 54 +#define CLK_GPIO 55 -#define CLK_NR_CLKS (CLK_RMII_REF + 1) +/* additional clocks */ +#define CLK_APB 56 +#define CLK_DMAC 57 +#define CLK_NIC 58 +#define CLK_ETHERNET 59 + +#define CLK_NR_CLKS (CLK_ETHERNET + 1) #endif /* __DT_BINDINGS_CLOCK_S500_CMU_H */ diff --git a/include/dt-bindings/clock/agilex-clock.h b/include/dt-bindings/clock/agilex-clock.h new file mode 100644 index 000000000000..06feca07e08e --- /dev/null +++ b/include/dt-bindings/clock/agilex-clock.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019, Intel Corporation + */ + +#ifndef __AGILEX_CLOCK_H +#define __AGILEX_CLOCK_H + +/* fixed rate clocks */ +#define AGILEX_OSC1 0 +#define AGILEX_CB_INTOSC_HS_DIV2_CLK 1 +#define AGILEX_CB_INTOSC_LS_CLK 2 +#define AGILEX_L4_SYS_FREE_CLK 3 +#define AGILEX_F2S_FREE_CLK 4 + +/* PLL clocks */ +#define AGILEX_MAIN_PLL_CLK 5 +#define AGILEX_MAIN_PLL_C0_CLK 6 +#define AGILEX_MAIN_PLL_C1_CLK 7 +#define AGILEX_MAIN_PLL_C2_CLK 8 +#define AGILEX_MAIN_PLL_C3_CLK 9 +#define AGILEX_PERIPH_PLL_CLK 10 +#define AGILEX_PERIPH_PLL_C0_CLK 11 +#define AGILEX_PERIPH_PLL_C1_CLK 12 +#define AGILEX_PERIPH_PLL_C2_CLK 13 +#define AGILEX_PERIPH_PLL_C3_CLK 14 +#define AGILEX_MPU_FREE_CLK 15 +#define AGILEX_MPU_CCU_CLK 16 +#define AGILEX_BOOT_CLK 17 + +/* fixed factor clocks */ +#define AGILEX_L3_MAIN_FREE_CLK 18 +#define AGILEX_NOC_FREE_CLK 19 +#define AGILEX_S2F_USR0_CLK 20 +#define AGILEX_NOC_CLK 21 +#define AGILEX_EMAC_A_FREE_CLK 22 +#define AGILEX_EMAC_B_FREE_CLK 23 +#define AGILEX_EMAC_PTP_FREE_CLK 24 +#define AGILEX_GPIO_DB_FREE_CLK 25 +#define AGILEX_SDMMC_FREE_CLK 26 +#define AGILEX_S2F_USER0_FREE_CLK 27 +#define AGILEX_S2F_USER1_FREE_CLK 28 +#define AGILEX_PSI_REF_FREE_CLK 29 + +/* Gate clocks */ +#define AGILEX_MPU_CLK 30 +#define AGILEX_MPU_L2RAM_CLK 31 +#define AGILEX_MPU_PERIPH_CLK 32 +#define AGILEX_L4_MAIN_CLK 33 +#define AGILEX_L4_MP_CLK 34 +#define AGILEX_L4_SP_CLK 35 +#define AGILEX_CS_AT_CLK 36 +#define AGILEX_CS_TRACE_CLK 37 +#define AGILEX_CS_PDBG_CLK 38 +#define AGILEX_CS_TIMER_CLK 39 +#define AGILEX_S2F_USER0_CLK 40 +#define AGILEX_EMAC0_CLK 41 +#define AGILEX_EMAC1_CLK 43 +#define AGILEX_EMAC2_CLK 44 +#define AGILEX_EMAC_PTP_CLK 45 +#define AGILEX_GPIO_DB_CLK 46 +#define AGILEX_NAND_CLK 47 +#define AGILEX_PSI_REF_CLK 48 +#define AGILEX_S2F_USER1_CLK 49 +#define AGILEX_SDMMC_CLK 50 +#define AGILEX_SPI_M_CLK 51 +#define AGILEX_USB_CLK 52 +#define AGILEX_NAND_X_CLK 53 +#define AGILEX_NAND_ECC_CLK 54 +#define AGILEX_NUM_CLKS 55 + +#endif /* __AGILEX_CLOCK_H */ diff --git a/include/dt-bindings/clock/alphascale,asm9260.h b/include/dt-bindings/clock/alphascale,asm9260.h index d3871c63308b..f53f8b16883d 100644 --- a/include/dt-bindings/clock/alphascale,asm9260.h +++ b/include/dt-bindings/clock/alphascale,asm9260.h @@ -55,7 +55,7 @@ #define CLKID_AHB_I2S1 45 #define CLKID_AHB_MAC1 46 -/* devider */ +/* divider */ #define CLKID_SYS_CPU 47 #define CLKID_SYS_AHB 48 #define CLKID_SYS_I2S0M 49 diff --git a/include/dt-bindings/clock/am3.h b/include/dt-bindings/clock/am3.h index 894951541276..dfbad5c87933 100644 --- a/include/dt-bindings/clock/am3.h +++ b/include/dt-bindings/clock/am3.h @@ -8,99 +8,6 @@ #define AM3_CLKCTRL_OFFSET 0x0 #define AM3_CLKCTRL_INDEX(offset) ((offset) - AM3_CLKCTRL_OFFSET) -/* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */ - -/* l4_per clocks */ -#define AM3_L4_PER_CLKCTRL_OFFSET 0x14 -#define AM3_L4_PER_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_PER_CLKCTRL_OFFSET) -#define AM3_CPGMAC0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x14) -#define AM3_LCDC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x18) -#define AM3_USB_OTG_HS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x1c) -#define AM3_TPTC0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x24) -#define AM3_EMIF_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x28) -#define AM3_OCMCRAM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x2c) -#define AM3_GPMC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x30) -#define AM3_MCASP0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x34) -#define AM3_UART6_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x38) -#define AM3_MMC1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x3c) -#define AM3_ELM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x40) -#define AM3_I2C3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x44) -#define AM3_I2C2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x48) -#define AM3_SPI0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x4c) -#define AM3_SPI1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x50) -#define AM3_L4_LS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x60) -#define AM3_MCASP1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x68) -#define AM3_UART2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x6c) -#define AM3_UART3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x70) -#define AM3_UART4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x74) -#define AM3_UART5_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x78) -#define AM3_TIMER7_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x7c) -#define AM3_TIMER2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x80) -#define AM3_TIMER3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x84) -#define AM3_TIMER4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x88) -#define AM3_RNG_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x90) -#define AM3_AES_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x94) -#define AM3_SHAM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xa0) -#define AM3_GPIO2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xac) -#define AM3_GPIO3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xb0) -#define AM3_GPIO4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xb4) -#define AM3_TPCC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xbc) -#define AM3_D_CAN0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xc0) -#define AM3_D_CAN1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xc4) -#define AM3_EPWMSS1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xcc) -#define AM3_EPWMSS0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xd4) -#define AM3_EPWMSS2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xd8) -#define AM3_L3_INSTR_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xdc) -#define AM3_L3_MAIN_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xe0) -#define AM3_PRUSS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xe8) -#define AM3_TIMER5_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xec) -#define AM3_TIMER6_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf0) -#define AM3_MMC2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf4) -#define AM3_MMC3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf8) -#define AM3_TPTC1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xfc) -#define AM3_TPTC2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x100) -#define AM3_SPINLOCK_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x10c) -#define AM3_MAILBOX_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x110) -#define AM3_L4_HS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x120) -#define AM3_OCPWP_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x130) -#define AM3_CLKDIV32K_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x14c) - -/* l4_wkup clocks */ -#define AM3_L4_WKUP_CLKCTRL_OFFSET 0x4 -#define AM3_L4_WKUP_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_WKUP_CLKCTRL_OFFSET) -#define AM3_CONTROL_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x4) -#define AM3_GPIO1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x8) -#define AM3_L4_WKUP_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc) -#define AM3_DEBUGSS_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x14) -#define AM3_WKUP_M3_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb0) -#define AM3_UART1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb4) -#define AM3_I2C1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb8) -#define AM3_ADC_TSC_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xbc) -#define AM3_SMARTREFLEX0_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc0) -#define AM3_TIMER1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc4) -#define AM3_SMARTREFLEX1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc8) -#define AM3_WD_TIMER2_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xd4) - -/* mpu clocks */ -#define AM3_MPU_CLKCTRL_OFFSET 0x4 -#define AM3_MPU_CLKCTRL_INDEX(offset) ((offset) - AM3_MPU_CLKCTRL_OFFSET) -#define AM3_MPU_CLKCTRL AM3_MPU_CLKCTRL_INDEX(0x4) - -/* l4_rtc clocks */ -#define AM3_RTC_CLKCTRL AM3_CLKCTRL_INDEX(0x0) - -/* gfx_l3 clocks */ -#define AM3_GFX_L3_CLKCTRL_OFFSET 0x4 -#define AM3_GFX_L3_CLKCTRL_INDEX(offset) ((offset) - AM3_GFX_L3_CLKCTRL_OFFSET) -#define AM3_GFX_CLKCTRL AM3_GFX_L3_CLKCTRL_INDEX(0x4) - -/* l4_cefuse clocks */ -#define AM3_L4_CEFUSE_CLKCTRL_OFFSET 0x20 -#define AM3_L4_CEFUSE_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_CEFUSE_CLKCTRL_OFFSET) -#define AM3_CEFUSE_CLKCTRL AM3_L4_CEFUSE_CLKCTRL_INDEX(0x20) - -/* XXX: Compatibility part end */ - /* l4ls clocks */ #define AM3_L4LS_CLKCTRL_OFFSET 0x38 #define AM3_L4LS_CLKCTRL_INDEX(offset) ((offset) - AM3_L4LS_CLKCTRL_OFFSET) diff --git a/include/dt-bindings/clock/am4.h b/include/dt-bindings/clock/am4.h index d961e7cb3682..a65b082e9cff 100644 --- a/include/dt-bindings/clock/am4.h +++ b/include/dt-bindings/clock/am4.h @@ -8,104 +8,6 @@ #define AM4_CLKCTRL_OFFSET 0x20 #define AM4_CLKCTRL_INDEX(offset) ((offset) - AM4_CLKCTRL_OFFSET) -/* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */ - -/* l4_wkup clocks */ -#define AM4_ADC_TSC_CLKCTRL AM4_CLKCTRL_INDEX(0x120) -#define AM4_L4_WKUP_CLKCTRL AM4_CLKCTRL_INDEX(0x220) -#define AM4_WKUP_M3_CLKCTRL AM4_CLKCTRL_INDEX(0x228) -#define AM4_COUNTER_32K_CLKCTRL AM4_CLKCTRL_INDEX(0x230) -#define AM4_TIMER1_CLKCTRL AM4_CLKCTRL_INDEX(0x328) -#define AM4_WD_TIMER2_CLKCTRL AM4_CLKCTRL_INDEX(0x338) -#define AM4_I2C1_CLKCTRL AM4_CLKCTRL_INDEX(0x340) -#define AM4_UART1_CLKCTRL AM4_CLKCTRL_INDEX(0x348) -#define AM4_SMARTREFLEX0_CLKCTRL AM4_CLKCTRL_INDEX(0x350) -#define AM4_SMARTREFLEX1_CLKCTRL AM4_CLKCTRL_INDEX(0x358) -#define AM4_CONTROL_CLKCTRL AM4_CLKCTRL_INDEX(0x360) -#define AM4_GPIO1_CLKCTRL AM4_CLKCTRL_INDEX(0x368) - -/* mpu clocks */ -#define AM4_MPU_CLKCTRL AM4_CLKCTRL_INDEX(0x20) - -/* gfx_l3 clocks */ -#define AM4_GFX_CLKCTRL AM4_CLKCTRL_INDEX(0x20) - -/* l4_rtc clocks */ -#define AM4_RTC_CLKCTRL AM4_CLKCTRL_INDEX(0x20) - -/* l4_per clocks */ -#define AM4_L3_MAIN_CLKCTRL AM4_CLKCTRL_INDEX(0x20) -#define AM4_AES_CLKCTRL AM4_CLKCTRL_INDEX(0x28) -#define AM4_DES_CLKCTRL AM4_CLKCTRL_INDEX(0x30) -#define AM4_L3_INSTR_CLKCTRL AM4_CLKCTRL_INDEX(0x40) -#define AM4_OCMCRAM_CLKCTRL AM4_CLKCTRL_INDEX(0x50) -#define AM4_SHAM_CLKCTRL AM4_CLKCTRL_INDEX(0x58) -#define AM4_VPFE0_CLKCTRL AM4_CLKCTRL_INDEX(0x68) -#define AM4_VPFE1_CLKCTRL AM4_CLKCTRL_INDEX(0x70) -#define AM4_TPCC_CLKCTRL AM4_CLKCTRL_INDEX(0x78) -#define AM4_TPTC0_CLKCTRL AM4_CLKCTRL_INDEX(0x80) -#define AM4_TPTC1_CLKCTRL AM4_CLKCTRL_INDEX(0x88) -#define AM4_TPTC2_CLKCTRL AM4_CLKCTRL_INDEX(0x90) -#define AM4_L4_HS_CLKCTRL AM4_CLKCTRL_INDEX(0xa0) -#define AM4_GPMC_CLKCTRL AM4_CLKCTRL_INDEX(0x220) -#define AM4_MCASP0_CLKCTRL AM4_CLKCTRL_INDEX(0x238) -#define AM4_MCASP1_CLKCTRL AM4_CLKCTRL_INDEX(0x240) -#define AM4_MMC3_CLKCTRL AM4_CLKCTRL_INDEX(0x248) -#define AM4_QSPI_CLKCTRL AM4_CLKCTRL_INDEX(0x258) -#define AM4_USB_OTG_SS0_CLKCTRL AM4_CLKCTRL_INDEX(0x260) -#define AM4_USB_OTG_SS1_CLKCTRL AM4_CLKCTRL_INDEX(0x268) -#define AM4_PRUSS_CLKCTRL AM4_CLKCTRL_INDEX(0x320) -#define AM4_L4_LS_CLKCTRL AM4_CLKCTRL_INDEX(0x420) -#define AM4_D_CAN0_CLKCTRL AM4_CLKCTRL_INDEX(0x428) -#define AM4_D_CAN1_CLKCTRL AM4_CLKCTRL_INDEX(0x430) -#define AM4_EPWMSS0_CLKCTRL AM4_CLKCTRL_INDEX(0x438) -#define AM4_EPWMSS1_CLKCTRL AM4_CLKCTRL_INDEX(0x440) -#define AM4_EPWMSS2_CLKCTRL AM4_CLKCTRL_INDEX(0x448) -#define AM4_EPWMSS3_CLKCTRL AM4_CLKCTRL_INDEX(0x450) -#define AM4_EPWMSS4_CLKCTRL AM4_CLKCTRL_INDEX(0x458) -#define AM4_EPWMSS5_CLKCTRL AM4_CLKCTRL_INDEX(0x460) -#define AM4_ELM_CLKCTRL AM4_CLKCTRL_INDEX(0x468) -#define AM4_GPIO2_CLKCTRL AM4_CLKCTRL_INDEX(0x478) -#define AM4_GPIO3_CLKCTRL AM4_CLKCTRL_INDEX(0x480) -#define AM4_GPIO4_CLKCTRL AM4_CLKCTRL_INDEX(0x488) -#define AM4_GPIO5_CLKCTRL AM4_CLKCTRL_INDEX(0x490) -#define AM4_GPIO6_CLKCTRL AM4_CLKCTRL_INDEX(0x498) -#define AM4_HDQ1W_CLKCTRL AM4_CLKCTRL_INDEX(0x4a0) -#define AM4_I2C2_CLKCTRL AM4_CLKCTRL_INDEX(0x4a8) -#define AM4_I2C3_CLKCTRL AM4_CLKCTRL_INDEX(0x4b0) -#define AM4_MAILBOX_CLKCTRL AM4_CLKCTRL_INDEX(0x4b8) -#define AM4_MMC1_CLKCTRL AM4_CLKCTRL_INDEX(0x4c0) -#define AM4_MMC2_CLKCTRL AM4_CLKCTRL_INDEX(0x4c8) -#define AM4_RNG_CLKCTRL AM4_CLKCTRL_INDEX(0x4e0) -#define AM4_SPI0_CLKCTRL AM4_CLKCTRL_INDEX(0x500) -#define AM4_SPI1_CLKCTRL AM4_CLKCTRL_INDEX(0x508) -#define AM4_SPI2_CLKCTRL AM4_CLKCTRL_INDEX(0x510) -#define AM4_SPI3_CLKCTRL AM4_CLKCTRL_INDEX(0x518) -#define AM4_SPI4_CLKCTRL AM4_CLKCTRL_INDEX(0x520) -#define AM4_SPINLOCK_CLKCTRL AM4_CLKCTRL_INDEX(0x528) -#define AM4_TIMER2_CLKCTRL AM4_CLKCTRL_INDEX(0x530) -#define AM4_TIMER3_CLKCTRL AM4_CLKCTRL_INDEX(0x538) -#define AM4_TIMER4_CLKCTRL AM4_CLKCTRL_INDEX(0x540) -#define AM4_TIMER5_CLKCTRL AM4_CLKCTRL_INDEX(0x548) -#define AM4_TIMER6_CLKCTRL AM4_CLKCTRL_INDEX(0x550) -#define AM4_TIMER7_CLKCTRL AM4_CLKCTRL_INDEX(0x558) -#define AM4_TIMER8_CLKCTRL AM4_CLKCTRL_INDEX(0x560) -#define AM4_TIMER9_CLKCTRL AM4_CLKCTRL_INDEX(0x568) -#define AM4_TIMER10_CLKCTRL AM4_CLKCTRL_INDEX(0x570) -#define AM4_TIMER11_CLKCTRL AM4_CLKCTRL_INDEX(0x578) -#define AM4_UART2_CLKCTRL AM4_CLKCTRL_INDEX(0x580) -#define AM4_UART3_CLKCTRL AM4_CLKCTRL_INDEX(0x588) -#define AM4_UART4_CLKCTRL AM4_CLKCTRL_INDEX(0x590) -#define AM4_UART5_CLKCTRL AM4_CLKCTRL_INDEX(0x598) -#define AM4_UART6_CLKCTRL AM4_CLKCTRL_INDEX(0x5a0) -#define AM4_OCP2SCP0_CLKCTRL AM4_CLKCTRL_INDEX(0x5b8) -#define AM4_OCP2SCP1_CLKCTRL AM4_CLKCTRL_INDEX(0x5c0) -#define AM4_EMIF_CLKCTRL AM4_CLKCTRL_INDEX(0x720) -#define AM4_DSS_CORE_CLKCTRL AM4_CLKCTRL_INDEX(0xa20) -#define AM4_CPGMAC0_CLKCTRL AM4_CLKCTRL_INDEX(0xb20) - -/* XXX: Compatibility part end. */ - /* l3s_tsc clocks */ #define AM4_L3S_TSC_CLKCTRL_OFFSET 0x120 #define AM4_L3S_TSC_CLKCTRL_INDEX(offset) ((offset) - AM4_L3S_TSC_CLKCTRL_OFFSET) @@ -158,6 +60,7 @@ #define AM4_L3S_VPFE0_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x68) #define AM4_L3S_VPFE1_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x70) #define AM4_L3S_GPMC_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x220) +#define AM4_L3S_ADC1_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x230) #define AM4_L3S_MCASP0_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x238) #define AM4_L3S_MCASP1_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x240) #define AM4_L3S_MMC3_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x248) diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h index 9ff4f6e4558c..06d568382c77 100644 --- a/include/dt-bindings/clock/aspeed-clock.h +++ b/include/dt-bindings/clock/aspeed-clock.h @@ -52,5 +52,6 @@ #define ASPEED_RESET_I2C 7 #define ASPEED_RESET_AHB 8 #define ASPEED_RESET_CRT1 9 +#define ASPEED_RESET_HACE 10 #endif diff --git a/include/dt-bindings/clock/ast2600-clock.h b/include/dt-bindings/clock/ast2600-clock.h index 62b9520a00fd..d8b0db2f7a7d 100644 --- a/include/dt-bindings/clock/ast2600-clock.h +++ b/include/dt-bindings/clock/ast2600-clock.h @@ -111,6 +111,7 @@ #define ASPEED_RESET_PCIE_RC_O 19 #define ASPEED_RESET_PCIE_RC_OEN 18 #define ASPEED_RESET_PCI_DP 5 +#define ASPEED_RESET_HACE 4 #define ASPEED_RESET_AHB 1 #define ASPEED_RESET_SDRAM 0 diff --git a/include/dt-bindings/clock/at91.h b/include/dt-bindings/clock/at91.h index 38b5554153c8..3e3972a814c1 100644 --- a/include/dt-bindings/clock/at91.h +++ b/include/dt-bindings/clock/at91.h @@ -12,6 +12,7 @@ #define PMC_TYPE_SYSTEM 1 #define PMC_TYPE_PERIPHERAL 2 #define PMC_TYPE_GCK 3 +#define PMC_TYPE_PROGRAMMABLE 4 #define PMC_SLOW 0 #define PMC_MCK 1 @@ -20,6 +21,22 @@ #define PMC_MCK2 4 #define PMC_I2S0_MUX 5 #define PMC_I2S1_MUX 6 +#define PMC_PLLACK 7 +#define PMC_PLLBCK 8 +#define PMC_AUDIOPLLCK 9 +#define PMC_AUDIOPINCK 10 + +/* SAMA7G5 */ +#define PMC_CPUPLL (PMC_MAIN + 1) +#define PMC_SYSPLL (PMC_MAIN + 2) +#define PMC_DDRPLL (PMC_MAIN + 3) +#define PMC_IMGPLL (PMC_MAIN + 4) +#define PMC_BAUDPLL (PMC_MAIN + 5) +#define PMC_AUDIOPMCPLL (PMC_MAIN + 6) +#define PMC_AUDIOIOPLL (PMC_MAIN + 7) +#define PMC_ETHPLL (PMC_MAIN + 8) +#define PMC_CPU (PMC_MAIN + 9) +#define PMC_MCK1 (PMC_MAIN + 10) #ifndef AT91_PMC_MOSCS #define AT91_PMC_MOSCS 0 /* MOSCS Flag */ diff --git a/include/dt-bindings/clock/axg-clkc.h b/include/dt-bindings/clock/axg-clkc.h index fd1f938c38d1..93752ea107e3 100644 --- a/include/dt-bindings/clock/axg-clkc.h +++ b/include/dt-bindings/clock/axg-clkc.h @@ -70,7 +70,31 @@ #define CLKID_HIFI_PLL 69 #define CLKID_PCIE_CML_EN0 79 #define CLKID_PCIE_CML_EN1 80 -#define CLKID_MIPI_ENABLE 81 #define CLKID_GEN_CLK 84 +#define CLKID_VPU_0_SEL 92 +#define CLKID_VPU_0 93 +#define CLKID_VPU_1_SEL 95 +#define CLKID_VPU_1 96 +#define CLKID_VPU 97 +#define CLKID_VAPB_0_SEL 99 +#define CLKID_VAPB_0 100 +#define CLKID_VAPB_1_SEL 102 +#define CLKID_VAPB_1 103 +#define CLKID_VAPB_SEL 104 +#define CLKID_VAPB 105 +#define CLKID_VCLK 106 +#define CLKID_VCLK2 107 +#define CLKID_VCLK_DIV1 122 +#define CLKID_VCLK_DIV2 123 +#define CLKID_VCLK_DIV4 124 +#define CLKID_VCLK_DIV6 125 +#define CLKID_VCLK_DIV12 126 +#define CLKID_VCLK2_DIV1 127 +#define CLKID_VCLK2_DIV2 128 +#define CLKID_VCLK2_DIV4 129 +#define CLKID_VCLK2_DIV6 130 +#define CLKID_VCLK2_DIV12 131 +#define CLKID_CTS_ENCL 133 +#define CLKID_VDIN_MEAS 136 #endif /* __AXG_CLKC_H */ diff --git a/include/dt-bindings/clock/axis,artpec6-clkctrl.h b/include/dt-bindings/clock/axis,artpec6-clkctrl.h index b1f4971642e6..14e424a7c08c 100644 --- a/include/dt-bindings/clock/axis,artpec6-clkctrl.h +++ b/include/dt-bindings/clock/axis,artpec6-clkctrl.h @@ -2,7 +2,7 @@ /* * ARTPEC-6 clock controller indexes * - * Copyright 2016 Axis Comunications AB. + * Copyright 2016 Axis Communications AB. */ #ifndef DT_BINDINGS_CLK_ARTPEC6_CLKCTRL_H diff --git a/include/dt-bindings/clock/bcm21664.h b/include/dt-bindings/clock/bcm21664.h index 5a7f0e4750a8..7c7492742f3d 100644 --- a/include/dt-bindings/clock/bcm21664.h +++ b/include/dt-bindings/clock/bcm21664.h @@ -1,15 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 2013 Broadcom Corporation * Copyright 2013 Linaro Limited - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #ifndef _CLOCK_BCM21664_H diff --git a/include/dt-bindings/clock/bcm281xx.h b/include/dt-bindings/clock/bcm281xx.h index a763460cf1af..d74ca42112e7 100644 --- a/include/dt-bindings/clock/bcm281xx.h +++ b/include/dt-bindings/clock/bcm281xx.h @@ -1,15 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 2013 Broadcom Corporation * Copyright 2013 Linaro Limited - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #ifndef _CLOCK_BCM281XX_H diff --git a/include/dt-bindings/clock/bcm3368-clock.h b/include/dt-bindings/clock/bcm3368-clock.h new file mode 100644 index 000000000000..74a7382f77b8 --- /dev/null +++ b/include/dt-bindings/clock/bcm3368-clock.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __DT_BINDINGS_CLOCK_BCM3368_H +#define __DT_BINDINGS_CLOCK_BCM3368_H + +#define BCM3368_CLK_MAC 3 +#define BCM3368_CLK_TC 5 +#define BCM3368_CLK_US_TOP 6 +#define BCM3368_CLK_DS_TOP 7 +#define BCM3368_CLK_ACM 8 +#define BCM3368_CLK_SPI 9 +#define BCM3368_CLK_USBS 10 +#define BCM3368_CLK_BMU 11 +#define BCM3368_CLK_PCM 12 +#define BCM3368_CLK_NTP 13 +#define BCM3368_CLK_ACP_B 14 +#define BCM3368_CLK_ACP_A 15 +#define BCM3368_CLK_EMUSB 17 +#define BCM3368_CLK_ENET0 18 +#define BCM3368_CLK_ENET1 19 +#define BCM3368_CLK_USBSU 20 +#define BCM3368_CLK_EPHY 21 + +#endif /* __DT_BINDINGS_CLOCK_BCM3368_H */ diff --git a/include/dt-bindings/clock/bcm6318-clock.h b/include/dt-bindings/clock/bcm6318-clock.h new file mode 100644 index 000000000000..c4417f8983ab --- /dev/null +++ b/include/dt-bindings/clock/bcm6318-clock.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __DT_BINDINGS_CLOCK_BCM6318_H +#define __DT_BINDINGS_CLOCK_BCM6318_H + +#define BCM6318_CLK_ADSL_ASB 0 +#define BCM6318_CLK_USB_ASB 1 +#define BCM6318_CLK_MIPS_ASB 2 +#define BCM6318_CLK_PCIE_ASB 3 +#define BCM6318_CLK_PHYMIPS_ASB 4 +#define BCM6318_CLK_ROBOSW_ASB 5 +#define BCM6318_CLK_SAR_ASB 6 +#define BCM6318_CLK_SDR_ASB 7 +#define BCM6318_CLK_SWREG_ASB 8 +#define BCM6318_CLK_PERIPH_ASB 9 +#define BCM6318_CLK_CPUBUS160 10 +#define BCM6318_CLK_ADSL 11 +#define BCM6318_CLK_SAR125 12 +#define BCM6318_CLK_MIPS 13 +#define BCM6318_CLK_PCIE 14 +#define BCM6318_CLK_ROBOSW250 16 +#define BCM6318_CLK_ROBOSW025 17 +#define BCM6318_CLK_SDR 19 +#define BCM6318_CLK_USBD 20 +#define BCM6318_CLK_HSSPI 25 +#define BCM6318_CLK_PCIE25 27 +#define BCM6318_CLK_PHYMIPS 28 +#define BCM6318_CLK_AFE 29 +#define BCM6318_CLK_QPROC 30 + +#define BCM6318_UCLK_ADSL 0 +#define BCM6318_UCLK_ARB 1 +#define BCM6318_UCLK_MIPS 2 +#define BCM6318_UCLK_PCIE 3 +#define BCM6318_UCLK_PERIPH 4 +#define BCM6318_UCLK_PHYMIPS 5 +#define BCM6318_UCLK_ROBOSW 6 +#define BCM6318_UCLK_SAR 7 +#define BCM6318_UCLK_SDR 8 +#define BCM6318_UCLK_USB 9 + +#endif /* __DT_BINDINGS_CLOCK_BCM6318_H */ diff --git a/include/dt-bindings/clock/bcm63268-clock.h b/include/dt-bindings/clock/bcm63268-clock.h new file mode 100644 index 000000000000..da23e691d359 --- /dev/null +++ b/include/dt-bindings/clock/bcm63268-clock.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __DT_BINDINGS_CLOCK_BCM63268_H +#define __DT_BINDINGS_CLOCK_BCM63268_H + +#define BCM63268_CLK_DIS_GLESS 0 +#define BCM63268_CLK_VDSL_QPROC 1 +#define BCM63268_CLK_VDSL_AFE 2 +#define BCM63268_CLK_VDSL 3 +#define BCM63268_CLK_MIPS 4 +#define BCM63268_CLK_WLAN_OCP 5 +#define BCM63268_CLK_DECT 6 +#define BCM63268_CLK_FAP0 7 +#define BCM63268_CLK_FAP1 8 +#define BCM63268_CLK_SAR 9 +#define BCM63268_CLK_ROBOSW 10 +#define BCM63268_CLK_PCM 11 +#define BCM63268_CLK_USBD 12 +#define BCM63268_CLK_USBH 13 +#define BCM63268_CLK_IPSEC 14 +#define BCM63268_CLK_SPI 15 +#define BCM63268_CLK_HSSPI 16 +#define BCM63268_CLK_PCIE 17 +#define BCM63268_CLK_PHYMIPS 18 +#define BCM63268_CLK_GMAC 19 +#define BCM63268_CLK_NAND 20 +#define BCM63268_CLK_TBUS 27 +#define BCM63268_CLK_ROBOSW250 31 + +#endif /* __DT_BINDINGS_CLOCK_BCM63268_H */ diff --git a/include/dt-bindings/clock/bcm6328-clock.h b/include/dt-bindings/clock/bcm6328-clock.h new file mode 100644 index 000000000000..1f6a3103f3dc --- /dev/null +++ b/include/dt-bindings/clock/bcm6328-clock.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __DT_BINDINGS_CLOCK_BCM6328_H +#define __DT_BINDINGS_CLOCK_BCM6328_H + +#define BCM6328_CLK_PHYMIPS 0 +#define BCM6328_CLK_ADSL_QPROC 1 +#define BCM6328_CLK_ADSL_AFE 2 +#define BCM6328_CLK_ADSL 3 +#define BCM6328_CLK_MIPS 4 +#define BCM6328_CLK_SAR 5 +#define BCM6328_CLK_PCM 6 +#define BCM6328_CLK_USBD 7 +#define BCM6328_CLK_USBH 8 +#define BCM6328_CLK_HSSPI 9 +#define BCM6328_CLK_PCIE 10 +#define BCM6328_CLK_ROBOSW 11 + +#endif /* __DT_BINDINGS_CLOCK_BCM6328_H */ diff --git a/include/dt-bindings/clock/bcm6358-clock.h b/include/dt-bindings/clock/bcm6358-clock.h new file mode 100644 index 000000000000..980c9cac4765 --- /dev/null +++ b/include/dt-bindings/clock/bcm6358-clock.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __DT_BINDINGS_CLOCK_BCM6358_H +#define __DT_BINDINGS_CLOCK_BCM6358_H + +#define BCM6358_CLK_ENET 4 +#define BCM6358_CLK_ADSLPHY 5 +#define BCM6358_CLK_PCM 8 +#define BCM6358_CLK_SPI 9 +#define BCM6358_CLK_USBS 10 +#define BCM6358_CLK_SAR 11 +#define BCM6358_CLK_EMUSB 17 +#define BCM6358_CLK_ENET0 18 +#define BCM6358_CLK_ENET1 19 +#define BCM6358_CLK_USBSU 20 +#define BCM6358_CLK_EPHY 21 + +#endif /* __DT_BINDINGS_CLOCK_BCM6358_H */ diff --git a/include/dt-bindings/clock/bcm6362-clock.h b/include/dt-bindings/clock/bcm6362-clock.h new file mode 100644 index 000000000000..17655cd5bf25 --- /dev/null +++ b/include/dt-bindings/clock/bcm6362-clock.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __DT_BINDINGS_CLOCK_BCM6362_H +#define __DT_BINDINGS_CLOCK_BCM6362_H + +#define BCM6362_CLK_ADSL_QPROC 1 +#define BCM6362_CLK_ADSL_AFE 2 +#define BCM6362_CLK_ADSL 3 +#define BCM6362_CLK_MIPS 4 +#define BCM6362_CLK_WLAN_OCP 5 +#define BCM6362_CLK_SWPKT_USB 7 +#define BCM6362_CLK_SWPKT_SAR 8 +#define BCM6362_CLK_SAR 9 +#define BCM6362_CLK_ROBOSW 10 +#define BCM6362_CLK_PCM 11 +#define BCM6362_CLK_USBD 12 +#define BCM6362_CLK_USBH 13 +#define BCM6362_CLK_IPSEC 14 +#define BCM6362_CLK_SPI 15 +#define BCM6362_CLK_HSSPI 16 +#define BCM6362_CLK_PCIE 17 +#define BCM6362_CLK_FAP 18 +#define BCM6362_CLK_PHYMIPS 19 +#define BCM6362_CLK_NAND 20 + +#endif /* __DT_BINDINGS_CLOCK_BCM6362_H */ diff --git a/include/dt-bindings/clock/bcm6368-clock.h b/include/dt-bindings/clock/bcm6368-clock.h new file mode 100644 index 000000000000..f161d5333883 --- /dev/null +++ b/include/dt-bindings/clock/bcm6368-clock.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __DT_BINDINGS_CLOCK_BCM6368_H +#define __DT_BINDINGS_CLOCK_BCM6368_H + +#define BCM6368_CLK_VDSL_QPROC 2 +#define BCM6368_CLK_VDSL_AFE 3 +#define BCM6368_CLK_VDSL_BONDING 4 +#define BCM6368_CLK_VDSL 5 +#define BCM6368_CLK_PHYMIPS 6 +#define BCM6368_CLK_SWPKT_USB 7 +#define BCM6368_CLK_SWPKT_SAR 8 +#define BCM6368_CLK_SPI 9 +#define BCM6368_CLK_USBD 10 +#define BCM6368_CLK_SAR 11 +#define BCM6368_CLK_ROBOSW 12 +#define BCM6368_CLK_UTOPIA 13 +#define BCM6368_CLK_PCM 14 +#define BCM6368_CLK_USBH 15 +#define BCM6368_CLK_DIS_GLESS 16 +#define BCM6368_CLK_NAND 17 +#define BCM6368_CLK_IPSEC 18 + +#endif /* __DT_BINDINGS_CLOCK_BCM6368_H */ diff --git a/include/dt-bindings/clock/boston-clock.h b/include/dt-bindings/clock/boston-clock.h index a6f009821137..38140fa87b09 100644 --- a/include/dt-bindings/clock/boston-clock.h +++ b/include/dt-bindings/clock/boston-clock.h @@ -1,7 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2016 Imagination Technologies - * - * SPDX-License-Identifier: GPL-2.0 */ #ifndef __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__ diff --git a/include/dt-bindings/clock/bt1-ccu.h b/include/dt-bindings/clock/bt1-ccu.h new file mode 100644 index 000000000000..5f166d27a00a --- /dev/null +++ b/include/dt-bindings/clock/bt1-ccu.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC + * + * Baikal-T1 CCU clock indices + */ +#ifndef __DT_BINDINGS_CLOCK_BT1_CCU_H +#define __DT_BINDINGS_CLOCK_BT1_CCU_H + +#define CCU_CPU_PLL 0 +#define CCU_SATA_PLL 1 +#define CCU_DDR_PLL 2 +#define CCU_PCIE_PLL 3 +#define CCU_ETH_PLL 4 + +#define CCU_AXI_MAIN_CLK 0 +#define CCU_AXI_DDR_CLK 1 +#define CCU_AXI_SATA_CLK 2 +#define CCU_AXI_GMAC0_CLK 3 +#define CCU_AXI_GMAC1_CLK 4 +#define CCU_AXI_XGMAC_CLK 5 +#define CCU_AXI_PCIE_M_CLK 6 +#define CCU_AXI_PCIE_S_CLK 7 +#define CCU_AXI_USB_CLK 8 +#define CCU_AXI_HWA_CLK 9 +#define CCU_AXI_SRAM_CLK 10 + +#define CCU_SYS_SATA_REF_CLK 0 +#define CCU_SYS_APB_CLK 1 +#define CCU_SYS_GMAC0_TX_CLK 2 +#define CCU_SYS_GMAC0_PTP_CLK 3 +#define CCU_SYS_GMAC1_TX_CLK 4 +#define CCU_SYS_GMAC1_PTP_CLK 5 +#define CCU_SYS_XGMAC_REF_CLK 6 +#define CCU_SYS_XGMAC_PTP_CLK 7 +#define CCU_SYS_USB_CLK 8 +#define CCU_SYS_PVT_CLK 9 +#define CCU_SYS_HWA_CLK 10 +#define CCU_SYS_UART_CLK 11 +#define CCU_SYS_I2C1_CLK 12 +#define CCU_SYS_I2C2_CLK 13 +#define CCU_SYS_GPIO_CLK 14 +#define CCU_SYS_TIMER0_CLK 15 +#define CCU_SYS_TIMER1_CLK 16 +#define CCU_SYS_TIMER2_CLK 17 +#define CCU_SYS_WDT_CLK 18 + +#endif /* __DT_BINDINGS_CLOCK_BT1_CCU_H */ diff --git a/include/dt-bindings/clock/cirrus,cs2000-cp.h b/include/dt-bindings/clock/cirrus,cs2000-cp.h new file mode 100644 index 000000000000..fe3ac71750a8 --- /dev/null +++ b/include/dt-bindings/clock/cirrus,cs2000-cp.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2021 Daniel Mack + */ + +#ifndef __DT_BINDINGS_CS2000CP_CLK_H +#define __DT_BINDINGS_CS2000CP_CLK_H + +#define CS2000CP_AUX_OUTPUT_REF_CLK 0 +#define CS2000CP_AUX_OUTPUT_CLK_IN 1 +#define CS2000CP_AUX_OUTPUT_CLK_OUT 2 +#define CS2000CP_AUX_OUTPUT_PLL_LOCK 3 + +#endif /* __DT_BINDINGS_CS2000CP_CLK_H */ diff --git a/include/dt-bindings/clock/dm814.h b/include/dt-bindings/clock/dm814.h index f0f04e0a249e..33b8826d936b 100644 --- a/include/dt-bindings/clock/dm814.h +++ b/include/dt-bindings/clock/dm814.h @@ -34,4 +34,9 @@ #define DM814_MMC2_CLKCTRL DM814_CLKCTRL_INDEX(0x220) #define DM814_MMC3_CLKCTRL DM814_CLKCTRL_INDEX(0x224) +/* alwon_ethernet clocks */ +#define DM814_ETHERNET_CLKCTRL_OFFSET 0x1d4 +#define DM814_ETHERNET_CLKCTRL_INDEX(offset) ((offset) - DM814_ETHERNET_CLKCTRL_OFFSET) +#define DM814_ETHERNET_CPGMAC0_CLKCTRL DM814_ETHERNET_CLKCTRL_INDEX(0x1d4) + #endif diff --git a/include/dt-bindings/clock/dra7.h b/include/dt-bindings/clock/dra7.h index 8cec5a1e1806..8a903c78c5a5 100644 --- a/include/dt-bindings/clock/dra7.h +++ b/include/dt-bindings/clock/dra7.h @@ -8,177 +8,6 @@ #define DRA7_CLKCTRL_OFFSET 0x20 #define DRA7_CLKCTRL_INDEX(offset) ((offset) - DRA7_CLKCTRL_OFFSET) -/* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */ - -/* mpu clocks */ -#define DRA7_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) - -/* ipu clocks */ -#define _DRA7_IPU_CLKCTRL_OFFSET 0x40 -#define _DRA7_IPU_CLKCTRL_INDEX(offset) ((offset) - _DRA7_IPU_CLKCTRL_OFFSET) -#define DRA7_MCASP1_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x50) -#define DRA7_TIMER5_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x58) -#define DRA7_TIMER6_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x60) -#define DRA7_TIMER7_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x68) -#define DRA7_TIMER8_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x70) -#define DRA7_I2C5_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x78) -#define DRA7_UART6_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x80) - -/* rtc clocks */ -#define DRA7_RTC_CLKCTRL_OFFSET 0x40 -#define DRA7_RTC_CLKCTRL_INDEX(offset) ((offset) - DRA7_RTC_CLKCTRL_OFFSET) -#define DRA7_RTCSS_CLKCTRL DRA7_RTC_CLKCTRL_INDEX(0x44) - -/* vip clocks */ -#define DRA7_VIP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) -#define DRA7_VIP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) -#define DRA7_VIP3_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) - -/* vpe clocks */ -#define DRA7_VPE_CLKCTRL_OFFSET 0x60 -#define DRA7_VPE_CLKCTRL_INDEX(offset) ((offset) - DRA7_VPE_CLKCTRL_OFFSET) -#define DRA7_VPE_CLKCTRL DRA7_VPE_CLKCTRL_INDEX(0x64) - -/* coreaon clocks */ -#define DRA7_SMARTREFLEX_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) -#define DRA7_SMARTREFLEX_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x38) - -/* l3main1 clocks */ -#define DRA7_L3_MAIN_1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) -#define DRA7_GPMC_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) -#define DRA7_TPCC_CLKCTRL DRA7_CLKCTRL_INDEX(0x70) -#define DRA7_TPTC0_CLKCTRL DRA7_CLKCTRL_INDEX(0x78) -#define DRA7_TPTC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x80) -#define DRA7_VCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) -#define DRA7_VCP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x90) - -/* dma clocks */ -#define DRA7_DMA_SYSTEM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) - -/* emif clocks */ -#define DRA7_DMM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) - -/* atl clocks */ -#define DRA7_ATL_CLKCTRL_OFFSET 0x0 -#define DRA7_ATL_CLKCTRL_INDEX(offset) ((offset) - DRA7_ATL_CLKCTRL_OFFSET) -#define DRA7_ATL_CLKCTRL DRA7_ATL_CLKCTRL_INDEX(0x0) - -/* l4cfg clocks */ -#define DRA7_L4_CFG_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) -#define DRA7_SPINLOCK_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) -#define DRA7_MAILBOX1_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) -#define DRA7_MAILBOX2_CLKCTRL DRA7_CLKCTRL_INDEX(0x48) -#define DRA7_MAILBOX3_CLKCTRL DRA7_CLKCTRL_INDEX(0x50) -#define DRA7_MAILBOX4_CLKCTRL DRA7_CLKCTRL_INDEX(0x58) -#define DRA7_MAILBOX5_CLKCTRL DRA7_CLKCTRL_INDEX(0x60) -#define DRA7_MAILBOX6_CLKCTRL DRA7_CLKCTRL_INDEX(0x68) -#define DRA7_MAILBOX7_CLKCTRL DRA7_CLKCTRL_INDEX(0x70) -#define DRA7_MAILBOX8_CLKCTRL DRA7_CLKCTRL_INDEX(0x78) -#define DRA7_MAILBOX9_CLKCTRL DRA7_CLKCTRL_INDEX(0x80) -#define DRA7_MAILBOX10_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) -#define DRA7_MAILBOX11_CLKCTRL DRA7_CLKCTRL_INDEX(0x90) -#define DRA7_MAILBOX12_CLKCTRL DRA7_CLKCTRL_INDEX(0x98) -#define DRA7_MAILBOX13_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0) - -/* l3instr clocks */ -#define DRA7_L3_MAIN_2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) -#define DRA7_L3_INSTR_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) - -/* dss clocks */ -#define DRA7_DSS_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) -#define DRA7_BB2D_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) - -/* gpu clocks */ -#define DRA7_GPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) - -/* l3init clocks */ -#define DRA7_MMC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) -#define DRA7_MMC2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) -#define DRA7_USB_OTG_SS2_CLKCTRL DRA7_CLKCTRL_INDEX(0x40) -#define DRA7_USB_OTG_SS3_CLKCTRL DRA7_CLKCTRL_INDEX(0x48) -#define DRA7_USB_OTG_SS4_CLKCTRL DRA7_CLKCTRL_INDEX(0x50) -#define DRA7_SATA_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) -#define DRA7_PCIE1_CLKCTRL DRA7_CLKCTRL_INDEX(0xb0) -#define DRA7_PCIE2_CLKCTRL DRA7_CLKCTRL_INDEX(0xb8) -#define DRA7_GMAC_CLKCTRL DRA7_CLKCTRL_INDEX(0xd0) -#define DRA7_OCP2SCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0xe0) -#define DRA7_OCP2SCP3_CLKCTRL DRA7_CLKCTRL_INDEX(0xe8) -#define DRA7_USB_OTG_SS1_CLKCTRL DRA7_CLKCTRL_INDEX(0xf0) - -/* l4per clocks */ -#define _DRA7_L4PER_CLKCTRL_OFFSET 0x0 -#define _DRA7_L4PER_CLKCTRL_INDEX(offset) ((offset) - _DRA7_L4PER_CLKCTRL_OFFSET) -#define DRA7_L4_PER2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc) -#define DRA7_L4_PER3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x14) -#define DRA7_TIMER10_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x28) -#define DRA7_TIMER11_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x30) -#define DRA7_TIMER2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x38) -#define DRA7_TIMER3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x40) -#define DRA7_TIMER4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x48) -#define DRA7_TIMER9_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x50) -#define DRA7_ELM_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x58) -#define DRA7_GPIO2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x60) -#define DRA7_GPIO3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x68) -#define DRA7_GPIO4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x70) -#define DRA7_GPIO5_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x78) -#define DRA7_GPIO6_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x80) -#define DRA7_HDQ1W_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x88) -#define DRA7_EPWMSS1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x90) -#define DRA7_EPWMSS2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x98) -#define DRA7_I2C1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xa0) -#define DRA7_I2C2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xa8) -#define DRA7_I2C3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xb0) -#define DRA7_I2C4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xb8) -#define DRA7_L4_PER1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc0) -#define DRA7_EPWMSS0_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc4) -#define DRA7_TIMER13_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc8) -#define DRA7_TIMER14_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xd0) -#define DRA7_TIMER15_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xd8) -#define DRA7_MCSPI1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xf0) -#define DRA7_MCSPI2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xf8) -#define DRA7_MCSPI3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x100) -#define DRA7_MCSPI4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x108) -#define DRA7_GPIO7_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x110) -#define DRA7_GPIO8_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x118) -#define DRA7_MMC3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x120) -#define DRA7_MMC4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x128) -#define DRA7_TIMER16_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x130) -#define DRA7_QSPI_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x138) -#define DRA7_UART1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x140) -#define DRA7_UART2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x148) -#define DRA7_UART3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x150) -#define DRA7_UART4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x158) -#define DRA7_MCASP2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x160) -#define DRA7_MCASP3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x168) -#define DRA7_UART5_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x170) -#define DRA7_MCASP5_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x178) -#define DRA7_MCASP8_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x190) -#define DRA7_MCASP4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x198) -#define DRA7_AES1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1a0) -#define DRA7_AES2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1a8) -#define DRA7_DES_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1b0) -#define DRA7_RNG_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1c0) -#define DRA7_SHAM_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1c8) -#define DRA7_UART7_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1d0) -#define DRA7_UART8_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1e0) -#define DRA7_UART9_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1e8) -#define DRA7_DCAN2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1f0) -#define DRA7_MCASP6_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x204) -#define DRA7_MCASP7_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x208) - -/* wkupaon clocks */ -#define DRA7_L4_WKUP_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) -#define DRA7_WD_TIMER2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) -#define DRA7_GPIO1_CLKCTRL DRA7_CLKCTRL_INDEX(0x38) -#define DRA7_TIMER1_CLKCTRL DRA7_CLKCTRL_INDEX(0x40) -#define DRA7_TIMER12_CLKCTRL DRA7_CLKCTRL_INDEX(0x48) -#define DRA7_COUNTER_32K_CLKCTRL DRA7_CLKCTRL_INDEX(0x50) -#define DRA7_UART10_CLKCTRL DRA7_CLKCTRL_INDEX(0x80) -#define DRA7_DCAN1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) -#define DRA7_ADC_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0) - -/* XXX: Compatibility part end. */ - /* mpu clocks */ #define DRA7_MPU_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) @@ -263,10 +92,17 @@ #define DRA7_L3INSTR_L3_MAIN_2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) #define DRA7_L3INSTR_L3_INSTR_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) +/* iva clocks */ +#define DRA7_IVA_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) +#define DRA7_SL2IF_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) + /* dss clocks */ #define DRA7_DSS_DSS_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) #define DRA7_DSS_BB2D_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) +/* gpu clocks */ +#define DRA7_GPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) + /* l3init clocks */ #define DRA7_L3INIT_MMC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) #define DRA7_L3INIT_MMC2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) @@ -332,6 +168,7 @@ #define DRA7_L4SEC_DES_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1b0) #define DRA7_L4SEC_RNG_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1c0) #define DRA7_L4SEC_SHAM_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1c8) +#define DRA7_L4SEC_SHAM2_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1f8) /* l4per2 clocks */ #define DRA7_L4PER2_CLKCTRL_OFFSET 0xc diff --git a/include/dt-bindings/clock/efm32-cmu.h b/include/dt-bindings/clock/efm32-cmu.h deleted file mode 100644 index 4b48d15fe194..000000000000 --- a/include/dt-bindings/clock/efm32-cmu.h +++ /dev/null @@ -1,43 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_BINDINGS_CLOCK_EFM32_CMU_H -#define __DT_BINDINGS_CLOCK_EFM32_CMU_H - -#define clk_HFXO 0 -#define clk_HFRCO 1 -#define clk_LFXO 2 -#define clk_LFRCO 3 -#define clk_ULFRCO 4 -#define clk_AUXHFRCO 5 -#define clk_HFCLKNODIV 6 -#define clk_HFCLK 7 -#define clk_HFPERCLK 8 -#define clk_HFCORECLK 9 -#define clk_LFACLK 10 -#define clk_LFBCLK 11 -#define clk_WDOGCLK 12 -#define clk_HFCORECLKDMA 13 -#define clk_HFCORECLKAES 14 -#define clk_HFCORECLKUSBC 15 -#define clk_HFCORECLKUSB 16 -#define clk_HFCORECLKLE 17 -#define clk_HFCORECLKEBI 18 -#define clk_HFPERCLKUSART0 19 -#define clk_HFPERCLKUSART1 20 -#define clk_HFPERCLKUSART2 21 -#define clk_HFPERCLKUART0 22 -#define clk_HFPERCLKUART1 23 -#define clk_HFPERCLKTIMER0 24 -#define clk_HFPERCLKTIMER1 25 -#define clk_HFPERCLKTIMER2 26 -#define clk_HFPERCLKTIMER3 27 -#define clk_HFPERCLKACMP0 28 -#define clk_HFPERCLKACMP1 29 -#define clk_HFPERCLKI2C0 30 -#define clk_HFPERCLKI2C1 31 -#define clk_HFPERCLKGPIO 32 -#define clk_HFPERCLKVCMP 33 -#define clk_HFPERCLKPRS 34 -#define clk_HFPERCLKADC0 35 -#define clk_HFPERCLKDAC0 36 - -#endif /* __DT_BINDINGS_CLOCK_EFM32_CMU_H */ diff --git a/include/dt-bindings/clock/en7523-clk.h b/include/dt-bindings/clock/en7523-clk.h new file mode 100644 index 000000000000..717d23a5e5ae --- /dev/null +++ b/include/dt-bindings/clock/en7523-clk.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLOCK_AIROHA_EN7523_H_ +#define _DT_BINDINGS_CLOCK_AIROHA_EN7523_H_ + +#define EN7523_CLK_GSW 0 +#define EN7523_CLK_EMI 1 +#define EN7523_CLK_BUS 2 +#define EN7523_CLK_SLIC 3 +#define EN7523_CLK_SPI 4 +#define EN7523_CLK_NPU 5 +#define EN7523_CLK_CRYPTO 6 +#define EN7523_CLK_PCIE 7 + +#define EN7523_NUM_CLOCKS 8 + +#endif /* _DT_BINDINGS_CLOCK_AIROHA_EN7523_H_ */ diff --git a/include/dt-bindings/clock/exynos4.h b/include/dt-bindings/clock/exynos4.h index 88ec3968b90a..acbfbab875ec 100644 --- a/include/dt-bindings/clock/exynos4.h +++ b/include/dt-bindings/clock/exynos4.h @@ -209,6 +209,7 @@ #define CLK_ACLK400_MCUISP 395 /* Exynos4x12 only */ #define CLK_MOUT_HDMI 396 #define CLK_MOUT_MIXER 397 +#define CLK_MOUT_VPLLSRC 398 /* gate clocks - ppmu */ #define CLK_PPMULEFT 400 @@ -236,9 +237,10 @@ #define CLK_DIV_C2C 458 /* Exynos4x12 only */ #define CLK_DIV_GDL 459 #define CLK_DIV_GDR 460 +#define CLK_DIV_CORE2 461 /* must be greater than maximal clock id */ -#define CLK_NR_CLKS 461 +#define CLK_NR_CLKS 462 /* Exynos4x12 ISP clocks */ #define CLK_ISP_FIMC_ISP 1 diff --git a/include/dt-bindings/clock/exynos5250.h b/include/dt-bindings/clock/exynos5250.h index bc8a3c53a54b..4680da7357d3 100644 --- a/include/dt-bindings/clock/exynos5250.h +++ b/include/dt-bindings/clock/exynos5250.h @@ -19,6 +19,7 @@ #define CLK_FOUT_EPLL 7 #define CLK_FOUT_VPLL 8 #define CLK_ARM_CLK 9 +#define CLK_DIV_ARM2 10 /* gate for special clocks (sclk) */ #define CLK_SCLK_CAM_BAYER 128 @@ -172,8 +173,11 @@ #define CLK_MOUT_GPLL 1025 #define CLK_MOUT_ACLK200_DISP1_SUB 1026 #define CLK_MOUT_ACLK300_DISP1_SUB 1027 +#define CLK_MOUT_APLL 1028 +#define CLK_MOUT_MPLL 1029 +#define CLK_MOUT_VPLLSRC 1030 /* must be greater than maximal clock id */ -#define CLK_NR_CLKS 1028 +#define CLK_NR_CLKS 1031 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5250_H */ diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h index 02d5ac469a3d..9fffc6ceaadd 100644 --- a/include/dt-bindings/clock/exynos5420.h +++ b/include/dt-bindings/clock/exynos5420.h @@ -230,6 +230,12 @@ #define CLK_MOUT_USER_MAU_EPLL 659 #define CLK_MOUT_SCLK_SPLL 660 #define CLK_MOUT_MX_MSPLL_CCORE_PHY 661 +#define CLK_MOUT_SW_ACLK_G3D 662 +#define CLK_MOUT_APLL 663 +#define CLK_MOUT_MSPLL_CPU 664 +#define CLK_MOUT_KPLL 665 +#define CLK_MOUT_MSPLL_KFC 666 + /* divider clocks */ #define CLK_DOUT_PIXEL 768 diff --git a/include/dt-bindings/clock/exynos7885.h b/include/dt-bindings/clock/exynos7885.h new file mode 100644 index 000000000000..8256e7430b63 --- /dev/null +++ b/include/dt-bindings/clock/exynos7885.h @@ -0,0 +1,151 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2021 Dávid Virág + * + * Device Tree binding constants for Exynos7885 clock controller. + */ + +#ifndef _DT_BINDINGS_CLOCK_EXYNOS_7885_H +#define _DT_BINDINGS_CLOCK_EXYNOS_7885_H + +/* CMU_TOP */ +#define CLK_FOUT_SHARED0_PLL 1 +#define CLK_FOUT_SHARED1_PLL 2 +#define CLK_DOUT_SHARED0_DIV2 3 +#define CLK_DOUT_SHARED0_DIV3 4 +#define CLK_DOUT_SHARED0_DIV4 5 +#define CLK_DOUT_SHARED0_DIV5 6 +#define CLK_DOUT_SHARED1_DIV2 7 +#define CLK_DOUT_SHARED1_DIV3 8 +#define CLK_DOUT_SHARED1_DIV4 9 +#define CLK_MOUT_CORE_BUS 10 +#define CLK_MOUT_CORE_CCI 11 +#define CLK_MOUT_CORE_G3D 12 +#define CLK_DOUT_CORE_BUS 13 +#define CLK_DOUT_CORE_CCI 14 +#define CLK_DOUT_CORE_G3D 15 +#define CLK_GOUT_CORE_BUS 16 +#define CLK_GOUT_CORE_CCI 17 +#define CLK_GOUT_CORE_G3D 18 +#define CLK_MOUT_PERI_BUS 19 +#define CLK_MOUT_PERI_SPI0 20 +#define CLK_MOUT_PERI_SPI1 21 +#define CLK_MOUT_PERI_UART0 22 +#define CLK_MOUT_PERI_UART1 23 +#define CLK_MOUT_PERI_UART2 24 +#define CLK_MOUT_PERI_USI0 25 +#define CLK_MOUT_PERI_USI1 26 +#define CLK_MOUT_PERI_USI2 27 +#define CLK_DOUT_PERI_BUS 28 +#define CLK_DOUT_PERI_SPI0 29 +#define CLK_DOUT_PERI_SPI1 30 +#define CLK_DOUT_PERI_UART0 31 +#define CLK_DOUT_PERI_UART1 32 +#define CLK_DOUT_PERI_UART2 33 +#define CLK_DOUT_PERI_USI0 34 +#define CLK_DOUT_PERI_USI1 35 +#define CLK_DOUT_PERI_USI2 36 +#define CLK_GOUT_PERI_BUS 37 +#define CLK_GOUT_PERI_SPI0 38 +#define CLK_GOUT_PERI_SPI1 39 +#define CLK_GOUT_PERI_UART0 40 +#define CLK_GOUT_PERI_UART1 41 +#define CLK_GOUT_PERI_UART2 42 +#define CLK_GOUT_PERI_USI0 43 +#define CLK_GOUT_PERI_USI1 44 +#define CLK_GOUT_PERI_USI2 45 +#define CLK_MOUT_FSYS_BUS 46 +#define CLK_MOUT_FSYS_MMC_CARD 47 +#define CLK_MOUT_FSYS_MMC_EMBD 48 +#define CLK_MOUT_FSYS_MMC_SDIO 49 +#define CLK_MOUT_FSYS_USB30DRD 50 +#define CLK_DOUT_FSYS_BUS 51 +#define CLK_DOUT_FSYS_MMC_CARD 52 +#define CLK_DOUT_FSYS_MMC_EMBD 53 +#define CLK_DOUT_FSYS_MMC_SDIO 54 +#define CLK_DOUT_FSYS_USB30DRD 55 +#define CLK_GOUT_FSYS_BUS 56 +#define CLK_GOUT_FSYS_MMC_CARD 57 +#define CLK_GOUT_FSYS_MMC_EMBD 58 +#define CLK_GOUT_FSYS_MMC_SDIO 59 +#define CLK_GOUT_FSYS_USB30DRD 60 +#define TOP_NR_CLK 61 + +/* CMU_CORE */ +#define CLK_MOUT_CORE_BUS_USER 1 +#define CLK_MOUT_CORE_CCI_USER 2 +#define CLK_MOUT_CORE_G3D_USER 3 +#define CLK_MOUT_CORE_GIC 4 +#define CLK_DOUT_CORE_BUSP 5 +#define CLK_GOUT_CCI_ACLK 6 +#define CLK_GOUT_GIC400_CLK 7 +#define CLK_GOUT_TREX_D_CORE_ACLK 8 +#define CLK_GOUT_TREX_D_CORE_GCLK 9 +#define CLK_GOUT_TREX_D_CORE_PCLK 10 +#define CLK_GOUT_TREX_P_CORE_ACLK_P_CORE 11 +#define CLK_GOUT_TREX_P_CORE_CCLK_P_CORE 12 +#define CLK_GOUT_TREX_P_CORE_PCLK 13 +#define CLK_GOUT_TREX_P_CORE_PCLK_P_CORE 14 +#define CORE_NR_CLK 15 + +/* CMU_PERI */ +#define CLK_MOUT_PERI_BUS_USER 1 +#define CLK_MOUT_PERI_SPI0_USER 2 +#define CLK_MOUT_PERI_SPI1_USER 3 +#define CLK_MOUT_PERI_UART0_USER 4 +#define CLK_MOUT_PERI_UART1_USER 5 +#define CLK_MOUT_PERI_UART2_USER 6 +#define CLK_MOUT_PERI_USI0_USER 7 +#define CLK_MOUT_PERI_USI1_USER 8 +#define CLK_MOUT_PERI_USI2_USER 9 +#define CLK_GOUT_GPIO_TOP_PCLK 10 +#define CLK_GOUT_HSI2C0_PCLK 11 +#define CLK_GOUT_HSI2C1_PCLK 12 +#define CLK_GOUT_HSI2C2_PCLK 13 +#define CLK_GOUT_HSI2C3_PCLK 14 +#define CLK_GOUT_I2C0_PCLK 15 +#define CLK_GOUT_I2C1_PCLK 16 +#define CLK_GOUT_I2C2_PCLK 17 +#define CLK_GOUT_I2C3_PCLK 18 +#define CLK_GOUT_I2C4_PCLK 19 +#define CLK_GOUT_I2C5_PCLK 20 +#define CLK_GOUT_I2C6_PCLK 21 +#define CLK_GOUT_I2C7_PCLK 22 +#define CLK_GOUT_PWM_MOTOR_PCLK 23 +#define CLK_GOUT_SPI0_PCLK 24 +#define CLK_GOUT_SPI0_EXT_CLK 25 +#define CLK_GOUT_SPI1_PCLK 26 +#define CLK_GOUT_SPI1_EXT_CLK 27 +#define CLK_GOUT_UART0_EXT_UCLK 28 +#define CLK_GOUT_UART0_PCLK 29 +#define CLK_GOUT_UART1_EXT_UCLK 30 +#define CLK_GOUT_UART1_PCLK 31 +#define CLK_GOUT_UART2_EXT_UCLK 32 +#define CLK_GOUT_UART2_PCLK 33 +#define CLK_GOUT_USI0_PCLK 34 +#define CLK_GOUT_USI0_SCLK 35 +#define CLK_GOUT_USI1_PCLK 36 +#define CLK_GOUT_USI1_SCLK 37 +#define CLK_GOUT_USI2_PCLK 38 +#define CLK_GOUT_USI2_SCLK 39 +#define CLK_GOUT_MCT_PCLK 40 +#define CLK_GOUT_SYSREG_PERI_PCLK 41 +#define CLK_GOUT_WDT0_PCLK 42 +#define CLK_GOUT_WDT1_PCLK 43 +#define PERI_NR_CLK 44 + +/* CMU_FSYS */ +#define CLK_MOUT_FSYS_BUS_USER 1 +#define CLK_MOUT_FSYS_MMC_CARD_USER 2 +#define CLK_MOUT_FSYS_MMC_EMBD_USER 3 +#define CLK_MOUT_FSYS_MMC_SDIO_USER 4 +#define CLK_MOUT_FSYS_USB30DRD_USER 4 +#define CLK_GOUT_MMC_CARD_ACLK 5 +#define CLK_GOUT_MMC_CARD_SDCLKIN 6 +#define CLK_GOUT_MMC_EMBD_ACLK 7 +#define CLK_GOUT_MMC_EMBD_SDCLKIN 8 +#define CLK_GOUT_MMC_SDIO_ACLK 9 +#define CLK_GOUT_MMC_SDIO_SDCLKIN 10 +#define FSYS_NR_CLK 11 + +#endif /* _DT_BINDINGS_CLOCK_EXYNOS_7885_H */ diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/clock/exynos850.h new file mode 100644 index 000000000000..88d5289883d3 --- /dev/null +++ b/include/dt-bindings/clock/exynos850.h @@ -0,0 +1,325 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2021 Linaro Ltd. + * Author: Sam Protsenko <semen.protsenko@linaro.org> + * + * Device Tree binding constants for Exynos850 clock controller. + */ + +#ifndef _DT_BINDINGS_CLOCK_EXYNOS_850_H +#define _DT_BINDINGS_CLOCK_EXYNOS_850_H + +/* CMU_TOP */ +#define CLK_FOUT_SHARED0_PLL 1 +#define CLK_FOUT_SHARED1_PLL 2 +#define CLK_FOUT_MMC_PLL 3 +#define CLK_MOUT_SHARED0_PLL 4 +#define CLK_MOUT_SHARED1_PLL 5 +#define CLK_MOUT_MMC_PLL 6 +#define CLK_MOUT_CORE_BUS 7 +#define CLK_MOUT_CORE_CCI 8 +#define CLK_MOUT_CORE_MMC_EMBD 9 +#define CLK_MOUT_CORE_SSS 10 +#define CLK_MOUT_DPU 11 +#define CLK_MOUT_HSI_BUS 12 +#define CLK_MOUT_HSI_MMC_CARD 13 +#define CLK_MOUT_HSI_USB20DRD 14 +#define CLK_MOUT_PERI_BUS 15 +#define CLK_MOUT_PERI_UART 16 +#define CLK_MOUT_PERI_IP 17 +#define CLK_DOUT_SHARED0_DIV3 18 +#define CLK_DOUT_SHARED0_DIV2 19 +#define CLK_DOUT_SHARED1_DIV3 20 +#define CLK_DOUT_SHARED1_DIV2 21 +#define CLK_DOUT_SHARED0_DIV4 22 +#define CLK_DOUT_SHARED1_DIV4 23 +#define CLK_DOUT_CORE_BUS 24 +#define CLK_DOUT_CORE_CCI 25 +#define CLK_DOUT_CORE_MMC_EMBD 26 +#define CLK_DOUT_CORE_SSS 27 +#define CLK_DOUT_DPU 28 +#define CLK_DOUT_HSI_BUS 29 +#define CLK_DOUT_HSI_MMC_CARD 30 +#define CLK_DOUT_HSI_USB20DRD 31 +#define CLK_DOUT_PERI_BUS 32 +#define CLK_DOUT_PERI_UART 33 +#define CLK_DOUT_PERI_IP 34 +#define CLK_GOUT_CORE_BUS 35 +#define CLK_GOUT_CORE_CCI 36 +#define CLK_GOUT_CORE_MMC_EMBD 37 +#define CLK_GOUT_CORE_SSS 38 +#define CLK_GOUT_DPU 39 +#define CLK_GOUT_HSI_BUS 40 +#define CLK_GOUT_HSI_MMC_CARD 41 +#define CLK_GOUT_HSI_USB20DRD 42 +#define CLK_GOUT_PERI_BUS 43 +#define CLK_GOUT_PERI_UART 44 +#define CLK_GOUT_PERI_IP 45 +#define CLK_MOUT_CLKCMU_APM_BUS 46 +#define CLK_DOUT_CLKCMU_APM_BUS 47 +#define CLK_GOUT_CLKCMU_APM_BUS 48 +#define CLK_MOUT_AUD 49 +#define CLK_GOUT_AUD 50 +#define CLK_DOUT_AUD 51 +#define CLK_MOUT_IS_BUS 52 +#define CLK_MOUT_IS_ITP 53 +#define CLK_MOUT_IS_VRA 54 +#define CLK_MOUT_IS_GDC 55 +#define CLK_GOUT_IS_BUS 56 +#define CLK_GOUT_IS_ITP 57 +#define CLK_GOUT_IS_VRA 58 +#define CLK_GOUT_IS_GDC 59 +#define CLK_DOUT_IS_BUS 60 +#define CLK_DOUT_IS_ITP 61 +#define CLK_DOUT_IS_VRA 62 +#define CLK_DOUT_IS_GDC 63 +#define CLK_MOUT_MFCMSCL_MFC 64 +#define CLK_MOUT_MFCMSCL_M2M 65 +#define CLK_MOUT_MFCMSCL_MCSC 66 +#define CLK_MOUT_MFCMSCL_JPEG 67 +#define CLK_GOUT_MFCMSCL_MFC 68 +#define CLK_GOUT_MFCMSCL_M2M 69 +#define CLK_GOUT_MFCMSCL_MCSC 70 +#define CLK_GOUT_MFCMSCL_JPEG 71 +#define CLK_DOUT_MFCMSCL_MFC 72 +#define CLK_DOUT_MFCMSCL_M2M 73 +#define CLK_DOUT_MFCMSCL_MCSC 74 +#define CLK_DOUT_MFCMSCL_JPEG 75 +#define TOP_NR_CLK 76 + +/* CMU_APM */ +#define CLK_RCO_I3C_PMIC 1 +#define OSCCLK_RCO_APM 2 +#define CLK_RCO_APM__ALV 3 +#define CLK_DLL_DCO 4 +#define CLK_MOUT_APM_BUS_USER 5 +#define CLK_MOUT_RCO_APM_I3C_USER 6 +#define CLK_MOUT_RCO_APM_USER 7 +#define CLK_MOUT_DLL_USER 8 +#define CLK_MOUT_CLKCMU_CHUB_BUS 9 +#define CLK_MOUT_APM_BUS 10 +#define CLK_MOUT_APM_I3C 11 +#define CLK_DOUT_CLKCMU_CHUB_BUS 12 +#define CLK_DOUT_APM_BUS 13 +#define CLK_DOUT_APM_I3C 14 +#define CLK_GOUT_CLKCMU_CMGP_BUS 15 +#define CLK_GOUT_CLKCMU_CHUB_BUS 16 +#define CLK_GOUT_RTC_PCLK 17 +#define CLK_GOUT_TOP_RTC_PCLK 18 +#define CLK_GOUT_I3C_PCLK 19 +#define CLK_GOUT_I3C_SCLK 20 +#define CLK_GOUT_SPEEDY_PCLK 21 +#define CLK_GOUT_GPIO_ALIVE_PCLK 22 +#define CLK_GOUT_PMU_ALIVE_PCLK 23 +#define CLK_GOUT_SYSREG_APM_PCLK 24 +#define APM_NR_CLK 25 + +/* CMU_AUD */ +#define CLK_DOUT_AUD_AUDIF 1 +#define CLK_DOUT_AUD_BUSD 2 +#define CLK_DOUT_AUD_BUSP 3 +#define CLK_DOUT_AUD_CNT 4 +#define CLK_DOUT_AUD_CPU 5 +#define CLK_DOUT_AUD_CPU_ACLK 6 +#define CLK_DOUT_AUD_CPU_PCLKDBG 7 +#define CLK_DOUT_AUD_FM 8 +#define CLK_DOUT_AUD_FM_SPDY 9 +#define CLK_DOUT_AUD_MCLK 10 +#define CLK_DOUT_AUD_UAIF0 11 +#define CLK_DOUT_AUD_UAIF1 12 +#define CLK_DOUT_AUD_UAIF2 13 +#define CLK_DOUT_AUD_UAIF3 14 +#define CLK_DOUT_AUD_UAIF4 15 +#define CLK_DOUT_AUD_UAIF5 16 +#define CLK_DOUT_AUD_UAIF6 17 +#define CLK_FOUT_AUD_PLL 18 +#define CLK_GOUT_AUD_ABOX_ACLK 19 +#define CLK_GOUT_AUD_ASB_CCLK 20 +#define CLK_GOUT_AUD_CA32_CCLK 21 +#define CLK_GOUT_AUD_CNT_BCLK 22 +#define CLK_GOUT_AUD_CODEC_MCLK 23 +#define CLK_GOUT_AUD_DAP_CCLK 24 +#define CLK_GOUT_AUD_GPIO_PCLK 25 +#define CLK_GOUT_AUD_PPMU_ACLK 26 +#define CLK_GOUT_AUD_PPMU_PCLK 27 +#define CLK_GOUT_AUD_SPDY_BCLK 28 +#define CLK_GOUT_AUD_SYSMMU_CLK 29 +#define CLK_GOUT_AUD_SYSREG_PCLK 30 +#define CLK_GOUT_AUD_TZPC_PCLK 31 +#define CLK_GOUT_AUD_UAIF0_BCLK 32 +#define CLK_GOUT_AUD_UAIF1_BCLK 33 +#define CLK_GOUT_AUD_UAIF2_BCLK 34 +#define CLK_GOUT_AUD_UAIF3_BCLK 35 +#define CLK_GOUT_AUD_UAIF4_BCLK 36 +#define CLK_GOUT_AUD_UAIF5_BCLK 37 +#define CLK_GOUT_AUD_UAIF6_BCLK 38 +#define CLK_GOUT_AUD_WDT_PCLK 39 +#define CLK_MOUT_AUD_CPU 40 +#define CLK_MOUT_AUD_CPU_HCH 41 +#define CLK_MOUT_AUD_CPU_USER 42 +#define CLK_MOUT_AUD_FM 43 +#define CLK_MOUT_AUD_PLL 44 +#define CLK_MOUT_AUD_TICK_USB_USER 45 +#define CLK_MOUT_AUD_UAIF0 46 +#define CLK_MOUT_AUD_UAIF1 47 +#define CLK_MOUT_AUD_UAIF2 48 +#define CLK_MOUT_AUD_UAIF3 49 +#define CLK_MOUT_AUD_UAIF4 50 +#define CLK_MOUT_AUD_UAIF5 51 +#define CLK_MOUT_AUD_UAIF6 52 +#define IOCLK_AUDIOCDCLK0 53 +#define IOCLK_AUDIOCDCLK1 54 +#define IOCLK_AUDIOCDCLK2 55 +#define IOCLK_AUDIOCDCLK3 56 +#define IOCLK_AUDIOCDCLK4 57 +#define IOCLK_AUDIOCDCLK5 58 +#define IOCLK_AUDIOCDCLK6 59 +#define TICK_USB 60 +#define AUD_NR_CLK 61 + +/* CMU_CMGP */ +#define CLK_RCO_CMGP 1 +#define CLK_MOUT_CMGP_ADC 2 +#define CLK_MOUT_CMGP_USI0 3 +#define CLK_MOUT_CMGP_USI1 4 +#define CLK_DOUT_CMGP_ADC 5 +#define CLK_DOUT_CMGP_USI0 6 +#define CLK_DOUT_CMGP_USI1 7 +#define CLK_GOUT_CMGP_ADC_S0_PCLK 8 +#define CLK_GOUT_CMGP_ADC_S1_PCLK 9 +#define CLK_GOUT_CMGP_GPIO_PCLK 10 +#define CLK_GOUT_CMGP_USI0_IPCLK 11 +#define CLK_GOUT_CMGP_USI0_PCLK 12 +#define CLK_GOUT_CMGP_USI1_IPCLK 13 +#define CLK_GOUT_CMGP_USI1_PCLK 14 +#define CLK_GOUT_SYSREG_CMGP_PCLK 15 +#define CMGP_NR_CLK 16 + +/* CMU_HSI */ +#define CLK_MOUT_HSI_BUS_USER 1 +#define CLK_MOUT_HSI_MMC_CARD_USER 2 +#define CLK_MOUT_HSI_USB20DRD_USER 3 +#define CLK_MOUT_HSI_RTC 4 +#define CLK_GOUT_USB_RTC_CLK 5 +#define CLK_GOUT_USB_REF_CLK 6 +#define CLK_GOUT_USB_PHY_REF_CLK 7 +#define CLK_GOUT_USB_PHY_ACLK 8 +#define CLK_GOUT_USB_BUS_EARLY_CLK 9 +#define CLK_GOUT_GPIO_HSI_PCLK 10 +#define CLK_GOUT_MMC_CARD_ACLK 11 +#define CLK_GOUT_MMC_CARD_SDCLKIN 12 +#define CLK_GOUT_SYSREG_HSI_PCLK 13 +#define HSI_NR_CLK 14 + +/* CMU_IS */ +#define CLK_MOUT_IS_BUS_USER 1 +#define CLK_MOUT_IS_ITP_USER 2 +#define CLK_MOUT_IS_VRA_USER 3 +#define CLK_MOUT_IS_GDC_USER 4 +#define CLK_DOUT_IS_BUSP 5 +#define CLK_GOUT_IS_CMU_IS_PCLK 6 +#define CLK_GOUT_IS_CSIS0_ACLK 7 +#define CLK_GOUT_IS_CSIS1_ACLK 8 +#define CLK_GOUT_IS_CSIS2_ACLK 9 +#define CLK_GOUT_IS_TZPC_PCLK 10 +#define CLK_GOUT_IS_CSIS_DMA_CLK 11 +#define CLK_GOUT_IS_GDC_CLK 12 +#define CLK_GOUT_IS_IPP_CLK 13 +#define CLK_GOUT_IS_ITP_CLK 14 +#define CLK_GOUT_IS_MCSC_CLK 15 +#define CLK_GOUT_IS_VRA_CLK 16 +#define CLK_GOUT_IS_PPMU_IS0_ACLK 17 +#define CLK_GOUT_IS_PPMU_IS0_PCLK 18 +#define CLK_GOUT_IS_PPMU_IS1_ACLK 19 +#define CLK_GOUT_IS_PPMU_IS1_PCLK 20 +#define CLK_GOUT_IS_SYSMMU_IS0_CLK 21 +#define CLK_GOUT_IS_SYSMMU_IS1_CLK 22 +#define CLK_GOUT_IS_SYSREG_PCLK 23 +#define IS_NR_CLK 24 + +/* CMU_MFCMSCL */ +#define CLK_MOUT_MFCMSCL_MFC_USER 1 +#define CLK_MOUT_MFCMSCL_M2M_USER 2 +#define CLK_MOUT_MFCMSCL_MCSC_USER 3 +#define CLK_MOUT_MFCMSCL_JPEG_USER 4 +#define CLK_DOUT_MFCMSCL_BUSP 5 +#define CLK_GOUT_MFCMSCL_CMU_MFCMSCL_PCLK 6 +#define CLK_GOUT_MFCMSCL_TZPC_PCLK 7 +#define CLK_GOUT_MFCMSCL_JPEG_ACLK 8 +#define CLK_GOUT_MFCMSCL_M2M_ACLK 9 +#define CLK_GOUT_MFCMSCL_MCSC_CLK 10 +#define CLK_GOUT_MFCMSCL_MFC_ACLK 11 +#define CLK_GOUT_MFCMSCL_PPMU_ACLK 12 +#define CLK_GOUT_MFCMSCL_PPMU_PCLK 13 +#define CLK_GOUT_MFCMSCL_SYSMMU_CLK 14 +#define CLK_GOUT_MFCMSCL_SYSREG_PCLK 15 +#define MFCMSCL_NR_CLK 16 + +/* CMU_PERI */ +#define CLK_MOUT_PERI_BUS_USER 1 +#define CLK_MOUT_PERI_UART_USER 2 +#define CLK_MOUT_PERI_HSI2C_USER 3 +#define CLK_MOUT_PERI_SPI_USER 4 +#define CLK_DOUT_PERI_HSI2C0 5 +#define CLK_DOUT_PERI_HSI2C1 6 +#define CLK_DOUT_PERI_HSI2C2 7 +#define CLK_DOUT_PERI_SPI0 8 +#define CLK_GOUT_PERI_HSI2C0 9 +#define CLK_GOUT_PERI_HSI2C1 10 +#define CLK_GOUT_PERI_HSI2C2 11 +#define CLK_GOUT_GPIO_PERI_PCLK 12 +#define CLK_GOUT_HSI2C0_IPCLK 13 +#define CLK_GOUT_HSI2C0_PCLK 14 +#define CLK_GOUT_HSI2C1_IPCLK 15 +#define CLK_GOUT_HSI2C1_PCLK 16 +#define CLK_GOUT_HSI2C2_IPCLK 17 +#define CLK_GOUT_HSI2C2_PCLK 18 +#define CLK_GOUT_I2C0_PCLK 19 +#define CLK_GOUT_I2C1_PCLK 20 +#define CLK_GOUT_I2C2_PCLK 21 +#define CLK_GOUT_I2C3_PCLK 22 +#define CLK_GOUT_I2C4_PCLK 23 +#define CLK_GOUT_I2C5_PCLK 24 +#define CLK_GOUT_I2C6_PCLK 25 +#define CLK_GOUT_MCT_PCLK 26 +#define CLK_GOUT_PWM_MOTOR_PCLK 27 +#define CLK_GOUT_SPI0_IPCLK 28 +#define CLK_GOUT_SPI0_PCLK 29 +#define CLK_GOUT_SYSREG_PERI_PCLK 30 +#define CLK_GOUT_UART_IPCLK 31 +#define CLK_GOUT_UART_PCLK 32 +#define CLK_GOUT_WDT0_PCLK 33 +#define CLK_GOUT_WDT1_PCLK 34 +#define PERI_NR_CLK 35 + +/* CMU_CORE */ +#define CLK_MOUT_CORE_BUS_USER 1 +#define CLK_MOUT_CORE_CCI_USER 2 +#define CLK_MOUT_CORE_MMC_EMBD_USER 3 +#define CLK_MOUT_CORE_SSS_USER 4 +#define CLK_MOUT_CORE_GIC 5 +#define CLK_DOUT_CORE_BUSP 6 +#define CLK_GOUT_CCI_ACLK 7 +#define CLK_GOUT_GIC_CLK 8 +#define CLK_GOUT_MMC_EMBD_ACLK 9 +#define CLK_GOUT_MMC_EMBD_SDCLKIN 10 +#define CLK_GOUT_SSS_ACLK 11 +#define CLK_GOUT_SSS_PCLK 12 +#define CLK_GOUT_GPIO_CORE_PCLK 13 +#define CLK_GOUT_SYSREG_CORE_PCLK 14 +#define CORE_NR_CLK 15 + +/* CMU_DPU */ +#define CLK_MOUT_DPU_USER 1 +#define CLK_DOUT_DPU_BUSP 2 +#define CLK_GOUT_DPU_CMU_DPU_PCLK 3 +#define CLK_GOUT_DPU_DECON0_ACLK 4 +#define CLK_GOUT_DPU_DMA_ACLK 5 +#define CLK_GOUT_DPU_DPP_ACLK 6 +#define CLK_GOUT_DPU_PPMU_ACLK 7 +#define CLK_GOUT_DPU_PPMU_PCLK 8 +#define CLK_GOUT_DPU_SMMU_CLK 9 +#define CLK_GOUT_DPU_SYSREG_PCLK 10 +#define DPU_NR_CLK 11 + +#endif /* _DT_BINDINGS_CLOCK_EXYNOS_850_H */ diff --git a/include/dt-bindings/clock/fsd-clk.h b/include/dt-bindings/clock/fsd-clk.h new file mode 100644 index 000000000000..c8a2af1dd1ad --- /dev/null +++ b/include/dt-bindings/clock/fsd-clk.h @@ -0,0 +1,150 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017 - 2022: Samsung Electronics Co., Ltd. + * https://www.samsung.com + * Copyright (c) 2017-2022 Tesla, Inc. + * https://www.tesla.com + * + * The constants defined in this header are being used in dts + * and fsd platform driver. + */ + +#ifndef _DT_BINDINGS_CLOCK_FSD_H +#define _DT_BINDINGS_CLOCK_FSD_H + +/* CMU */ +#define DOUT_CMU_PLL_SHARED0_DIV4 1 +#define DOUT_CMU_PERIC_SHARED1DIV36 2 +#define DOUT_CMU_PERIC_SHARED0DIV3_TBUCLK 3 +#define DOUT_CMU_PERIC_SHARED0DIV20 4 +#define DOUT_CMU_PERIC_SHARED1DIV4_DMACLK 5 +#define DOUT_CMU_PLL_SHARED0_DIV6 6 +#define DOUT_CMU_FSYS0_SHARED1DIV4 7 +#define DOUT_CMU_FSYS0_SHARED0DIV4 8 +#define DOUT_CMU_FSYS1_SHARED0DIV8 9 +#define DOUT_CMU_FSYS1_SHARED0DIV4 10 +#define CMU_CPUCL_SWITCH_GATE 11 +#define DOUT_CMU_IMEM_TCUCLK 12 +#define DOUT_CMU_IMEM_ACLK 13 +#define DOUT_CMU_IMEM_DMACLK 14 +#define GAT_CMU_FSYS0_SHARED0DIV4 15 +#define CMU_NR_CLK 16 + +/* PERIC */ +#define PERIC_SCLK_UART0 1 +#define PERIC_PCLK_UART0 2 +#define PERIC_SCLK_UART1 3 +#define PERIC_PCLK_UART1 4 +#define PERIC_DMA0_IPCLKPORT_ACLK 5 +#define PERIC_DMA1_IPCLKPORT_ACLK 6 +#define PERIC_PWM0_IPCLKPORT_I_PCLK_S0 7 +#define PERIC_PWM1_IPCLKPORT_I_PCLK_S0 8 +#define PERIC_PCLK_SPI0 9 +#define PERIC_SCLK_SPI0 10 +#define PERIC_PCLK_SPI1 11 +#define PERIC_SCLK_SPI1 12 +#define PERIC_PCLK_SPI2 13 +#define PERIC_SCLK_SPI2 14 +#define PERIC_PCLK_TDM0 15 +#define PERIC_PCLK_HSI2C0 16 +#define PERIC_PCLK_HSI2C1 17 +#define PERIC_PCLK_HSI2C2 18 +#define PERIC_PCLK_HSI2C3 19 +#define PERIC_PCLK_HSI2C4 20 +#define PERIC_PCLK_HSI2C5 21 +#define PERIC_PCLK_HSI2C6 22 +#define PERIC_PCLK_HSI2C7 23 +#define PERIC_MCAN0_IPCLKPORT_CCLK 24 +#define PERIC_MCAN0_IPCLKPORT_PCLK 25 +#define PERIC_MCAN1_IPCLKPORT_CCLK 26 +#define PERIC_MCAN1_IPCLKPORT_PCLK 27 +#define PERIC_MCAN2_IPCLKPORT_CCLK 28 +#define PERIC_MCAN2_IPCLKPORT_PCLK 29 +#define PERIC_MCAN3_IPCLKPORT_CCLK 30 +#define PERIC_MCAN3_IPCLKPORT_PCLK 31 +#define PERIC_PCLK_ADCIF 32 +#define PERIC_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I 33 +#define PERIC_EQOS_TOP_IPCLKPORT_ACLK_I 34 +#define PERIC_EQOS_TOP_IPCLKPORT_HCLK_I 35 +#define PERIC_EQOS_TOP_IPCLKPORT_RGMII_CLK_I 36 +#define PERIC_EQOS_TOP_IPCLKPORT_CLK_RX_I 37 +#define PERIC_BUS_D_PERIC_IPCLKPORT_EQOSCLK 38 +#define PERIC_BUS_P_PERIC_IPCLKPORT_EQOSCLK 39 +#define PERIC_HCLK_TDM0 40 +#define PERIC_PCLK_TDM1 41 +#define PERIC_HCLK_TDM1 42 +#define PERIC_EQOS_PHYRXCLK_MUX 43 +#define PERIC_EQOS_PHYRXCLK 44 +#define PERIC_DOUT_RGMII_CLK 45 +#define PERIC_NR_CLK 46 + +/* FSYS0 */ +#define UFS0_MPHY_REFCLK_IXTAL24 1 +#define UFS0_MPHY_REFCLK_IXTAL26 2 +#define UFS1_MPHY_REFCLK_IXTAL24 3 +#define UFS1_MPHY_REFCLK_IXTAL26 4 +#define UFS0_TOP0_HCLK_BUS 5 +#define UFS0_TOP0_ACLK 6 +#define UFS0_TOP0_CLK_UNIPRO 7 +#define UFS0_TOP0_FMP_CLK 8 +#define UFS1_TOP1_HCLK_BUS 9 +#define UFS1_TOP1_ACLK 10 +#define UFS1_TOP1_CLK_UNIPRO 11 +#define UFS1_TOP1_FMP_CLK 12 +#define PCIE_SUBCTRL_INST0_DBI_ACLK_SOC 13 +#define PCIE_SUBCTRL_INST0_AUX_CLK_SOC 14 +#define PCIE_SUBCTRL_INST0_MSTR_ACLK_SOC 15 +#define PCIE_SUBCTRL_INST0_SLV_ACLK_SOC 16 +#define FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I 17 +#define FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I 18 +#define FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I 19 +#define FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I 20 +#define FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I 21 +#define FSYS0_DOUT_FSYS0_PERIBUS_GRP 22 +#define FSYS0_NR_CLK 23 + +/* FSYS1 */ +#define PCIE_LINK0_IPCLKPORT_DBI_ACLK 1 +#define PCIE_LINK0_IPCLKPORT_AUX_ACLK 2 +#define PCIE_LINK0_IPCLKPORT_MSTR_ACLK 3 +#define PCIE_LINK0_IPCLKPORT_SLV_ACLK 4 +#define PCIE_LINK1_IPCLKPORT_DBI_ACLK 5 +#define PCIE_LINK1_IPCLKPORT_AUX_ACLK 6 +#define PCIE_LINK1_IPCLKPORT_MSTR_ACLK 7 +#define PCIE_LINK1_IPCLKPORT_SLV_ACLK 8 +#define FSYS1_NR_CLK 9 + +/* IMEM */ +#define IMEM_DMA0_IPCLKPORT_ACLK 1 +#define IMEM_DMA1_IPCLKPORT_ACLK 2 +#define IMEM_WDT0_IPCLKPORT_PCLK 3 +#define IMEM_WDT1_IPCLKPORT_PCLK 4 +#define IMEM_WDT2_IPCLKPORT_PCLK 5 +#define IMEM_MCT_PCLK 6 +#define IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS 7 +#define IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS 8 +#define IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS 9 +#define IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS 10 +#define IMEM_TMU_GT_IPCLKPORT_I_CLK_TS 11 +#define IMEM_NR_CLK 12 + +/* MFC */ +#define MFC_MFC_IPCLKPORT_ACLK 1 +#define MFC_NR_CLK 2 + +/* CAM_CSI */ +#define CAM_CSI0_0_IPCLKPORT_I_ACLK 1 +#define CAM_CSI0_1_IPCLKPORT_I_ACLK 2 +#define CAM_CSI0_2_IPCLKPORT_I_ACLK 3 +#define CAM_CSI0_3_IPCLKPORT_I_ACLK 4 +#define CAM_CSI1_0_IPCLKPORT_I_ACLK 5 +#define CAM_CSI1_1_IPCLKPORT_I_ACLK 6 +#define CAM_CSI1_2_IPCLKPORT_I_ACLK 7 +#define CAM_CSI1_3_IPCLKPORT_I_ACLK 8 +#define CAM_CSI2_0_IPCLKPORT_I_ACLK 9 +#define CAM_CSI2_1_IPCLKPORT_I_ACLK 10 +#define CAM_CSI2_2_IPCLKPORT_I_ACLK 11 +#define CAM_CSI2_3_IPCLKPORT_I_ACLK 12 +#define CAM_CSI_NR_CLK 13 + +#endif /*_DT_BINDINGS_CLOCK_FSD_H */ diff --git a/include/dt-bindings/clock/fsl,qoriq-clockgen.h b/include/dt-bindings/clock/fsl,qoriq-clockgen.h new file mode 100644 index 000000000000..ddec7d0bdc7f --- /dev/null +++ b/include/dt-bindings/clock/fsl,qoriq-clockgen.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef DT_CLOCK_FSL_QORIQ_CLOCKGEN_H +#define DT_CLOCK_FSL_QORIQ_CLOCKGEN_H + +#define QORIQ_CLK_SYSCLK 0 +#define QORIQ_CLK_CMUX 1 +#define QORIQ_CLK_HWACCEL 2 +#define QORIQ_CLK_FMAN 3 +#define QORIQ_CLK_PLATFORM_PLL 4 +#define QORIQ_CLK_CORECLK 5 + +#define QORIQ_CLK_PLL_DIV(x) ((x) - 1) + +#endif /* DT_CLOCK_FSL_QORIQ_CLOCKGEN_H */ diff --git a/include/dt-bindings/clock/g12a-clkc.h b/include/dt-bindings/clock/g12a-clkc.h index 0837c1a7ae49..a93b58c5e18e 100644 --- a/include/dt-bindings/clock/g12a-clkc.h +++ b/include/dt-bindings/clock/g12a-clkc.h @@ -143,5 +143,11 @@ #define CLKID_CPU1_CLK 253 #define CLKID_CPU2_CLK 254 #define CLKID_CPU3_CLK 255 +#define CLKID_SPICC0_SCLK 258 +#define CLKID_SPICC1_SCLK 261 +#define CLKID_NNA_AXI_CLK 264 +#define CLKID_NNA_CORE_CLK 267 +#define CLKID_MIPI_DSI_PXCLK_SEL 269 +#define CLKID_MIPI_DSI_PXCLK 270 #endif /* __G12A_CLKC_H */ diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h index db0763e96173..4073eb7a9da1 100644 --- a/include/dt-bindings/clock/gxbb-clkc.h +++ b/include/dt-bindings/clock/gxbb-clkc.h @@ -146,5 +146,6 @@ #define CLKID_CTS_VDAC 201 #define CLKID_HDMI_TX 202 #define CLKID_HDMI 205 +#define CLKID_ACODEC 206 #endif /* __GXBB_CLKC_H */ diff --git a/include/dt-bindings/clock/hi3559av100-clock.h b/include/dt-bindings/clock/hi3559av100-clock.h new file mode 100644 index 000000000000..5fe7689010a0 --- /dev/null +++ b/include/dt-bindings/clock/hi3559av100-clock.h @@ -0,0 +1,165 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later or BSD-2-Clause */ +/* + * Copyright (c) 2019-2020, Huawei Tech. Co., Ltd. + * + * Author: Dongjiu Geng <gengdongjiu@huawei.com> + */ + +#ifndef __DTS_HI3559AV100_CLOCK_H +#define __DTS_HI3559AV100_CLOCK_H + +/* fixed rate */ +#define HI3559AV100_FIXED_1188M 1 +#define HI3559AV100_FIXED_1000M 2 +#define HI3559AV100_FIXED_842M 3 +#define HI3559AV100_FIXED_792M 4 +#define HI3559AV100_FIXED_750M 5 +#define HI3559AV100_FIXED_710M 6 +#define HI3559AV100_FIXED_680M 7 +#define HI3559AV100_FIXED_667M 8 +#define HI3559AV100_FIXED_631M 9 +#define HI3559AV100_FIXED_600M 10 +#define HI3559AV100_FIXED_568M 11 +#define HI3559AV100_FIXED_500M 12 +#define HI3559AV100_FIXED_475M 13 +#define HI3559AV100_FIXED_428M 14 +#define HI3559AV100_FIXED_400M 15 +#define HI3559AV100_FIXED_396M 16 +#define HI3559AV100_FIXED_300M 17 +#define HI3559AV100_FIXED_250M 18 +#define HI3559AV100_FIXED_198M 19 +#define HI3559AV100_FIXED_187p5M 20 +#define HI3559AV100_FIXED_150M 21 +#define HI3559AV100_FIXED_148p5M 22 +#define HI3559AV100_FIXED_125M 23 +#define HI3559AV100_FIXED_107M 24 +#define HI3559AV100_FIXED_100M 25 +#define HI3559AV100_FIXED_99M 26 +#define HI3559AV100_FIXED_74p25M 27 +#define HI3559AV100_FIXED_72M 28 +#define HI3559AV100_FIXED_60M 29 +#define HI3559AV100_FIXED_54M 30 +#define HI3559AV100_FIXED_50M 31 +#define HI3559AV100_FIXED_49p5M 32 +#define HI3559AV100_FIXED_37p125M 33 +#define HI3559AV100_FIXED_36M 34 +#define HI3559AV100_FIXED_32p4M 35 +#define HI3559AV100_FIXED_27M 36 +#define HI3559AV100_FIXED_25M 37 +#define HI3559AV100_FIXED_24M 38 +#define HI3559AV100_FIXED_12M 39 +#define HI3559AV100_FIXED_3M 40 +#define HI3559AV100_FIXED_1p6M 41 +#define HI3559AV100_FIXED_400K 42 +#define HI3559AV100_FIXED_100K 43 +#define HI3559AV100_FIXED_200M 44 +#define HI3559AV100_FIXED_75M 75 + +#define HI3559AV100_I2C0_CLK 50 +#define HI3559AV100_I2C1_CLK 51 +#define HI3559AV100_I2C2_CLK 52 +#define HI3559AV100_I2C3_CLK 53 +#define HI3559AV100_I2C4_CLK 54 +#define HI3559AV100_I2C5_CLK 55 +#define HI3559AV100_I2C6_CLK 56 +#define HI3559AV100_I2C7_CLK 57 +#define HI3559AV100_I2C8_CLK 58 +#define HI3559AV100_I2C9_CLK 59 +#define HI3559AV100_I2C10_CLK 60 +#define HI3559AV100_I2C11_CLK 61 + +#define HI3559AV100_SPI0_CLK 62 +#define HI3559AV100_SPI1_CLK 63 +#define HI3559AV100_SPI2_CLK 64 +#define HI3559AV100_SPI3_CLK 65 +#define HI3559AV100_SPI4_CLK 66 +#define HI3559AV100_SPI5_CLK 67 +#define HI3559AV100_SPI6_CLK 68 + +#define HI3559AV100_EDMAC_CLK 69 +#define HI3559AV100_EDMAC_AXICLK 70 +#define HI3559AV100_EDMAC1_CLK 71 +#define HI3559AV100_EDMAC1_AXICLK 72 +#define HI3559AV100_VDMAC_CLK 73 + +/* mux clocks */ +#define HI3559AV100_FMC_MUX 80 +#define HI3559AV100_SYSAPB_MUX 81 +#define HI3559AV100_UART_MUX 82 +#define HI3559AV100_SYSBUS_MUX 83 +#define HI3559AV100_A73_MUX 84 +#define HI3559AV100_MMC0_MUX 85 +#define HI3559AV100_MMC1_MUX 86 +#define HI3559AV100_MMC2_MUX 87 +#define HI3559AV100_MMC3_MUX 88 + +/* gate clocks */ +#define HI3559AV100_FMC_CLK 90 +#define HI3559AV100_UART0_CLK 91 +#define HI3559AV100_UART1_CLK 92 +#define HI3559AV100_UART2_CLK 93 +#define HI3559AV100_UART3_CLK 94 +#define HI3559AV100_UART4_CLK 95 +#define HI3559AV100_MMC0_CLK 96 +#define HI3559AV100_MMC1_CLK 97 +#define HI3559AV100_MMC2_CLK 98 +#define HI3559AV100_MMC3_CLK 99 + +#define HI3559AV100_ETH_CLK 100 +#define HI3559AV100_ETH_MACIF_CLK 101 +#define HI3559AV100_ETH1_CLK 102 +#define HI3559AV100_ETH1_MACIF_CLK 103 + +/* complex */ +#define HI3559AV100_MAC0_CLK 110 +#define HI3559AV100_MAC1_CLK 111 +#define HI3559AV100_SATA_CLK 112 +#define HI3559AV100_USB_CLK 113 +#define HI3559AV100_USB1_CLK 114 + +/* pll clocks */ +#define HI3559AV100_APLL_CLK 250 +#define HI3559AV100_GPLL_CLK 251 + +#define HI3559AV100_CRG_NR_CLKS 256 + +#define HI3559AV100_SHUB_SOURCE_SOC_24M 0 +#define HI3559AV100_SHUB_SOURCE_SOC_200M 1 +#define HI3559AV100_SHUB_SOURCE_SOC_300M 2 +#define HI3559AV100_SHUB_SOURCE_PLL 3 +#define HI3559AV100_SHUB_SOURCE_CLK 4 + +#define HI3559AV100_SHUB_I2C0_CLK 10 +#define HI3559AV100_SHUB_I2C1_CLK 11 +#define HI3559AV100_SHUB_I2C2_CLK 12 +#define HI3559AV100_SHUB_I2C3_CLK 13 +#define HI3559AV100_SHUB_I2C4_CLK 14 +#define HI3559AV100_SHUB_I2C5_CLK 15 +#define HI3559AV100_SHUB_I2C6_CLK 16 +#define HI3559AV100_SHUB_I2C7_CLK 17 + +#define HI3559AV100_SHUB_SPI_SOURCE_CLK 20 +#define HI3559AV100_SHUB_SPI4_SOURCE_CLK 21 +#define HI3559AV100_SHUB_SPI0_CLK 22 +#define HI3559AV100_SHUB_SPI1_CLK 23 +#define HI3559AV100_SHUB_SPI2_CLK 24 +#define HI3559AV100_SHUB_SPI3_CLK 25 +#define HI3559AV100_SHUB_SPI4_CLK 26 + +#define HI3559AV100_SHUB_UART_CLK_32K 30 +#define HI3559AV100_SHUB_UART_SOURCE_CLK 31 +#define HI3559AV100_SHUB_UART_DIV_CLK 32 +#define HI3559AV100_SHUB_UART0_CLK 33 +#define HI3559AV100_SHUB_UART1_CLK 34 +#define HI3559AV100_SHUB_UART2_CLK 35 +#define HI3559AV100_SHUB_UART3_CLK 36 +#define HI3559AV100_SHUB_UART4_CLK 37 +#define HI3559AV100_SHUB_UART5_CLK 38 +#define HI3559AV100_SHUB_UART6_CLK 39 + +#define HI3559AV100_SHUB_EDMAC_CLK 40 + +#define HI3559AV100_SHUB_NR_CLKS 50 + +#endif /* __DTS_HI3559AV100_CLOCK_H */ + diff --git a/include/dt-bindings/clock/imx7d-clock.h b/include/dt-bindings/clock/imx7d-clock.h index e6a670e1a3f8..1d4c0dfe0202 100644 --- a/include/dt-bindings/clock/imx7d-clock.h +++ b/include/dt-bindings/clock/imx7d-clock.h @@ -451,5 +451,6 @@ #define IMX7D_SNVS_CLK 442 #define IMX7D_CAAM_CLK 443 #define IMX7D_KPP_ROOT_CLK 444 -#define IMX7D_CLK_END 445 +#define IMX7D_PXP_CLK 445 +#define IMX7D_CLK_END 446 #endif /* __DT_BINDINGS_CLOCK_IMX7D_H */ diff --git a/include/dt-bindings/clock/imx7ulp-clock.h b/include/dt-bindings/clock/imx7ulp-clock.h index 38145bdcd975..b58370d146e2 100644 --- a/include/dt-bindings/clock/imx7ulp-clock.h +++ b/include/dt-bindings/clock/imx7ulp-clock.h @@ -58,7 +58,10 @@ #define IMX7ULP_CLK_HSRUN_SYS_SEL 44 #define IMX7ULP_CLK_HSRUN_CORE_DIV 45 -#define IMX7ULP_CLK_SCG1_END 46 +#define IMX7ULP_CLK_CORE 46 +#define IMX7ULP_CLK_HSRUN_CORE 47 + +#define IMX7ULP_CLK_SCG1_END 48 /* PCC2 */ #define IMX7ULP_CLK_DMA1 0 diff --git a/include/dt-bindings/clock/imx8-clock.h b/include/dt-bindings/clock/imx8-clock.h index 673a8c662340..2e60ce4d2622 100644 --- a/include/dt-bindings/clock/imx8-clock.h +++ b/include/dt-bindings/clock/imx8-clock.h @@ -7,132 +7,6 @@ #ifndef __DT_BINDINGS_CLOCK_IMX_H #define __DT_BINDINGS_CLOCK_IMX_H -/* SCU Clocks */ - -#define IMX_CLK_DUMMY 0 - -/* CPU */ -#define IMX_A35_CLK 1 - -/* LSIO SS */ -#define IMX_LSIO_MEM_CLK 2 -#define IMX_LSIO_BUS_CLK 3 -#define IMX_LSIO_PWM0_CLK 10 -#define IMX_LSIO_PWM1_CLK 11 -#define IMX_LSIO_PWM2_CLK 12 -#define IMX_LSIO_PWM3_CLK 13 -#define IMX_LSIO_PWM4_CLK 14 -#define IMX_LSIO_PWM5_CLK 15 -#define IMX_LSIO_PWM6_CLK 16 -#define IMX_LSIO_PWM7_CLK 17 -#define IMX_LSIO_GPT0_CLK 18 -#define IMX_LSIO_GPT1_CLK 19 -#define IMX_LSIO_GPT2_CLK 20 -#define IMX_LSIO_GPT3_CLK 21 -#define IMX_LSIO_GPT4_CLK 22 -#define IMX_LSIO_FSPI0_CLK 23 -#define IMX_LSIO_FSPI1_CLK 24 - -/* Connectivity SS */ -#define IMX_CONN_AXI_CLK_ROOT 30 -#define IMX_CONN_AHB_CLK_ROOT 31 -#define IMX_CONN_IPG_CLK_ROOT 32 -#define IMX_CONN_SDHC0_CLK 40 -#define IMX_CONN_SDHC1_CLK 41 -#define IMX_CONN_SDHC2_CLK 42 -#define IMX_CONN_ENET0_ROOT_CLK 43 -#define IMX_CONN_ENET0_BYPASS_CLK 44 -#define IMX_CONN_ENET0_RGMII_CLK 45 -#define IMX_CONN_ENET1_ROOT_CLK 46 -#define IMX_CONN_ENET1_BYPASS_CLK 47 -#define IMX_CONN_ENET1_RGMII_CLK 48 -#define IMX_CONN_GPMI_BCH_IO_CLK 49 -#define IMX_CONN_GPMI_BCH_CLK 50 -#define IMX_CONN_USB2_ACLK 51 -#define IMX_CONN_USB2_BUS_CLK 52 -#define IMX_CONN_USB2_LPM_CLK 53 - -/* HSIO SS */ -#define IMX_HSIO_AXI_CLK 60 -#define IMX_HSIO_PER_CLK 61 - -/* Display controller SS */ -#define IMX_DC_AXI_EXT_CLK 70 -#define IMX_DC_AXI_INT_CLK 71 -#define IMX_DC_CFG_CLK 72 -#define IMX_DC0_PLL0_CLK 80 -#define IMX_DC0_PLL1_CLK 81 -#define IMX_DC0_DISP0_CLK 82 -#define IMX_DC0_DISP1_CLK 83 - -/* MIPI-LVDS SS */ -#define IMX_MIPI_IPG_CLK 90 -#define IMX_MIPI0_PIXEL_CLK 100 -#define IMX_MIPI0_BYPASS_CLK 101 -#define IMX_MIPI0_LVDS_PIXEL_CLK 102 -#define IMX_MIPI0_LVDS_BYPASS_CLK 103 -#define IMX_MIPI0_LVDS_PHY_CLK 104 -#define IMX_MIPI0_I2C0_CLK 105 -#define IMX_MIPI0_I2C1_CLK 106 -#define IMX_MIPI0_PWM0_CLK 107 -#define IMX_MIPI1_PIXEL_CLK 108 -#define IMX_MIPI1_BYPASS_CLK 109 -#define IMX_MIPI1_LVDS_PIXEL_CLK 110 -#define IMX_MIPI1_LVDS_BYPASS_CLK 111 -#define IMX_MIPI1_LVDS_PHY_CLK 112 -#define IMX_MIPI1_I2C0_CLK 113 -#define IMX_MIPI1_I2C1_CLK 114 -#define IMX_MIPI1_PWM0_CLK 115 - -/* IMG SS */ -#define IMX_IMG_AXI_CLK 120 -#define IMX_IMG_IPG_CLK 121 -#define IMX_IMG_PXL_CLK 122 - -/* MIPI-CSI SS */ -#define IMX_CSI0_CORE_CLK 130 -#define IMX_CSI0_ESC_CLK 131 -#define IMX_CSI0_PWM0_CLK 132 -#define IMX_CSI0_I2C0_CLK 133 - -/* PARALLER CSI SS */ -#define IMX_PARALLEL_CSI_DPLL_CLK 140 -#define IMX_PARALLEL_CSI_PIXEL_CLK 141 -#define IMX_PARALLEL_CSI_MCLK_CLK 142 - -/* VPU SS */ -#define IMX_VPU_ENC_CLK 150 -#define IMX_VPU_DEC_CLK 151 - -/* GPU SS */ -#define IMX_GPU0_CORE_CLK 160 -#define IMX_GPU0_SHADER_CLK 161 - -/* ADMA SS */ -#define IMX_ADMA_IPG_CLK_ROOT 165 -#define IMX_ADMA_UART0_CLK 170 -#define IMX_ADMA_UART1_CLK 171 -#define IMX_ADMA_UART2_CLK 172 -#define IMX_ADMA_UART3_CLK 173 -#define IMX_ADMA_SPI0_CLK 174 -#define IMX_ADMA_SPI1_CLK 175 -#define IMX_ADMA_SPI2_CLK 176 -#define IMX_ADMA_SPI3_CLK 177 -#define IMX_ADMA_CAN0_CLK 178 -#define IMX_ADMA_CAN1_CLK 179 -#define IMX_ADMA_CAN2_CLK 180 -#define IMX_ADMA_I2C0_CLK 181 -#define IMX_ADMA_I2C1_CLK 182 -#define IMX_ADMA_I2C2_CLK 183 -#define IMX_ADMA_I2C3_CLK 184 -#define IMX_ADMA_FTM0_CLK 185 -#define IMX_ADMA_FTM1_CLK 186 -#define IMX_ADMA_ADC0_CLK 187 -#define IMX_ADMA_PWM_CLK 188 -#define IMX_ADMA_LCD_CLK 189 - -#define IMX_SCU_CLK_END 190 - /* LPCG clocks */ /* LSIO SS LPCG */ diff --git a/include/dt-bindings/clock/imx8-lpcg.h b/include/dt-bindings/clock/imx8-lpcg.h new file mode 100644 index 000000000000..d202715652c3 --- /dev/null +++ b/include/dt-bindings/clock/imx8-lpcg.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019-2020 NXP + * Dong Aisheng <aisheng.dong@nxp.com> + */ + +#define IMX_LPCG_CLK_0 0 +#define IMX_LPCG_CLK_1 4 +#define IMX_LPCG_CLK_2 8 +#define IMX_LPCG_CLK_3 12 +#define IMX_LPCG_CLK_4 16 +#define IMX_LPCG_CLK_5 20 +#define IMX_LPCG_CLK_6 24 +#define IMX_LPCG_CLK_7 28 diff --git a/include/dt-bindings/clock/imx8mm-clock.h b/include/dt-bindings/clock/imx8mm-clock.h index edeece2289f0..1f768b2eeb1a 100644 --- a/include/dt-bindings/clock/imx8mm-clock.h +++ b/include/dt-bindings/clock/imx8mm-clock.h @@ -265,6 +265,22 @@ #define IMX8MM_SYS_PLL2_333M_CG 244 #define IMX8MM_SYS_PLL2_500M_CG 245 -#define IMX8MM_CLK_END 246 +#define IMX8MM_CLK_M4_CORE 246 +#define IMX8MM_CLK_VPU_CORE 247 +#define IMX8MM_CLK_GPU3D_CORE 248 +#define IMX8MM_CLK_GPU2D_CORE 249 + +#define IMX8MM_CLK_CLKO2 250 + +#define IMX8MM_CLK_A53_CORE 251 + +#define IMX8MM_CLK_CLKOUT1_SEL 252 +#define IMX8MM_CLK_CLKOUT1_DIV 253 +#define IMX8MM_CLK_CLKOUT1 254 +#define IMX8MM_CLK_CLKOUT2_SEL 255 +#define IMX8MM_CLK_CLKOUT2_DIV 256 +#define IMX8MM_CLK_CLKOUT2 257 + +#define IMX8MM_CLK_END 258 #endif diff --git a/include/dt-bindings/clock/imx8mn-clock.h b/include/dt-bindings/clock/imx8mn-clock.h index 65ac6eb6c733..07b8a282c268 100644 --- a/include/dt-bindings/clock/imx8mn-clock.h +++ b/include/dt-bindings/clock/imx8mn-clock.h @@ -228,6 +228,35 @@ #define IMX8MN_SYS_PLL2_333M_CG 209 #define IMX8MN_SYS_PLL2_500M_CG 210 -#define IMX8MN_CLK_END 211 +#define IMX8MN_CLK_SNVS_ROOT 211 +#define IMX8MN_CLK_GPU_CORE 212 +#define IMX8MN_CLK_GPU_SHADER 213 + +#define IMX8MN_CLK_A53_CORE 214 + +#define IMX8MN_CLK_CLKOUT1_SEL 215 +#define IMX8MN_CLK_CLKOUT1_DIV 216 +#define IMX8MN_CLK_CLKOUT1 217 +#define IMX8MN_CLK_CLKOUT2_SEL 218 +#define IMX8MN_CLK_CLKOUT2_DIV 219 +#define IMX8MN_CLK_CLKOUT2 220 + +#define IMX8MN_CLK_M7_CORE 221 + +#define IMX8MN_CLK_GPT_3M 222 +#define IMX8MN_CLK_GPT1 223 +#define IMX8MN_CLK_GPT1_ROOT 224 +#define IMX8MN_CLK_GPT2 225 +#define IMX8MN_CLK_GPT2_ROOT 226 +#define IMX8MN_CLK_GPT3 227 +#define IMX8MN_CLK_GPT3_ROOT 228 +#define IMX8MN_CLK_GPT4 229 +#define IMX8MN_CLK_GPT4_ROOT 230 +#define IMX8MN_CLK_GPT5 231 +#define IMX8MN_CLK_GPT5_ROOT 232 +#define IMX8MN_CLK_GPT6 233 +#define IMX8MN_CLK_GPT6_ROOT 234 + +#define IMX8MN_CLK_END 235 #endif diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h index 2fab63186bca..9d5cc2ddde89 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -117,7 +117,6 @@ #define IMX8MP_CLK_AUDIO_AHB 108 #define IMX8MP_CLK_MIPI_DSI_ESC_RX 109 #define IMX8MP_CLK_IPG_ROOT 110 -#define IMX8MP_CLK_IPG_AUDIO_ROOT 111 #define IMX8MP_CLK_DRAM_ALT 112 #define IMX8MP_CLK_DRAM_APB 113 #define IMX8MP_CLK_VPU_G1 114 @@ -125,7 +124,6 @@ #define IMX8MP_CLK_CAN1 116 #define IMX8MP_CLK_CAN2 117 #define IMX8MP_CLK_MEMREPAIR 118 -#define IMX8MP_CLK_PCIE_PHY 119 #define IMX8MP_CLK_PCIE_AUX 120 #define IMX8MP_CLK_I2C5 121 #define IMX8MP_CLK_I2C6 122 @@ -173,17 +171,15 @@ #define IMX8MP_CLK_IPP_DO_CLKO1 164 #define IMX8MP_CLK_IPP_DO_CLKO2 165 #define IMX8MP_CLK_HDMI_FDCC_TST 166 -#define IMX8MP_CLK_HDMI_27M 167 +#define IMX8MP_CLK_HDMI_24M 167 #define IMX8MP_CLK_HDMI_REF_266M 168 #define IMX8MP_CLK_USDHC3 169 #define IMX8MP_CLK_MEDIA_CAM1_PIX 170 #define IMX8MP_CLK_MEDIA_MIPI_PHY1_REF 171 #define IMX8MP_CLK_MEDIA_DISP1_PIX 172 #define IMX8MP_CLK_MEDIA_CAM2_PIX 173 -#define IMX8MP_CLK_MEDIA_MIPI_PHY2_REF 174 +#define IMX8MP_CLK_MEDIA_LDB 174 #define IMX8MP_CLK_MEDIA_MIPI_CSI2_ESC 175 -#define IMX8MP_CLK_PCIE2_CTRL 176 -#define IMX8MP_CLK_PCIE2_PHY 177 #define IMX8MP_CLK_MEDIA_MIPI_TEST_BYTE 178 #define IMX8MP_CLK_ECSPI3 179 #define IMX8MP_CLK_PDM 180 @@ -294,7 +290,103 @@ #define IMX8MP_CLK_DRAM_ALT_ROOT 285 #define IMX8MP_CLK_DRAM_CORE 286 #define IMX8MP_CLK_ARM 287 +#define IMX8MP_CLK_A53_CORE 288 -#define IMX8MP_CLK_END 288 +#define IMX8MP_SYS_PLL1_40M_CG 289 +#define IMX8MP_SYS_PLL1_80M_CG 290 +#define IMX8MP_SYS_PLL1_100M_CG 291 +#define IMX8MP_SYS_PLL1_133M_CG 292 +#define IMX8MP_SYS_PLL1_160M_CG 293 +#define IMX8MP_SYS_PLL1_200M_CG 294 +#define IMX8MP_SYS_PLL1_266M_CG 295 +#define IMX8MP_SYS_PLL1_400M_CG 296 +#define IMX8MP_SYS_PLL2_50M_CG 297 +#define IMX8MP_SYS_PLL2_100M_CG 298 +#define IMX8MP_SYS_PLL2_125M_CG 299 +#define IMX8MP_SYS_PLL2_166M_CG 300 +#define IMX8MP_SYS_PLL2_200M_CG 301 +#define IMX8MP_SYS_PLL2_250M_CG 302 +#define IMX8MP_SYS_PLL2_333M_CG 303 +#define IMX8MP_SYS_PLL2_500M_CG 304 + +#define IMX8MP_CLK_M7_CORE 305 +#define IMX8MP_CLK_ML_CORE 306 +#define IMX8MP_CLK_GPU3D_CORE 307 +#define IMX8MP_CLK_GPU3D_SHADER_CORE 308 +#define IMX8MP_CLK_GPU2D_CORE 309 +#define IMX8MP_CLK_AUDIO_AXI 310 +#define IMX8MP_CLK_HSIO_AXI 311 +#define IMX8MP_CLK_MEDIA_ISP 312 +#define IMX8MP_CLK_MEDIA_DISP2_PIX 313 +#define IMX8MP_CLK_CLKOUT1_SEL 314 +#define IMX8MP_CLK_CLKOUT1_DIV 315 +#define IMX8MP_CLK_CLKOUT1 316 +#define IMX8MP_CLK_CLKOUT2_SEL 317 +#define IMX8MP_CLK_CLKOUT2_DIV 318 +#define IMX8MP_CLK_CLKOUT2 319 + +#define IMX8MP_CLK_END 320 + +#define IMX8MP_CLK_AUDIOMIX_SAI1_IPG 0 +#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1 1 +#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2 2 +#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK3 3 +#define IMX8MP_CLK_AUDIOMIX_SAI2_IPG 4 +#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1 5 +#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2 6 +#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK3 7 +#define IMX8MP_CLK_AUDIOMIX_SAI3_IPG 8 +#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1 9 +#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2 10 +#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK3 11 +#define IMX8MP_CLK_AUDIOMIX_SAI5_IPG 12 +#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1 13 +#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2 14 +#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK3 15 +#define IMX8MP_CLK_AUDIOMIX_SAI6_IPG 16 +#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1 17 +#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2 18 +#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK3 19 +#define IMX8MP_CLK_AUDIOMIX_SAI7_IPG 20 +#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1 21 +#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2 22 +#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK3 23 +#define IMX8MP_CLK_AUDIOMIX_ASRC_IPG 24 +#define IMX8MP_CLK_AUDIOMIX_PDM_IPG 25 +#define IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT 26 +#define IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT 27 +#define IMX8MP_CLK_AUDIOMIX_SPBA2_ROOT 28 +#define IMX8MP_CLK_AUDIOMIX_DSP_ROOT 29 +#define IMX8MP_CLK_AUDIOMIX_DSPDBG_ROOT 30 +#define IMX8MP_CLK_AUDIOMIX_EARC_IPG 31 +#define IMX8MP_CLK_AUDIOMIX_OCRAMA_IPG 32 +#define IMX8MP_CLK_AUDIOMIX_AUD2HTX_IPG 33 +#define IMX8MP_CLK_AUDIOMIX_EDMA_ROOT 34 +#define IMX8MP_CLK_AUDIOMIX_AUDPLL_ROOT 35 +#define IMX8MP_CLK_AUDIOMIX_MU2_ROOT 36 +#define IMX8MP_CLK_AUDIOMIX_MU3_ROOT 37 +#define IMX8MP_CLK_AUDIOMIX_EARC_PHY 38 +#define IMX8MP_CLK_AUDIOMIX_PDM_ROOT 39 +#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1_SEL 40 +#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2_SEL 41 +#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1_SEL 42 +#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2_SEL 43 +#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1_SEL 44 +#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2_SEL 45 +#define IMX8MP_CLK_AUDIOMIX_SAI4_MCLK1_SEL 46 +#define IMX8MP_CLK_AUDIOMIX_SAI4_MCLK2_SEL 47 +#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1_SEL 48 +#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2_SEL 49 +#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1_SEL 50 +#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2_SEL 51 +#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1_SEL 52 +#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2_SEL 53 +#define IMX8MP_CLK_AUDIOMIX_PDM_SEL 54 +#define IMX8MP_CLK_AUDIOMIX_SAI_PLL_REF_SEL 55 +#define IMX8MP_CLK_AUDIOMIX_SAI_PLL 56 +#define IMX8MP_CLK_AUDIOMIX_SAI_PLL_BYPASS 57 +#define IMX8MP_CLK_AUDIOMIX_SAI_PLL_OUT 58 + +#define IMX8MP_CLK_AUDIOMIX_END 59 #endif diff --git a/include/dt-bindings/clock/imx8mq-clock.h b/include/dt-bindings/clock/imx8mq-clock.h index 3bab9b21c8d7..afa74d7ba100 100644 --- a/include/dt-bindings/clock/imx8mq-clock.h +++ b/include/dt-bindings/clock/imx8mq-clock.h @@ -405,25 +405,27 @@ #define IMX8MQ_VIDEO2_PLL1_REF_SEL 266 -#define IMX8MQ_SYS1_PLL_40M_CG 267 -#define IMX8MQ_SYS1_PLL_80M_CG 268 -#define IMX8MQ_SYS1_PLL_100M_CG 269 -#define IMX8MQ_SYS1_PLL_133M_CG 270 -#define IMX8MQ_SYS1_PLL_160M_CG 271 -#define IMX8MQ_SYS1_PLL_200M_CG 272 -#define IMX8MQ_SYS1_PLL_266M_CG 273 -#define IMX8MQ_SYS1_PLL_400M_CG 274 -#define IMX8MQ_SYS1_PLL_800M_CG 275 -#define IMX8MQ_SYS2_PLL_50M_CG 276 -#define IMX8MQ_SYS2_PLL_100M_CG 277 -#define IMX8MQ_SYS2_PLL_125M_CG 278 -#define IMX8MQ_SYS2_PLL_166M_CG 279 -#define IMX8MQ_SYS2_PLL_200M_CG 280 -#define IMX8MQ_SYS2_PLL_250M_CG 281 -#define IMX8MQ_SYS2_PLL_333M_CG 282 -#define IMX8MQ_SYS2_PLL_500M_CG 283 -#define IMX8MQ_SYS2_PLL_1000M_CG 284 - -#define IMX8MQ_CLK_END 285 +#define IMX8MQ_CLK_GPU_CORE 285 +#define IMX8MQ_CLK_GPU_SHADER 286 +#define IMX8MQ_CLK_M4_CORE 287 +#define IMX8MQ_CLK_VPU_CORE 288 + +#define IMX8MQ_CLK_A53_CORE 289 + +#define IMX8MQ_CLK_MON_AUDIO_PLL1_DIV 290 +#define IMX8MQ_CLK_MON_AUDIO_PLL2_DIV 291 +#define IMX8MQ_CLK_MON_VIDEO_PLL1_DIV 292 +#define IMX8MQ_CLK_MON_GPU_PLL_DIV 293 +#define IMX8MQ_CLK_MON_VPU_PLL_DIV 294 +#define IMX8MQ_CLK_MON_ARM_PLL_DIV 295 +#define IMX8MQ_CLK_MON_SYS_PLL1_DIV 296 +#define IMX8MQ_CLK_MON_SYS_PLL2_DIV 297 +#define IMX8MQ_CLK_MON_SYS_PLL3_DIV 298 +#define IMX8MQ_CLK_MON_DRAM_PLL_DIV 299 +#define IMX8MQ_CLK_MON_VIDEO_PLL2_DIV 300 +#define IMX8MQ_CLK_MON_SEL 301 +#define IMX8MQ_CLK_MON_CLK2_OUT 302 + +#define IMX8MQ_CLK_END 303 #endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */ diff --git a/include/dt-bindings/clock/imx8ulp-clock.h b/include/dt-bindings/clock/imx8ulp-clock.h new file mode 100644 index 000000000000..953ecfe8ebcc --- /dev/null +++ b/include/dt-bindings/clock/imx8ulp-clock.h @@ -0,0 +1,258 @@ +/* SPDX-License-Identifier: GPL-2.0+ OR MIT */ +/* + * Copyright 2021 NXP + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX8ULP_H +#define __DT_BINDINGS_CLOCK_IMX8ULP_H + +#define IMX8ULP_CLK_DUMMY 0 + +/* CGC1 */ +#define IMX8ULP_CLK_SPLL2 5 +#define IMX8ULP_CLK_SPLL3 6 +#define IMX8ULP_CLK_A35_SEL 7 +#define IMX8ULP_CLK_A35_DIV 8 +#define IMX8ULP_CLK_SPLL2_PRE_SEL 9 +#define IMX8ULP_CLK_SPLL3_PRE_SEL 10 +#define IMX8ULP_CLK_SPLL3_PFD0 11 +#define IMX8ULP_CLK_SPLL3_PFD1 12 +#define IMX8ULP_CLK_SPLL3_PFD2 13 +#define IMX8ULP_CLK_SPLL3_PFD3 14 +#define IMX8ULP_CLK_SPLL3_PFD0_DIV1 15 +#define IMX8ULP_CLK_SPLL3_PFD0_DIV2 16 +#define IMX8ULP_CLK_SPLL3_PFD1_DIV1 17 +#define IMX8ULP_CLK_SPLL3_PFD1_DIV2 18 +#define IMX8ULP_CLK_SPLL3_PFD2_DIV1 19 +#define IMX8ULP_CLK_SPLL3_PFD2_DIV2 20 +#define IMX8ULP_CLK_SPLL3_PFD3_DIV1 21 +#define IMX8ULP_CLK_SPLL3_PFD3_DIV2 22 +#define IMX8ULP_CLK_NIC_SEL 23 +#define IMX8ULP_CLK_NIC_AD_DIVPLAT 24 +#define IMX8ULP_CLK_NIC_PER_DIVPLAT 25 +#define IMX8ULP_CLK_XBAR_SEL 26 +#define IMX8ULP_CLK_XBAR_AD_DIVPLAT 27 +#define IMX8ULP_CLK_XBAR_DIVBUS 28 +#define IMX8ULP_CLK_XBAR_AD_SLOW 29 +#define IMX8ULP_CLK_SOSC_DIV1 30 +#define IMX8ULP_CLK_SOSC_DIV2 31 +#define IMX8ULP_CLK_SOSC_DIV3 32 +#define IMX8ULP_CLK_FROSC_DIV1 33 +#define IMX8ULP_CLK_FROSC_DIV2 34 +#define IMX8ULP_CLK_FROSC_DIV3 35 +#define IMX8ULP_CLK_SPLL3_VCODIV 36 +#define IMX8ULP_CLK_SPLL3_PFD0_DIV1_GATE 37 +#define IMX8ULP_CLK_SPLL3_PFD0_DIV2_GATE 38 +#define IMX8ULP_CLK_SPLL3_PFD1_DIV1_GATE 39 +#define IMX8ULP_CLK_SPLL3_PFD1_DIV2_GATE 40 +#define IMX8ULP_CLK_SPLL3_PFD2_DIV1_GATE 41 +#define IMX8ULP_CLK_SPLL3_PFD2_DIV2_GATE 42 +#define IMX8ULP_CLK_SPLL3_PFD3_DIV1_GATE 43 +#define IMX8ULP_CLK_SPLL3_PFD3_DIV2_GATE 44 +#define IMX8ULP_CLK_SOSC_DIV1_GATE 45 +#define IMX8ULP_CLK_SOSC_DIV2_GATE 46 +#define IMX8ULP_CLK_SOSC_DIV3_GATE 47 +#define IMX8ULP_CLK_FROSC_DIV1_GATE 48 +#define IMX8ULP_CLK_FROSC_DIV2_GATE 49 +#define IMX8ULP_CLK_FROSC_DIV3_GATE 50 +#define IMX8ULP_CLK_SAI4_SEL 51 +#define IMX8ULP_CLK_SAI5_SEL 52 +#define IMX8ULP_CLK_AUD_CLK1 53 +#define IMX8ULP_CLK_ARM 54 +#define IMX8ULP_CLK_ENET_TS_SEL 55 + +#define IMX8ULP_CLK_CGC1_END 56 + +/* CGC2 */ +#define IMX8ULP_CLK_PLL4_PRE_SEL 0 +#define IMX8ULP_CLK_PLL4 1 +#define IMX8ULP_CLK_PLL4_VCODIV 2 +#define IMX8ULP_CLK_DDR_SEL 3 +#define IMX8ULP_CLK_DDR_DIV 4 +#define IMX8ULP_CLK_LPAV_AXI_SEL 5 +#define IMX8ULP_CLK_LPAV_AXI_DIV 6 +#define IMX8ULP_CLK_LPAV_AHB_DIV 7 +#define IMX8ULP_CLK_LPAV_BUS_DIV 8 +#define IMX8ULP_CLK_PLL4_PFD0 9 +#define IMX8ULP_CLK_PLL4_PFD1 10 +#define IMX8ULP_CLK_PLL4_PFD2 11 +#define IMX8ULP_CLK_PLL4_PFD3 12 +#define IMX8ULP_CLK_PLL4_PFD0_DIV1_GATE 13 +#define IMX8ULP_CLK_PLL4_PFD0_DIV2_GATE 14 +#define IMX8ULP_CLK_PLL4_PFD1_DIV1_GATE 15 +#define IMX8ULP_CLK_PLL4_PFD1_DIV2_GATE 16 +#define IMX8ULP_CLK_PLL4_PFD2_DIV1_GATE 17 +#define IMX8ULP_CLK_PLL4_PFD2_DIV2_GATE 18 +#define IMX8ULP_CLK_PLL4_PFD3_DIV1_GATE 19 +#define IMX8ULP_CLK_PLL4_PFD3_DIV2_GATE 20 +#define IMX8ULP_CLK_PLL4_PFD0_DIV1 21 +#define IMX8ULP_CLK_PLL4_PFD0_DIV2 22 +#define IMX8ULP_CLK_PLL4_PFD1_DIV1 23 +#define IMX8ULP_CLK_PLL4_PFD1_DIV2 24 +#define IMX8ULP_CLK_PLL4_PFD2_DIV1 25 +#define IMX8ULP_CLK_PLL4_PFD2_DIV2 26 +#define IMX8ULP_CLK_PLL4_PFD3_DIV1 27 +#define IMX8ULP_CLK_PLL4_PFD3_DIV2 28 +#define IMX8ULP_CLK_CGC2_SOSC_DIV1_GATE 29 +#define IMX8ULP_CLK_CGC2_SOSC_DIV2_GATE 30 +#define IMX8ULP_CLK_CGC2_SOSC_DIV3_GATE 31 +#define IMX8ULP_CLK_CGC2_SOSC_DIV1 32 +#define IMX8ULP_CLK_CGC2_SOSC_DIV2 33 +#define IMX8ULP_CLK_CGC2_SOSC_DIV3 34 +#define IMX8ULP_CLK_CGC2_FROSC_DIV1_GATE 35 +#define IMX8ULP_CLK_CGC2_FROSC_DIV2_GATE 36 +#define IMX8ULP_CLK_CGC2_FROSC_DIV3_GATE 37 +#define IMX8ULP_CLK_CGC2_FROSC_DIV1 38 +#define IMX8ULP_CLK_CGC2_FROSC_DIV2 39 +#define IMX8ULP_CLK_CGC2_FROSC_DIV3 40 +#define IMX8ULP_CLK_AUD_CLK2 41 +#define IMX8ULP_CLK_SAI6_SEL 42 +#define IMX8ULP_CLK_SAI7_SEL 43 +#define IMX8ULP_CLK_SPDIF_SEL 44 +#define IMX8ULP_CLK_HIFI_SEL 45 +#define IMX8ULP_CLK_HIFI_DIVCORE 46 +#define IMX8ULP_CLK_HIFI_DIVPLAT 47 +#define IMX8ULP_CLK_DSI_PHY_REF 48 + +#define IMX8ULP_CLK_CGC2_END 49 + +/* PCC3 */ +#define IMX8ULP_CLK_WDOG3 0 +#define IMX8ULP_CLK_WDOG4 1 +#define IMX8ULP_CLK_LPIT1 2 +#define IMX8ULP_CLK_TPM4 3 +#define IMX8ULP_CLK_TPM5 4 +#define IMX8ULP_CLK_FLEXIO1 5 +#define IMX8ULP_CLK_I3C2 6 +#define IMX8ULP_CLK_LPI2C4 7 +#define IMX8ULP_CLK_LPI2C5 8 +#define IMX8ULP_CLK_LPUART4 9 +#define IMX8ULP_CLK_LPUART5 10 +#define IMX8ULP_CLK_LPSPI4 11 +#define IMX8ULP_CLK_LPSPI5 12 +#define IMX8ULP_CLK_DMA1_MP 13 +#define IMX8ULP_CLK_DMA1_CH0 14 +#define IMX8ULP_CLK_DMA1_CH1 15 +#define IMX8ULP_CLK_DMA1_CH2 16 +#define IMX8ULP_CLK_DMA1_CH3 17 +#define IMX8ULP_CLK_DMA1_CH4 18 +#define IMX8ULP_CLK_DMA1_CH5 19 +#define IMX8ULP_CLK_DMA1_CH6 20 +#define IMX8ULP_CLK_DMA1_CH7 21 +#define IMX8ULP_CLK_DMA1_CH8 22 +#define IMX8ULP_CLK_DMA1_CH9 23 +#define IMX8ULP_CLK_DMA1_CH10 24 +#define IMX8ULP_CLK_DMA1_CH11 25 +#define IMX8ULP_CLK_DMA1_CH12 26 +#define IMX8ULP_CLK_DMA1_CH13 27 +#define IMX8ULP_CLK_DMA1_CH14 28 +#define IMX8ULP_CLK_DMA1_CH15 29 +#define IMX8ULP_CLK_DMA1_CH16 30 +#define IMX8ULP_CLK_DMA1_CH17 31 +#define IMX8ULP_CLK_DMA1_CH18 32 +#define IMX8ULP_CLK_DMA1_CH19 33 +#define IMX8ULP_CLK_DMA1_CH20 34 +#define IMX8ULP_CLK_DMA1_CH21 35 +#define IMX8ULP_CLK_DMA1_CH22 36 +#define IMX8ULP_CLK_DMA1_CH23 37 +#define IMX8ULP_CLK_DMA1_CH24 38 +#define IMX8ULP_CLK_DMA1_CH25 39 +#define IMX8ULP_CLK_DMA1_CH26 40 +#define IMX8ULP_CLK_DMA1_CH27 41 +#define IMX8ULP_CLK_DMA1_CH28 42 +#define IMX8ULP_CLK_DMA1_CH29 43 +#define IMX8ULP_CLK_DMA1_CH30 44 +#define IMX8ULP_CLK_DMA1_CH31 45 +#define IMX8ULP_CLK_MU3_A 46 +#define IMX8ULP_CLK_MU0_B 47 + +#define IMX8ULP_CLK_PCC3_END 48 + +/* PCC4 */ +#define IMX8ULP_CLK_FLEXSPI2 0 +#define IMX8ULP_CLK_TPM6 1 +#define IMX8ULP_CLK_TPM7 2 +#define IMX8ULP_CLK_LPI2C6 3 +#define IMX8ULP_CLK_LPI2C7 4 +#define IMX8ULP_CLK_LPUART6 5 +#define IMX8ULP_CLK_LPUART7 6 +#define IMX8ULP_CLK_SAI4 7 +#define IMX8ULP_CLK_SAI5 8 +#define IMX8ULP_CLK_PCTLE 9 +#define IMX8ULP_CLK_PCTLF 10 +#define IMX8ULP_CLK_USDHC0 11 +#define IMX8ULP_CLK_USDHC1 12 +#define IMX8ULP_CLK_USDHC2 13 +#define IMX8ULP_CLK_USB0 14 +#define IMX8ULP_CLK_USB0_PHY 15 +#define IMX8ULP_CLK_USB1 16 +#define IMX8ULP_CLK_USB1_PHY 17 +#define IMX8ULP_CLK_USB_XBAR 18 +#define IMX8ULP_CLK_ENET 19 +#define IMX8ULP_CLK_SFA1 20 +#define IMX8ULP_CLK_RGPIOE 21 +#define IMX8ULP_CLK_RGPIOF 22 + +#define IMX8ULP_CLK_PCC4_END 23 + +/* PCC5 */ +#define IMX8ULP_CLK_TPM8 0 +#define IMX8ULP_CLK_SAI6 1 +#define IMX8ULP_CLK_SAI7 2 +#define IMX8ULP_CLK_SPDIF 3 +#define IMX8ULP_CLK_ISI 4 +#define IMX8ULP_CLK_CSI_REGS 5 +#define IMX8ULP_CLK_PCTLD 6 +#define IMX8ULP_CLK_CSI 7 +#define IMX8ULP_CLK_DSI 8 +#define IMX8ULP_CLK_WDOG5 9 +#define IMX8ULP_CLK_EPDC 10 +#define IMX8ULP_CLK_PXP 11 +#define IMX8ULP_CLK_SFA2 12 +#define IMX8ULP_CLK_GPU2D 13 +#define IMX8ULP_CLK_GPU3D 14 +#define IMX8ULP_CLK_DC_NANO 15 +#define IMX8ULP_CLK_CSI_CLK_UI 16 +#define IMX8ULP_CLK_CSI_CLK_ESC 17 +#define IMX8ULP_CLK_RGPIOD 18 +#define IMX8ULP_CLK_DMA2_MP 19 +#define IMX8ULP_CLK_DMA2_CH0 20 +#define IMX8ULP_CLK_DMA2_CH1 21 +#define IMX8ULP_CLK_DMA2_CH2 22 +#define IMX8ULP_CLK_DMA2_CH3 23 +#define IMX8ULP_CLK_DMA2_CH4 24 +#define IMX8ULP_CLK_DMA2_CH5 25 +#define IMX8ULP_CLK_DMA2_CH6 26 +#define IMX8ULP_CLK_DMA2_CH7 27 +#define IMX8ULP_CLK_DMA2_CH8 28 +#define IMX8ULP_CLK_DMA2_CH9 29 +#define IMX8ULP_CLK_DMA2_CH10 30 +#define IMX8ULP_CLK_DMA2_CH11 31 +#define IMX8ULP_CLK_DMA2_CH12 32 +#define IMX8ULP_CLK_DMA2_CH13 33 +#define IMX8ULP_CLK_DMA2_CH14 34 +#define IMX8ULP_CLK_DMA2_CH15 35 +#define IMX8ULP_CLK_DMA2_CH16 36 +#define IMX8ULP_CLK_DMA2_CH17 37 +#define IMX8ULP_CLK_DMA2_CH18 38 +#define IMX8ULP_CLK_DMA2_CH19 39 +#define IMX8ULP_CLK_DMA2_CH20 40 +#define IMX8ULP_CLK_DMA2_CH21 41 +#define IMX8ULP_CLK_DMA2_CH22 42 +#define IMX8ULP_CLK_DMA2_CH23 43 +#define IMX8ULP_CLK_DMA2_CH24 44 +#define IMX8ULP_CLK_DMA2_CH25 45 +#define IMX8ULP_CLK_DMA2_CH26 46 +#define IMX8ULP_CLK_DMA2_CH27 47 +#define IMX8ULP_CLK_DMA2_CH28 48 +#define IMX8ULP_CLK_DMA2_CH29 49 +#define IMX8ULP_CLK_DMA2_CH30 50 +#define IMX8ULP_CLK_DMA2_CH31 51 +#define IMX8ULP_CLK_MU2_B 52 +#define IMX8ULP_CLK_MU3_B 53 +#define IMX8ULP_CLK_AVD_SIM 54 +#define IMX8ULP_CLK_DSI_TX_ESC 55 + +#define IMX8ULP_CLK_PCC5_END 56 + +#endif diff --git a/include/dt-bindings/clock/imx93-clock.h b/include/dt-bindings/clock/imx93-clock.h new file mode 100644 index 000000000000..19bc32788d81 --- /dev/null +++ b/include/dt-bindings/clock/imx93-clock.h @@ -0,0 +1,208 @@ +/* SPDX-License-Identifier: GPL-2.0+ OR MIT */ +/* + * Copyright 2022 NXP + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX93_CLK_H +#define __DT_BINDINGS_CLOCK_IMX93_CLK_H + +#define IMX93_CLK_DUMMY 0 +#define IMX93_CLK_24M 1 +#define IMX93_CLK_EXT1 2 +#define IMX93_CLK_SYS_PLL_PFD0 3 +#define IMX93_CLK_SYS_PLL_PFD0_DIV2 4 +#define IMX93_CLK_SYS_PLL_PFD1 5 +#define IMX93_CLK_SYS_PLL_PFD1_DIV2 6 +#define IMX93_CLK_SYS_PLL_PFD2 7 +#define IMX93_CLK_SYS_PLL_PFD2_DIV2 8 +#define IMX93_CLK_AUDIO_PLL 9 +#define IMX93_CLK_VIDEO_PLL 10 +#define IMX93_CLK_A55_PERIPH 11 +#define IMX93_CLK_A55_MTR_BUS 12 +#define IMX93_CLK_A55 13 +#define IMX93_CLK_M33 14 +#define IMX93_CLK_BUS_WAKEUP 15 +#define IMX93_CLK_BUS_AON 16 +#define IMX93_CLK_WAKEUP_AXI 17 +#define IMX93_CLK_SWO_TRACE 18 +#define IMX93_CLK_M33_SYSTICK 19 +#define IMX93_CLK_FLEXIO1 20 +#define IMX93_CLK_FLEXIO2 21 +#define IMX93_CLK_LPIT1 22 +#define IMX93_CLK_LPIT2 23 +#define IMX93_CLK_LPTMR1 24 +#define IMX93_CLK_LPTMR2 25 +#define IMX93_CLK_TPM1 26 +#define IMX93_CLK_TPM2 27 +#define IMX93_CLK_TPM3 28 +#define IMX93_CLK_TPM4 29 +#define IMX93_CLK_TPM5 30 +#define IMX93_CLK_TPM6 31 +#define IMX93_CLK_FLEXSPI1 32 +#define IMX93_CLK_CAN1 33 +#define IMX93_CLK_CAN2 34 +#define IMX93_CLK_LPUART1 35 +#define IMX93_CLK_LPUART2 36 +#define IMX93_CLK_LPUART3 37 +#define IMX93_CLK_LPUART4 38 +#define IMX93_CLK_LPUART5 39 +#define IMX93_CLK_LPUART6 40 +#define IMX93_CLK_LPUART7 41 +#define IMX93_CLK_LPUART8 42 +#define IMX93_CLK_LPI2C1 43 +#define IMX93_CLK_LPI2C2 44 +#define IMX93_CLK_LPI2C3 45 +#define IMX93_CLK_LPI2C4 46 +#define IMX93_CLK_LPI2C5 47 +#define IMX93_CLK_LPI2C6 48 +#define IMX93_CLK_LPI2C7 49 +#define IMX93_CLK_LPI2C8 50 +#define IMX93_CLK_LPSPI1 51 +#define IMX93_CLK_LPSPI2 52 +#define IMX93_CLK_LPSPI3 53 +#define IMX93_CLK_LPSPI4 54 +#define IMX93_CLK_LPSPI5 55 +#define IMX93_CLK_LPSPI6 56 +#define IMX93_CLK_LPSPI7 57 +#define IMX93_CLK_LPSPI8 58 +#define IMX93_CLK_I3C1 59 +#define IMX93_CLK_I3C2 60 +#define IMX93_CLK_USDHC1 61 +#define IMX93_CLK_USDHC2 62 +#define IMX93_CLK_USDHC3 63 +#define IMX93_CLK_SAI1 64 +#define IMX93_CLK_SAI2 65 +#define IMX93_CLK_SAI3 66 +#define IMX93_CLK_CCM_CKO1 67 +#define IMX93_CLK_CCM_CKO2 68 +#define IMX93_CLK_CCM_CKO3 69 +#define IMX93_CLK_CCM_CKO4 70 +#define IMX93_CLK_HSIO 71 +#define IMX93_CLK_HSIO_USB_TEST_60M 72 +#define IMX93_CLK_HSIO_ACSCAN_80M 73 +#define IMX93_CLK_HSIO_ACSCAN_480M 74 +#define IMX93_CLK_ML_APB 75 +#define IMX93_CLK_ML 76 +#define IMX93_CLK_MEDIA_AXI 77 +#define IMX93_CLK_MEDIA_APB 78 +#define IMX93_CLK_MEDIA_LDB 79 +#define IMX93_CLK_MEDIA_DISP_PIX 80 +#define IMX93_CLK_CAM_PIX 81 +#define IMX93_CLK_MIPI_TEST_BYTE 82 +#define IMX93_CLK_MIPI_PHY_CFG 83 +#define IMX93_CLK_ADC 84 +#define IMX93_CLK_PDM 85 +#define IMX93_CLK_TSTMR1 86 +#define IMX93_CLK_TSTMR2 87 +#define IMX93_CLK_MQS1 88 +#define IMX93_CLK_MQS2 89 +#define IMX93_CLK_AUDIO_XCVR 90 +#define IMX93_CLK_SPDIF 91 +#define IMX93_CLK_ENET 92 +#define IMX93_CLK_ENET_TIMER1 93 +#define IMX93_CLK_ENET_TIMER2 94 +#define IMX93_CLK_ENET_REF 95 +#define IMX93_CLK_ENET_REF_PHY 96 +#define IMX93_CLK_I3C1_SLOW 97 +#define IMX93_CLK_I3C2_SLOW 98 +#define IMX93_CLK_USB_PHY_BURUNIN 99 +#define IMX93_CLK_PAL_CAME_SCAN 100 +#define IMX93_CLK_A55_GATE 101 +#define IMX93_CLK_CM33_GATE 102 +#define IMX93_CLK_ADC1_GATE 103 +#define IMX93_CLK_WDOG1_GATE 104 +#define IMX93_CLK_WDOG2_GATE 105 +#define IMX93_CLK_WDOG3_GATE 106 +#define IMX93_CLK_WDOG4_GATE 107 +#define IMX93_CLK_WDOG5_GATE 108 +#define IMX93_CLK_SEMA1_GATE 109 +#define IMX93_CLK_SEMA2_GATE 110 +#define IMX93_CLK_MU_A_GATE 111 +#define IMX93_CLK_MU_B_GATE 112 +#define IMX93_CLK_EDMA1_GATE 113 +#define IMX93_CLK_EDMA2_GATE 114 +#define IMX93_CLK_FLEXSPI1_GATE 115 +#define IMX93_CLK_GPIO1_GATE 116 +#define IMX93_CLK_GPIO2_GATE 117 +#define IMX93_CLK_GPIO3_GATE 118 +#define IMX93_CLK_GPIO4_GATE 119 +#define IMX93_CLK_FLEXIO1_GATE 120 +#define IMX93_CLK_FLEXIO2_GATE 121 +#define IMX93_CLK_LPIT1_GATE 122 +#define IMX93_CLK_LPIT2_GATE 123 +#define IMX93_CLK_LPTMR1_GATE 124 +#define IMX93_CLK_LPTMR2_GATE 125 +#define IMX93_CLK_TPM1_GATE 126 +#define IMX93_CLK_TPM2_GATE 127 +#define IMX93_CLK_TPM3_GATE 128 +#define IMX93_CLK_TPM4_GATE 129 +#define IMX93_CLK_TPM5_GATE 130 +#define IMX93_CLK_TPM6_GATE 131 +#define IMX93_CLK_CAN1_GATE 132 +#define IMX93_CLK_CAN2_GATE 133 +#define IMX93_CLK_LPUART1_GATE 134 +#define IMX93_CLK_LPUART2_GATE 135 +#define IMX93_CLK_LPUART3_GATE 136 +#define IMX93_CLK_LPUART4_GATE 137 +#define IMX93_CLK_LPUART5_GATE 138 +#define IMX93_CLK_LPUART6_GATE 139 +#define IMX93_CLK_LPUART7_GATE 140 +#define IMX93_CLK_LPUART8_GATE 141 +#define IMX93_CLK_LPI2C1_GATE 142 +#define IMX93_CLK_LPI2C2_GATE 143 +#define IMX93_CLK_LPI2C3_GATE 144 +#define IMX93_CLK_LPI2C4_GATE 145 +#define IMX93_CLK_LPI2C5_GATE 146 +#define IMX93_CLK_LPI2C6_GATE 147 +#define IMX93_CLK_LPI2C7_GATE 148 +#define IMX93_CLK_LPI2C8_GATE 149 +#define IMX93_CLK_LPSPI1_GATE 150 +#define IMX93_CLK_LPSPI2_GATE 151 +#define IMX93_CLK_LPSPI3_GATE 152 +#define IMX93_CLK_LPSPI4_GATE 153 +#define IMX93_CLK_LPSPI5_GATE 154 +#define IMX93_CLK_LPSPI6_GATE 155 +#define IMX93_CLK_LPSPI7_GATE 156 +#define IMX93_CLK_LPSPI8_GATE 157 +#define IMX93_CLK_I3C1_GATE 158 +#define IMX93_CLK_I3C2_GATE 159 +#define IMX93_CLK_USDHC1_GATE 160 +#define IMX93_CLK_USDHC2_GATE 161 +#define IMX93_CLK_USDHC3_GATE 162 +#define IMX93_CLK_SAI1_GATE 163 +#define IMX93_CLK_SAI2_GATE 164 +#define IMX93_CLK_SAI3_GATE 165 +#define IMX93_CLK_MIPI_CSI_GATE 166 +#define IMX93_CLK_MIPI_DSI_GATE 167 +#define IMX93_CLK_LVDS_GATE 168 +#define IMX93_CLK_LCDIF_GATE 169 +#define IMX93_CLK_PXP_GATE 170 +#define IMX93_CLK_ISI_GATE 171 +#define IMX93_CLK_NIC_MEDIA_GATE 172 +#define IMX93_CLK_USB_CONTROLLER_GATE 173 +#define IMX93_CLK_USB_TEST_60M_GATE 174 +#define IMX93_CLK_HSIO_TROUT_24M_GATE 175 +#define IMX93_CLK_PDM_GATE 176 +#define IMX93_CLK_MQS1_GATE 177 +#define IMX93_CLK_MQS2_GATE 178 +#define IMX93_CLK_AUD_XCVR_GATE 179 +#define IMX93_CLK_SPDIF_GATE 180 +#define IMX93_CLK_HSIO_32K_GATE 181 +#define IMX93_CLK_ENET1_GATE 182 +#define IMX93_CLK_ENET_QOS_GATE 183 +#define IMX93_CLK_SYS_CNT_GATE 184 +#define IMX93_CLK_TSTMR1_GATE 185 +#define IMX93_CLK_TSTMR2_GATE 186 +#define IMX93_CLK_TMC_GATE 187 +#define IMX93_CLK_PMRO_GATE 188 +#define IMX93_CLK_32K 189 +#define IMX93_CLK_SAI1_IPG 190 +#define IMX93_CLK_SAI2_IPG 191 +#define IMX93_CLK_SAI3_IPG 192 +#define IMX93_CLK_MU1_A_GATE 193 +#define IMX93_CLK_MU1_B_GATE 194 +#define IMX93_CLK_MU2_A_GATE 195 +#define IMX93_CLK_MU2_B_GATE 196 +#define IMX93_CLK_END 197 + +#endif diff --git a/include/dt-bindings/clock/imxrt1050-clock.h b/include/dt-bindings/clock/imxrt1050-clock.h new file mode 100644 index 000000000000..93bef0832d16 --- /dev/null +++ b/include/dt-bindings/clock/imxrt1050-clock.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright(C) 2019 + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com> + */ + +#ifndef __DT_BINDINGS_CLOCK_IMXRT1050_H +#define __DT_BINDINGS_CLOCK_IMXRT1050_H + +#define IMXRT1050_CLK_DUMMY 0 +#define IMXRT1050_CLK_CKIL 1 +#define IMXRT1050_CLK_CKIH 2 +#define IMXRT1050_CLK_OSC 3 +#define IMXRT1050_CLK_PLL2_PFD0_352M 4 +#define IMXRT1050_CLK_PLL2_PFD1_594M 5 +#define IMXRT1050_CLK_PLL2_PFD2_396M 6 +#define IMXRT1050_CLK_PLL3_PFD0_720M 7 +#define IMXRT1050_CLK_PLL3_PFD1_664_62M 8 +#define IMXRT1050_CLK_PLL3_PFD2_508_24M 9 +#define IMXRT1050_CLK_PLL3_PFD3_454_74M 10 +#define IMXRT1050_CLK_PLL2_198M 11 +#define IMXRT1050_CLK_PLL3_120M 12 +#define IMXRT1050_CLK_PLL3_80M 13 +#define IMXRT1050_CLK_PLL3_60M 14 +#define IMXRT1050_CLK_PLL1_BYPASS 15 +#define IMXRT1050_CLK_PLL2_BYPASS 16 +#define IMXRT1050_CLK_PLL3_BYPASS 17 +#define IMXRT1050_CLK_PLL5_BYPASS 19 +#define IMXRT1050_CLK_PLL1_REF_SEL 20 +#define IMXRT1050_CLK_PLL2_REF_SEL 21 +#define IMXRT1050_CLK_PLL3_REF_SEL 22 +#define IMXRT1050_CLK_PLL5_REF_SEL 23 +#define IMXRT1050_CLK_PRE_PERIPH_SEL 24 +#define IMXRT1050_CLK_PERIPH_SEL 25 +#define IMXRT1050_CLK_SEMC_ALT_SEL 26 +#define IMXRT1050_CLK_SEMC_SEL 27 +#define IMXRT1050_CLK_USDHC1_SEL 28 +#define IMXRT1050_CLK_USDHC2_SEL 29 +#define IMXRT1050_CLK_LPUART_SEL 30 +#define IMXRT1050_CLK_LCDIF_SEL 31 +#define IMXRT1050_CLK_VIDEO_POST_DIV_SEL 32 +#define IMXRT1050_CLK_VIDEO_DIV 33 +#define IMXRT1050_CLK_ARM_PODF 34 +#define IMXRT1050_CLK_LPUART_PODF 35 +#define IMXRT1050_CLK_USDHC1_PODF 36 +#define IMXRT1050_CLK_USDHC2_PODF 37 +#define IMXRT1050_CLK_SEMC_PODF 38 +#define IMXRT1050_CLK_AHB_PODF 39 +#define IMXRT1050_CLK_LCDIF_PRED 40 +#define IMXRT1050_CLK_LCDIF_PODF 41 +#define IMXRT1050_CLK_USDHC1 42 +#define IMXRT1050_CLK_USDHC2 43 +#define IMXRT1050_CLK_LPUART1 44 +#define IMXRT1050_CLK_SEMC 45 +#define IMXRT1050_CLK_LCDIF_APB 46 +#define IMXRT1050_CLK_PLL1_ARM 47 +#define IMXRT1050_CLK_PLL2_SYS 48 +#define IMXRT1050_CLK_PLL3_USB_OTG 49 +#define IMXRT1050_CLK_PLL4_AUDIO 50 +#define IMXRT1050_CLK_PLL5_VIDEO 51 +#define IMXRT1050_CLK_PLL6_ENET 52 +#define IMXRT1050_CLK_PLL7_USB_HOST 53 +#define IMXRT1050_CLK_LCDIF_PIX 54 +#define IMXRT1050_CLK_USBOH3 55 +#define IMXRT1050_CLK_IPG_PDOF 56 +#define IMXRT1050_CLK_PER_CLK_SEL 57 +#define IMXRT1050_CLK_PER_PDOF 58 +#define IMXRT1050_CLK_DMA 59 +#define IMXRT1050_CLK_DMA_MUX 60 +#define IMXRT1050_CLK_END 61 + +#endif /* __DT_BINDINGS_CLOCK_IMXRT1050_H */ diff --git a/include/dt-bindings/clock/jz4725b-cgu.h b/include/dt-bindings/clock/ingenic,jz4725b-cgu.h index 31f1ab0fe42c..31f1ab0fe42c 100644 --- a/include/dt-bindings/clock/jz4725b-cgu.h +++ b/include/dt-bindings/clock/ingenic,jz4725b-cgu.h diff --git a/include/dt-bindings/clock/jz4740-cgu.h b/include/dt-bindings/clock/ingenic,jz4740-cgu.h index e82d77028581..e82d77028581 100644 --- a/include/dt-bindings/clock/jz4740-cgu.h +++ b/include/dt-bindings/clock/ingenic,jz4740-cgu.h diff --git a/include/dt-bindings/clock/ingenic,jz4760-cgu.h b/include/dt-bindings/clock/ingenic,jz4760-cgu.h new file mode 100644 index 000000000000..9fb04ebac6de --- /dev/null +++ b/include/dt-bindings/clock/ingenic,jz4760-cgu.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides clock numbers for the ingenic,jz4760-cgu DT binding. + */ + +#ifndef __DT_BINDINGS_CLOCK_JZ4760_CGU_H__ +#define __DT_BINDINGS_CLOCK_JZ4760_CGU_H__ + +#define JZ4760_CLK_EXT 0 +#define JZ4760_CLK_OSC32K 1 +#define JZ4760_CLK_PLL0 2 +#define JZ4760_CLK_PLL0_HALF 3 +#define JZ4760_CLK_PLL1 4 +#define JZ4760_CLK_CCLK 5 +#define JZ4760_CLK_HCLK 6 +#define JZ4760_CLK_SCLK 7 +#define JZ4760_CLK_H2CLK 8 +#define JZ4760_CLK_MCLK 9 +#define JZ4760_CLK_PCLK 10 +#define JZ4760_CLK_MMC_MUX 11 +#define JZ4760_CLK_MMC0 12 +#define JZ4760_CLK_MMC1 13 +#define JZ4760_CLK_MMC2 14 +#define JZ4760_CLK_CIM 15 +#define JZ4760_CLK_UHC 16 +#define JZ4760_CLK_GPU 17 +#define JZ4760_CLK_GPS 18 +#define JZ4760_CLK_SSI_MUX 19 +#define JZ4760_CLK_PCM 20 +#define JZ4760_CLK_I2S 21 +#define JZ4760_CLK_OTG 22 +#define JZ4760_CLK_SSI0 23 +#define JZ4760_CLK_SSI1 24 +#define JZ4760_CLK_SSI2 25 +#define JZ4760_CLK_DMA 26 +#define JZ4760_CLK_I2C0 27 +#define JZ4760_CLK_I2C1 28 +#define JZ4760_CLK_UART0 29 +#define JZ4760_CLK_UART1 30 +#define JZ4760_CLK_UART2 31 +#define JZ4760_CLK_UART3 32 +#define JZ4760_CLK_IPU 33 +#define JZ4760_CLK_ADC 34 +#define JZ4760_CLK_AIC 35 +#define JZ4760_CLK_VPU 36 +#define JZ4760_CLK_UHC_PHY 37 +#define JZ4760_CLK_OTG_PHY 38 +#define JZ4760_CLK_EXT512 39 +#define JZ4760_CLK_RTC 40 +#define JZ4760_CLK_LPCLK_DIV 41 +#define JZ4760_CLK_TVE 42 +#define JZ4760_CLK_LPCLK 43 +#define JZ4760_CLK_MDMA 44 +#define JZ4760_CLK_BDMA 45 + +#endif /* __DT_BINDINGS_CLOCK_JZ4760_CGU_H__ */ diff --git a/include/dt-bindings/clock/jz4770-cgu.h b/include/dt-bindings/clock/ingenic,jz4770-cgu.h index d68a7695a1f8..0b475e8ae321 100644 --- a/include/dt-bindings/clock/jz4770-cgu.h +++ b/include/dt-bindings/clock/ingenic,jz4770-cgu.h @@ -54,5 +54,6 @@ #define JZ4770_CLK_OTG_PHY 45 #define JZ4770_CLK_EXT512 46 #define JZ4770_CLK_RTC 47 +#define JZ4770_CLK_BDMA 48 #endif /* __DT_BINDINGS_CLOCK_JZ4770_CGU_H__ */ diff --git a/include/dt-bindings/clock/ingenic,jz4780-cgu.h b/include/dt-bindings/clock/ingenic,jz4780-cgu.h new file mode 100644 index 000000000000..85cf8eb5081b --- /dev/null +++ b/include/dt-bindings/clock/ingenic,jz4780-cgu.h @@ -0,0 +1,91 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides clock numbers for the ingenic,jz4780-cgu DT binding. + * + * They are roughly ordered as: + * - external clocks + * - PLLs + * - muxes/dividers in the order they appear in the jz4780 programmers manual + * - gates in order of their bit in the CLKGR* registers + */ + +#ifndef __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ +#define __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ + +#define JZ4780_CLK_EXCLK 0 +#define JZ4780_CLK_RTCLK 1 +#define JZ4780_CLK_APLL 2 +#define JZ4780_CLK_MPLL 3 +#define JZ4780_CLK_EPLL 4 +#define JZ4780_CLK_VPLL 5 +#define JZ4780_CLK_OTGPHY 6 +#define JZ4780_CLK_SCLKA 7 +#define JZ4780_CLK_CPUMUX 8 +#define JZ4780_CLK_CPU 9 +#define JZ4780_CLK_L2CACHE 10 +#define JZ4780_CLK_AHB0 11 +#define JZ4780_CLK_AHB2PMUX 12 +#define JZ4780_CLK_AHB2 13 +#define JZ4780_CLK_PCLK 14 +#define JZ4780_CLK_DDR 15 +#define JZ4780_CLK_VPU 16 +#define JZ4780_CLK_I2SPLL 17 +#define JZ4780_CLK_I2S 18 +#define JZ4780_CLK_LCD0PIXCLK 19 +#define JZ4780_CLK_LCD1PIXCLK 20 +#define JZ4780_CLK_MSCMUX 21 +#define JZ4780_CLK_MSC0 22 +#define JZ4780_CLK_MSC1 23 +#define JZ4780_CLK_MSC2 24 +#define JZ4780_CLK_UHC 25 +#define JZ4780_CLK_SSIPLL 26 +#define JZ4780_CLK_SSI 27 +#define JZ4780_CLK_CIMMCLK 28 +#define JZ4780_CLK_PCMPLL 29 +#define JZ4780_CLK_PCM 30 +#define JZ4780_CLK_GPU 31 +#define JZ4780_CLK_HDMI 32 +#define JZ4780_CLK_BCH 33 +#define JZ4780_CLK_NEMC 34 +#define JZ4780_CLK_OTG0 35 +#define JZ4780_CLK_SSI0 36 +#define JZ4780_CLK_SMB0 37 +#define JZ4780_CLK_SMB1 38 +#define JZ4780_CLK_SCC 39 +#define JZ4780_CLK_AIC 40 +#define JZ4780_CLK_TSSI0 41 +#define JZ4780_CLK_OWI 42 +#define JZ4780_CLK_KBC 43 +#define JZ4780_CLK_SADC 44 +#define JZ4780_CLK_UART0 45 +#define JZ4780_CLK_UART1 46 +#define JZ4780_CLK_UART2 47 +#define JZ4780_CLK_UART3 48 +#define JZ4780_CLK_SSI1 49 +#define JZ4780_CLK_SSI2 50 +#define JZ4780_CLK_PDMA 51 +#define JZ4780_CLK_GPS 52 +#define JZ4780_CLK_MAC 53 +#define JZ4780_CLK_SMB2 54 +#define JZ4780_CLK_CIM 55 +#define JZ4780_CLK_LCD 56 +#define JZ4780_CLK_TVE 57 +#define JZ4780_CLK_IPU 58 +#define JZ4780_CLK_DDR0 59 +#define JZ4780_CLK_DDR1 60 +#define JZ4780_CLK_SMB3 61 +#define JZ4780_CLK_TSSI1 62 +#define JZ4780_CLK_COMPRESS 63 +#define JZ4780_CLK_AIC1 64 +#define JZ4780_CLK_GPVLC 65 +#define JZ4780_CLK_OTG1 66 +#define JZ4780_CLK_UART4 67 +#define JZ4780_CLK_AHBMON 68 +#define JZ4780_CLK_SMB4 69 +#define JZ4780_CLK_DES 70 +#define JZ4780_CLK_X2D 71 +#define JZ4780_CLK_CORE1 72 +#define JZ4780_CLK_EXCLK_DIV512 73 +#define JZ4780_CLK_RTC 74 + +#endif /* __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ */ diff --git a/include/dt-bindings/clock/ingenic,sysost.h b/include/dt-bindings/clock/ingenic,sysost.h new file mode 100644 index 000000000000..d7aa42c08ded --- /dev/null +++ b/include/dt-bindings/clock/ingenic,sysost.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides clock numbers for the Ingenic OST DT binding. + */ + +#ifndef __DT_BINDINGS_CLOCK_INGENIC_OST_H__ +#define __DT_BINDINGS_CLOCK_INGENIC_OST_H__ + +#define OST_CLK_PERCPU_TIMER 1 +#define OST_CLK_GLOBAL_TIMER 0 +#define OST_CLK_PERCPU_TIMER0 1 +#define OST_CLK_PERCPU_TIMER1 2 +#define OST_CLK_PERCPU_TIMER2 3 +#define OST_CLK_PERCPU_TIMER3 4 + +#define OST_CLK_EVENT_TIMER 1 + +#define OST_CLK_EVENT_TIMER0 0 +#define OST_CLK_EVENT_TIMER1 1 +#define OST_CLK_EVENT_TIMER2 2 +#define OST_CLK_EVENT_TIMER3 3 +#define OST_CLK_EVENT_TIMER4 4 +#define OST_CLK_EVENT_TIMER5 5 +#define OST_CLK_EVENT_TIMER6 6 +#define OST_CLK_EVENT_TIMER7 7 +#define OST_CLK_EVENT_TIMER8 8 +#define OST_CLK_EVENT_TIMER9 9 +#define OST_CLK_EVENT_TIMER10 10 +#define OST_CLK_EVENT_TIMER11 11 +#define OST_CLK_EVENT_TIMER12 12 +#define OST_CLK_EVENT_TIMER13 13 +#define OST_CLK_EVENT_TIMER14 14 +#define OST_CLK_EVENT_TIMER15 15 + +#endif /* __DT_BINDINGS_CLOCK_INGENIC_OST_H__ */ diff --git a/include/dt-bindings/clock/ingenic,x1000-cgu.h b/include/dt-bindings/clock/ingenic,x1000-cgu.h new file mode 100644 index 000000000000..f187e0719fd3 --- /dev/null +++ b/include/dt-bindings/clock/ingenic,x1000-cgu.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides clock numbers for the ingenic,x1000-cgu DT binding. + * + * They are roughly ordered as: + * - external clocks + * - PLLs + * - muxes/dividers in the order they appear in the x1000 programmers manual + * - gates in order of their bit in the CLKGR* registers + */ + +#ifndef __DT_BINDINGS_CLOCK_X1000_CGU_H__ +#define __DT_BINDINGS_CLOCK_X1000_CGU_H__ + +#define X1000_CLK_EXCLK 0 +#define X1000_CLK_RTCLK 1 +#define X1000_CLK_APLL 2 +#define X1000_CLK_MPLL 3 +#define X1000_CLK_OTGPHY 4 +#define X1000_CLK_SCLKA 5 +#define X1000_CLK_CPUMUX 6 +#define X1000_CLK_CPU 7 +#define X1000_CLK_L2CACHE 8 +#define X1000_CLK_AHB0 9 +#define X1000_CLK_AHB2PMUX 10 +#define X1000_CLK_AHB2 11 +#define X1000_CLK_PCLK 12 +#define X1000_CLK_DDR 13 +#define X1000_CLK_MAC 14 +#define X1000_CLK_LCD 15 +#define X1000_CLK_MSCMUX 16 +#define X1000_CLK_MSC0 17 +#define X1000_CLK_MSC1 18 +#define X1000_CLK_OTG 19 +#define X1000_CLK_SSIPLL 20 +#define X1000_CLK_SSIPLL_DIV2 21 +#define X1000_CLK_SSIMUX 22 +#define X1000_CLK_EMC 23 +#define X1000_CLK_EFUSE 24 +#define X1000_CLK_SFC 25 +#define X1000_CLK_I2C0 26 +#define X1000_CLK_I2C1 27 +#define X1000_CLK_I2C2 28 +#define X1000_CLK_UART0 29 +#define X1000_CLK_UART1 30 +#define X1000_CLK_UART2 31 +#define X1000_CLK_TCU 32 +#define X1000_CLK_SSI 33 +#define X1000_CLK_OST 34 +#define X1000_CLK_PDMA 35 +#define X1000_CLK_EXCLK_DIV512 36 +#define X1000_CLK_RTC 37 + +#endif /* __DT_BINDINGS_CLOCK_X1000_CGU_H__ */ diff --git a/include/dt-bindings/clock/ingenic,x1830-cgu.h b/include/dt-bindings/clock/ingenic,x1830-cgu.h new file mode 100644 index 000000000000..88455376a950 --- /dev/null +++ b/include/dt-bindings/clock/ingenic,x1830-cgu.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides clock numbers for the ingenic,x1830-cgu DT binding. + * + * They are roughly ordered as: + * - external clocks + * - PLLs + * - muxes/dividers in the order they appear in the x1830 programmers manual + * - gates in order of their bit in the CLKGR* registers + */ + +#ifndef __DT_BINDINGS_CLOCK_X1830_CGU_H__ +#define __DT_BINDINGS_CLOCK_X1830_CGU_H__ + +#define X1830_CLK_EXCLK 0 +#define X1830_CLK_RTCLK 1 +#define X1830_CLK_APLL 2 +#define X1830_CLK_MPLL 3 +#define X1830_CLK_EPLL 4 +#define X1830_CLK_VPLL 5 +#define X1830_CLK_OTGPHY 6 +#define X1830_CLK_SCLKA 7 +#define X1830_CLK_CPUMUX 8 +#define X1830_CLK_CPU 9 +#define X1830_CLK_L2CACHE 10 +#define X1830_CLK_AHB0 11 +#define X1830_CLK_AHB2PMUX 12 +#define X1830_CLK_AHB2 13 +#define X1830_CLK_PCLK 14 +#define X1830_CLK_DDR 15 +#define X1830_CLK_MAC 16 +#define X1830_CLK_LCD 17 +#define X1830_CLK_MSCMUX 18 +#define X1830_CLK_MSC0 19 +#define X1830_CLK_MSC1 20 +#define X1830_CLK_SSIPLL 21 +#define X1830_CLK_SSIPLL_DIV2 22 +#define X1830_CLK_SSIMUX 23 +#define X1830_CLK_EMC 24 +#define X1830_CLK_EFUSE 25 +#define X1830_CLK_OTG 26 +#define X1830_CLK_SSI0 27 +#define X1830_CLK_SMB0 28 +#define X1830_CLK_SMB1 29 +#define X1830_CLK_SMB2 30 +#define X1830_CLK_UART0 31 +#define X1830_CLK_UART1 32 +#define X1830_CLK_SSI1 33 +#define X1830_CLK_SFC 34 +#define X1830_CLK_PDMA 35 +#define X1830_CLK_TCU 36 +#define X1830_CLK_DTRNG 37 +#define X1830_CLK_OST 38 +#define X1830_CLK_EXCLK_DIV512 39 +#define X1830_CLK_RTC 40 + +#endif /* __DT_BINDINGS_CLOCK_X1830_CGU_H__ */ diff --git a/include/dt-bindings/clock/intel,lgm-clk.h b/include/dt-bindings/clock/intel,lgm-clk.h new file mode 100644 index 000000000000..92f5be6490bb --- /dev/null +++ b/include/dt-bindings/clock/intel,lgm-clk.h @@ -0,0 +1,165 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2020 Intel Corporation. + * Lei Chuanhua <Chuanhua.lei@intel.com> + * Zhu Yixin <Yixin.zhu@intel.com> + */ +#ifndef __INTEL_LGM_CLK_H +#define __INTEL_LGM_CLK_H + +/* PLL clocks */ +#define LGM_CLK_OSC 1 +#define LGM_CLK_PLLPP 2 +#define LGM_CLK_PLL2 3 +#define LGM_CLK_PLL0CZ 4 +#define LGM_CLK_PLL0B 5 +#define LGM_CLK_PLL1 6 +#define LGM_CLK_LJPLL3 7 +#define LGM_CLK_LJPLL4 8 +#define LGM_CLK_PLL0CM0 9 +#define LGM_CLK_PLL0CM1 10 + +/* clocks from PLLs */ + +/* ROPLL clocks */ +#define LGM_CLK_PP_HW 15 +#define LGM_CLK_PP_UC 16 +#define LGM_CLK_PP_FXD 17 +#define LGM_CLK_PP_TBM 18 + +/* PLL2 clocks */ +#define LGM_CLK_DDR 20 + +/* PLL0CZ */ +#define LGM_CLK_CM 25 +#define LGM_CLK_IC 26 +#define LGM_CLK_SDXC3 27 + +/* PLL0B */ +#define LGM_CLK_NGI 30 +#define LGM_CLK_NOC4 31 +#define LGM_CLK_SW 32 +#define LGM_CLK_QSPI 33 +#define LGM_CLK_CQEM LGM_CLK_SW +#define LGM_CLK_EMMC5 LGM_CLK_NOC4 + +/* PLL1 */ +#define LGM_CLK_CT 35 +#define LGM_CLK_DSP 36 +#define LGM_CLK_VIF 37 + +/* LJPLL3 */ +#define LGM_CLK_CML 40 +#define LGM_CLK_SERDES 41 +#define LGM_CLK_POOL 42 +#define LGM_CLK_PTP 43 + +/* LJPLL4 */ +#define LGM_CLK_PCIE 45 +#define LGM_CLK_SATA LGM_CLK_PCIE + +/* PLL0CM0 */ +#define LGM_CLK_CPU0 50 + +/* PLL0CM1 */ +#define LGM_CLK_CPU1 55 + +/* Miscellaneous clocks */ +#define LGM_CLK_EMMC4 60 +#define LGM_CLK_SDXC2 61 +#define LGM_CLK_EMMC 62 +#define LGM_CLK_SDXC 63 +#define LGM_CLK_SLIC 64 +#define LGM_CLK_DCL 65 +#define LGM_CLK_DOCSIS 66 +#define LGM_CLK_PCM 67 +#define LGM_CLK_DDR_PHY 68 +#define LGM_CLK_PONDEF 69 +#define LGM_CLK_PL25M 70 +#define LGM_CLK_PL10M 71 +#define LGM_CLK_PL1544K 72 +#define LGM_CLK_PL2048K 73 +#define LGM_CLK_PL8K 74 +#define LGM_CLK_PON_NTR 75 +#define LGM_CLK_SYNC0 76 +#define LGM_CLK_SYNC1 77 +#define LGM_CLK_PROGDIV 78 +#define LGM_CLK_OD0 79 +#define LGM_CLK_OD1 80 +#define LGM_CLK_CBPHY0 81 +#define LGM_CLK_CBPHY1 82 +#define LGM_CLK_CBPHY2 83 +#define LGM_CLK_CBPHY3 84 + +/* Gate clocks */ +/* Gate CLK0 */ +#define LGM_GCLK_C55 100 +#define LGM_GCLK_QSPI 101 +#define LGM_GCLK_EIP197 102 +#define LGM_GCLK_VAULT 103 +#define LGM_GCLK_TOE 104 +#define LGM_GCLK_SDXC 105 +#define LGM_GCLK_EMMC 106 +#define LGM_GCLK_SPI_DBG 107 +#define LGM_GCLK_DMA3 108 + +/* Gate CLK1 */ +#define LGM_GCLK_DMA0 120 +#define LGM_GCLK_LEDC0 121 +#define LGM_GCLK_LEDC1 122 +#define LGM_GCLK_I2S0 123 +#define LGM_GCLK_I2S1 124 +#define LGM_GCLK_EBU 125 +#define LGM_GCLK_PWM 126 +#define LGM_GCLK_I2C0 127 +#define LGM_GCLK_I2C1 128 +#define LGM_GCLK_I2C2 129 +#define LGM_GCLK_I2C3 130 +#define LGM_GCLK_SSC0 131 +#define LGM_GCLK_SSC1 132 +#define LGM_GCLK_SSC2 133 +#define LGM_GCLK_SSC3 134 +#define LGM_GCLK_GPTC0 135 +#define LGM_GCLK_GPTC1 136 +#define LGM_GCLK_GPTC2 137 +#define LGM_GCLK_GPTC3 138 +#define LGM_GCLK_ASC0 139 +#define LGM_GCLK_ASC1 140 +#define LGM_GCLK_ASC2 141 +#define LGM_GCLK_ASC3 142 +#define LGM_GCLK_PCM0 143 +#define LGM_GCLK_PCM1 144 +#define LGM_GCLK_PCM2 145 + +/* Gate CLK2 */ +#define LGM_GCLK_PCIE10 150 +#define LGM_GCLK_PCIE11 151 +#define LGM_GCLK_PCIE30 152 +#define LGM_GCLK_PCIE31 153 +#define LGM_GCLK_PCIE20 154 +#define LGM_GCLK_PCIE21 155 +#define LGM_GCLK_PCIE40 156 +#define LGM_GCLK_PCIE41 157 +#define LGM_GCLK_XPCS0 158 +#define LGM_GCLK_XPCS1 159 +#define LGM_GCLK_XPCS2 160 +#define LGM_GCLK_XPCS3 161 +#define LGM_GCLK_SATA0 162 +#define LGM_GCLK_SATA1 163 +#define LGM_GCLK_SATA2 164 +#define LGM_GCLK_SATA3 165 + +/* Gate CLK3 */ +#define LGM_GCLK_ARCEM4 170 +#define LGM_GCLK_IDMAR1 171 +#define LGM_GCLK_IDMAT0 172 +#define LGM_GCLK_IDMAT1 173 +#define LGM_GCLK_IDMAT2 174 +#define LGM_GCLK_PPV4 175 +#define LGM_GCLK_GSWIPO 176 +#define LGM_GCLK_CQEM 177 +#define LGM_GCLK_XPCS5 178 +#define LGM_GCLK_USB1 179 +#define LGM_GCLK_USB2 180 + +#endif /* __INTEL_LGM_CLK_H */ diff --git a/include/dt-bindings/clock/jz4780-cgu.h b/include/dt-bindings/clock/jz4780-cgu.h deleted file mode 100644 index 1859ce53ee38..000000000000 --- a/include/dt-bindings/clock/jz4780-cgu.h +++ /dev/null @@ -1,89 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides clock numbers for the ingenic,jz4780-cgu DT binding. - * - * They are roughly ordered as: - * - external clocks - * - PLLs - * - muxes/dividers in the order they appear in the jz4780 programmers manual - * - gates in order of their bit in the CLKGR* registers - */ - -#ifndef __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ -#define __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ - -#define JZ4780_CLK_EXCLK 0 -#define JZ4780_CLK_RTCLK 1 -#define JZ4780_CLK_APLL 2 -#define JZ4780_CLK_MPLL 3 -#define JZ4780_CLK_EPLL 4 -#define JZ4780_CLK_VPLL 5 -#define JZ4780_CLK_OTGPHY 6 -#define JZ4780_CLK_SCLKA 7 -#define JZ4780_CLK_CPUMUX 8 -#define JZ4780_CLK_CPU 9 -#define JZ4780_CLK_L2CACHE 10 -#define JZ4780_CLK_AHB0 11 -#define JZ4780_CLK_AHB2PMUX 12 -#define JZ4780_CLK_AHB2 13 -#define JZ4780_CLK_PCLK 14 -#define JZ4780_CLK_DDR 15 -#define JZ4780_CLK_VPU 16 -#define JZ4780_CLK_I2SPLL 17 -#define JZ4780_CLK_I2S 18 -#define JZ4780_CLK_LCD0PIXCLK 19 -#define JZ4780_CLK_LCD1PIXCLK 20 -#define JZ4780_CLK_MSCMUX 21 -#define JZ4780_CLK_MSC0 22 -#define JZ4780_CLK_MSC1 23 -#define JZ4780_CLK_MSC2 24 -#define JZ4780_CLK_UHC 25 -#define JZ4780_CLK_SSIPLL 26 -#define JZ4780_CLK_SSI 27 -#define JZ4780_CLK_CIMMCLK 28 -#define JZ4780_CLK_PCMPLL 29 -#define JZ4780_CLK_PCM 30 -#define JZ4780_CLK_GPU 31 -#define JZ4780_CLK_HDMI 32 -#define JZ4780_CLK_BCH 33 -#define JZ4780_CLK_NEMC 34 -#define JZ4780_CLK_OTG0 35 -#define JZ4780_CLK_SSI0 36 -#define JZ4780_CLK_SMB0 37 -#define JZ4780_CLK_SMB1 38 -#define JZ4780_CLK_SCC 39 -#define JZ4780_CLK_AIC 40 -#define JZ4780_CLK_TSSI0 41 -#define JZ4780_CLK_OWI 42 -#define JZ4780_CLK_KBC 43 -#define JZ4780_CLK_SADC 44 -#define JZ4780_CLK_UART0 45 -#define JZ4780_CLK_UART1 46 -#define JZ4780_CLK_UART2 47 -#define JZ4780_CLK_UART3 48 -#define JZ4780_CLK_SSI1 49 -#define JZ4780_CLK_SSI2 50 -#define JZ4780_CLK_PDMA 51 -#define JZ4780_CLK_GPS 52 -#define JZ4780_CLK_MAC 53 -#define JZ4780_CLK_SMB2 54 -#define JZ4780_CLK_CIM 55 -#define JZ4780_CLK_LCD 56 -#define JZ4780_CLK_TVE 57 -#define JZ4780_CLK_IPU 58 -#define JZ4780_CLK_DDR0 59 -#define JZ4780_CLK_DDR1 60 -#define JZ4780_CLK_SMB3 61 -#define JZ4780_CLK_TSSI1 62 -#define JZ4780_CLK_COMPRESS 63 -#define JZ4780_CLK_AIC1 64 -#define JZ4780_CLK_GPVLC 65 -#define JZ4780_CLK_OTG1 66 -#define JZ4780_CLK_UART4 67 -#define JZ4780_CLK_AHBMON 68 -#define JZ4780_CLK_SMB4 69 -#define JZ4780_CLK_DES 70 -#define JZ4780_CLK_X2D 71 -#define JZ4780_CLK_CORE1 72 - -#endif /* __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ */ diff --git a/include/dt-bindings/clock/k210-clk.h b/include/dt-bindings/clock/k210-clk.h new file mode 100644 index 000000000000..b2de702cbf75 --- /dev/null +++ b/include/dt-bindings/clock/k210-clk.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com> + * Copyright (c) 2020 Western Digital Corporation or its affiliates. + */ +#ifndef CLOCK_K210_CLK_H +#define CLOCK_K210_CLK_H + +/* + * Kendryte K210 SoC clock identifiers (arbitrary values). + */ +#define K210_CLK_CPU 0 +#define K210_CLK_SRAM0 1 +#define K210_CLK_SRAM1 2 +#define K210_CLK_AI 3 +#define K210_CLK_DMA 4 +#define K210_CLK_FFT 5 +#define K210_CLK_ROM 6 +#define K210_CLK_DVP 7 +#define K210_CLK_APB0 8 +#define K210_CLK_APB1 9 +#define K210_CLK_APB2 10 +#define K210_CLK_I2S0 11 +#define K210_CLK_I2S1 12 +#define K210_CLK_I2S2 13 +#define K210_CLK_I2S0_M 14 +#define K210_CLK_I2S1_M 15 +#define K210_CLK_I2S2_M 16 +#define K210_CLK_WDT0 17 +#define K210_CLK_WDT1 18 +#define K210_CLK_SPI0 19 +#define K210_CLK_SPI1 20 +#define K210_CLK_SPI2 21 +#define K210_CLK_I2C0 22 +#define K210_CLK_I2C1 23 +#define K210_CLK_I2C2 24 +#define K210_CLK_SPI3 25 +#define K210_CLK_TIMER0 26 +#define K210_CLK_TIMER1 27 +#define K210_CLK_TIMER2 28 +#define K210_CLK_GPIO 29 +#define K210_CLK_UART1 30 +#define K210_CLK_UART2 31 +#define K210_CLK_UART3 32 +#define K210_CLK_FPIOA 33 +#define K210_CLK_SHA 34 +#define K210_CLK_AES 35 +#define K210_CLK_OTP 36 +#define K210_CLK_RTC 37 + +#define K210_NUM_CLKS 38 + +#endif /* CLOCK_K210_CLK_H */ diff --git a/include/dt-bindings/clk/lochnagar.h b/include/dt-bindings/clock/lochnagar.h index 8fa20551ff17..8fa20551ff17 100644 --- a/include/dt-bindings/clk/lochnagar.h +++ b/include/dt-bindings/clock/lochnagar.h diff --git a/include/dt-bindings/clock/marvell,mmp2-audio.h b/include/dt-bindings/clock/marvell,mmp2-audio.h new file mode 100644 index 000000000000..20664776f497 --- /dev/null +++ b/include/dt-bindings/clock/marvell,mmp2-audio.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) */ +#ifndef __DT_BINDINGS_CLOCK_MARVELL_MMP2_AUDIO_H +#define __DT_BINDINGS_CLOCK_MARVELL_MMP2_AUDIO_H + +#define MMP2_CLK_AUDIO_SYSCLK 0 +#define MMP2_CLK_AUDIO_SSPA0 1 +#define MMP2_CLK_AUDIO_SSPA1 2 + +#define MMP2_CLK_AUDIO_NR_CLKS 3 +#endif diff --git a/include/dt-bindings/clock/marvell,mmp2.h b/include/dt-bindings/clock/marvell,mmp2.h index 4b1a7724f20d..f0819d66b230 100644 --- a/include/dt-bindings/clock/marvell,mmp2.h +++ b/include/dt-bindings/clock/marvell,mmp2.h @@ -26,8 +26,13 @@ #define MMP2_CLK_VCTCXO_4 25 #define MMP2_CLK_UART_PLL 26 #define MMP2_CLK_USB_PLL 27 +#define MMP3_CLK_PLL1_P 28 +#define MMP3_CLK_PLL2_P 29 +#define MMP3_CLK_PLL3 30 +#define MMP2_CLK_I2S0 31 +#define MMP2_CLK_I2S1 32 -/* apb periphrals */ +/* apb peripherals */ #define MMP2_CLK_TWSI0 60 #define MMP2_CLK_TWSI1 61 #define MMP2_CLK_TWSI2 62 @@ -50,8 +55,12 @@ #define MMP2_CLK_SSP2 79 #define MMP2_CLK_SSP3 80 #define MMP2_CLK_TIMER 81 +#define MMP2_CLK_THERMAL0 82 +#define MMP3_CLK_THERMAL1 83 +#define MMP3_CLK_THERMAL2 84 +#define MMP3_CLK_THERMAL3 85 -/* axi periphrals */ +/* axi peripherals */ #define MMP2_CLK_SDH0 101 #define MMP2_CLK_SDH1 102 #define MMP2_CLK_SDH2 103 @@ -74,6 +83,13 @@ #define MMP2_CLK_DISP0_LCDC 120 #define MMP2_CLK_USBHSIC0 121 #define MMP2_CLK_USBHSIC1 122 +#define MMP2_CLK_GPU_BUS 123 +#define MMP3_CLK_GPU_BUS MMP2_CLK_GPU_BUS +#define MMP2_CLK_GPU_3D 124 +#define MMP3_CLK_GPU_3D MMP2_CLK_GPU_3D +#define MMP3_CLK_GPU_2D 125 +#define MMP3_CLK_SDH4 126 +#define MMP2_CLK_AUDIO 127 #define MMP2_NR_CLKS 200 #endif diff --git a/include/dt-bindings/clock/marvell,pxa168.h b/include/dt-bindings/clock/marvell,pxa168.h index caf90436b848..c92d969ae941 100644 --- a/include/dt-bindings/clock/marvell,pxa168.h +++ b/include/dt-bindings/clock/marvell,pxa168.h @@ -20,10 +20,13 @@ #define PXA168_CLK_PLL1_2_1_5 19 #define PXA168_CLK_PLL1_3_16 20 #define PXA168_CLK_PLL1_192 21 +#define PXA168_CLK_PLL1_2_1_10 22 +#define PXA168_CLK_PLL1_2_3_16 23 #define PXA168_CLK_UART_PLL 27 #define PXA168_CLK_USB_PLL 28 +#define PXA168_CLK_CLK32_2 50 -/* apb periphrals */ +/* apb peripherals */ #define PXA168_CLK_TWSI0 60 #define PXA168_CLK_TWSI1 61 #define PXA168_CLK_TWSI2 62 @@ -45,7 +48,7 @@ #define PXA168_CLK_SSP4 78 #define PXA168_CLK_TIMER 79 -/* axi periphrals */ +/* axi peripherals */ #define PXA168_CLK_DFC 100 #define PXA168_CLK_SDH0 101 #define PXA168_CLK_SDH1 102 @@ -56,6 +59,9 @@ #define PXA168_CLK_CCIC0 107 #define PXA168_CLK_CCIC0_PHY 108 #define PXA168_CLK_CCIC0_SPHY 109 +#define PXA168_CLK_SDH3 110 +#define PXA168_CLK_SDH01_AXI 111 +#define PXA168_CLK_SDH23_AXI 112 #define PXA168_NR_CLKS 200 #endif diff --git a/include/dt-bindings/clock/marvell,pxa910.h b/include/dt-bindings/clock/marvell,pxa910.h index 7bf46238946e..c9018ab354d0 100644 --- a/include/dt-bindings/clock/marvell,pxa910.h +++ b/include/dt-bindings/clock/marvell,pxa910.h @@ -23,7 +23,7 @@ #define PXA910_CLK_UART_PLL 27 #define PXA910_CLK_USB_PLL 28 -/* apb periphrals */ +/* apb peripherals */ #define PXA910_CLK_TWSI0 60 #define PXA910_CLK_TWSI1 61 #define PXA910_CLK_TWSI2 62 @@ -43,7 +43,7 @@ #define PXA910_CLK_TIMER0 76 #define PXA910_CLK_TIMER1 77 -/* axi periphrals */ +/* axi peripherals */ #define PXA910_CLK_DFC 100 #define PXA910_CLK_SDH0 101 #define PXA910_CLK_SDH1 102 diff --git a/include/dt-bindings/clock/mediatek,mt6795-clk.h b/include/dt-bindings/clock/mediatek,mt6795-clk.h new file mode 100644 index 000000000000..9902906ac902 --- /dev/null +++ b/include/dt-bindings/clock/mediatek,mt6795-clk.h @@ -0,0 +1,275 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) */ +/* + * Copyright (c) 2022 Collabora Ltd. + * Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> + */ + +#ifndef _DT_BINDINGS_CLK_MT6795_H +#define _DT_BINDINGS_CLK_MT6795_H + +/* TOPCKGEN */ +#define CLK_TOP_ADSYS_26M 0 +#define CLK_TOP_CLKPH_MCK_O 1 +#define CLK_TOP_USB_SYSPLL_125M 2 +#define CLK_TOP_DSI0_DIG 3 +#define CLK_TOP_DSI1_DIG 4 +#define CLK_TOP_ARMCA53PLL_754M 5 +#define CLK_TOP_ARMCA53PLL_502M 6 +#define CLK_TOP_MAIN_H546M 7 +#define CLK_TOP_MAIN_H364M 8 +#define CLK_TOP_MAIN_H218P4M 9 +#define CLK_TOP_MAIN_H156M 10 +#define CLK_TOP_TVDPLL_445P5M 11 +#define CLK_TOP_TVDPLL_594M 12 +#define CLK_TOP_UNIV_624M 13 +#define CLK_TOP_UNIV_416M 14 +#define CLK_TOP_UNIV_249P6M 15 +#define CLK_TOP_UNIV_178P3M 16 +#define CLK_TOP_UNIV_48M 17 +#define CLK_TOP_CLKRTC_EXT 18 +#define CLK_TOP_CLKRTC_INT 19 +#define CLK_TOP_FPC 20 +#define CLK_TOP_HDMITXPLL_D2 21 +#define CLK_TOP_HDMITXPLL_D3 22 +#define CLK_TOP_ARMCA53PLL_D2 23 +#define CLK_TOP_ARMCA53PLL_D3 24 +#define CLK_TOP_APLL1 25 +#define CLK_TOP_APLL2 26 +#define CLK_TOP_DMPLL 27 +#define CLK_TOP_DMPLL_D2 28 +#define CLK_TOP_DMPLL_D4 29 +#define CLK_TOP_DMPLL_D8 30 +#define CLK_TOP_DMPLL_D16 31 +#define CLK_TOP_MMPLL 32 +#define CLK_TOP_MMPLL_D2 33 +#define CLK_TOP_MSDCPLL 34 +#define CLK_TOP_MSDCPLL_D2 35 +#define CLK_TOP_MSDCPLL_D4 36 +#define CLK_TOP_MSDCPLL2 37 +#define CLK_TOP_MSDCPLL2_D2 38 +#define CLK_TOP_MSDCPLL2_D4 39 +#define CLK_TOP_SYSPLL_D2 40 +#define CLK_TOP_SYSPLL1_D2 41 +#define CLK_TOP_SYSPLL1_D4 42 +#define CLK_TOP_SYSPLL1_D8 43 +#define CLK_TOP_SYSPLL1_D16 44 +#define CLK_TOP_SYSPLL_D3 45 +#define CLK_TOP_SYSPLL2_D2 46 +#define CLK_TOP_SYSPLL2_D4 47 +#define CLK_TOP_SYSPLL_D5 48 +#define CLK_TOP_SYSPLL3_D2 49 +#define CLK_TOP_SYSPLL3_D4 50 +#define CLK_TOP_SYSPLL_D7 51 +#define CLK_TOP_SYSPLL4_D2 52 +#define CLK_TOP_SYSPLL4_D4 53 +#define CLK_TOP_TVDPLL 54 +#define CLK_TOP_TVDPLL_D2 55 +#define CLK_TOP_TVDPLL_D4 56 +#define CLK_TOP_TVDPLL_D8 57 +#define CLK_TOP_TVDPLL_D16 58 +#define CLK_TOP_UNIVPLL_D2 59 +#define CLK_TOP_UNIVPLL1_D2 60 +#define CLK_TOP_UNIVPLL1_D4 61 +#define CLK_TOP_UNIVPLL1_D8 62 +#define CLK_TOP_UNIVPLL_D3 63 +#define CLK_TOP_UNIVPLL2_D2 64 +#define CLK_TOP_UNIVPLL2_D4 65 +#define CLK_TOP_UNIVPLL2_D8 66 +#define CLK_TOP_UNIVPLL_D5 67 +#define CLK_TOP_UNIVPLL3_D2 68 +#define CLK_TOP_UNIVPLL3_D4 69 +#define CLK_TOP_UNIVPLL3_D8 70 +#define CLK_TOP_UNIVPLL_D7 71 +#define CLK_TOP_UNIVPLL_D26 72 +#define CLK_TOP_UNIVPLL_D52 73 +#define CLK_TOP_VCODECPLL 74 +#define CLK_TOP_VCODECPLL_370P5 75 +#define CLK_TOP_VENCPLL 76 +#define CLK_TOP_VENCPLL_D2 77 +#define CLK_TOP_VENCPLL_D4 78 +#define CLK_TOP_AXI_SEL 79 +#define CLK_TOP_MEM_SEL 80 +#define CLK_TOP_DDRPHYCFG_SEL 81 +#define CLK_TOP_MM_SEL 82 +#define CLK_TOP_PWM_SEL 83 +#define CLK_TOP_VDEC_SEL 84 +#define CLK_TOP_VENC_SEL 85 +#define CLK_TOP_MFG_SEL 86 +#define CLK_TOP_CAMTG_SEL 87 +#define CLK_TOP_UART_SEL 88 +#define CLK_TOP_SPI_SEL 89 +#define CLK_TOP_USB20_SEL 90 +#define CLK_TOP_USB30_SEL 91 +#define CLK_TOP_MSDC50_0_H_SEL 92 +#define CLK_TOP_MSDC50_0_SEL 93 +#define CLK_TOP_MSDC30_1_SEL 94 +#define CLK_TOP_MSDC30_2_SEL 95 +#define CLK_TOP_MSDC30_3_SEL 96 +#define CLK_TOP_AUDIO_SEL 97 +#define CLK_TOP_AUD_INTBUS_SEL 98 +#define CLK_TOP_PMICSPI_SEL 99 +#define CLK_TOP_SCP_SEL 100 +#define CLK_TOP_MJC_SEL 101 +#define CLK_TOP_DPI0_SEL 102 +#define CLK_TOP_IRDA_SEL 103 +#define CLK_TOP_CCI400_SEL 104 +#define CLK_TOP_AUD_1_SEL 105 +#define CLK_TOP_AUD_2_SEL 106 +#define CLK_TOP_MEM_MFG_IN_SEL 107 +#define CLK_TOP_AXI_MFG_IN_SEL 108 +#define CLK_TOP_SCAM_SEL 109 +#define CLK_TOP_I2S0_M_SEL 110 +#define CLK_TOP_I2S1_M_SEL 111 +#define CLK_TOP_I2S2_M_SEL 112 +#define CLK_TOP_I2S3_M_SEL 113 +#define CLK_TOP_I2S3_B_SEL 114 +#define CLK_TOP_APLL1_DIV0 115 +#define CLK_TOP_APLL1_DIV1 116 +#define CLK_TOP_APLL1_DIV2 117 +#define CLK_TOP_APLL1_DIV3 118 +#define CLK_TOP_APLL1_DIV4 119 +#define CLK_TOP_APLL1_DIV5 120 +#define CLK_TOP_APLL2_DIV0 121 +#define CLK_TOP_APLL2_DIV1 122 +#define CLK_TOP_APLL2_DIV2 123 +#define CLK_TOP_APLL2_DIV3 124 +#define CLK_TOP_APLL2_DIV4 125 +#define CLK_TOP_APLL2_DIV5 126 +#define CLK_TOP_NR_CLK 127 + +/* APMIXED_SYS */ +#define CLK_APMIXED_ARMCA53PLL 0 +#define CLK_APMIXED_MAINPLL 1 +#define CLK_APMIXED_UNIVPLL 2 +#define CLK_APMIXED_MMPLL 3 +#define CLK_APMIXED_MSDCPLL 4 +#define CLK_APMIXED_VENCPLL 5 +#define CLK_APMIXED_TVDPLL 6 +#define CLK_APMIXED_MPLL 7 +#define CLK_APMIXED_VCODECPLL 8 +#define CLK_APMIXED_APLL1 9 +#define CLK_APMIXED_APLL2 10 +#define CLK_APMIXED_REF2USB_TX 11 +#define CLK_APMIXED_NR_CLK 12 + +/* INFRA_SYS */ +#define CLK_INFRA_DBGCLK 0 +#define CLK_INFRA_SMI 1 +#define CLK_INFRA_AUDIO 2 +#define CLK_INFRA_GCE 3 +#define CLK_INFRA_L2C_SRAM 4 +#define CLK_INFRA_M4U 5 +#define CLK_INFRA_MD1MCU 6 +#define CLK_INFRA_MD1BUS 7 +#define CLK_INFRA_MD1DBB 8 +#define CLK_INFRA_DEVICE_APC 9 +#define CLK_INFRA_TRNG 10 +#define CLK_INFRA_MD1LTE 11 +#define CLK_INFRA_CPUM 12 +#define CLK_INFRA_KP 13 +#define CLK_INFRA_CA53_C0_SEL 14 +#define CLK_INFRA_CA53_C1_SEL 15 +#define CLK_INFRA_NR_CLK 16 + +/* PERI_SYS */ +#define CLK_PERI_NFI 0 +#define CLK_PERI_THERM 1 +#define CLK_PERI_PWM1 2 +#define CLK_PERI_PWM2 3 +#define CLK_PERI_PWM3 4 +#define CLK_PERI_PWM4 5 +#define CLK_PERI_PWM5 6 +#define CLK_PERI_PWM6 7 +#define CLK_PERI_PWM7 8 +#define CLK_PERI_PWM 9 +#define CLK_PERI_USB0 10 +#define CLK_PERI_USB1 11 +#define CLK_PERI_AP_DMA 12 +#define CLK_PERI_MSDC30_0 13 +#define CLK_PERI_MSDC30_1 14 +#define CLK_PERI_MSDC30_2 15 +#define CLK_PERI_MSDC30_3 16 +#define CLK_PERI_NLI_ARB 17 +#define CLK_PERI_IRDA 18 +#define CLK_PERI_UART0 19 +#define CLK_PERI_UART1 20 +#define CLK_PERI_UART2 21 +#define CLK_PERI_UART3 22 +#define CLK_PERI_I2C0 23 +#define CLK_PERI_I2C1 24 +#define CLK_PERI_I2C2 25 +#define CLK_PERI_I2C3 26 +#define CLK_PERI_I2C4 27 +#define CLK_PERI_AUXADC 28 +#define CLK_PERI_SPI0 29 +#define CLK_PERI_UART0_SEL 30 +#define CLK_PERI_UART1_SEL 31 +#define CLK_PERI_UART2_SEL 32 +#define CLK_PERI_UART3_SEL 33 +#define CLK_PERI_NR_CLK 34 + +/* MFG */ +#define CLK_MFG_BAXI 0 +#define CLK_MFG_BMEM 1 +#define CLK_MFG_BG3D 2 +#define CLK_MFG_B26M 3 +#define CLK_MFG_NR_CLK 4 + +/* MM_SYS */ +#define CLK_MM_SMI_COMMON 0 +#define CLK_MM_SMI_LARB0 1 +#define CLK_MM_CAM_MDP 2 +#define CLK_MM_MDP_RDMA0 3 +#define CLK_MM_MDP_RDMA1 4 +#define CLK_MM_MDP_RSZ0 5 +#define CLK_MM_MDP_RSZ1 6 +#define CLK_MM_MDP_RSZ2 7 +#define CLK_MM_MDP_TDSHP0 8 +#define CLK_MM_MDP_TDSHP1 9 +#define CLK_MM_MDP_CROP 10 +#define CLK_MM_MDP_WDMA 11 +#define CLK_MM_MDP_WROT0 12 +#define CLK_MM_MDP_WROT1 13 +#define CLK_MM_FAKE_ENG 14 +#define CLK_MM_MUTEX_32K 15 +#define CLK_MM_DISP_OVL0 16 +#define CLK_MM_DISP_OVL1 17 +#define CLK_MM_DISP_RDMA0 18 +#define CLK_MM_DISP_RDMA1 19 +#define CLK_MM_DISP_RDMA2 20 +#define CLK_MM_DISP_WDMA0 21 +#define CLK_MM_DISP_WDMA1 22 +#define CLK_MM_DISP_COLOR0 23 +#define CLK_MM_DISP_COLOR1 24 +#define CLK_MM_DISP_AAL 25 +#define CLK_MM_DISP_GAMMA 26 +#define CLK_MM_DISP_UFOE 27 +#define CLK_MM_DISP_SPLIT0 28 +#define CLK_MM_DISP_SPLIT1 29 +#define CLK_MM_DISP_MERGE 30 +#define CLK_MM_DISP_OD 31 +#define CLK_MM_DISP_PWM0MM 32 +#define CLK_MM_DISP_PWM026M 33 +#define CLK_MM_DISP_PWM1MM 34 +#define CLK_MM_DISP_PWM126M 35 +#define CLK_MM_DSI0_ENGINE 36 +#define CLK_MM_DSI0_DIGITAL 37 +#define CLK_MM_DSI1_ENGINE 38 +#define CLK_MM_DSI1_DIGITAL 39 +#define CLK_MM_DPI_PIXEL 40 +#define CLK_MM_DPI_ENGINE 41 +#define CLK_MM_NR_CLK 42 + +/* VDEC_SYS */ +#define CLK_VDEC_CKEN 0 +#define CLK_VDEC_LARB_CKEN 1 +#define CLK_VDEC_NR_CLK 2 + +/* VENC_SYS */ +#define CLK_VENC_LARB 0 +#define CLK_VENC_VENC 1 +#define CLK_VENC_JPGENC 2 +#define CLK_VENC_JPGDEC 3 +#define CLK_VENC_NR_CLK 4 + +#endif /* _DT_BINDINGS_CLK_MT6795_H */ diff --git a/include/dt-bindings/clock/mediatek,mt8365-clk.h b/include/dt-bindings/clock/mediatek,mt8365-clk.h new file mode 100644 index 000000000000..f9aff1775810 --- /dev/null +++ b/include/dt-bindings/clock/mediatek,mt8365-clk.h @@ -0,0 +1,373 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) + * + * Copyright (c) 2022 MediaTek Inc. + */ + +#ifndef _DT_BINDINGS_CLK_MT8365_H +#define _DT_BINDINGS_CLK_MT8365_H + +/* TOPCKGEN */ +#define CLK_TOP_CLK_NULL 0 +#define CLK_TOP_I2S0_BCK 1 +#define CLK_TOP_DSI0_LNTC_DSICK 2 +#define CLK_TOP_VPLL_DPIX 3 +#define CLK_TOP_LVDSTX_CLKDIG_CTS 4 +#define CLK_TOP_MFGPLL 5 +#define CLK_TOP_SYSPLL_D2 6 +#define CLK_TOP_SYSPLL1_D2 7 +#define CLK_TOP_SYSPLL1_D4 8 +#define CLK_TOP_SYSPLL1_D8 9 +#define CLK_TOP_SYSPLL1_D16 10 +#define CLK_TOP_SYSPLL_D3 11 +#define CLK_TOP_SYSPLL2_D2 12 +#define CLK_TOP_SYSPLL2_D4 13 +#define CLK_TOP_SYSPLL2_D8 14 +#define CLK_TOP_SYSPLL_D5 15 +#define CLK_TOP_SYSPLL3_D2 16 +#define CLK_TOP_SYSPLL3_D4 17 +#define CLK_TOP_SYSPLL_D7 18 +#define CLK_TOP_SYSPLL4_D2 19 +#define CLK_TOP_SYSPLL4_D4 20 +#define CLK_TOP_UNIVPLL 21 +#define CLK_TOP_UNIVPLL_D2 22 +#define CLK_TOP_UNIVPLL1_D2 23 +#define CLK_TOP_UNIVPLL1_D4 24 +#define CLK_TOP_UNIVPLL_D3 25 +#define CLK_TOP_UNIVPLL2_D2 26 +#define CLK_TOP_UNIVPLL2_D4 27 +#define CLK_TOP_UNIVPLL2_D8 28 +#define CLK_TOP_UNIVPLL2_D32 29 +#define CLK_TOP_UNIVPLL_D5 30 +#define CLK_TOP_UNIVPLL3_D2 31 +#define CLK_TOP_UNIVPLL3_D4 32 +#define CLK_TOP_MMPLL 33 +#define CLK_TOP_MMPLL_D2 34 +#define CLK_TOP_LVDSPLL_D2 35 +#define CLK_TOP_LVDSPLL_D4 36 +#define CLK_TOP_LVDSPLL_D8 37 +#define CLK_TOP_LVDSPLL_D16 38 +#define CLK_TOP_USB20_192M 39 +#define CLK_TOP_USB20_192M_D4 40 +#define CLK_TOP_USB20_192M_D8 41 +#define CLK_TOP_USB20_192M_D16 42 +#define CLK_TOP_USB20_192M_D32 43 +#define CLK_TOP_APLL1 44 +#define CLK_TOP_APLL1_D2 45 +#define CLK_TOP_APLL1_D4 46 +#define CLK_TOP_APLL1_D8 47 +#define CLK_TOP_APLL2 48 +#define CLK_TOP_APLL2_D2 49 +#define CLK_TOP_APLL2_D4 50 +#define CLK_TOP_APLL2_D8 51 +#define CLK_TOP_SYS_26M_D2 52 +#define CLK_TOP_MSDCPLL 53 +#define CLK_TOP_MSDCPLL_D2 54 +#define CLK_TOP_DSPPLL 55 +#define CLK_TOP_DSPPLL_D2 56 +#define CLK_TOP_DSPPLL_D4 57 +#define CLK_TOP_DSPPLL_D8 58 +#define CLK_TOP_APUPLL 59 +#define CLK_TOP_CLK26M_D52 60 +#define CLK_TOP_AXI_SEL 61 +#define CLK_TOP_MEM_SEL 62 +#define CLK_TOP_MM_SEL 63 +#define CLK_TOP_SCP_SEL 64 +#define CLK_TOP_MFG_SEL 65 +#define CLK_TOP_ATB_SEL 66 +#define CLK_TOP_CAMTG_SEL 67 +#define CLK_TOP_CAMTG1_SEL 68 +#define CLK_TOP_UART_SEL 69 +#define CLK_TOP_SPI_SEL 70 +#define CLK_TOP_MSDC50_0_HC_SEL 71 +#define CLK_TOP_MSDC2_2_HC_SEL 72 +#define CLK_TOP_MSDC50_0_SEL 73 +#define CLK_TOP_MSDC50_2_SEL 74 +#define CLK_TOP_MSDC30_1_SEL 75 +#define CLK_TOP_AUDIO_SEL 76 +#define CLK_TOP_AUD_INTBUS_SEL 77 +#define CLK_TOP_AUD_1_SEL 78 +#define CLK_TOP_AUD_2_SEL 79 +#define CLK_TOP_AUD_ENGEN1_SEL 80 +#define CLK_TOP_AUD_ENGEN2_SEL 81 +#define CLK_TOP_AUD_SPDIF_SEL 82 +#define CLK_TOP_DISP_PWM_SEL 83 +#define CLK_TOP_DXCC_SEL 84 +#define CLK_TOP_SSUSB_SYS_SEL 85 +#define CLK_TOP_SSUSB_XHCI_SEL 86 +#define CLK_TOP_SPM_SEL 87 +#define CLK_TOP_I2C_SEL 88 +#define CLK_TOP_PWM_SEL 89 +#define CLK_TOP_SENIF_SEL 90 +#define CLK_TOP_AES_FDE_SEL 91 +#define CLK_TOP_CAMTM_SEL 92 +#define CLK_TOP_DPI0_SEL 93 +#define CLK_TOP_DPI1_SEL 94 +#define CLK_TOP_DSP_SEL 95 +#define CLK_TOP_NFI2X_SEL 96 +#define CLK_TOP_NFIECC_SEL 97 +#define CLK_TOP_ECC_SEL 98 +#define CLK_TOP_ETH_SEL 99 +#define CLK_TOP_GCPU_SEL 100 +#define CLK_TOP_GCPU_CPM_SEL 101 +#define CLK_TOP_APU_SEL 102 +#define CLK_TOP_APU_IF_SEL 103 +#define CLK_TOP_MBIST_DIAG_SEL 104 +#define CLK_TOP_APLL_I2S0_SEL 105 +#define CLK_TOP_APLL_I2S1_SEL 106 +#define CLK_TOP_APLL_I2S2_SEL 107 +#define CLK_TOP_APLL_I2S3_SEL 108 +#define CLK_TOP_APLL_TDMOUT_SEL 109 +#define CLK_TOP_APLL_TDMIN_SEL 110 +#define CLK_TOP_APLL_SPDIF_SEL 111 +#define CLK_TOP_APLL12_CK_DIV0 112 +#define CLK_TOP_APLL12_CK_DIV1 113 +#define CLK_TOP_APLL12_CK_DIV2 114 +#define CLK_TOP_APLL12_CK_DIV3 115 +#define CLK_TOP_APLL12_CK_DIV4 116 +#define CLK_TOP_APLL12_CK_DIV4B 117 +#define CLK_TOP_APLL12_CK_DIV5 118 +#define CLK_TOP_APLL12_CK_DIV5B 119 +#define CLK_TOP_APLL12_CK_DIV6 120 +#define CLK_TOP_AUD_I2S0_M 121 +#define CLK_TOP_AUD_I2S1_M 122 +#define CLK_TOP_AUD_I2S2_M 123 +#define CLK_TOP_AUD_I2S3_M 124 +#define CLK_TOP_AUD_TDMOUT_M 125 +#define CLK_TOP_AUD_TDMOUT_B 126 +#define CLK_TOP_AUD_TDMIN_M 127 +#define CLK_TOP_AUD_TDMIN_B 128 +#define CLK_TOP_AUD_SPDIF_M 129 +#define CLK_TOP_USB20_48M_EN 130 +#define CLK_TOP_UNIVPLL_48M_EN 131 +#define CLK_TOP_LVDSTX_CLKDIG_EN 132 +#define CLK_TOP_VPLL_DPIX_EN 133 +#define CLK_TOP_SSUSB_TOP_CK_EN 134 +#define CLK_TOP_SSUSB_PHY_CK_EN 135 +#define CLK_TOP_CONN_32K 136 +#define CLK_TOP_CONN_26M 137 +#define CLK_TOP_DSP_32K 138 +#define CLK_TOP_DSP_26M 139 +#define CLK_TOP_NR_CLK 140 + +/* INFRACFG */ +#define CLK_IFR_PMIC_TMR 0 +#define CLK_IFR_PMIC_AP 1 +#define CLK_IFR_PMIC_MD 2 +#define CLK_IFR_PMIC_CONN 3 +#define CLK_IFR_ICUSB 4 +#define CLK_IFR_GCE 5 +#define CLK_IFR_THERM 6 +#define CLK_IFR_PWM_HCLK 7 +#define CLK_IFR_PWM1 8 +#define CLK_IFR_PWM2 9 +#define CLK_IFR_PWM3 10 +#define CLK_IFR_PWM4 11 +#define CLK_IFR_PWM5 12 +#define CLK_IFR_PWM 13 +#define CLK_IFR_UART0 14 +#define CLK_IFR_UART1 15 +#define CLK_IFR_UART2 16 +#define CLK_IFR_DSP_UART 17 +#define CLK_IFR_GCE_26M 18 +#define CLK_IFR_CQ_DMA_FPC 19 +#define CLK_IFR_BTIF 20 +#define CLK_IFR_SPI0 21 +#define CLK_IFR_MSDC0_HCLK 22 +#define CLK_IFR_MSDC2_HCLK 23 +#define CLK_IFR_MSDC1_HCLK 24 +#define CLK_IFR_DVFSRC 25 +#define CLK_IFR_GCPU 26 +#define CLK_IFR_TRNG 27 +#define CLK_IFR_AUXADC 28 +#define CLK_IFR_CPUM 29 +#define CLK_IFR_AUXADC_MD 30 +#define CLK_IFR_AP_DMA 31 +#define CLK_IFR_DEBUGSYS 32 +#define CLK_IFR_AUDIO 33 +#define CLK_IFR_PWM_FBCLK6 34 +#define CLK_IFR_DISP_PWM 35 +#define CLK_IFR_AUD_26M_BK 36 +#define CLK_IFR_CQ_DMA 37 +#define CLK_IFR_MSDC0_SF 38 +#define CLK_IFR_MSDC1_SF 39 +#define CLK_IFR_MSDC2_SF 40 +#define CLK_IFR_AP_MSDC0 41 +#define CLK_IFR_MD_MSDC0 42 +#define CLK_IFR_MSDC0_SRC 43 +#define CLK_IFR_MSDC1_SRC 44 +#define CLK_IFR_MSDC2_SRC 45 +#define CLK_IFR_PWRAP_TMR 46 +#define CLK_IFR_PWRAP_SPI 47 +#define CLK_IFR_PWRAP_SYS 48 +#define CLK_IFR_MCU_PM_BK 49 +#define CLK_IFR_IRRX_26M 50 +#define CLK_IFR_IRRX_32K 51 +#define CLK_IFR_I2C0_AXI 52 +#define CLK_IFR_I2C1_AXI 53 +#define CLK_IFR_I2C2_AXI 54 +#define CLK_IFR_I2C3_AXI 55 +#define CLK_IFR_NIC_AXI 56 +#define CLK_IFR_NIC_SLV_AXI 57 +#define CLK_IFR_APU_AXI 58 +#define CLK_IFR_NFIECC 59 +#define CLK_IFR_NFIECC_BK 60 +#define CLK_IFR_NFI1X_BK 61 +#define CLK_IFR_NFI_BK 62 +#define CLK_IFR_MSDC2_AP_BK 63 +#define CLK_IFR_MSDC2_MD_BK 64 +#define CLK_IFR_MSDC2_BK 65 +#define CLK_IFR_SUSB_133_BK 66 +#define CLK_IFR_SUSB_66_BK 67 +#define CLK_IFR_SSUSB_SYS 68 +#define CLK_IFR_SSUSB_REF 69 +#define CLK_IFR_SSUSB_XHCI 70 +#define CLK_IFR_NR_CLK 71 + +/* PERICFG */ +#define CLK_PERIAXI 0 +#define CLK_PERI_NR_CLK 1 + +/* APMIXEDSYS */ +#define CLK_APMIXED_ARMPLL 0 +#define CLK_APMIXED_MAINPLL 1 +#define CLK_APMIXED_UNIVPLL 2 +#define CLK_APMIXED_MFGPLL 3 +#define CLK_APMIXED_MSDCPLL 4 +#define CLK_APMIXED_MMPLL 5 +#define CLK_APMIXED_APLL1 6 +#define CLK_APMIXED_APLL2 7 +#define CLK_APMIXED_LVDSPLL 8 +#define CLK_APMIXED_DSPPLL 9 +#define CLK_APMIXED_APUPLL 10 +#define CLK_APMIXED_UNIV_EN 11 +#define CLK_APMIXED_USB20_EN 12 +#define CLK_APMIXED_NR_CLK 13 + +/* GCE */ +#define CLK_GCE_FAXI 0 +#define CLK_GCE_NR_CLK 1 + +/* AUDIOTOP */ +#define CLK_AUD_AFE 0 +#define CLK_AUD_I2S 1 +#define CLK_AUD_22M 2 +#define CLK_AUD_24M 3 +#define CLK_AUD_INTDIR 4 +#define CLK_AUD_APLL2_TUNER 5 +#define CLK_AUD_APLL_TUNER 6 +#define CLK_AUD_SPDF 7 +#define CLK_AUD_HDMI 8 +#define CLK_AUD_HDMI_IN 9 +#define CLK_AUD_ADC 10 +#define CLK_AUD_DAC 11 +#define CLK_AUD_DAC_PREDIS 12 +#define CLK_AUD_TML 13 +#define CLK_AUD_I2S1_BK 14 +#define CLK_AUD_I2S2_BK 15 +#define CLK_AUD_I2S3_BK 16 +#define CLK_AUD_I2S4_BK 17 +#define CLK_AUD_NR_CLK 18 + +/* MIPI_CSI0A */ +#define CLK_MIPI0A_CSR_CSI_EN_0A 0 +#define CLK_MIPI_RX_ANA_CSI0A_NR_CLK 1 + +/* MIPI_CSI0B */ +#define CLK_MIPI0B_CSR_CSI_EN_0B 0 +#define CLK_MIPI_RX_ANA_CSI0B_NR_CLK 1 + +/* MIPI_CSI1A */ +#define CLK_MIPI1A_CSR_CSI_EN_1A 0 +#define CLK_MIPI_RX_ANA_CSI1A_NR_CLK 1 + +/* MIPI_CSI1B */ +#define CLK_MIPI1B_CSR_CSI_EN_1B 0 +#define CLK_MIPI_RX_ANA_CSI1B_NR_CLK 1 + +/* MIPI_CSI2A */ +#define CLK_MIPI2A_CSR_CSI_EN_2A 0 +#define CLK_MIPI_RX_ANA_CSI2A_NR_CLK 1 + +/* MIPI_CSI2B */ +#define CLK_MIPI2B_CSR_CSI_EN_2B 0 +#define CLK_MIPI_RX_ANA_CSI2B_NR_CLK 1 + +/* MCUCFG */ +#define CLK_MCU_BUS_SEL 0 +#define CLK_MCU_NR_CLK 1 + +/* MFGCFG */ +#define CLK_MFG_BG3D 0 +#define CLK_MFG_MBIST_DIAG 1 +#define CLK_MFG_NR_CLK 2 + +/* MMSYS */ +#define CLK_MM_MM_MDP_RDMA0 0 +#define CLK_MM_MM_MDP_CCORR0 1 +#define CLK_MM_MM_MDP_RSZ0 2 +#define CLK_MM_MM_MDP_RSZ1 3 +#define CLK_MM_MM_MDP_TDSHP0 4 +#define CLK_MM_MM_MDP_WROT0 5 +#define CLK_MM_MM_MDP_WDMA0 6 +#define CLK_MM_MM_DISP_OVL0 7 +#define CLK_MM_MM_DISP_OVL0_2L 8 +#define CLK_MM_MM_DISP_RSZ0 9 +#define CLK_MM_MM_DISP_RDMA0 10 +#define CLK_MM_MM_DISP_WDMA0 11 +#define CLK_MM_MM_DISP_COLOR0 12 +#define CLK_MM_MM_DISP_CCORR0 13 +#define CLK_MM_MM_DISP_AAL0 14 +#define CLK_MM_MM_DISP_GAMMA0 15 +#define CLK_MM_MM_DISP_DITHER0 16 +#define CLK_MM_MM_DSI0 17 +#define CLK_MM_MM_DISP_RDMA1 18 +#define CLK_MM_MM_MDP_RDMA1 19 +#define CLK_MM_DPI0_DPI0 20 +#define CLK_MM_MM_FAKE 21 +#define CLK_MM_MM_SMI_COMMON 22 +#define CLK_MM_MM_SMI_LARB0 23 +#define CLK_MM_MM_SMI_COMM0 24 +#define CLK_MM_MM_SMI_COMM1 25 +#define CLK_MM_MM_CAM_MDP 26 +#define CLK_MM_MM_SMI_IMG 27 +#define CLK_MM_MM_SMI_CAM 28 +#define CLK_MM_IMG_IMG_DL_RELAY 29 +#define CLK_MM_IMG_IMG_DL_ASYNC_TOP 30 +#define CLK_MM_DSI0_DIG_DSI 31 +#define CLK_MM_26M_HRTWT 32 +#define CLK_MM_MM_DPI0 33 +#define CLK_MM_LVDSTX_PXL 34 +#define CLK_MM_LVDSTX_CTS 35 +#define CLK_MM_NR_CLK 36 + +/* IMGSYS */ +#define CLK_CAM_LARB2 0 +#define CLK_CAM 1 +#define CLK_CAMTG 2 +#define CLK_CAM_SENIF 3 +#define CLK_CAMSV0 4 +#define CLK_CAMSV1 5 +#define CLK_CAM_FDVT 6 +#define CLK_CAM_WPE 7 +#define CLK_CAM_NR_CLK 8 + +/* VDECSYS */ +#define CLK_VDEC_VDEC 0 +#define CLK_VDEC_LARB1 1 +#define CLK_VDEC_NR_CLK 2 + +/* VENCSYS */ +#define CLK_VENC 0 +#define CLK_VENC_JPGENC 1 +#define CLK_VENC_NR_CLK 2 + +/* APUSYS */ +#define CLK_APU_IPU_CK 0 +#define CLK_APU_AXI 1 +#define CLK_APU_JTAG 2 +#define CLK_APU_IF_CK 3 +#define CLK_APU_EDMA 4 +#define CLK_APU_AHB 5 +#define CLK_APU_NR_CLK 6 + +#endif /* _DT_BINDINGS_CLK_MT8365_H */ diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h index 68862aaf977e..78aa07fd7cc0 100644 --- a/include/dt-bindings/clock/meson8b-clkc.h +++ b/include/dt-bindings/clock/meson8b-clkc.h @@ -6,8 +6,6 @@ #ifndef __MESON8B_CLKC_H #define __MESON8B_CLKC_H -#define CLKID_UNUSED 0 -#define CLKID_XTAL 1 #define CLKID_PLL_FIXED 2 #define CLKID_PLL_VID 3 #define CLKID_PLL_SYS 4 @@ -107,6 +105,17 @@ #define CLKID_PERIPH 126 #define CLKID_AXI 128 #define CLKID_L2_DRAM 130 +#define CLKID_HDMI_PLL_HDMI_OUT 132 +#define CLKID_VID_PLL_FINAL_DIV 137 +#define CLKID_VCLK_IN_SEL 138 +#define CLKID_VCLK2_IN_SEL 149 +#define CLKID_CTS_ENCT 161 +#define CLKID_CTS_ENCP 163 +#define CLKID_CTS_ENCI 165 +#define CLKID_HDMI_TX_PIXEL 167 +#define CLKID_CTS_ENCL 169 +#define CLKID_CTS_VDAC0 171 +#define CLKID_HDMI_SYS 174 #define CLKID_VPU 190 #define CLKID_VDEC_1 196 #define CLKID_VDEC_HCODEC 199 diff --git a/include/dt-bindings/clock/microchip,lan966x.h b/include/dt-bindings/clock/microchip,lan966x.h new file mode 100644 index 000000000000..6f9d43d76d5a --- /dev/null +++ b/include/dt-bindings/clock/microchip,lan966x.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2021 Microchip Inc. + * + * Author: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com> + */ + +#ifndef _DT_BINDINGS_CLK_LAN966X_H +#define _DT_BINDINGS_CLK_LAN966X_H + +#define GCK_ID_QSPI0 0 +#define GCK_ID_QSPI1 1 +#define GCK_ID_QSPI2 2 +#define GCK_ID_SDMMC0 3 +#define GCK_ID_PI 4 +#define GCK_ID_MCAN0 5 +#define GCK_ID_MCAN1 6 +#define GCK_ID_FLEXCOM0 7 +#define GCK_ID_FLEXCOM1 8 +#define GCK_ID_FLEXCOM2 9 +#define GCK_ID_FLEXCOM3 10 +#define GCK_ID_FLEXCOM4 11 +#define GCK_ID_TIMER 12 +#define GCK_ID_USB_REFCLK 13 + +/* Gate clocks */ +#define GCK_GATE_UHPHS 14 +#define GCK_GATE_UDPHS 15 +#define GCK_GATE_MCRAMC 16 +#define GCK_GATE_HMATRIX 17 + +#define N_CLOCKS 18 + +#endif diff --git a/include/dt-bindings/clock/microchip,mpfs-clock.h b/include/dt-bindings/clock/microchip,mpfs-clock.h new file mode 100644 index 000000000000..79775a5134ca --- /dev/null +++ b/include/dt-bindings/clock/microchip,mpfs-clock.h @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Daire McNamara,<daire.mcnamara@microchip.com> + * Copyright (C) 2020-2022 Microchip Technology Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ +#define _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ + +#define CLK_CPU 0 +#define CLK_AXI 1 +#define CLK_AHB 2 + +#define CLK_ENVM 3 +#define CLK_MAC0 4 +#define CLK_MAC1 5 +#define CLK_MMC 6 +#define CLK_TIMER 7 +#define CLK_MMUART0 8 +#define CLK_MMUART1 9 +#define CLK_MMUART2 10 +#define CLK_MMUART3 11 +#define CLK_MMUART4 12 +#define CLK_SPI0 13 +#define CLK_SPI1 14 +#define CLK_I2C0 15 +#define CLK_I2C1 16 +#define CLK_CAN0 17 +#define CLK_CAN1 18 +#define CLK_USB 19 +#define CLK_RESERVED 20 +#define CLK_RTC 21 +#define CLK_QSPI 22 +#define CLK_GPIO0 23 +#define CLK_GPIO1 24 +#define CLK_GPIO2 25 +#define CLK_DDRC 26 +#define CLK_FIC0 27 +#define CLK_FIC1 28 +#define CLK_FIC2 29 +#define CLK_FIC3 30 +#define CLK_ATHENA 31 +#define CLK_CFM 32 + +#define CLK_RTCREF 33 +#define CLK_MSSPLL 34 + +/* Clock Conditioning Circuitry Clock IDs */ + +#define CLK_CCC_PLL0 0 +#define CLK_CCC_PLL1 1 +#define CLK_CCC_DLL0 2 +#define CLK_CCC_DLL1 3 + +#define CLK_CCC_PLL0_OUT0 4 +#define CLK_CCC_PLL0_OUT1 5 +#define CLK_CCC_PLL0_OUT2 6 +#define CLK_CCC_PLL0_OUT3 7 + +#define CLK_CCC_PLL1_OUT0 8 +#define CLK_CCC_PLL1_OUT1 9 +#define CLK_CCC_PLL1_OUT2 10 +#define CLK_CCC_PLL1_OUT3 11 + +#define CLK_CCC_DLL0_OUT0 12 +#define CLK_CCC_DLL0_OUT1 13 + +#define CLK_CCC_DLL1_OUT0 14 +#define CLK_CCC_DLL1_OUT1 15 + +#endif /* _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ */ diff --git a/include/dt-bindings/clock/microchip,sparx5.h b/include/dt-bindings/clock/microchip,sparx5.h new file mode 100644 index 000000000000..4b04dabacec2 --- /dev/null +++ b/include/dt-bindings/clock/microchip,sparx5.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019 Microchip Inc. + * + * Author: Lars Povlsen <lars.povlsen@microchip.com> + */ + +#ifndef _DT_BINDINGS_CLK_SPARX5_H +#define _DT_BINDINGS_CLK_SPARX5_H + +#define CLK_ID_CORE 0 +#define CLK_ID_DDR 1 +#define CLK_ID_CPU2 2 +#define CLK_ID_ARM2 3 +#define CLK_ID_AUX1 4 +#define CLK_ID_AUX2 5 +#define CLK_ID_AUX3 6 +#define CLK_ID_AUX4 7 +#define CLK_ID_SYNCE 8 + +#define N_CLOCKS 9 + +#endif diff --git a/include/dt-bindings/clock/mstar-msc313-mpll.h b/include/dt-bindings/clock/mstar-msc313-mpll.h new file mode 100644 index 000000000000..1b30b02317b6 --- /dev/null +++ b/include/dt-bindings/clock/mstar-msc313-mpll.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Output definitions for the MStar/SigmaStar MPLL + * + * Copyright (C) 2020 Daniel Palmer <daniel@thingy.jp> + */ + +#ifndef _DT_BINDINGS_CLOCK_MSTAR_MSC313_MPLL_H +#define _DT_BINDINGS_CLOCK_MSTAR_MSC313_MPLL_H + +#define MSTAR_MSC313_MPLL_DIV2 1 +#define MSTAR_MSC313_MPLL_DIV3 2 +#define MSTAR_MSC313_MPLL_DIV4 3 +#define MSTAR_MSC313_MPLL_DIV5 4 +#define MSTAR_MSC313_MPLL_DIV6 5 +#define MSTAR_MSC313_MPLL_DIV7 6 +#define MSTAR_MSC313_MPLL_DIV10 7 + +#endif diff --git a/include/dt-bindings/clock/mt6765-clk.h b/include/dt-bindings/clock/mt6765-clk.h new file mode 100644 index 000000000000..eb97e568518e --- /dev/null +++ b/include/dt-bindings/clock/mt6765-clk.h @@ -0,0 +1,313 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef _DT_BINDINGS_CLK_MT6765_H +#define _DT_BINDINGS_CLK_MT6765_H + +/* FIX Clks */ +#define CLK_TOP_CLK26M 0 + +/* APMIXEDSYS */ +#define CLK_APMIXED_ARMPLL_L 0 +#define CLK_APMIXED_ARMPLL 1 +#define CLK_APMIXED_CCIPLL 2 +#define CLK_APMIXED_MAINPLL 3 +#define CLK_APMIXED_MFGPLL 4 +#define CLK_APMIXED_MMPLL 5 +#define CLK_APMIXED_UNIV2PLL 6 +#define CLK_APMIXED_MSDCPLL 7 +#define CLK_APMIXED_APLL1 8 +#define CLK_APMIXED_MPLL 9 +#define CLK_APMIXED_ULPOSC1 10 +#define CLK_APMIXED_ULPOSC2 11 +#define CLK_APMIXED_SSUSB26M 12 +#define CLK_APMIXED_APPLL26M 13 +#define CLK_APMIXED_MIPIC0_26M 14 +#define CLK_APMIXED_MDPLLGP26M 15 +#define CLK_APMIXED_MMSYS_F26M 16 +#define CLK_APMIXED_UFS26M 17 +#define CLK_APMIXED_MIPIC1_26M 18 +#define CLK_APMIXED_MEMPLL26M 19 +#define CLK_APMIXED_CLKSQ_LVPLL_26M 20 +#define CLK_APMIXED_MIPID0_26M 21 +#define CLK_APMIXED_NR_CLK 22 + +/* TOPCKGEN */ +#define CLK_TOP_SYSPLL 0 +#define CLK_TOP_SYSPLL_D2 1 +#define CLK_TOP_SYSPLL1_D2 2 +#define CLK_TOP_SYSPLL1_D4 3 +#define CLK_TOP_SYSPLL1_D8 4 +#define CLK_TOP_SYSPLL1_D16 5 +#define CLK_TOP_SYSPLL_D3 6 +#define CLK_TOP_SYSPLL2_D2 7 +#define CLK_TOP_SYSPLL2_D4 8 +#define CLK_TOP_SYSPLL2_D8 9 +#define CLK_TOP_SYSPLL_D5 10 +#define CLK_TOP_SYSPLL3_D2 11 +#define CLK_TOP_SYSPLL3_D4 12 +#define CLK_TOP_SYSPLL_D7 13 +#define CLK_TOP_SYSPLL4_D2 14 +#define CLK_TOP_SYSPLL4_D4 15 +#define CLK_TOP_USB20_192M 16 +#define CLK_TOP_USB20_192M_D4 17 +#define CLK_TOP_USB20_192M_D8 18 +#define CLK_TOP_USB20_192M_D16 19 +#define CLK_TOP_USB20_192M_D32 20 +#define CLK_TOP_UNIVPLL 21 +#define CLK_TOP_UNIVPLL_D2 22 +#define CLK_TOP_UNIVPLL1_D2 23 +#define CLK_TOP_UNIVPLL1_D4 24 +#define CLK_TOP_UNIVPLL_D3 25 +#define CLK_TOP_UNIVPLL2_D2 26 +#define CLK_TOP_UNIVPLL2_D4 27 +#define CLK_TOP_UNIVPLL2_D8 28 +#define CLK_TOP_UNIVPLL2_D32 29 +#define CLK_TOP_UNIVPLL_D5 30 +#define CLK_TOP_UNIVPLL3_D2 31 +#define CLK_TOP_UNIVPLL3_D4 32 +#define CLK_TOP_MMPLL 33 +#define CLK_TOP_MMPLL_D2 34 +#define CLK_TOP_MPLL 35 +#define CLK_TOP_DA_MPLL_104M_DIV 36 +#define CLK_TOP_DA_MPLL_52M_DIV 37 +#define CLK_TOP_MFGPLL 38 +#define CLK_TOP_MSDCPLL 39 +#define CLK_TOP_MSDCPLL_D2 40 +#define CLK_TOP_APLL1 41 +#define CLK_TOP_APLL1_D2 42 +#define CLK_TOP_APLL1_D4 43 +#define CLK_TOP_APLL1_D8 44 +#define CLK_TOP_ULPOSC1 45 +#define CLK_TOP_ULPOSC1_D2 46 +#define CLK_TOP_ULPOSC1_D4 47 +#define CLK_TOP_ULPOSC1_D8 48 +#define CLK_TOP_ULPOSC1_D16 49 +#define CLK_TOP_ULPOSC1_D32 50 +#define CLK_TOP_DMPLL 51 +#define CLK_TOP_F_FRTC 52 +#define CLK_TOP_F_F26M 53 +#define CLK_TOP_AXI 54 +#define CLK_TOP_MM 55 +#define CLK_TOP_SCP 56 +#define CLK_TOP_MFG 57 +#define CLK_TOP_F_FUART 58 +#define CLK_TOP_SPI 59 +#define CLK_TOP_MSDC50_0 60 +#define CLK_TOP_MSDC30_1 61 +#define CLK_TOP_AUDIO 62 +#define CLK_TOP_AUD_1 63 +#define CLK_TOP_AUD_ENGEN1 64 +#define CLK_TOP_F_FDISP_PWM 65 +#define CLK_TOP_SSPM 66 +#define CLK_TOP_DXCC 67 +#define CLK_TOP_I2C 68 +#define CLK_TOP_F_FPWM 69 +#define CLK_TOP_F_FSENINF 70 +#define CLK_TOP_AES_FDE 71 +#define CLK_TOP_F_BIST2FPC 72 +#define CLK_TOP_ARMPLL_DIVIDER_PLL0 73 +#define CLK_TOP_ARMPLL_DIVIDER_PLL1 74 +#define CLK_TOP_ARMPLL_DIVIDER_PLL2 75 +#define CLK_TOP_DA_USB20_48M_DIV 76 +#define CLK_TOP_DA_UNIV_48M_DIV 77 +#define CLK_TOP_APLL12_DIV0 78 +#define CLK_TOP_APLL12_DIV1 79 +#define CLK_TOP_APLL12_DIV2 80 +#define CLK_TOP_APLL12_DIV3 81 +#define CLK_TOP_ARMPLL_DIVIDER_PLL0_EN 82 +#define CLK_TOP_ARMPLL_DIVIDER_PLL1_EN 83 +#define CLK_TOP_ARMPLL_DIVIDER_PLL2_EN 84 +#define CLK_TOP_FMEM_OCC_DRC_EN 85 +#define CLK_TOP_USB20_48M_EN 86 +#define CLK_TOP_UNIVPLL_48M_EN 87 +#define CLK_TOP_MPLL_104M_EN 88 +#define CLK_TOP_MPLL_52M_EN 89 +#define CLK_TOP_F_UFS_MP_SAP_CFG_EN 90 +#define CLK_TOP_F_BIST2FPC_EN 91 +#define CLK_TOP_MD_32K 92 +#define CLK_TOP_MD_26M 93 +#define CLK_TOP_MD2_32K 94 +#define CLK_TOP_MD2_26M 95 +#define CLK_TOP_AXI_SEL 96 +#define CLK_TOP_MEM_SEL 97 +#define CLK_TOP_MM_SEL 98 +#define CLK_TOP_SCP_SEL 99 +#define CLK_TOP_MFG_SEL 100 +#define CLK_TOP_ATB_SEL 101 +#define CLK_TOP_CAMTG_SEL 102 +#define CLK_TOP_CAMTG1_SEL 103 +#define CLK_TOP_CAMTG2_SEL 104 +#define CLK_TOP_CAMTG3_SEL 105 +#define CLK_TOP_UART_SEL 106 +#define CLK_TOP_SPI_SEL 107 +#define CLK_TOP_MSDC50_0_HCLK_SEL 108 +#define CLK_TOP_MSDC50_0_SEL 109 +#define CLK_TOP_MSDC30_1_SEL 110 +#define CLK_TOP_AUDIO_SEL 111 +#define CLK_TOP_AUD_INTBUS_SEL 112 +#define CLK_TOP_AUD_1_SEL 113 +#define CLK_TOP_AUD_ENGEN1_SEL 114 +#define CLK_TOP_DISP_PWM_SEL 115 +#define CLK_TOP_SSPM_SEL 116 +#define CLK_TOP_DXCC_SEL 117 +#define CLK_TOP_USB_TOP_SEL 118 +#define CLK_TOP_SPM_SEL 119 +#define CLK_TOP_I2C_SEL 120 +#define CLK_TOP_PWM_SEL 121 +#define CLK_TOP_SENINF_SEL 122 +#define CLK_TOP_AES_FDE_SEL 123 +#define CLK_TOP_PWRAP_ULPOSC_SEL 124 +#define CLK_TOP_CAMTM_SEL 125 +#define CLK_TOP_NR_CLK 126 + +/* INFRACFG */ +#define CLK_IFR_ICUSB 0 +#define CLK_IFR_GCE 1 +#define CLK_IFR_THERM 2 +#define CLK_IFR_I2C_AP 3 +#define CLK_IFR_I2C_CCU 4 +#define CLK_IFR_I2C_SSPM 5 +#define CLK_IFR_I2C_RSV 6 +#define CLK_IFR_PWM_HCLK 7 +#define CLK_IFR_PWM1 8 +#define CLK_IFR_PWM2 9 +#define CLK_IFR_PWM3 10 +#define CLK_IFR_PWM4 11 +#define CLK_IFR_PWM5 12 +#define CLK_IFR_PWM 13 +#define CLK_IFR_UART0 14 +#define CLK_IFR_UART1 15 +#define CLK_IFR_GCE_26M 16 +#define CLK_IFR_CQ_DMA_FPC 17 +#define CLK_IFR_BTIF 18 +#define CLK_IFR_SPI0 19 +#define CLK_IFR_MSDC0 20 +#define CLK_IFR_MSDC1 21 +#define CLK_IFR_TRNG 22 +#define CLK_IFR_AUXADC 23 +#define CLK_IFR_CCIF1_AP 24 +#define CLK_IFR_CCIF1_MD 25 +#define CLK_IFR_AUXADC_MD 26 +#define CLK_IFR_AP_DMA 27 +#define CLK_IFR_DEVICE_APC 28 +#define CLK_IFR_CCIF_AP 29 +#define CLK_IFR_AUDIO 30 +#define CLK_IFR_CCIF_MD 31 +#define CLK_IFR_RG_PWM_FBCLK6 32 +#define CLK_IFR_DISP_PWM 33 +#define CLK_IFR_CLDMA_BCLK 34 +#define CLK_IFR_AUDIO_26M_BCLK 35 +#define CLK_IFR_SPI1 36 +#define CLK_IFR_I2C4 37 +#define CLK_IFR_SPI2 38 +#define CLK_IFR_SPI3 39 +#define CLK_IFR_I2C5 40 +#define CLK_IFR_I2C5_ARBITER 41 +#define CLK_IFR_I2C5_IMM 42 +#define CLK_IFR_I2C1_ARBITER 43 +#define CLK_IFR_I2C1_IMM 44 +#define CLK_IFR_I2C2_ARBITER 45 +#define CLK_IFR_I2C2_IMM 46 +#define CLK_IFR_SPI4 47 +#define CLK_IFR_SPI5 48 +#define CLK_IFR_CQ_DMA 49 +#define CLK_IFR_FAES_FDE 50 +#define CLK_IFR_MSDC0_SELF 51 +#define CLK_IFR_MSDC1_SELF 52 +#define CLK_IFR_I2C6 53 +#define CLK_IFR_AP_MSDC0 54 +#define CLK_IFR_MD_MSDC0 55 +#define CLK_IFR_MSDC0_SRC 56 +#define CLK_IFR_MSDC1_SRC 57 +#define CLK_IFR_AES_TOP0_BCLK 58 +#define CLK_IFR_MCU_PM_BCLK 59 +#define CLK_IFR_CCIF2_AP 60 +#define CLK_IFR_CCIF2_MD 61 +#define CLK_IFR_CCIF3_AP 62 +#define CLK_IFR_CCIF3_MD 63 +#define CLK_IFR_NR_CLK 64 + +/* AUDIO */ +#define CLK_AUDIO_AFE 0 +#define CLK_AUDIO_22M 1 +#define CLK_AUDIO_APLL_TUNER 2 +#define CLK_AUDIO_ADC 3 +#define CLK_AUDIO_DAC 4 +#define CLK_AUDIO_DAC_PREDIS 5 +#define CLK_AUDIO_TML 6 +#define CLK_AUDIO_I2S1_BCLK 7 +#define CLK_AUDIO_I2S2_BCLK 8 +#define CLK_AUDIO_I2S3_BCLK 9 +#define CLK_AUDIO_I2S4_BCLK 10 +#define CLK_AUDIO_NR_CLK 11 + +/* MIPI_RX_ANA_CSI0A */ + +#define CLK_MIPI0A_CSR_CSI_EN_0A 0 +#define CLK_MIPI0A_NR_CLK 1 + +/* MMSYS_CONFIG */ + +#define CLK_MM_MDP_RDMA0 0 +#define CLK_MM_MDP_CCORR0 1 +#define CLK_MM_MDP_RSZ0 2 +#define CLK_MM_MDP_RSZ1 3 +#define CLK_MM_MDP_TDSHP0 4 +#define CLK_MM_MDP_WROT0 5 +#define CLK_MM_MDP_WDMA0 6 +#define CLK_MM_DISP_OVL0 7 +#define CLK_MM_DISP_OVL0_2L 8 +#define CLK_MM_DISP_RSZ0 9 +#define CLK_MM_DISP_RDMA0 10 +#define CLK_MM_DISP_WDMA0 11 +#define CLK_MM_DISP_COLOR0 12 +#define CLK_MM_DISP_CCORR0 13 +#define CLK_MM_DISP_AAL0 14 +#define CLK_MM_DISP_GAMMA0 15 +#define CLK_MM_DISP_DITHER0 16 +#define CLK_MM_DSI0 17 +#define CLK_MM_FAKE_ENG 18 +#define CLK_MM_SMI_COMMON 19 +#define CLK_MM_SMI_LARB0 20 +#define CLK_MM_SMI_COMM0 21 +#define CLK_MM_SMI_COMM1 22 +#define CLK_MM_CAM_MDP 23 +#define CLK_MM_SMI_IMG 24 +#define CLK_MM_SMI_CAM 25 +#define CLK_MM_IMG_DL_RELAY 26 +#define CLK_MM_IMG_DL_ASYNC_TOP 27 +#define CLK_MM_DIG_DSI 28 +#define CLK_MM_F26M_HRTWT 29 +#define CLK_MM_NR_CLK 30 + +/* IMGSYS */ + +#define CLK_IMG_LARB2 0 +#define CLK_IMG_DIP 1 +#define CLK_IMG_FDVT 2 +#define CLK_IMG_DPE 3 +#define CLK_IMG_RSC 4 +#define CLK_IMG_NR_CLK 5 + +/* VENCSYS */ + +#define CLK_VENC_SET0_LARB 0 +#define CLK_VENC_SET1_VENC 1 +#define CLK_VENC_SET2_JPGENC 2 +#define CLK_VENC_SET3_VDEC 3 +#define CLK_VENC_NR_CLK 4 + +/* CAMSYS */ + +#define CLK_CAM_LARB3 0 +#define CLK_CAM_DFP_VAD 1 +#define CLK_CAM 2 +#define CLK_CAMTG 3 +#define CLK_CAM_SENINF 4 +#define CLK_CAMSV0 5 +#define CLK_CAMSV1 6 +#define CLK_CAMSV2 7 +#define CLK_CAM_CCU 8 +#define CLK_CAM_NR_CLK 9 + +#endif /* _DT_BINDINGS_CLK_MT6765_H */ diff --git a/include/dt-bindings/clock/mt7621-clk.h b/include/dt-bindings/clock/mt7621-clk.h new file mode 100644 index 000000000000..1422badcf9de --- /dev/null +++ b/include/dt-bindings/clock/mt7621-clk.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Author: Sergio Paracuellos <sergio.paracuellos@gmail.com> + */ + +#ifndef _DT_BINDINGS_CLK_MT7621_H +#define _DT_BINDINGS_CLK_MT7621_H + +#define MT7621_CLK_XTAL 0 +#define MT7621_CLK_CPU 1 +#define MT7621_CLK_BUS 2 +#define MT7621_CLK_50M 3 +#define MT7621_CLK_125M 4 +#define MT7621_CLK_150M 5 +#define MT7621_CLK_250M 6 +#define MT7621_CLK_270M 7 + +#define MT7621_CLK_HSDMA 8 +#define MT7621_CLK_FE 9 +#define MT7621_CLK_SP_DIVTX 10 +#define MT7621_CLK_TIMER 11 +#define MT7621_CLK_PCM 12 +#define MT7621_CLK_PIO 13 +#define MT7621_CLK_GDMA 14 +#define MT7621_CLK_NAND 15 +#define MT7621_CLK_I2C 16 +#define MT7621_CLK_I2S 17 +#define MT7621_CLK_SPI 18 +#define MT7621_CLK_UART1 19 +#define MT7621_CLK_UART2 20 +#define MT7621_CLK_UART3 21 +#define MT7621_CLK_ETH 22 +#define MT7621_CLK_PCIE0 23 +#define MT7621_CLK_PCIE1 24 +#define MT7621_CLK_PCIE2 25 +#define MT7621_CLK_CRYPTO 26 +#define MT7621_CLK_SHXC 27 + +#define MT7621_CLK_MAX 28 + +#endif /* _DT_BINDINGS_CLK_MT7621_H */ diff --git a/include/dt-bindings/clock/mt7986-clk.h b/include/dt-bindings/clock/mt7986-clk.h new file mode 100644 index 000000000000..5a9b169324b0 --- /dev/null +++ b/include/dt-bindings/clock/mt7986-clk.h @@ -0,0 +1,169 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2021 MediaTek Inc. + * Author: Sam Shih <sam.shih@mediatek.com> + */ + +#ifndef _DT_BINDINGS_CLK_MT7986_H +#define _DT_BINDINGS_CLK_MT7986_H + +/* APMIXEDSYS */ + +#define CLK_APMIXED_ARMPLL 0 +#define CLK_APMIXED_NET2PLL 1 +#define CLK_APMIXED_MMPLL 2 +#define CLK_APMIXED_SGMPLL 3 +#define CLK_APMIXED_WEDMCUPLL 4 +#define CLK_APMIXED_NET1PLL 5 +#define CLK_APMIXED_MPLL 6 +#define CLK_APMIXED_APLL2 7 + +/* TOPCKGEN */ + +#define CLK_TOP_XTAL 0 +#define CLK_TOP_XTAL_D2 1 +#define CLK_TOP_RTC_32K 2 +#define CLK_TOP_RTC_32P7K 3 +#define CLK_TOP_MPLL_D2 4 +#define CLK_TOP_MPLL_D4 5 +#define CLK_TOP_MPLL_D8 6 +#define CLK_TOP_MPLL_D8_D2 7 +#define CLK_TOP_MPLL_D3_D2 8 +#define CLK_TOP_MMPLL_D2 9 +#define CLK_TOP_MMPLL_D4 10 +#define CLK_TOP_MMPLL_D8 11 +#define CLK_TOP_MMPLL_D8_D2 12 +#define CLK_TOP_MMPLL_D3_D8 13 +#define CLK_TOP_MMPLL_U2PHY 14 +#define CLK_TOP_APLL2_D4 15 +#define CLK_TOP_NET1PLL_D4 16 +#define CLK_TOP_NET1PLL_D5 17 +#define CLK_TOP_NET1PLL_D5_D2 18 +#define CLK_TOP_NET1PLL_D5_D4 19 +#define CLK_TOP_NET1PLL_D8_D2 20 +#define CLK_TOP_NET1PLL_D8_D4 21 +#define CLK_TOP_NET2PLL_D4 22 +#define CLK_TOP_NET2PLL_D4_D2 23 +#define CLK_TOP_NET2PLL_D3_D2 24 +#define CLK_TOP_WEDMCUPLL_D5_D2 25 +#define CLK_TOP_NFI1X_SEL 26 +#define CLK_TOP_SPINFI_SEL 27 +#define CLK_TOP_SPI_SEL 28 +#define CLK_TOP_SPIM_MST_SEL 29 +#define CLK_TOP_UART_SEL 30 +#define CLK_TOP_PWM_SEL 31 +#define CLK_TOP_I2C_SEL 32 +#define CLK_TOP_PEXTP_TL_SEL 33 +#define CLK_TOP_EMMC_250M_SEL 34 +#define CLK_TOP_EMMC_416M_SEL 35 +#define CLK_TOP_F_26M_ADC_SEL 36 +#define CLK_TOP_DRAMC_SEL 37 +#define CLK_TOP_DRAMC_MD32_SEL 38 +#define CLK_TOP_SYSAXI_SEL 39 +#define CLK_TOP_SYSAPB_SEL 40 +#define CLK_TOP_ARM_DB_MAIN_SEL 41 +#define CLK_TOP_ARM_DB_JTSEL 42 +#define CLK_TOP_NETSYS_SEL 43 +#define CLK_TOP_NETSYS_500M_SEL 44 +#define CLK_TOP_NETSYS_MCU_SEL 45 +#define CLK_TOP_NETSYS_2X_SEL 46 +#define CLK_TOP_SGM_325M_SEL 47 +#define CLK_TOP_SGM_REG_SEL 48 +#define CLK_TOP_A1SYS_SEL 49 +#define CLK_TOP_CONN_MCUSYS_SEL 50 +#define CLK_TOP_EIP_B_SEL 51 +#define CLK_TOP_PCIE_PHY_SEL 52 +#define CLK_TOP_USB3_PHY_SEL 53 +#define CLK_TOP_F26M_SEL 54 +#define CLK_TOP_AUD_L_SEL 55 +#define CLK_TOP_A_TUNER_SEL 56 +#define CLK_TOP_U2U3_SEL 57 +#define CLK_TOP_U2U3_SYS_SEL 58 +#define CLK_TOP_U2U3_XHCI_SEL 59 +#define CLK_TOP_DA_U2_REFSEL 60 +#define CLK_TOP_DA_U2_CK_1P_SEL 61 +#define CLK_TOP_AP2CNN_HOST_SEL 62 +#define CLK_TOP_JTAG 63 + +/* INFRACFG */ + +#define CLK_INFRA_SYSAXI_D2 0 +#define CLK_INFRA_UART0_SEL 1 +#define CLK_INFRA_UART1_SEL 2 +#define CLK_INFRA_UART2_SEL 3 +#define CLK_INFRA_SPI0_SEL 4 +#define CLK_INFRA_SPI1_SEL 5 +#define CLK_INFRA_PWM1_SEL 6 +#define CLK_INFRA_PWM2_SEL 7 +#define CLK_INFRA_PWM_BSEL 8 +#define CLK_INFRA_PCIE_SEL 9 +#define CLK_INFRA_GPT_STA 10 +#define CLK_INFRA_PWM_HCK 11 +#define CLK_INFRA_PWM_STA 12 +#define CLK_INFRA_PWM1_CK 13 +#define CLK_INFRA_PWM2_CK 14 +#define CLK_INFRA_CQ_DMA_CK 15 +#define CLK_INFRA_EIP97_CK 16 +#define CLK_INFRA_AUD_BUS_CK 17 +#define CLK_INFRA_AUD_26M_CK 18 +#define CLK_INFRA_AUD_L_CK 19 +#define CLK_INFRA_AUD_AUD_CK 20 +#define CLK_INFRA_AUD_EG2_CK 21 +#define CLK_INFRA_DRAMC_26M_CK 22 +#define CLK_INFRA_DBG_CK 23 +#define CLK_INFRA_AP_DMA_CK 24 +#define CLK_INFRA_SEJ_CK 25 +#define CLK_INFRA_SEJ_13M_CK 26 +#define CLK_INFRA_THERM_CK 27 +#define CLK_INFRA_I2C0_CK 28 +#define CLK_INFRA_UART0_CK 29 +#define CLK_INFRA_UART1_CK 30 +#define CLK_INFRA_UART2_CK 31 +#define CLK_INFRA_NFI1_CK 32 +#define CLK_INFRA_SPINFI1_CK 33 +#define CLK_INFRA_NFI_HCK_CK 34 +#define CLK_INFRA_SPI0_CK 35 +#define CLK_INFRA_SPI1_CK 36 +#define CLK_INFRA_SPI0_HCK_CK 37 +#define CLK_INFRA_SPI1_HCK_CK 38 +#define CLK_INFRA_FRTC_CK 39 +#define CLK_INFRA_MSDC_CK 40 +#define CLK_INFRA_MSDC_HCK_CK 41 +#define CLK_INFRA_MSDC_133M_CK 42 +#define CLK_INFRA_MSDC_66M_CK 43 +#define CLK_INFRA_ADC_26M_CK 44 +#define CLK_INFRA_ADC_FRC_CK 45 +#define CLK_INFRA_FBIST2FPC_CK 46 +#define CLK_INFRA_IUSB_133_CK 47 +#define CLK_INFRA_IUSB_66M_CK 48 +#define CLK_INFRA_IUSB_SYS_CK 49 +#define CLK_INFRA_IUSB_CK 50 +#define CLK_INFRA_IPCIE_CK 51 +#define CLK_INFRA_IPCIE_PIPE_CK 52 +#define CLK_INFRA_IPCIER_CK 53 +#define CLK_INFRA_IPCIEB_CK 54 +#define CLK_INFRA_TRNG_CK 55 + +/* SGMIISYS_0 */ + +#define CLK_SGMII0_TX250M_EN 0 +#define CLK_SGMII0_RX250M_EN 1 +#define CLK_SGMII0_CDR_REF 2 +#define CLK_SGMII0_CDR_FB 3 + +/* SGMIISYS_1 */ + +#define CLK_SGMII1_TX250M_EN 0 +#define CLK_SGMII1_RX250M_EN 1 +#define CLK_SGMII1_CDR_REF 2 +#define CLK_SGMII1_CDR_FB 3 + +/* ETHSYS */ + +#define CLK_ETH_FE_EN 0 +#define CLK_ETH_GP2_EN 1 +#define CLK_ETH_GP1_EN 2 +#define CLK_ETH_WOCPU1_EN 3 +#define CLK_ETH_WOCPU0_EN 4 + +#endif /* _DT_BINDINGS_CLK_MT7986_H */ diff --git a/include/dt-bindings/clock/mt8167-clk.h b/include/dt-bindings/clock/mt8167-clk.h new file mode 100644 index 000000000000..a96158edd817 --- /dev/null +++ b/include/dt-bindings/clock/mt8167-clk.h @@ -0,0 +1,131 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 MediaTek Inc. + * Copyright (c) 2020 BayLibre, SAS. + * Author: James Liao <jamesjj.liao@mediatek.com> + * Fabien Parent <fparent@baylibre.com> + */ + +#ifndef _DT_BINDINGS_CLK_MT8167_H +#define _DT_BINDINGS_CLK_MT8167_H + +/* MT8167 is based on MT8516 */ +#include <dt-bindings/clock/mt8516-clk.h> + +/* APMIXEDSYS */ + +#define CLK_APMIXED_TVDPLL (CLK_APMIXED_NR_CLK + 0) +#define CLK_APMIXED_LVDSPLL (CLK_APMIXED_NR_CLK + 1) +#define CLK_APMIXED_HDMI_REF (CLK_APMIXED_NR_CLK + 2) +#define MT8167_CLK_APMIXED_NR_CLK (CLK_APMIXED_NR_CLK + 3) + +/* TOPCKGEN */ + +#define CLK_TOP_DSI0_LNTC_DSICK (CLK_TOP_NR_CLK + 0) +#define CLK_TOP_VPLL_DPIX (CLK_TOP_NR_CLK + 1) +#define CLK_TOP_LVDSTX_CLKDIG_CTS (CLK_TOP_NR_CLK + 2) +#define CLK_TOP_HDMTX_CLKDIG_CTS (CLK_TOP_NR_CLK + 3) +#define CLK_TOP_LVDSPLL (CLK_TOP_NR_CLK + 4) +#define CLK_TOP_LVDSPLL_D2 (CLK_TOP_NR_CLK + 5) +#define CLK_TOP_LVDSPLL_D4 (CLK_TOP_NR_CLK + 6) +#define CLK_TOP_LVDSPLL_D8 (CLK_TOP_NR_CLK + 7) +#define CLK_TOP_MIPI_26M (CLK_TOP_NR_CLK + 8) +#define CLK_TOP_TVDPLL (CLK_TOP_NR_CLK + 9) +#define CLK_TOP_TVDPLL_D2 (CLK_TOP_NR_CLK + 10) +#define CLK_TOP_TVDPLL_D4 (CLK_TOP_NR_CLK + 11) +#define CLK_TOP_TVDPLL_D8 (CLK_TOP_NR_CLK + 12) +#define CLK_TOP_TVDPLL_D16 (CLK_TOP_NR_CLK + 13) +#define CLK_TOP_PWM_MM (CLK_TOP_NR_CLK + 14) +#define CLK_TOP_CAM_MM (CLK_TOP_NR_CLK + 15) +#define CLK_TOP_MFG_MM (CLK_TOP_NR_CLK + 16) +#define CLK_TOP_SPM_52M (CLK_TOP_NR_CLK + 17) +#define CLK_TOP_MIPI_26M_DBG (CLK_TOP_NR_CLK + 18) +#define CLK_TOP_SCAM_MM (CLK_TOP_NR_CLK + 19) +#define CLK_TOP_SMI_MM (CLK_TOP_NR_CLK + 20) +#define CLK_TOP_26M_HDMI_SIFM (CLK_TOP_NR_CLK + 21) +#define CLK_TOP_26M_CEC (CLK_TOP_NR_CLK + 22) +#define CLK_TOP_32K_CEC (CLK_TOP_NR_CLK + 23) +#define CLK_TOP_GCPU_B (CLK_TOP_NR_CLK + 24) +#define CLK_TOP_RG_VDEC (CLK_TOP_NR_CLK + 25) +#define CLK_TOP_RG_FDPI0 (CLK_TOP_NR_CLK + 26) +#define CLK_TOP_RG_FDPI1 (CLK_TOP_NR_CLK + 27) +#define CLK_TOP_RG_AXI_MFG (CLK_TOP_NR_CLK + 28) +#define CLK_TOP_RG_SLOW_MFG (CLK_TOP_NR_CLK + 29) +#define CLK_TOP_GFMUX_EMI1X_SEL (CLK_TOP_NR_CLK + 30) +#define CLK_TOP_CSW_MUX_MFG_SEL (CLK_TOP_NR_CLK + 31) +#define CLK_TOP_CAMTG_MM_SEL (CLK_TOP_NR_CLK + 32) +#define CLK_TOP_PWM_MM_SEL (CLK_TOP_NR_CLK + 33) +#define CLK_TOP_SPM_52M_SEL (CLK_TOP_NR_CLK + 34) +#define CLK_TOP_MFG_MM_SEL (CLK_TOP_NR_CLK + 35) +#define CLK_TOP_SMI_MM_SEL (CLK_TOP_NR_CLK + 36) +#define CLK_TOP_SCAM_MM_SEL (CLK_TOP_NR_CLK + 37) +#define CLK_TOP_VDEC_MM_SEL (CLK_TOP_NR_CLK + 38) +#define CLK_TOP_DPI0_MM_SEL (CLK_TOP_NR_CLK + 39) +#define CLK_TOP_DPI1_MM_SEL (CLK_TOP_NR_CLK + 40) +#define CLK_TOP_AXI_MFG_IN_SEL (CLK_TOP_NR_CLK + 41) +#define CLK_TOP_SLOW_MFG_SEL (CLK_TOP_NR_CLK + 42) +#define MT8167_CLK_TOP_NR_CLK (CLK_TOP_NR_CLK + 43) + +/* MFGCFG */ + +#define CLK_MFG_BAXI 0 +#define CLK_MFG_BMEM 1 +#define CLK_MFG_BG3D 2 +#define CLK_MFG_B26M 3 +#define CLK_MFG_NR_CLK 4 + +/* MMSYS */ + +#define CLK_MM_SMI_COMMON 0 +#define CLK_MM_SMI_LARB0 1 +#define CLK_MM_CAM_MDP 2 +#define CLK_MM_MDP_RDMA 3 +#define CLK_MM_MDP_RSZ0 4 +#define CLK_MM_MDP_RSZ1 5 +#define CLK_MM_MDP_TDSHP 6 +#define CLK_MM_MDP_WDMA 7 +#define CLK_MM_MDP_WROT 8 +#define CLK_MM_FAKE_ENG 9 +#define CLK_MM_DISP_OVL0 10 +#define CLK_MM_DISP_RDMA0 11 +#define CLK_MM_DISP_RDMA1 12 +#define CLK_MM_DISP_WDMA 13 +#define CLK_MM_DISP_COLOR 14 +#define CLK_MM_DISP_CCORR 15 +#define CLK_MM_DISP_AAL 16 +#define CLK_MM_DISP_GAMMA 17 +#define CLK_MM_DISP_DITHER 18 +#define CLK_MM_DISP_UFOE 19 +#define CLK_MM_DISP_PWM_MM 20 +#define CLK_MM_DISP_PWM_26M 21 +#define CLK_MM_DSI_ENGINE 22 +#define CLK_MM_DSI_DIGITAL 23 +#define CLK_MM_DPI0_ENGINE 24 +#define CLK_MM_DPI0_PXL 25 +#define CLK_MM_LVDS_PXL 26 +#define CLK_MM_LVDS_CTS 27 +#define CLK_MM_DPI1_ENGINE 28 +#define CLK_MM_DPI1_PXL 29 +#define CLK_MM_HDMI_PXL 30 +#define CLK_MM_HDMI_SPDIF 31 +#define CLK_MM_HDMI_ADSP_BCK 32 +#define CLK_MM_HDMI_PLL 33 +#define CLK_MM_NR_CLK 34 + +/* IMGSYS */ + +#define CLK_IMG_LARB1_SMI 0 +#define CLK_IMG_CAM_SMI 1 +#define CLK_IMG_CAM_CAM 2 +#define CLK_IMG_SEN_TG 3 +#define CLK_IMG_SEN_CAM 4 +#define CLK_IMG_VENC 5 +#define CLK_IMG_NR_CLK 6 + +/* VDECSYS */ + +#define CLK_VDEC_CKEN 0 +#define CLK_VDEC_LARB1_CKEN 1 +#define CLK_VDEC_NR_CLK 2 + +#endif /* _DT_BINDINGS_CLK_MT8167_H */ diff --git a/include/dt-bindings/clock/mt8173-clk.h b/include/dt-bindings/clock/mt8173-clk.h index 3acebe937bfc..3d00c98b9654 100644 --- a/include/dt-bindings/clock/mt8173-clk.h +++ b/include/dt-bindings/clock/mt8173-clk.h @@ -186,7 +186,6 @@ #define CLK_INFRA_PMICWRAP 11 #define CLK_INFRA_CLK_13M 12 #define CLK_INFRA_CA53SEL 13 -#define CLK_INFRA_CA57SEL 14 /* Deprecated. Don't use it. */ #define CLK_INFRA_CA72SEL 14 #define CLK_INFRA_NR_CLK 15 diff --git a/include/dt-bindings/clock/mt8186-clk.h b/include/dt-bindings/clock/mt8186-clk.h new file mode 100644 index 000000000000..a70bf67af47d --- /dev/null +++ b/include/dt-bindings/clock/mt8186-clk.h @@ -0,0 +1,445 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> + */ + +#ifndef _DT_BINDINGS_CLK_MT8186_H +#define _DT_BINDINGS_CLK_MT8186_H + +/* MCUSYS */ + +#define CLK_MCU_ARMPLL_LL_SEL 0 +#define CLK_MCU_ARMPLL_BL_SEL 1 +#define CLK_MCU_ARMPLL_BUS_SEL 2 +#define CLK_MCU_NR_CLK 3 + +/* TOPCKGEN */ + +#define CLK_TOP_AXI 0 +#define CLK_TOP_SCP 1 +#define CLK_TOP_MFG 2 +#define CLK_TOP_CAMTG 3 +#define CLK_TOP_CAMTG1 4 +#define CLK_TOP_CAMTG2 5 +#define CLK_TOP_CAMTG3 6 +#define CLK_TOP_CAMTG4 7 +#define CLK_TOP_CAMTG5 8 +#define CLK_TOP_CAMTG6 9 +#define CLK_TOP_UART 10 +#define CLK_TOP_SPI 11 +#define CLK_TOP_MSDC50_0_HCLK 12 +#define CLK_TOP_MSDC50_0 13 +#define CLK_TOP_MSDC30_1 14 +#define CLK_TOP_AUDIO 15 +#define CLK_TOP_AUD_INTBUS 16 +#define CLK_TOP_AUD_1 17 +#define CLK_TOP_AUD_2 18 +#define CLK_TOP_AUD_ENGEN1 19 +#define CLK_TOP_AUD_ENGEN2 20 +#define CLK_TOP_DISP_PWM 21 +#define CLK_TOP_SSPM 22 +#define CLK_TOP_DXCC 23 +#define CLK_TOP_USB_TOP 24 +#define CLK_TOP_SRCK 25 +#define CLK_TOP_SPM 26 +#define CLK_TOP_I2C 27 +#define CLK_TOP_PWM 28 +#define CLK_TOP_SENINF 29 +#define CLK_TOP_SENINF1 30 +#define CLK_TOP_SENINF2 31 +#define CLK_TOP_SENINF3 32 +#define CLK_TOP_AES_MSDCFDE 33 +#define CLK_TOP_PWRAP_ULPOSC 34 +#define CLK_TOP_CAMTM 35 +#define CLK_TOP_VENC 36 +#define CLK_TOP_CAM 37 +#define CLK_TOP_IMG1 38 +#define CLK_TOP_IPE 39 +#define CLK_TOP_DPMAIF 40 +#define CLK_TOP_VDEC 41 +#define CLK_TOP_DISP 42 +#define CLK_TOP_MDP 43 +#define CLK_TOP_AUDIO_H 44 +#define CLK_TOP_UFS 45 +#define CLK_TOP_AES_FDE 46 +#define CLK_TOP_AUDIODSP 47 +#define CLK_TOP_DVFSRC 48 +#define CLK_TOP_DSI_OCC 49 +#define CLK_TOP_SPMI_MST 50 +#define CLK_TOP_SPINOR 51 +#define CLK_TOP_NNA 52 +#define CLK_TOP_NNA1 53 +#define CLK_TOP_NNA2 54 +#define CLK_TOP_SSUSB_XHCI 55 +#define CLK_TOP_SSUSB_TOP_1P 56 +#define CLK_TOP_SSUSB_XHCI_1P 57 +#define CLK_TOP_WPE 58 +#define CLK_TOP_DPI 59 +#define CLK_TOP_U3_OCC_250M 60 +#define CLK_TOP_U3_OCC_500M 61 +#define CLK_TOP_ADSP_BUS 62 +#define CLK_TOP_APLL_I2S0_MCK_SEL 63 +#define CLK_TOP_APLL_I2S1_MCK_SEL 64 +#define CLK_TOP_APLL_I2S2_MCK_SEL 65 +#define CLK_TOP_APLL_I2S4_MCK_SEL 66 +#define CLK_TOP_APLL_TDMOUT_MCK_SEL 67 +#define CLK_TOP_MAINPLL_D2 68 +#define CLK_TOP_MAINPLL_D2_D2 69 +#define CLK_TOP_MAINPLL_D2_D4 70 +#define CLK_TOP_MAINPLL_D2_D16 71 +#define CLK_TOP_MAINPLL_D3 72 +#define CLK_TOP_MAINPLL_D3_D2 73 +#define CLK_TOP_MAINPLL_D3_D4 74 +#define CLK_TOP_MAINPLL_D5 75 +#define CLK_TOP_MAINPLL_D5_D2 76 +#define CLK_TOP_MAINPLL_D5_D4 77 +#define CLK_TOP_MAINPLL_D7 78 +#define CLK_TOP_MAINPLL_D7_D2 79 +#define CLK_TOP_MAINPLL_D7_D4 80 +#define CLK_TOP_UNIVPLL 81 +#define CLK_TOP_UNIVPLL_D2 82 +#define CLK_TOP_UNIVPLL_D2_D2 83 +#define CLK_TOP_UNIVPLL_D2_D4 84 +#define CLK_TOP_UNIVPLL_D3 85 +#define CLK_TOP_UNIVPLL_D3_D2 86 +#define CLK_TOP_UNIVPLL_D3_D4 87 +#define CLK_TOP_UNIVPLL_D3_D8 88 +#define CLK_TOP_UNIVPLL_D3_D32 89 +#define CLK_TOP_UNIVPLL_D5 90 +#define CLK_TOP_UNIVPLL_D5_D2 91 +#define CLK_TOP_UNIVPLL_D5_D4 92 +#define CLK_TOP_UNIVPLL_D7 93 +#define CLK_TOP_UNIVPLL_192M 94 +#define CLK_TOP_UNIVPLL_192M_D4 95 +#define CLK_TOP_UNIVPLL_192M_D8 96 +#define CLK_TOP_UNIVPLL_192M_D16 97 +#define CLK_TOP_UNIVPLL_192M_D32 98 +#define CLK_TOP_APLL1_D2 99 +#define CLK_TOP_APLL1_D4 100 +#define CLK_TOP_APLL1_D8 101 +#define CLK_TOP_APLL2_D2 102 +#define CLK_TOP_APLL2_D4 103 +#define CLK_TOP_APLL2_D8 104 +#define CLK_TOP_MMPLL_D2 105 +#define CLK_TOP_TVDPLL_D2 106 +#define CLK_TOP_TVDPLL_D4 107 +#define CLK_TOP_TVDPLL_D8 108 +#define CLK_TOP_TVDPLL_D16 109 +#define CLK_TOP_TVDPLL_D32 110 +#define CLK_TOP_MSDCPLL_D2 111 +#define CLK_TOP_ULPOSC1 112 +#define CLK_TOP_ULPOSC1_D2 113 +#define CLK_TOP_ULPOSC1_D4 114 +#define CLK_TOP_ULPOSC1_D8 115 +#define CLK_TOP_ULPOSC1_D10 116 +#define CLK_TOP_ULPOSC1_D16 117 +#define CLK_TOP_ULPOSC1_D32 118 +#define CLK_TOP_ADSPPLL_D2 119 +#define CLK_TOP_ADSPPLL_D4 120 +#define CLK_TOP_ADSPPLL_D8 121 +#define CLK_TOP_NNAPLL_D2 122 +#define CLK_TOP_NNAPLL_D4 123 +#define CLK_TOP_NNAPLL_D8 124 +#define CLK_TOP_NNA2PLL_D2 125 +#define CLK_TOP_NNA2PLL_D4 126 +#define CLK_TOP_NNA2PLL_D8 127 +#define CLK_TOP_F_BIST2FPC 128 +#define CLK_TOP_466M_FMEM 129 +#define CLK_TOP_MPLL 130 +#define CLK_TOP_APLL12_CK_DIV0 131 +#define CLK_TOP_APLL12_CK_DIV1 132 +#define CLK_TOP_APLL12_CK_DIV2 133 +#define CLK_TOP_APLL12_CK_DIV4 134 +#define CLK_TOP_APLL12_CK_DIV_TDMOUT_M 135 +#define CLK_TOP_NR_CLK 136 + +/* INFRACFG_AO */ + +#define CLK_INFRA_AO_PMIC_TMR 0 +#define CLK_INFRA_AO_PMIC_AP 1 +#define CLK_INFRA_AO_PMIC_MD 2 +#define CLK_INFRA_AO_PMIC_CONN 3 +#define CLK_INFRA_AO_SCP_CORE 4 +#define CLK_INFRA_AO_SEJ 5 +#define CLK_INFRA_AO_APXGPT 6 +#define CLK_INFRA_AO_ICUSB 7 +#define CLK_INFRA_AO_GCE 8 +#define CLK_INFRA_AO_THERM 9 +#define CLK_INFRA_AO_I2C_AP 10 +#define CLK_INFRA_AO_I2C_CCU 11 +#define CLK_INFRA_AO_I2C_SSPM 12 +#define CLK_INFRA_AO_I2C_RSV 13 +#define CLK_INFRA_AO_PWM_HCLK 14 +#define CLK_INFRA_AO_PWM1 15 +#define CLK_INFRA_AO_PWM2 16 +#define CLK_INFRA_AO_PWM3 17 +#define CLK_INFRA_AO_PWM4 18 +#define CLK_INFRA_AO_PWM5 19 +#define CLK_INFRA_AO_PWM 20 +#define CLK_INFRA_AO_UART0 21 +#define CLK_INFRA_AO_UART1 22 +#define CLK_INFRA_AO_UART2 23 +#define CLK_INFRA_AO_GCE_26M 24 +#define CLK_INFRA_AO_CQ_DMA_FPC 25 +#define CLK_INFRA_AO_BTIF 26 +#define CLK_INFRA_AO_SPI0 27 +#define CLK_INFRA_AO_MSDC0 28 +#define CLK_INFRA_AO_MSDCFDE 29 +#define CLK_INFRA_AO_MSDC1 30 +#define CLK_INFRA_AO_DVFSRC 31 +#define CLK_INFRA_AO_GCPU 32 +#define CLK_INFRA_AO_TRNG 33 +#define CLK_INFRA_AO_AUXADC 34 +#define CLK_INFRA_AO_CPUM 35 +#define CLK_INFRA_AO_CCIF1_AP 36 +#define CLK_INFRA_AO_CCIF1_MD 37 +#define CLK_INFRA_AO_AUXADC_MD 38 +#define CLK_INFRA_AO_AP_DMA 39 +#define CLK_INFRA_AO_XIU 40 +#define CLK_INFRA_AO_DEVICE_APC 41 +#define CLK_INFRA_AO_CCIF_AP 42 +#define CLK_INFRA_AO_DEBUGTOP 43 +#define CLK_INFRA_AO_AUDIO 44 +#define CLK_INFRA_AO_CCIF_MD 45 +#define CLK_INFRA_AO_DXCC_SEC_CORE 46 +#define CLK_INFRA_AO_DXCC_AO 47 +#define CLK_INFRA_AO_IMP_IIC 48 +#define CLK_INFRA_AO_DRAMC_F26M 49 +#define CLK_INFRA_AO_RG_PWM_FBCLK6 50 +#define CLK_INFRA_AO_SSUSB_TOP_HCLK 51 +#define CLK_INFRA_AO_DISP_PWM 52 +#define CLK_INFRA_AO_CLDMA_BCLK 53 +#define CLK_INFRA_AO_AUDIO_26M_BCLK 54 +#define CLK_INFRA_AO_SSUSB_TOP_P1_HCLK 55 +#define CLK_INFRA_AO_SPI1 56 +#define CLK_INFRA_AO_I2C4 57 +#define CLK_INFRA_AO_MODEM_TEMP_SHARE 58 +#define CLK_INFRA_AO_SPI2 59 +#define CLK_INFRA_AO_SPI3 60 +#define CLK_INFRA_AO_SSUSB_TOP_REF 61 +#define CLK_INFRA_AO_SSUSB_TOP_XHCI 62 +#define CLK_INFRA_AO_SSUSB_TOP_P1_REF 63 +#define CLK_INFRA_AO_SSUSB_TOP_P1_XHCI 64 +#define CLK_INFRA_AO_SSPM 65 +#define CLK_INFRA_AO_SSUSB_TOP_P1_SYS 66 +#define CLK_INFRA_AO_I2C5 67 +#define CLK_INFRA_AO_I2C5_ARBITER 68 +#define CLK_INFRA_AO_I2C5_IMM 69 +#define CLK_INFRA_AO_I2C1_ARBITER 70 +#define CLK_INFRA_AO_I2C1_IMM 71 +#define CLK_INFRA_AO_I2C2_ARBITER 72 +#define CLK_INFRA_AO_I2C2_IMM 73 +#define CLK_INFRA_AO_SPI4 74 +#define CLK_INFRA_AO_SPI5 75 +#define CLK_INFRA_AO_CQ_DMA 76 +#define CLK_INFRA_AO_BIST2FPC 77 +#define CLK_INFRA_AO_MSDC0_SELF 78 +#define CLK_INFRA_AO_SPINOR 79 +#define CLK_INFRA_AO_SSPM_26M_SELF 80 +#define CLK_INFRA_AO_SSPM_32K_SELF 81 +#define CLK_INFRA_AO_I2C6 82 +#define CLK_INFRA_AO_AP_MSDC0 83 +#define CLK_INFRA_AO_MD_MSDC0 84 +#define CLK_INFRA_AO_MSDC0_SRC 85 +#define CLK_INFRA_AO_MSDC1_SRC 86 +#define CLK_INFRA_AO_SEJ_F13M 87 +#define CLK_INFRA_AO_AES_TOP0_BCLK 88 +#define CLK_INFRA_AO_MCU_PM_BCLK 89 +#define CLK_INFRA_AO_CCIF2_AP 90 +#define CLK_INFRA_AO_CCIF2_MD 91 +#define CLK_INFRA_AO_CCIF3_AP 92 +#define CLK_INFRA_AO_CCIF3_MD 93 +#define CLK_INFRA_AO_FADSP_26M 94 +#define CLK_INFRA_AO_FADSP_32K 95 +#define CLK_INFRA_AO_CCIF4_AP 96 +#define CLK_INFRA_AO_CCIF4_MD 97 +#define CLK_INFRA_AO_FADSP 98 +#define CLK_INFRA_AO_FLASHIF_133M 99 +#define CLK_INFRA_AO_FLASHIF_66M 100 +#define CLK_INFRA_AO_NR_CLK 101 + +/* APMIXEDSYS */ + +#define CLK_APMIXED_ARMPLL_LL 0 +#define CLK_APMIXED_ARMPLL_BL 1 +#define CLK_APMIXED_CCIPLL 2 +#define CLK_APMIXED_MAINPLL 3 +#define CLK_APMIXED_UNIV2PLL 4 +#define CLK_APMIXED_MSDCPLL 5 +#define CLK_APMIXED_MMPLL 6 +#define CLK_APMIXED_NNAPLL 7 +#define CLK_APMIXED_NNA2PLL 8 +#define CLK_APMIXED_ADSPPLL 9 +#define CLK_APMIXED_MFGPLL 10 +#define CLK_APMIXED_TVDPLL 11 +#define CLK_APMIXED_APLL1 12 +#define CLK_APMIXED_APLL2 13 +#define CLK_APMIXED_NR_CLK 14 + +/* IMP_IIC_WRAP */ + +#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C0 0 +#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C1 1 +#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C2 2 +#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C3 3 +#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C4 4 +#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C5 5 +#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C6 6 +#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C7 7 +#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C8 8 +#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C9 9 +#define CLK_IMP_IIC_WRAP_NR_CLK 10 + +/* MFGCFG */ + +#define CLK_MFG_BG3D 0 +#define CLK_MFG_NR_CLK 1 + +/* MMSYS */ + +#define CLK_MM_DISP_MUTEX0 0 +#define CLK_MM_APB_MM_BUS 1 +#define CLK_MM_DISP_OVL0 2 +#define CLK_MM_DISP_RDMA0 3 +#define CLK_MM_DISP_OVL0_2L 4 +#define CLK_MM_DISP_WDMA0 5 +#define CLK_MM_DISP_RSZ0 6 +#define CLK_MM_DISP_AAL0 7 +#define CLK_MM_DISP_CCORR0 8 +#define CLK_MM_DISP_COLOR0 9 +#define CLK_MM_SMI_INFRA 10 +#define CLK_MM_DISP_DSC_WRAP0 11 +#define CLK_MM_DISP_GAMMA0 12 +#define CLK_MM_DISP_POSTMASK0 13 +#define CLK_MM_DISP_DITHER0 14 +#define CLK_MM_SMI_COMMON 15 +#define CLK_MM_DSI0 16 +#define CLK_MM_DISP_FAKE_ENG0 17 +#define CLK_MM_DISP_FAKE_ENG1 18 +#define CLK_MM_SMI_GALS 19 +#define CLK_MM_SMI_IOMMU 20 +#define CLK_MM_DISP_RDMA1 21 +#define CLK_MM_DISP_DPI 22 +#define CLK_MM_DSI0_DSI_CK_DOMAIN 23 +#define CLK_MM_DISP_26M 24 +#define CLK_MM_NR_CLK 25 + +/* WPESYS */ + +#define CLK_WPE_CK_EN 0 +#define CLK_WPE_SMI_LARB8_CK_EN 1 +#define CLK_WPE_SYS_EVENT_TX_CK_EN 2 +#define CLK_WPE_SMI_LARB8_PCLK_EN 3 +#define CLK_WPE_NR_CLK 4 + +/* IMGSYS1 */ + +#define CLK_IMG1_LARB9_IMG1 0 +#define CLK_IMG1_LARB10_IMG1 1 +#define CLK_IMG1_DIP 2 +#define CLK_IMG1_GALS_IMG1 3 +#define CLK_IMG1_NR_CLK 4 + +/* IMGSYS2 */ + +#define CLK_IMG2_LARB9_IMG2 0 +#define CLK_IMG2_LARB10_IMG2 1 +#define CLK_IMG2_MFB 2 +#define CLK_IMG2_WPE 3 +#define CLK_IMG2_MSS 4 +#define CLK_IMG2_GALS_IMG2 5 +#define CLK_IMG2_NR_CLK 6 + +/* VDECSYS */ + +#define CLK_VDEC_LARB1_CKEN 0 +#define CLK_VDEC_LAT_CKEN 1 +#define CLK_VDEC_LAT_ACTIVE 2 +#define CLK_VDEC_LAT_CKEN_ENG 3 +#define CLK_VDEC_MINI_MDP_CKEN_CFG_RG 4 +#define CLK_VDEC_CKEN 5 +#define CLK_VDEC_ACTIVE 6 +#define CLK_VDEC_CKEN_ENG 7 +#define CLK_VDEC_NR_CLK 8 + +/* VENCSYS */ + +#define CLK_VENC_CKE0_LARB 0 +#define CLK_VENC_CKE1_VENC 1 +#define CLK_VENC_CKE2_JPGENC 2 +#define CLK_VENC_CKE5_GALS 3 +#define CLK_VENC_NR_CLK 4 + +/* CAMSYS */ + +#define CLK_CAM_LARB13 0 +#define CLK_CAM_DFP_VAD 1 +#define CLK_CAM_LARB14 2 +#define CLK_CAM 3 +#define CLK_CAMTG 4 +#define CLK_CAM_SENINF 5 +#define CLK_CAMSV1 6 +#define CLK_CAMSV2 7 +#define CLK_CAMSV3 8 +#define CLK_CAM_CCU0 9 +#define CLK_CAM_CCU1 10 +#define CLK_CAM_MRAW0 11 +#define CLK_CAM_FAKE_ENG 12 +#define CLK_CAM_CCU_GALS 13 +#define CLK_CAM2MM_GALS 14 +#define CLK_CAM_NR_CLK 15 + +/* CAMSYS_RAWA */ + +#define CLK_CAM_RAWA_LARBX_RAWA 0 +#define CLK_CAM_RAWA 1 +#define CLK_CAM_RAWA_CAMTG_RAWA 2 +#define CLK_CAM_RAWA_NR_CLK 3 + +/* CAMSYS_RAWB */ + +#define CLK_CAM_RAWB_LARBX_RAWB 0 +#define CLK_CAM_RAWB 1 +#define CLK_CAM_RAWB_CAMTG_RAWB 2 +#define CLK_CAM_RAWB_NR_CLK 3 + +/* MDPSYS */ + +#define CLK_MDP_RDMA0 0 +#define CLK_MDP_TDSHP0 1 +#define CLK_MDP_IMG_DL_ASYNC0 2 +#define CLK_MDP_IMG_DL_ASYNC1 3 +#define CLK_MDP_DISP_RDMA 4 +#define CLK_MDP_HMS 5 +#define CLK_MDP_SMI0 6 +#define CLK_MDP_APB_BUS 7 +#define CLK_MDP_WROT0 8 +#define CLK_MDP_RSZ0 9 +#define CLK_MDP_HDR0 10 +#define CLK_MDP_MUTEX0 11 +#define CLK_MDP_WROT1 12 +#define CLK_MDP_RSZ1 13 +#define CLK_MDP_FAKE_ENG0 14 +#define CLK_MDP_AAL0 15 +#define CLK_MDP_DISP_WDMA 16 +#define CLK_MDP_COLOR 17 +#define CLK_MDP_IMG_DL_ASYNC2 18 +#define CLK_MDP_IMG_DL_RELAY0_ASYNC0 19 +#define CLK_MDP_IMG_DL_RELAY1_ASYNC1 20 +#define CLK_MDP_IMG_DL_RELAY2_ASYNC2 21 +#define CLK_MDP_NR_CLK 22 + +/* IPESYS */ + +#define CLK_IPE_LARB19 0 +#define CLK_IPE_LARB20 1 +#define CLK_IPE_SMI_SUBCOM 2 +#define CLK_IPE_FD 3 +#define CLK_IPE_FE 4 +#define CLK_IPE_RSC 5 +#define CLK_IPE_DPE 6 +#define CLK_IPE_GALS_IPE 7 +#define CLK_IPE_NR_CLK 8 + +#endif /* _DT_BINDINGS_CLK_MT8186_H */ diff --git a/include/dt-bindings/clock/mt8192-clk.h b/include/dt-bindings/clock/mt8192-clk.h new file mode 100644 index 000000000000..5ab68f15a256 --- /dev/null +++ b/include/dt-bindings/clock/mt8192-clk.h @@ -0,0 +1,585 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021 MediaTek Inc. + * Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> + */ + +#ifndef _DT_BINDINGS_CLK_MT8192_H +#define _DT_BINDINGS_CLK_MT8192_H + +/* TOPCKGEN */ + +#define CLK_TOP_AXI_SEL 0 +#define CLK_TOP_SPM_SEL 1 +#define CLK_TOP_SCP_SEL 2 +#define CLK_TOP_BUS_AXIMEM_SEL 3 +#define CLK_TOP_DISP_SEL 4 +#define CLK_TOP_MDP_SEL 5 +#define CLK_TOP_IMG1_SEL 6 +#define CLK_TOP_IMG2_SEL 7 +#define CLK_TOP_IPE_SEL 8 +#define CLK_TOP_DPE_SEL 9 +#define CLK_TOP_CAM_SEL 10 +#define CLK_TOP_CCU_SEL 11 +#define CLK_TOP_DSP7_SEL 12 +#define CLK_TOP_MFG_REF_SEL 13 +#define CLK_TOP_MFG_PLL_SEL 14 +#define CLK_TOP_CAMTG_SEL 15 +#define CLK_TOP_CAMTG2_SEL 16 +#define CLK_TOP_CAMTG3_SEL 17 +#define CLK_TOP_CAMTG4_SEL 18 +#define CLK_TOP_CAMTG5_SEL 19 +#define CLK_TOP_CAMTG6_SEL 20 +#define CLK_TOP_UART_SEL 21 +#define CLK_TOP_SPI_SEL 22 +#define CLK_TOP_MSDC50_0_H_SEL 23 +#define CLK_TOP_MSDC50_0_SEL 24 +#define CLK_TOP_MSDC30_1_SEL 25 +#define CLK_TOP_MSDC30_2_SEL 26 +#define CLK_TOP_AUDIO_SEL 27 +#define CLK_TOP_AUD_INTBUS_SEL 28 +#define CLK_TOP_PWRAP_ULPOSC_SEL 29 +#define CLK_TOP_ATB_SEL 30 +#define CLK_TOP_DPI_SEL 31 +#define CLK_TOP_SCAM_SEL 32 +#define CLK_TOP_DISP_PWM_SEL 33 +#define CLK_TOP_USB_TOP_SEL 34 +#define CLK_TOP_SSUSB_XHCI_SEL 35 +#define CLK_TOP_I2C_SEL 36 +#define CLK_TOP_SENINF_SEL 37 +#define CLK_TOP_SENINF1_SEL 38 +#define CLK_TOP_SENINF2_SEL 39 +#define CLK_TOP_SENINF3_SEL 40 +#define CLK_TOP_TL_SEL 41 +#define CLK_TOP_DXCC_SEL 42 +#define CLK_TOP_AUD_ENGEN1_SEL 43 +#define CLK_TOP_AUD_ENGEN2_SEL 44 +#define CLK_TOP_AES_UFSFDE_SEL 45 +#define CLK_TOP_UFS_SEL 46 +#define CLK_TOP_AUD_1_SEL 47 +#define CLK_TOP_AUD_2_SEL 48 +#define CLK_TOP_ADSP_SEL 49 +#define CLK_TOP_DPMAIF_MAIN_SEL 50 +#define CLK_TOP_VENC_SEL 51 +#define CLK_TOP_VDEC_SEL 52 +#define CLK_TOP_CAMTM_SEL 53 +#define CLK_TOP_PWM_SEL 54 +#define CLK_TOP_AUDIO_H_SEL 55 +#define CLK_TOP_SPMI_MST_SEL 56 +#define CLK_TOP_AES_MSDCFDE_SEL 57 +#define CLK_TOP_SFLASH_SEL 58 +#define CLK_TOP_APLL_I2S0_M_SEL 59 +#define CLK_TOP_APLL_I2S1_M_SEL 60 +#define CLK_TOP_APLL_I2S2_M_SEL 61 +#define CLK_TOP_APLL_I2S3_M_SEL 62 +#define CLK_TOP_APLL_I2S4_M_SEL 63 +#define CLK_TOP_APLL_I2S5_M_SEL 64 +#define CLK_TOP_APLL_I2S6_M_SEL 65 +#define CLK_TOP_APLL_I2S7_M_SEL 66 +#define CLK_TOP_APLL_I2S8_M_SEL 67 +#define CLK_TOP_APLL_I2S9_M_SEL 68 +#define CLK_TOP_MAINPLL_D3 69 +#define CLK_TOP_MAINPLL_D4 70 +#define CLK_TOP_MAINPLL_D4_D2 71 +#define CLK_TOP_MAINPLL_D4_D4 72 +#define CLK_TOP_MAINPLL_D4_D8 73 +#define CLK_TOP_MAINPLL_D4_D16 74 +#define CLK_TOP_MAINPLL_D5 75 +#define CLK_TOP_MAINPLL_D5_D2 76 +#define CLK_TOP_MAINPLL_D5_D4 77 +#define CLK_TOP_MAINPLL_D5_D8 78 +#define CLK_TOP_MAINPLL_D6 79 +#define CLK_TOP_MAINPLL_D6_D2 80 +#define CLK_TOP_MAINPLL_D6_D4 81 +#define CLK_TOP_MAINPLL_D7 82 +#define CLK_TOP_MAINPLL_D7_D2 83 +#define CLK_TOP_MAINPLL_D7_D4 84 +#define CLK_TOP_MAINPLL_D7_D8 85 +#define CLK_TOP_UNIVPLL_D3 86 +#define CLK_TOP_UNIVPLL_D4 87 +#define CLK_TOP_UNIVPLL_D4_D2 88 +#define CLK_TOP_UNIVPLL_D4_D4 89 +#define CLK_TOP_UNIVPLL_D4_D8 90 +#define CLK_TOP_UNIVPLL_D5 91 +#define CLK_TOP_UNIVPLL_D5_D2 92 +#define CLK_TOP_UNIVPLL_D5_D4 93 +#define CLK_TOP_UNIVPLL_D5_D8 94 +#define CLK_TOP_UNIVPLL_D6 95 +#define CLK_TOP_UNIVPLL_D6_D2 96 +#define CLK_TOP_UNIVPLL_D6_D4 97 +#define CLK_TOP_UNIVPLL_D6_D8 98 +#define CLK_TOP_UNIVPLL_D6_D16 99 +#define CLK_TOP_UNIVPLL_D7 100 +#define CLK_TOP_APLL1 101 +#define CLK_TOP_APLL1_D2 102 +#define CLK_TOP_APLL1_D4 103 +#define CLK_TOP_APLL1_D8 104 +#define CLK_TOP_APLL2 105 +#define CLK_TOP_APLL2_D2 106 +#define CLK_TOP_APLL2_D4 107 +#define CLK_TOP_APLL2_D8 108 +#define CLK_TOP_MMPLL_D4 109 +#define CLK_TOP_MMPLL_D4_D2 110 +#define CLK_TOP_MMPLL_D5 111 +#define CLK_TOP_MMPLL_D5_D2 112 +#define CLK_TOP_MMPLL_D6 113 +#define CLK_TOP_MMPLL_D6_D2 114 +#define CLK_TOP_MMPLL_D7 115 +#define CLK_TOP_MMPLL_D9 116 +#define CLK_TOP_APUPLL 117 +#define CLK_TOP_NPUPLL 118 +#define CLK_TOP_TVDPLL 119 +#define CLK_TOP_TVDPLL_D2 120 +#define CLK_TOP_TVDPLL_D4 121 +#define CLK_TOP_TVDPLL_D8 122 +#define CLK_TOP_TVDPLL_D16 123 +#define CLK_TOP_MSDCPLL 124 +#define CLK_TOP_MSDCPLL_D2 125 +#define CLK_TOP_MSDCPLL_D4 126 +#define CLK_TOP_ULPOSC 127 +#define CLK_TOP_OSC_D2 128 +#define CLK_TOP_OSC_D4 129 +#define CLK_TOP_OSC_D8 130 +#define CLK_TOP_OSC_D10 131 +#define CLK_TOP_OSC_D16 132 +#define CLK_TOP_OSC_D20 133 +#define CLK_TOP_CSW_F26M_D2 134 +#define CLK_TOP_ADSPPLL 135 +#define CLK_TOP_UNIVPLL_192M 136 +#define CLK_TOP_UNIVPLL_192M_D2 137 +#define CLK_TOP_UNIVPLL_192M_D4 138 +#define CLK_TOP_UNIVPLL_192M_D8 139 +#define CLK_TOP_UNIVPLL_192M_D16 140 +#define CLK_TOP_UNIVPLL_192M_D32 141 +#define CLK_TOP_APLL12_DIV0 142 +#define CLK_TOP_APLL12_DIV1 143 +#define CLK_TOP_APLL12_DIV2 144 +#define CLK_TOP_APLL12_DIV3 145 +#define CLK_TOP_APLL12_DIV4 146 +#define CLK_TOP_APLL12_DIVB 147 +#define CLK_TOP_APLL12_DIV5 148 +#define CLK_TOP_APLL12_DIV6 149 +#define CLK_TOP_APLL12_DIV7 150 +#define CLK_TOP_APLL12_DIV8 151 +#define CLK_TOP_APLL12_DIV9 152 +#define CLK_TOP_SSUSB_TOP_REF 153 +#define CLK_TOP_SSUSB_PHY_REF 154 +#define CLK_TOP_NR_CLK 155 + +/* INFRACFG */ + +#define CLK_INFRA_PMIC_TMR 0 +#define CLK_INFRA_PMIC_AP 1 +#define CLK_INFRA_PMIC_MD 2 +#define CLK_INFRA_PMIC_CONN 3 +#define CLK_INFRA_SCPSYS 4 +#define CLK_INFRA_SEJ 5 +#define CLK_INFRA_APXGPT 6 +#define CLK_INFRA_GCE 7 +#define CLK_INFRA_GCE2 8 +#define CLK_INFRA_THERM 9 +#define CLK_INFRA_I2C0 10 +#define CLK_INFRA_AP_DMA_PSEUDO 11 +#define CLK_INFRA_I2C2 12 +#define CLK_INFRA_I2C3 13 +#define CLK_INFRA_PWM_H 14 +#define CLK_INFRA_PWM1 15 +#define CLK_INFRA_PWM2 16 +#define CLK_INFRA_PWM3 17 +#define CLK_INFRA_PWM4 18 +#define CLK_INFRA_PWM 19 +#define CLK_INFRA_UART0 20 +#define CLK_INFRA_UART1 21 +#define CLK_INFRA_UART2 22 +#define CLK_INFRA_UART3 23 +#define CLK_INFRA_GCE_26M 24 +#define CLK_INFRA_CQ_DMA_FPC 25 +#define CLK_INFRA_BTIF 26 +#define CLK_INFRA_SPI0 27 +#define CLK_INFRA_MSDC0 28 +#define CLK_INFRA_MSDC1 29 +#define CLK_INFRA_MSDC2 30 +#define CLK_INFRA_MSDC0_SRC 31 +#define CLK_INFRA_GCPU 32 +#define CLK_INFRA_TRNG 33 +#define CLK_INFRA_AUXADC 34 +#define CLK_INFRA_CPUM 35 +#define CLK_INFRA_CCIF1_AP 36 +#define CLK_INFRA_CCIF1_MD 37 +#define CLK_INFRA_AUXADC_MD 38 +#define CLK_INFRA_PCIE_TL_26M 39 +#define CLK_INFRA_MSDC1_SRC 40 +#define CLK_INFRA_MSDC2_SRC 41 +#define CLK_INFRA_PCIE_TL_96M 42 +#define CLK_INFRA_PCIE_PL_P_250M 43 +#define CLK_INFRA_DEVICE_APC 44 +#define CLK_INFRA_CCIF_AP 45 +#define CLK_INFRA_DEBUGSYS 46 +#define CLK_INFRA_AUDIO 47 +#define CLK_INFRA_CCIF_MD 48 +#define CLK_INFRA_DXCC_SEC_CORE 49 +#define CLK_INFRA_DXCC_AO 50 +#define CLK_INFRA_DBG_TRACE 51 +#define CLK_INFRA_DEVMPU_B 52 +#define CLK_INFRA_DRAMC_F26M 53 +#define CLK_INFRA_IRTX 54 +#define CLK_INFRA_SSUSB 55 +#define CLK_INFRA_DISP_PWM 56 +#define CLK_INFRA_CLDMA_B 57 +#define CLK_INFRA_AUDIO_26M_B 58 +#define CLK_INFRA_MODEM_TEMP_SHARE 59 +#define CLK_INFRA_SPI1 60 +#define CLK_INFRA_I2C4 61 +#define CLK_INFRA_SPI2 62 +#define CLK_INFRA_SPI3 63 +#define CLK_INFRA_UNIPRO_SYS 64 +#define CLK_INFRA_UNIPRO_TICK 65 +#define CLK_INFRA_UFS_MP_SAP_B 66 +#define CLK_INFRA_MD32_B 67 +#define CLK_INFRA_UNIPRO_MBIST 68 +#define CLK_INFRA_I2C5 69 +#define CLK_INFRA_I2C5_ARBITER 70 +#define CLK_INFRA_I2C5_IMM 71 +#define CLK_INFRA_I2C1_ARBITER 72 +#define CLK_INFRA_I2C1_IMM 73 +#define CLK_INFRA_I2C2_ARBITER 74 +#define CLK_INFRA_I2C2_IMM 75 +#define CLK_INFRA_SPI4 76 +#define CLK_INFRA_SPI5 77 +#define CLK_INFRA_CQ_DMA 78 +#define CLK_INFRA_UFS 79 +#define CLK_INFRA_AES_UFSFDE 80 +#define CLK_INFRA_UFS_TICK 81 +#define CLK_INFRA_SSUSB_XHCI 82 +#define CLK_INFRA_MSDC0_SELF 83 +#define CLK_INFRA_MSDC1_SELF 84 +#define CLK_INFRA_MSDC2_SELF 85 +#define CLK_INFRA_UFS_AXI 86 +#define CLK_INFRA_I2C6 87 +#define CLK_INFRA_AP_MSDC0 88 +#define CLK_INFRA_MD_MSDC0 89 +#define CLK_INFRA_CCIF5_AP 90 +#define CLK_INFRA_CCIF5_MD 91 +#define CLK_INFRA_PCIE_TOP_H_133M 92 +#define CLK_INFRA_FLASHIF_TOP_H_133M 93 +#define CLK_INFRA_PCIE_PERI_26M 94 +#define CLK_INFRA_CCIF2_AP 95 +#define CLK_INFRA_CCIF2_MD 96 +#define CLK_INFRA_CCIF3_AP 97 +#define CLK_INFRA_CCIF3_MD 98 +#define CLK_INFRA_SEJ_F13M 99 +#define CLK_INFRA_AES 100 +#define CLK_INFRA_I2C7 101 +#define CLK_INFRA_I2C8 102 +#define CLK_INFRA_FBIST2FPC 103 +#define CLK_INFRA_DEVICE_APC_SYNC 104 +#define CLK_INFRA_DPMAIF_MAIN 105 +#define CLK_INFRA_PCIE_TL_32K 106 +#define CLK_INFRA_CCIF4_AP 107 +#define CLK_INFRA_CCIF4_MD 108 +#define CLK_INFRA_SPI6 109 +#define CLK_INFRA_SPI7 110 +#define CLK_INFRA_133M 111 +#define CLK_INFRA_66M 112 +#define CLK_INFRA_66M_PERI_BUS 113 +#define CLK_INFRA_FREE_DCM_133M 114 +#define CLK_INFRA_FREE_DCM_66M 115 +#define CLK_INFRA_PERI_BUS_DCM_133M 116 +#define CLK_INFRA_PERI_BUS_DCM_66M 117 +#define CLK_INFRA_FLASHIF_PERI_26M 118 +#define CLK_INFRA_FLASHIF_SFLASH 119 +#define CLK_INFRA_AP_DMA 120 +#define CLK_INFRA_NR_CLK 121 + +/* PERICFG */ + +#define CLK_PERI_PERIAXI 0 +#define CLK_PERI_NR_CLK 1 + +/* APMIXEDSYS */ + +#define CLK_APMIXED_MAINPLL 0 +#define CLK_APMIXED_UNIVPLL 1 +#define CLK_APMIXED_USBPLL 2 +#define CLK_APMIXED_MSDCPLL 3 +#define CLK_APMIXED_MMPLL 4 +#define CLK_APMIXED_ADSPPLL 5 +#define CLK_APMIXED_MFGPLL 6 +#define CLK_APMIXED_TVDPLL 7 +#define CLK_APMIXED_APLL1 8 +#define CLK_APMIXED_APLL2 9 +#define CLK_APMIXED_MIPID26M 10 +#define CLK_APMIXED_NR_CLK 11 + +/* SCP_ADSP */ + +#define CLK_SCP_ADSP_AUDIODSP 0 +#define CLK_SCP_ADSP_NR_CLK 1 + +/* IMP_IIC_WRAP_C */ + +#define CLK_IMP_IIC_WRAP_C_I2C10 0 +#define CLK_IMP_IIC_WRAP_C_I2C11 1 +#define CLK_IMP_IIC_WRAP_C_I2C12 2 +#define CLK_IMP_IIC_WRAP_C_I2C13 3 +#define CLK_IMP_IIC_WRAP_C_NR_CLK 4 + +/* AUDSYS */ + +#define CLK_AUD_AFE 0 +#define CLK_AUD_22M 1 +#define CLK_AUD_24M 2 +#define CLK_AUD_APLL2_TUNER 3 +#define CLK_AUD_APLL_TUNER 4 +#define CLK_AUD_TDM 5 +#define CLK_AUD_ADC 6 +#define CLK_AUD_DAC 7 +#define CLK_AUD_DAC_PREDIS 8 +#define CLK_AUD_TML 9 +#define CLK_AUD_NLE 10 +#define CLK_AUD_I2S1_B 11 +#define CLK_AUD_I2S2_B 12 +#define CLK_AUD_I2S3_B 13 +#define CLK_AUD_I2S4_B 14 +#define CLK_AUD_CONNSYS_I2S_ASRC 15 +#define CLK_AUD_GENERAL1_ASRC 16 +#define CLK_AUD_GENERAL2_ASRC 17 +#define CLK_AUD_DAC_HIRES 18 +#define CLK_AUD_ADC_HIRES 19 +#define CLK_AUD_ADC_HIRES_TML 20 +#define CLK_AUD_ADDA6_ADC 21 +#define CLK_AUD_ADDA6_ADC_HIRES 22 +#define CLK_AUD_3RD_DAC 23 +#define CLK_AUD_3RD_DAC_PREDIS 24 +#define CLK_AUD_3RD_DAC_TML 25 +#define CLK_AUD_3RD_DAC_HIRES 26 +#define CLK_AUD_I2S5_B 27 +#define CLK_AUD_I2S6_B 28 +#define CLK_AUD_I2S7_B 29 +#define CLK_AUD_I2S8_B 30 +#define CLK_AUD_I2S9_B 31 +#define CLK_AUD_NR_CLK 32 + +/* IMP_IIC_WRAP_E */ + +#define CLK_IMP_IIC_WRAP_E_I2C3 0 +#define CLK_IMP_IIC_WRAP_E_NR_CLK 1 + +/* IMP_IIC_WRAP_S */ + +#define CLK_IMP_IIC_WRAP_S_I2C7 0 +#define CLK_IMP_IIC_WRAP_S_I2C8 1 +#define CLK_IMP_IIC_WRAP_S_I2C9 2 +#define CLK_IMP_IIC_WRAP_S_NR_CLK 3 + +/* IMP_IIC_WRAP_WS */ + +#define CLK_IMP_IIC_WRAP_WS_I2C1 0 +#define CLK_IMP_IIC_WRAP_WS_I2C2 1 +#define CLK_IMP_IIC_WRAP_WS_I2C4 2 +#define CLK_IMP_IIC_WRAP_WS_NR_CLK 3 + +/* IMP_IIC_WRAP_W */ + +#define CLK_IMP_IIC_WRAP_W_I2C5 0 +#define CLK_IMP_IIC_WRAP_W_NR_CLK 1 + +/* IMP_IIC_WRAP_N */ + +#define CLK_IMP_IIC_WRAP_N_I2C0 0 +#define CLK_IMP_IIC_WRAP_N_I2C6 1 +#define CLK_IMP_IIC_WRAP_N_NR_CLK 2 + +/* MSDC_TOP */ + +#define CLK_MSDC_TOP_AES_0P 0 +#define CLK_MSDC_TOP_SRC_0P 1 +#define CLK_MSDC_TOP_SRC_1P 2 +#define CLK_MSDC_TOP_SRC_2P 3 +#define CLK_MSDC_TOP_P_MSDC0 4 +#define CLK_MSDC_TOP_P_MSDC1 5 +#define CLK_MSDC_TOP_P_MSDC2 6 +#define CLK_MSDC_TOP_P_CFG 7 +#define CLK_MSDC_TOP_AXI 8 +#define CLK_MSDC_TOP_H_MST_0P 9 +#define CLK_MSDC_TOP_H_MST_1P 10 +#define CLK_MSDC_TOP_H_MST_2P 11 +#define CLK_MSDC_TOP_MEM_OFF_DLY_26M 12 +#define CLK_MSDC_TOP_32K 13 +#define CLK_MSDC_TOP_AHB2AXI_BRG_AXI 14 +#define CLK_MSDC_TOP_NR_CLK 15 + +/* MSDC */ + +#define CLK_MSDC_AXI_WRAP 0 +#define CLK_MSDC_NR_CLK 1 + +/* MFGCFG */ + +#define CLK_MFG_BG3D 0 +#define CLK_MFG_NR_CLK 1 + +/* MMSYS */ + +#define CLK_MM_DISP_MUTEX0 0 +#define CLK_MM_DISP_CONFIG 1 +#define CLK_MM_DISP_OVL0 2 +#define CLK_MM_DISP_RDMA0 3 +#define CLK_MM_DISP_OVL0_2L 4 +#define CLK_MM_DISP_WDMA0 5 +#define CLK_MM_DISP_UFBC_WDMA0 6 +#define CLK_MM_DISP_RSZ0 7 +#define CLK_MM_DISP_AAL0 8 +#define CLK_MM_DISP_CCORR0 9 +#define CLK_MM_DISP_DITHER0 10 +#define CLK_MM_SMI_INFRA 11 +#define CLK_MM_DISP_GAMMA0 12 +#define CLK_MM_DISP_POSTMASK0 13 +#define CLK_MM_DISP_DSC_WRAP0 14 +#define CLK_MM_DSI0 15 +#define CLK_MM_DISP_COLOR0 16 +#define CLK_MM_SMI_COMMON 17 +#define CLK_MM_DISP_FAKE_ENG0 18 +#define CLK_MM_DISP_FAKE_ENG1 19 +#define CLK_MM_MDP_TDSHP4 20 +#define CLK_MM_MDP_RSZ4 21 +#define CLK_MM_MDP_AAL4 22 +#define CLK_MM_MDP_HDR4 23 +#define CLK_MM_MDP_RDMA4 24 +#define CLK_MM_MDP_COLOR4 25 +#define CLK_MM_DISP_Y2R0 26 +#define CLK_MM_SMI_GALS 27 +#define CLK_MM_DISP_OVL2_2L 28 +#define CLK_MM_DISP_RDMA4 29 +#define CLK_MM_DISP_DPI0 30 +#define CLK_MM_SMI_IOMMU 31 +#define CLK_MM_DSI_DSI0 32 +#define CLK_MM_DPI_DPI0 33 +#define CLK_MM_26MHZ 34 +#define CLK_MM_32KHZ 35 +#define CLK_MM_NR_CLK 36 + +/* IMGSYS */ + +#define CLK_IMG_LARB9 0 +#define CLK_IMG_LARB10 1 +#define CLK_IMG_DIP 2 +#define CLK_IMG_GALS 3 +#define CLK_IMG_NR_CLK 4 + +/* IMGSYS2 */ + +#define CLK_IMG2_LARB11 0 +#define CLK_IMG2_LARB12 1 +#define CLK_IMG2_MFB 2 +#define CLK_IMG2_WPE 3 +#define CLK_IMG2_MSS 4 +#define CLK_IMG2_GALS 5 +#define CLK_IMG2_NR_CLK 6 + +/* VDECSYS_SOC */ + +#define CLK_VDEC_SOC_LARB1 0 +#define CLK_VDEC_SOC_LAT 1 +#define CLK_VDEC_SOC_LAT_ACTIVE 2 +#define CLK_VDEC_SOC_VDEC 3 +#define CLK_VDEC_SOC_VDEC_ACTIVE 4 +#define CLK_VDEC_SOC_NR_CLK 5 + +/* VDECSYS */ + +#define CLK_VDEC_LARB1 0 +#define CLK_VDEC_LAT 1 +#define CLK_VDEC_LAT_ACTIVE 2 +#define CLK_VDEC_VDEC 3 +#define CLK_VDEC_ACTIVE 4 +#define CLK_VDEC_NR_CLK 5 + +/* VENCSYS */ + +#define CLK_VENC_SET0_LARB 0 +#define CLK_VENC_SET1_VENC 1 +#define CLK_VENC_SET2_JPGENC 2 +#define CLK_VENC_SET5_GALS 3 +#define CLK_VENC_NR_CLK 4 + +/* CAMSYS */ + +#define CLK_CAM_LARB13 0 +#define CLK_CAM_DFP_VAD 1 +#define CLK_CAM_LARB14 2 +#define CLK_CAM_CAM 3 +#define CLK_CAM_CAMTG 4 +#define CLK_CAM_SENINF 5 +#define CLK_CAM_CAMSV0 6 +#define CLK_CAM_CAMSV1 7 +#define CLK_CAM_CAMSV2 8 +#define CLK_CAM_CAMSV3 9 +#define CLK_CAM_CCU0 10 +#define CLK_CAM_CCU1 11 +#define CLK_CAM_MRAW0 12 +#define CLK_CAM_FAKE_ENG 13 +#define CLK_CAM_CCU_GALS 14 +#define CLK_CAM_CAM2MM_GALS 15 +#define CLK_CAM_NR_CLK 16 + +/* CAMSYS_RAWA */ + +#define CLK_CAM_RAWA_LARBX 0 +#define CLK_CAM_RAWA_CAM 1 +#define CLK_CAM_RAWA_CAMTG 2 +#define CLK_CAM_RAWA_NR_CLK 3 + +/* CAMSYS_RAWB */ + +#define CLK_CAM_RAWB_LARBX 0 +#define CLK_CAM_RAWB_CAM 1 +#define CLK_CAM_RAWB_CAMTG 2 +#define CLK_CAM_RAWB_NR_CLK 3 + +/* CAMSYS_RAWC */ + +#define CLK_CAM_RAWC_LARBX 0 +#define CLK_CAM_RAWC_CAM 1 +#define CLK_CAM_RAWC_CAMTG 2 +#define CLK_CAM_RAWC_NR_CLK 3 + +/* IPESYS */ + +#define CLK_IPE_LARB19 0 +#define CLK_IPE_LARB20 1 +#define CLK_IPE_SMI_SUBCOM 2 +#define CLK_IPE_FD 3 +#define CLK_IPE_FE 4 +#define CLK_IPE_RSC 5 +#define CLK_IPE_DPE 6 +#define CLK_IPE_GALS 7 +#define CLK_IPE_NR_CLK 8 + +/* MDPSYS */ + +#define CLK_MDP_RDMA0 0 +#define CLK_MDP_TDSHP0 1 +#define CLK_MDP_IMG_DL_ASYNC0 2 +#define CLK_MDP_IMG_DL_ASYNC1 3 +#define CLK_MDP_RDMA1 4 +#define CLK_MDP_TDSHP1 5 +#define CLK_MDP_SMI0 6 +#define CLK_MDP_APB_BUS 7 +#define CLK_MDP_WROT0 8 +#define CLK_MDP_RSZ0 9 +#define CLK_MDP_HDR0 10 +#define CLK_MDP_MUTEX0 11 +#define CLK_MDP_WROT1 12 +#define CLK_MDP_RSZ1 13 +#define CLK_MDP_HDR1 14 +#define CLK_MDP_FAKE_ENG0 15 +#define CLK_MDP_AAL0 16 +#define CLK_MDP_AAL1 17 +#define CLK_MDP_COLOR0 18 +#define CLK_MDP_COLOR1 19 +#define CLK_MDP_IMG_DL_RELAY0_ASYNC0 20 +#define CLK_MDP_IMG_DL_RELAY1_ASYNC1 21 +#define CLK_MDP_NR_CLK 22 + +#endif /* _DT_BINDINGS_CLK_MT8192_H */ diff --git a/include/dt-bindings/clock/mt8195-clk.h b/include/dt-bindings/clock/mt8195-clk.h new file mode 100644 index 000000000000..d70d017ad69c --- /dev/null +++ b/include/dt-bindings/clock/mt8195-clk.h @@ -0,0 +1,866 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (c) 2021 MediaTek Inc. + * Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> + */ + +#ifndef _DT_BINDINGS_CLK_MT8195_H +#define _DT_BINDINGS_CLK_MT8195_H + +/* TOPCKGEN */ + +#define CLK_TOP_AXI 0 +#define CLK_TOP_SPM 1 +#define CLK_TOP_SCP 2 +#define CLK_TOP_BUS_AXIMEM 3 +#define CLK_TOP_VPP 4 +#define CLK_TOP_ETHDR 5 +#define CLK_TOP_IPE 6 +#define CLK_TOP_CAM 7 +#define CLK_TOP_CCU 8 +#define CLK_TOP_IMG 9 +#define CLK_TOP_CAMTM 10 +#define CLK_TOP_DSP 11 +#define CLK_TOP_DSP1 12 +#define CLK_TOP_DSP2 13 +#define CLK_TOP_DSP3 14 +#define CLK_TOP_DSP4 15 +#define CLK_TOP_DSP5 16 +#define CLK_TOP_DSP6 17 +#define CLK_TOP_DSP7 18 +#define CLK_TOP_IPU_IF 19 +#define CLK_TOP_MFG_CORE_TMP 20 +#define CLK_TOP_CAMTG 21 +#define CLK_TOP_CAMTG2 22 +#define CLK_TOP_CAMTG3 23 +#define CLK_TOP_CAMTG4 24 +#define CLK_TOP_CAMTG5 25 +#define CLK_TOP_UART 26 +#define CLK_TOP_SPI 27 +#define CLK_TOP_SPIS 28 +#define CLK_TOP_MSDC50_0_HCLK 29 +#define CLK_TOP_MSDC50_0 30 +#define CLK_TOP_MSDC30_1 31 +#define CLK_TOP_MSDC30_2 32 +#define CLK_TOP_INTDIR 33 +#define CLK_TOP_AUD_INTBUS 34 +#define CLK_TOP_AUDIO_H 35 +#define CLK_TOP_PWRAP_ULPOSC 36 +#define CLK_TOP_ATB 37 +#define CLK_TOP_PWRMCU 38 +#define CLK_TOP_DP 39 +#define CLK_TOP_EDP 40 +#define CLK_TOP_DPI 41 +#define CLK_TOP_DISP_PWM0 42 +#define CLK_TOP_DISP_PWM1 43 +#define CLK_TOP_USB_TOP 44 +#define CLK_TOP_SSUSB_XHCI 45 +#define CLK_TOP_USB_TOP_1P 46 +#define CLK_TOP_SSUSB_XHCI_1P 47 +#define CLK_TOP_USB_TOP_2P 48 +#define CLK_TOP_SSUSB_XHCI_2P 49 +#define CLK_TOP_USB_TOP_3P 50 +#define CLK_TOP_SSUSB_XHCI_3P 51 +#define CLK_TOP_I2C 52 +#define CLK_TOP_SENINF 53 +#define CLK_TOP_SENINF1 54 +#define CLK_TOP_SENINF2 55 +#define CLK_TOP_SENINF3 56 +#define CLK_TOP_GCPU 57 +#define CLK_TOP_DXCC 58 +#define CLK_TOP_DPMAIF_MAIN 59 +#define CLK_TOP_AES_UFSFDE 60 +#define CLK_TOP_UFS 61 +#define CLK_TOP_UFS_TICK1US 62 +#define CLK_TOP_UFS_MP_SAP_CFG 63 +#define CLK_TOP_VENC 64 +#define CLK_TOP_VDEC 65 +#define CLK_TOP_PWM 66 +#define CLK_TOP_MCUPM 67 +#define CLK_TOP_SPMI_P_MST 68 +#define CLK_TOP_SPMI_M_MST 69 +#define CLK_TOP_DVFSRC 70 +#define CLK_TOP_TL 71 +#define CLK_TOP_TL_P1 72 +#define CLK_TOP_AES_MSDCFDE 73 +#define CLK_TOP_DSI_OCC 74 +#define CLK_TOP_WPE_VPP 75 +#define CLK_TOP_HDCP 76 +#define CLK_TOP_HDCP_24M 77 +#define CLK_TOP_HD20_DACR_REF_CLK 78 +#define CLK_TOP_HD20_HDCP_CCLK 79 +#define CLK_TOP_HDMI_XTAL 80 +#define CLK_TOP_HDMI_APB 81 +#define CLK_TOP_SNPS_ETH_250M 82 +#define CLK_TOP_SNPS_ETH_62P4M_PTP 83 +#define CLK_TOP_SNPS_ETH_50M_RMII 84 +#define CLK_TOP_DGI_OUT 85 +#define CLK_TOP_NNA0 86 +#define CLK_TOP_NNA1 87 +#define CLK_TOP_ADSP 88 +#define CLK_TOP_ASM_H 89 +#define CLK_TOP_ASM_M 90 +#define CLK_TOP_ASM_L 91 +#define CLK_TOP_APLL1 92 +#define CLK_TOP_APLL2 93 +#define CLK_TOP_APLL3 94 +#define CLK_TOP_APLL4 95 +#define CLK_TOP_APLL5 96 +#define CLK_TOP_I2SO1_MCK 97 +#define CLK_TOP_I2SO2_MCK 98 +#define CLK_TOP_I2SI1_MCK 99 +#define CLK_TOP_I2SI2_MCK 100 +#define CLK_TOP_DPTX_MCK 101 +#define CLK_TOP_AUD_IEC_CLK 102 +#define CLK_TOP_A1SYS_HP 103 +#define CLK_TOP_A2SYS_HF 104 +#define CLK_TOP_A3SYS_HF 105 +#define CLK_TOP_A4SYS_HF 106 +#define CLK_TOP_SPINFI_BCLK 107 +#define CLK_TOP_NFI1X 108 +#define CLK_TOP_ECC 109 +#define CLK_TOP_AUDIO_LOCAL_BUS 110 +#define CLK_TOP_SPINOR 111 +#define CLK_TOP_DVIO_DGI_REF 112 +#define CLK_TOP_ULPOSC 113 +#define CLK_TOP_ULPOSC_CORE 114 +#define CLK_TOP_SRCK 115 +#define CLK_TOP_MFG_CK_FAST_REF 116 +#define CLK_TOP_CLK26M_D2 117 +#define CLK_TOP_CLK26M_D52 118 +#define CLK_TOP_IN_DGI 119 +#define CLK_TOP_IN_DGI_D2 120 +#define CLK_TOP_IN_DGI_D4 121 +#define CLK_TOP_IN_DGI_D6 122 +#define CLK_TOP_IN_DGI_D8 123 +#define CLK_TOP_MAINPLL_D3 124 +#define CLK_TOP_MAINPLL_D4 125 +#define CLK_TOP_MAINPLL_D4_D2 126 +#define CLK_TOP_MAINPLL_D4_D4 127 +#define CLK_TOP_MAINPLL_D4_D8 128 +#define CLK_TOP_MAINPLL_D5 129 +#define CLK_TOP_MAINPLL_D5_D2 130 +#define CLK_TOP_MAINPLL_D5_D4 131 +#define CLK_TOP_MAINPLL_D5_D8 132 +#define CLK_TOP_MAINPLL_D6 133 +#define CLK_TOP_MAINPLL_D6_D2 134 +#define CLK_TOP_MAINPLL_D6_D4 135 +#define CLK_TOP_MAINPLL_D6_D8 136 +#define CLK_TOP_MAINPLL_D7 137 +#define CLK_TOP_MAINPLL_D7_D2 138 +#define CLK_TOP_MAINPLL_D7_D4 139 +#define CLK_TOP_MAINPLL_D7_D8 140 +#define CLK_TOP_MAINPLL_D9 141 +#define CLK_TOP_UNIVPLL_D2 142 +#define CLK_TOP_UNIVPLL_D3 143 +#define CLK_TOP_UNIVPLL_D4 144 +#define CLK_TOP_UNIVPLL_D4_D2 145 +#define CLK_TOP_UNIVPLL_D4_D4 146 +#define CLK_TOP_UNIVPLL_D4_D8 147 +#define CLK_TOP_UNIVPLL_D5 148 +#define CLK_TOP_UNIVPLL_D5_D2 149 +#define CLK_TOP_UNIVPLL_D5_D4 150 +#define CLK_TOP_UNIVPLL_D5_D8 151 +#define CLK_TOP_UNIVPLL_D6 152 +#define CLK_TOP_UNIVPLL_D6_D2 153 +#define CLK_TOP_UNIVPLL_D6_D4 154 +#define CLK_TOP_UNIVPLL_D6_D8 155 +#define CLK_TOP_UNIVPLL_D6_D16 156 +#define CLK_TOP_UNIVPLL_D7 157 +#define CLK_TOP_UNIVPLL_192M 158 +#define CLK_TOP_UNIVPLL_192M_D4 159 +#define CLK_TOP_UNIVPLL_192M_D8 160 +#define CLK_TOP_UNIVPLL_192M_D16 161 +#define CLK_TOP_UNIVPLL_192M_D32 162 +#define CLK_TOP_APLL1_D3 163 +#define CLK_TOP_APLL1_D4 164 +#define CLK_TOP_APLL2_D3 165 +#define CLK_TOP_APLL2_D4 166 +#define CLK_TOP_APLL3_D4 167 +#define CLK_TOP_APLL4_D4 168 +#define CLK_TOP_APLL5_D4 169 +#define CLK_TOP_HDMIRX_APLL_D3 170 +#define CLK_TOP_HDMIRX_APLL_D4 171 +#define CLK_TOP_HDMIRX_APLL_D6 172 +#define CLK_TOP_MMPLL_D4 173 +#define CLK_TOP_MMPLL_D4_D2 174 +#define CLK_TOP_MMPLL_D4_D4 175 +#define CLK_TOP_MMPLL_D5 176 +#define CLK_TOP_MMPLL_D5_D2 177 +#define CLK_TOP_MMPLL_D5_D4 178 +#define CLK_TOP_MMPLL_D6 179 +#define CLK_TOP_MMPLL_D6_D2 180 +#define CLK_TOP_MMPLL_D7 181 +#define CLK_TOP_MMPLL_D9 182 +#define CLK_TOP_TVDPLL1_D2 183 +#define CLK_TOP_TVDPLL1_D4 184 +#define CLK_TOP_TVDPLL1_D8 185 +#define CLK_TOP_TVDPLL1_D16 186 +#define CLK_TOP_TVDPLL2_D2 187 +#define CLK_TOP_TVDPLL2_D4 188 +#define CLK_TOP_TVDPLL2_D8 189 +#define CLK_TOP_TVDPLL2_D16 190 +#define CLK_TOP_MSDCPLL_D2 191 +#define CLK_TOP_MSDCPLL_D4 192 +#define CLK_TOP_MSDCPLL_D16 193 +#define CLK_TOP_ETHPLL_D2 194 +#define CLK_TOP_ETHPLL_D8 195 +#define CLK_TOP_ETHPLL_D10 196 +#define CLK_TOP_DGIPLL_D2 197 +#define CLK_TOP_ULPOSC1 198 +#define CLK_TOP_ULPOSC1_D2 199 +#define CLK_TOP_ULPOSC1_D4 200 +#define CLK_TOP_ULPOSC1_D7 201 +#define CLK_TOP_ULPOSC1_D8 202 +#define CLK_TOP_ULPOSC1_D10 203 +#define CLK_TOP_ULPOSC1_D16 204 +#define CLK_TOP_ULPOSC2 205 +#define CLK_TOP_ADSPPLL_D2 206 +#define CLK_TOP_ADSPPLL_D4 207 +#define CLK_TOP_ADSPPLL_D8 208 +#define CLK_TOP_MEM_466M 209 +#define CLK_TOP_MPHONE_SLAVE_B 210 +#define CLK_TOP_PEXTP_PIPE 211 +#define CLK_TOP_UFS_RX_SYMBOL 212 +#define CLK_TOP_UFS_TX_SYMBOL 213 +#define CLK_TOP_SSUSB_U3PHY_P1_P_P0 214 +#define CLK_TOP_UFS_RX_SYMBOL1 215 +#define CLK_TOP_FPC 216 +#define CLK_TOP_HDMIRX_P 217 +#define CLK_TOP_APLL12_DIV0 218 +#define CLK_TOP_APLL12_DIV1 219 +#define CLK_TOP_APLL12_DIV2 220 +#define CLK_TOP_APLL12_DIV3 221 +#define CLK_TOP_APLL12_DIV4 222 +#define CLK_TOP_APLL12_DIV9 223 +#define CLK_TOP_CFG_VPP0 224 +#define CLK_TOP_CFG_VPP1 225 +#define CLK_TOP_CFG_VDO0 226 +#define CLK_TOP_CFG_VDO1 227 +#define CLK_TOP_CFG_UNIPLL_SES 228 +#define CLK_TOP_CFG_26M_VPP0 229 +#define CLK_TOP_CFG_26M_VPP1 230 +#define CLK_TOP_CFG_26M_AUD 231 +#define CLK_TOP_CFG_AXI_EAST 232 +#define CLK_TOP_CFG_AXI_EAST_NORTH 233 +#define CLK_TOP_CFG_AXI_NORTH 234 +#define CLK_TOP_CFG_AXI_SOUTH 235 +#define CLK_TOP_CFG_EXT_TEST 236 +#define CLK_TOP_SSUSB_REF 237 +#define CLK_TOP_SSUSB_PHY_REF 238 +#define CLK_TOP_SSUSB_P1_REF 239 +#define CLK_TOP_SSUSB_PHY_P1_REF 240 +#define CLK_TOP_SSUSB_P2_REF 241 +#define CLK_TOP_SSUSB_PHY_P2_REF 242 +#define CLK_TOP_SSUSB_P3_REF 243 +#define CLK_TOP_SSUSB_PHY_P3_REF 244 +#define CLK_TOP_NR_CLK 245 + +/* INFRACFG_AO */ + +#define CLK_INFRA_AO_PMIC_TMR 0 +#define CLK_INFRA_AO_PMIC_AP 1 +#define CLK_INFRA_AO_PMIC_MD 2 +#define CLK_INFRA_AO_PMIC_CONN 3 +#define CLK_INFRA_AO_SEJ 4 +#define CLK_INFRA_AO_APXGPT 5 +#define CLK_INFRA_AO_GCE 6 +#define CLK_INFRA_AO_GCE2 7 +#define CLK_INFRA_AO_THERM 8 +#define CLK_INFRA_AO_PWM_H 9 +#define CLK_INFRA_AO_PWM1 10 +#define CLK_INFRA_AO_PWM2 11 +#define CLK_INFRA_AO_PWM3 12 +#define CLK_INFRA_AO_PWM4 13 +#define CLK_INFRA_AO_PWM 14 +#define CLK_INFRA_AO_UART0 15 +#define CLK_INFRA_AO_UART1 16 +#define CLK_INFRA_AO_UART2 17 +#define CLK_INFRA_AO_UART3 18 +#define CLK_INFRA_AO_UART4 19 +#define CLK_INFRA_AO_GCE_26M 20 +#define CLK_INFRA_AO_CQ_DMA_FPC 21 +#define CLK_INFRA_AO_UART5 22 +#define CLK_INFRA_AO_HDMI_26M 23 +#define CLK_INFRA_AO_SPI0 24 +#define CLK_INFRA_AO_MSDC0 25 +#define CLK_INFRA_AO_MSDC1 26 +#define CLK_INFRA_AO_CG1_MSDC2 27 +#define CLK_INFRA_AO_MSDC0_SRC 28 +#define CLK_INFRA_AO_TRNG 29 +#define CLK_INFRA_AO_AUXADC 30 +#define CLK_INFRA_AO_CPUM 31 +#define CLK_INFRA_AO_HDMI_32K 32 +#define CLK_INFRA_AO_CEC_66M_H 33 +#define CLK_INFRA_AO_IRRX 34 +#define CLK_INFRA_AO_PCIE_TL_26M 35 +#define CLK_INFRA_AO_MSDC1_SRC 36 +#define CLK_INFRA_AO_CEC_66M_B 37 +#define CLK_INFRA_AO_PCIE_TL_96M 38 +#define CLK_INFRA_AO_DEVICE_APC 39 +#define CLK_INFRA_AO_ECC_66M_H 40 +#define CLK_INFRA_AO_DEBUGSYS 41 +#define CLK_INFRA_AO_AUDIO 42 +#define CLK_INFRA_AO_PCIE_TL_32K 43 +#define CLK_INFRA_AO_DBG_TRACE 44 +#define CLK_INFRA_AO_DRAMC_F26M 45 +#define CLK_INFRA_AO_IRTX 46 +#define CLK_INFRA_AO_SSUSB 47 +#define CLK_INFRA_AO_DISP_PWM 48 +#define CLK_INFRA_AO_CLDMA_B 49 +#define CLK_INFRA_AO_AUDIO_26M_B 50 +#define CLK_INFRA_AO_SPI1 51 +#define CLK_INFRA_AO_SPI2 52 +#define CLK_INFRA_AO_SPI3 53 +#define CLK_INFRA_AO_UNIPRO_SYS 54 +#define CLK_INFRA_AO_UNIPRO_TICK 55 +#define CLK_INFRA_AO_UFS_MP_SAP_B 56 +#define CLK_INFRA_AO_PWRMCU 57 +#define CLK_INFRA_AO_PWRMCU_BUS_H 58 +#define CLK_INFRA_AO_APDMA_B 59 +#define CLK_INFRA_AO_SPI4 60 +#define CLK_INFRA_AO_SPI5 61 +#define CLK_INFRA_AO_CQ_DMA 62 +#define CLK_INFRA_AO_AES_UFSFDE 63 +#define CLK_INFRA_AO_AES 64 +#define CLK_INFRA_AO_UFS_TICK 65 +#define CLK_INFRA_AO_SSUSB_XHCI 66 +#define CLK_INFRA_AO_MSDC0_SELF 67 +#define CLK_INFRA_AO_MSDC1_SELF 68 +#define CLK_INFRA_AO_MSDC2_SELF 69 +#define CLK_INFRA_AO_I2S_DMA 70 +#define CLK_INFRA_AO_AP_MSDC0 71 +#define CLK_INFRA_AO_MD_MSDC0 72 +#define CLK_INFRA_AO_CG3_MSDC2 73 +#define CLK_INFRA_AO_GCPU 74 +#define CLK_INFRA_AO_PCIE_PERI_26M 75 +#define CLK_INFRA_AO_GCPU_66M_B 76 +#define CLK_INFRA_AO_GCPU_133M_B 77 +#define CLK_INFRA_AO_DISP_PWM1 78 +#define CLK_INFRA_AO_FBIST2FPC 79 +#define CLK_INFRA_AO_DEVICE_APC_SYNC 80 +#define CLK_INFRA_AO_PCIE_P1_PERI_26M 81 +#define CLK_INFRA_AO_SPIS0 82 +#define CLK_INFRA_AO_SPIS1 83 +#define CLK_INFRA_AO_133M_M_PERI 84 +#define CLK_INFRA_AO_66M_M_PERI 85 +#define CLK_INFRA_AO_PCIE_PL_P_250M_P0 86 +#define CLK_INFRA_AO_PCIE_PL_P_250M_P1 87 +#define CLK_INFRA_AO_PCIE_P1_TL_96M 88 +#define CLK_INFRA_AO_AES_MSDCFDE_0P 89 +#define CLK_INFRA_AO_UFS_TX_SYMBOL 90 +#define CLK_INFRA_AO_UFS_RX_SYMBOL 91 +#define CLK_INFRA_AO_UFS_RX_SYMBOL1 92 +#define CLK_INFRA_AO_PERI_UFS_MEM_SUB 93 +#define CLK_INFRA_AO_NR_CLK 94 + +/* APMIXEDSYS */ + +#define CLK_APMIXED_NNAPLL 0 +#define CLK_APMIXED_RESPLL 1 +#define CLK_APMIXED_ETHPLL 2 +#define CLK_APMIXED_MSDCPLL 3 +#define CLK_APMIXED_TVDPLL1 4 +#define CLK_APMIXED_TVDPLL2 5 +#define CLK_APMIXED_MMPLL 6 +#define CLK_APMIXED_MAINPLL 7 +#define CLK_APMIXED_VDECPLL 8 +#define CLK_APMIXED_IMGPLL 9 +#define CLK_APMIXED_UNIVPLL 10 +#define CLK_APMIXED_HDMIPLL1 11 +#define CLK_APMIXED_HDMIPLL2 12 +#define CLK_APMIXED_HDMIRX_APLL 13 +#define CLK_APMIXED_USB1PLL 14 +#define CLK_APMIXED_ADSPPLL 15 +#define CLK_APMIXED_APLL1 16 +#define CLK_APMIXED_APLL2 17 +#define CLK_APMIXED_APLL3 18 +#define CLK_APMIXED_APLL4 19 +#define CLK_APMIXED_APLL5 20 +#define CLK_APMIXED_MFGPLL 21 +#define CLK_APMIXED_DGIPLL 22 +#define CLK_APMIXED_PLL_SSUSB26M 23 +#define CLK_APMIXED_NR_CLK 24 + +/* SCP_ADSP */ + +#define CLK_SCP_ADSP_AUDIODSP 0 +#define CLK_SCP_ADSP_NR_CLK 1 + +/* PERICFG_AO */ + +#define CLK_PERI_AO_ETHERNET 0 +#define CLK_PERI_AO_ETHERNET_BUS 1 +#define CLK_PERI_AO_FLASHIF_BUS 2 +#define CLK_PERI_AO_FLASHIF_FLASH 3 +#define CLK_PERI_AO_SSUSB_1P_BUS 4 +#define CLK_PERI_AO_SSUSB_1P_XHCI 5 +#define CLK_PERI_AO_SSUSB_2P_BUS 6 +#define CLK_PERI_AO_SSUSB_2P_XHCI 7 +#define CLK_PERI_AO_SSUSB_3P_BUS 8 +#define CLK_PERI_AO_SSUSB_3P_XHCI 9 +#define CLK_PERI_AO_SPINFI 10 +#define CLK_PERI_AO_ETHERNET_MAC 11 +#define CLK_PERI_AO_NFI_H 12 +#define CLK_PERI_AO_FNFI1X 13 +#define CLK_PERI_AO_PCIE_P0_MEM 14 +#define CLK_PERI_AO_PCIE_P1_MEM 15 +#define CLK_PERI_AO_NR_CLK 16 + +/* IMP_IIC_WRAP_S */ + +#define CLK_IMP_IIC_WRAP_S_I2C5 0 +#define CLK_IMP_IIC_WRAP_S_I2C6 1 +#define CLK_IMP_IIC_WRAP_S_I2C7 2 +#define CLK_IMP_IIC_WRAP_S_NR_CLK 3 + +/* IMP_IIC_WRAP_W */ + +#define CLK_IMP_IIC_WRAP_W_I2C0 0 +#define CLK_IMP_IIC_WRAP_W_I2C1 1 +#define CLK_IMP_IIC_WRAP_W_I2C2 2 +#define CLK_IMP_IIC_WRAP_W_I2C3 3 +#define CLK_IMP_IIC_WRAP_W_I2C4 4 +#define CLK_IMP_IIC_WRAP_W_NR_CLK 5 + +/* MFGCFG */ + +#define CLK_MFG_BG3D 0 +#define CLK_MFG_NR_CLK 1 + +/* VPPSYS0 */ + +#define CLK_VPP0_MDP_FG 0 +#define CLK_VPP0_STITCH 1 +#define CLK_VPP0_PADDING 2 +#define CLK_VPP0_MDP_TCC 3 +#define CLK_VPP0_WARP0_ASYNC_TX 4 +#define CLK_VPP0_WARP1_ASYNC_TX 5 +#define CLK_VPP0_MUTEX 6 +#define CLK_VPP0_VPP02VPP1_RELAY 7 +#define CLK_VPP0_VPP12VPP0_ASYNC 8 +#define CLK_VPP0_MMSYSRAM_TOP 9 +#define CLK_VPP0_MDP_AAL 10 +#define CLK_VPP0_MDP_RSZ 11 +#define CLK_VPP0_SMI_COMMON 12 +#define CLK_VPP0_GALS_VDO0_LARB0 13 +#define CLK_VPP0_GALS_VDO0_LARB1 14 +#define CLK_VPP0_GALS_VENCSYS 15 +#define CLK_VPP0_GALS_VENCSYS_CORE1 16 +#define CLK_VPP0_GALS_INFRA 17 +#define CLK_VPP0_GALS_CAMSYS 18 +#define CLK_VPP0_GALS_VPP1_LARB5 19 +#define CLK_VPP0_GALS_VPP1_LARB6 20 +#define CLK_VPP0_SMI_REORDER 21 +#define CLK_VPP0_SMI_IOMMU 22 +#define CLK_VPP0_GALS_IMGSYS_CAMSYS 23 +#define CLK_VPP0_MDP_RDMA 24 +#define CLK_VPP0_MDP_WROT 25 +#define CLK_VPP0_GALS_EMI0_EMI1 26 +#define CLK_VPP0_SMI_SUB_COMMON_REORDER 27 +#define CLK_VPP0_SMI_RSI 28 +#define CLK_VPP0_SMI_COMMON_LARB4 29 +#define CLK_VPP0_GALS_VDEC_VDEC_CORE1 30 +#define CLK_VPP0_GALS_VPP1_WPE 31 +#define CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1 32 +#define CLK_VPP0_FAKE_ENG 33 +#define CLK_VPP0_MDP_HDR 34 +#define CLK_VPP0_MDP_TDSHP 35 +#define CLK_VPP0_MDP_COLOR 36 +#define CLK_VPP0_MDP_OVL 37 +#define CLK_VPP0_WARP0_RELAY 38 +#define CLK_VPP0_WARP0_MDP_DL_ASYNC 39 +#define CLK_VPP0_WARP1_RELAY 40 +#define CLK_VPP0_WARP1_MDP_DL_ASYNC 41 +#define CLK_VPP0_NR_CLK 42 + +/* WPESYS */ + +#define CLK_WPE_VPP0 0 +#define CLK_WPE_VPP1 1 +#define CLK_WPE_SMI_LARB7 2 +#define CLK_WPE_SMI_LARB8 3 +#define CLK_WPE_EVENT_TX 4 +#define CLK_WPE_SMI_LARB7_P 5 +#define CLK_WPE_SMI_LARB8_P 6 +#define CLK_WPE_NR_CLK 7 + +/* WPESYS_VPP0 */ + +#define CLK_WPE_VPP0_VECI 0 +#define CLK_WPE_VPP0_VEC2I 1 +#define CLK_WPE_VPP0_VEC3I 2 +#define CLK_WPE_VPP0_WPEO 3 +#define CLK_WPE_VPP0_MSKO 4 +#define CLK_WPE_VPP0_VGEN 5 +#define CLK_WPE_VPP0_EXT 6 +#define CLK_WPE_VPP0_VFC 7 +#define CLK_WPE_VPP0_CACH0_TOP 8 +#define CLK_WPE_VPP0_CACH0_DMA 9 +#define CLK_WPE_VPP0_CACH1_TOP 10 +#define CLK_WPE_VPP0_CACH1_DMA 11 +#define CLK_WPE_VPP0_CACH2_TOP 12 +#define CLK_WPE_VPP0_CACH2_DMA 13 +#define CLK_WPE_VPP0_CACH3_TOP 14 +#define CLK_WPE_VPP0_CACH3_DMA 15 +#define CLK_WPE_VPP0_PSP 16 +#define CLK_WPE_VPP0_PSP2 17 +#define CLK_WPE_VPP0_SYNC 18 +#define CLK_WPE_VPP0_C24 19 +#define CLK_WPE_VPP0_MDP_CROP 20 +#define CLK_WPE_VPP0_ISP_CROP 21 +#define CLK_WPE_VPP0_TOP 22 +#define CLK_WPE_VPP0_NR_CLK 23 + +/* WPESYS_VPP1 */ + +#define CLK_WPE_VPP1_VECI 0 +#define CLK_WPE_VPP1_VEC2I 1 +#define CLK_WPE_VPP1_VEC3I 2 +#define CLK_WPE_VPP1_WPEO 3 +#define CLK_WPE_VPP1_MSKO 4 +#define CLK_WPE_VPP1_VGEN 5 +#define CLK_WPE_VPP1_EXT 6 +#define CLK_WPE_VPP1_VFC 7 +#define CLK_WPE_VPP1_CACH0_TOP 8 +#define CLK_WPE_VPP1_CACH0_DMA 9 +#define CLK_WPE_VPP1_CACH1_TOP 10 +#define CLK_WPE_VPP1_CACH1_DMA 11 +#define CLK_WPE_VPP1_CACH2_TOP 12 +#define CLK_WPE_VPP1_CACH2_DMA 13 +#define CLK_WPE_VPP1_CACH3_TOP 14 +#define CLK_WPE_VPP1_CACH3_DMA 15 +#define CLK_WPE_VPP1_PSP 16 +#define CLK_WPE_VPP1_PSP2 17 +#define CLK_WPE_VPP1_SYNC 18 +#define CLK_WPE_VPP1_C24 19 +#define CLK_WPE_VPP1_MDP_CROP 20 +#define CLK_WPE_VPP1_ISP_CROP 21 +#define CLK_WPE_VPP1_TOP 22 +#define CLK_WPE_VPP1_NR_CLK 23 + +/* VPPSYS1 */ + +#define CLK_VPP1_SVPP1_MDP_OVL 0 +#define CLK_VPP1_SVPP1_MDP_TCC 1 +#define CLK_VPP1_SVPP1_MDP_WROT 2 +#define CLK_VPP1_SVPP1_VPP_PAD 3 +#define CLK_VPP1_SVPP2_MDP_WROT 4 +#define CLK_VPP1_SVPP2_VPP_PAD 5 +#define CLK_VPP1_SVPP3_MDP_WROT 6 +#define CLK_VPP1_SVPP3_VPP_PAD 7 +#define CLK_VPP1_SVPP1_MDP_RDMA 8 +#define CLK_VPP1_SVPP1_MDP_FG 9 +#define CLK_VPP1_SVPP2_MDP_RDMA 10 +#define CLK_VPP1_SVPP2_MDP_FG 11 +#define CLK_VPP1_SVPP3_MDP_RDMA 12 +#define CLK_VPP1_SVPP3_MDP_FG 13 +#define CLK_VPP1_VPP_SPLIT 14 +#define CLK_VPP1_SVPP2_VDO0_DL_RELAY 15 +#define CLK_VPP1_SVPP1_MDP_TDSHP 16 +#define CLK_VPP1_SVPP1_MDP_COLOR 17 +#define CLK_VPP1_SVPP3_VDO1_DL_RELAY 18 +#define CLK_VPP1_SVPP2_VPP_MERGE 19 +#define CLK_VPP1_SVPP2_MDP_COLOR 20 +#define CLK_VPP1_VPPSYS1_GALS 21 +#define CLK_VPP1_SVPP3_VPP_MERGE 22 +#define CLK_VPP1_SVPP3_MDP_COLOR 23 +#define CLK_VPP1_VPPSYS1_LARB 24 +#define CLK_VPP1_SVPP1_MDP_RSZ 25 +#define CLK_VPP1_SVPP1_MDP_HDR 26 +#define CLK_VPP1_SVPP1_MDP_AAL 27 +#define CLK_VPP1_SVPP2_MDP_HDR 28 +#define CLK_VPP1_SVPP2_MDP_AAL 29 +#define CLK_VPP1_DL_ASYNC 30 +#define CLK_VPP1_LARB5_FAKE_ENG 31 +#define CLK_VPP1_SVPP3_MDP_HDR 32 +#define CLK_VPP1_SVPP3_MDP_AAL 33 +#define CLK_VPP1_SVPP2_VDO1_DL_RELAY 34 +#define CLK_VPP1_LARB6_FAKE_ENG 35 +#define CLK_VPP1_SVPP2_MDP_RSZ 36 +#define CLK_VPP1_SVPP3_MDP_RSZ 37 +#define CLK_VPP1_SVPP3_VDO0_DL_RELAY 38 +#define CLK_VPP1_DISP_MUTEX 39 +#define CLK_VPP1_SVPP2_MDP_TDSHP 40 +#define CLK_VPP1_SVPP3_MDP_TDSHP 41 +#define CLK_VPP1_VPP0_DL1_RELAY 42 +#define CLK_VPP1_HDMI_META 43 +#define CLK_VPP1_VPP_SPLIT_HDMI 44 +#define CLK_VPP1_DGI_IN 45 +#define CLK_VPP1_DGI_OUT 46 +#define CLK_VPP1_VPP_SPLIT_DGI 47 +#define CLK_VPP1_VPP0_DL_ASYNC 48 +#define CLK_VPP1_VPP0_DL_RELAY 49 +#define CLK_VPP1_VPP_SPLIT_26M 50 +#define CLK_VPP1_NR_CLK 51 + +/* IMGSYS */ + +#define CLK_IMG_LARB9 0 +#define CLK_IMG_TRAW0 1 +#define CLK_IMG_TRAW1 2 +#define CLK_IMG_TRAW2 3 +#define CLK_IMG_TRAW3 4 +#define CLK_IMG_DIP0 5 +#define CLK_IMG_WPE0 6 +#define CLK_IMG_IPE 7 +#define CLK_IMG_DIP1 8 +#define CLK_IMG_WPE1 9 +#define CLK_IMG_GALS 10 +#define CLK_IMG_NR_CLK 11 + +/* IMGSYS1_DIP_TOP */ + +#define CLK_IMG1_DIP_TOP_LARB10 0 +#define CLK_IMG1_DIP_TOP_DIP_TOP 1 +#define CLK_IMG1_DIP_TOP_NR_CLK 2 + +/* IMGSYS1_DIP_NR */ + +#define CLK_IMG1_DIP_NR_RESERVE 0 +#define CLK_IMG1_DIP_NR_DIP_NR 1 +#define CLK_IMG1_DIP_NR_NR_CLK 2 + +/* IMGSYS1_WPE */ + +#define CLK_IMG1_WPE_LARB11 0 +#define CLK_IMG1_WPE_WPE 1 +#define CLK_IMG1_WPE_NR_CLK 2 + +/* IPESYS */ + +#define CLK_IPE_DPE 0 +#define CLK_IPE_FDVT 1 +#define CLK_IPE_ME 2 +#define CLK_IPE_TOP 3 +#define CLK_IPE_SMI_LARB12 4 +#define CLK_IPE_NR_CLK 5 + +/* CAMSYS */ + +#define CLK_CAM_LARB13 0 +#define CLK_CAM_LARB14 1 +#define CLK_CAM_MAIN_CAM 2 +#define CLK_CAM_MAIN_CAMTG 3 +#define CLK_CAM_SENINF 4 +#define CLK_CAM_GCAMSVA 5 +#define CLK_CAM_GCAMSVB 6 +#define CLK_CAM_GCAMSVC 7 +#define CLK_CAM_SCAMSA 8 +#define CLK_CAM_SCAMSB 9 +#define CLK_CAM_CAMSV_TOP 10 +#define CLK_CAM_CAMSV_CQ 11 +#define CLK_CAM_ADL 12 +#define CLK_CAM_ASG 13 +#define CLK_CAM_PDA 14 +#define CLK_CAM_FAKE_ENG 15 +#define CLK_CAM_MAIN_MRAW0 16 +#define CLK_CAM_MAIN_MRAW1 17 +#define CLK_CAM_MAIN_MRAW2 18 +#define CLK_CAM_MAIN_MRAW3 19 +#define CLK_CAM_CAM2MM0_GALS 20 +#define CLK_CAM_CAM2MM1_GALS 21 +#define CLK_CAM_CAM2SYS_GALS 22 +#define CLK_CAM_NR_CLK 23 + +/* CAMSYS_RAWA */ + +#define CLK_CAM_RAWA_LARBX 0 +#define CLK_CAM_RAWA_CAM 1 +#define CLK_CAM_RAWA_CAMTG 2 +#define CLK_CAM_RAWA_NR_CLK 3 + +/* CAMSYS_YUVA */ + +#define CLK_CAM_YUVA_LARBX 0 +#define CLK_CAM_YUVA_CAM 1 +#define CLK_CAM_YUVA_CAMTG 2 +#define CLK_CAM_YUVA_NR_CLK 3 + +/* CAMSYS_RAWB */ + +#define CLK_CAM_RAWB_LARBX 0 +#define CLK_CAM_RAWB_CAM 1 +#define CLK_CAM_RAWB_CAMTG 2 +#define CLK_CAM_RAWB_NR_CLK 3 + +/* CAMSYS_YUVB */ + +#define CLK_CAM_YUVB_LARBX 0 +#define CLK_CAM_YUVB_CAM 1 +#define CLK_CAM_YUVB_CAMTG 2 +#define CLK_CAM_YUVB_NR_CLK 3 + +/* CAMSYS_MRAW */ + +#define CLK_CAM_MRAW_LARBX 0 +#define CLK_CAM_MRAW_CAMTG 1 +#define CLK_CAM_MRAW_MRAW0 2 +#define CLK_CAM_MRAW_MRAW1 3 +#define CLK_CAM_MRAW_MRAW2 4 +#define CLK_CAM_MRAW_MRAW3 5 +#define CLK_CAM_MRAW_NR_CLK 6 + +/* CCUSYS */ + +#define CLK_CCU_LARB18 0 +#define CLK_CCU_AHB 1 +#define CLK_CCU_CCU0 2 +#define CLK_CCU_CCU1 3 +#define CLK_CCU_NR_CLK 4 + +/* VDECSYS_SOC */ + +#define CLK_VDEC_SOC_LARB1 0 +#define CLK_VDEC_SOC_LAT 1 +#define CLK_VDEC_SOC_VDEC 2 +#define CLK_VDEC_SOC_NR_CLK 3 + +/* VDECSYS */ + +#define CLK_VDEC_LARB1 0 +#define CLK_VDEC_LAT 1 +#define CLK_VDEC_VDEC 2 +#define CLK_VDEC_NR_CLK 3 + +/* VDECSYS_CORE1 */ + +#define CLK_VDEC_CORE1_LARB1 0 +#define CLK_VDEC_CORE1_LAT 1 +#define CLK_VDEC_CORE1_VDEC 2 +#define CLK_VDEC_CORE1_NR_CLK 3 + +/* APUSYS_PLL */ + +#define CLK_APUSYS_PLL_APUPLL 0 +#define CLK_APUSYS_PLL_NPUPLL 1 +#define CLK_APUSYS_PLL_APUPLL1 2 +#define CLK_APUSYS_PLL_APUPLL2 3 +#define CLK_APUSYS_PLL_NR_CLK 4 + +/* VENCSYS */ + +#define CLK_VENC_LARB 0 +#define CLK_VENC_VENC 1 +#define CLK_VENC_JPGENC 2 +#define CLK_VENC_JPGDEC 3 +#define CLK_VENC_JPGDEC_C1 4 +#define CLK_VENC_GALS 5 +#define CLK_VENC_NR_CLK 6 + +/* VENCSYS_CORE1 */ + +#define CLK_VENC_CORE1_LARB 0 +#define CLK_VENC_CORE1_VENC 1 +#define CLK_VENC_CORE1_JPGENC 2 +#define CLK_VENC_CORE1_JPGDEC 3 +#define CLK_VENC_CORE1_JPGDEC_C1 4 +#define CLK_VENC_CORE1_GALS 5 +#define CLK_VENC_CORE1_NR_CLK 6 + +/* VDOSYS0 */ + +#define CLK_VDO0_DISP_OVL0 0 +#define CLK_VDO0_DISP_COLOR0 1 +#define CLK_VDO0_DISP_COLOR1 2 +#define CLK_VDO0_DISP_CCORR0 3 +#define CLK_VDO0_DISP_CCORR1 4 +#define CLK_VDO0_DISP_AAL0 5 +#define CLK_VDO0_DISP_AAL1 6 +#define CLK_VDO0_DISP_GAMMA0 7 +#define CLK_VDO0_DISP_GAMMA1 8 +#define CLK_VDO0_DISP_DITHER0 9 +#define CLK_VDO0_DISP_DITHER1 10 +#define CLK_VDO0_DISP_OVL1 11 +#define CLK_VDO0_DISP_WDMA0 12 +#define CLK_VDO0_DISP_WDMA1 13 +#define CLK_VDO0_DISP_RDMA0 14 +#define CLK_VDO0_DISP_RDMA1 15 +#define CLK_VDO0_DSI0 16 +#define CLK_VDO0_DSI1 17 +#define CLK_VDO0_DSC_WRAP0 18 +#define CLK_VDO0_VPP_MERGE0 19 +#define CLK_VDO0_DP_INTF0 20 +#define CLK_VDO0_DISP_MUTEX0 21 +#define CLK_VDO0_DISP_IL_ROT0 22 +#define CLK_VDO0_APB_BUS 23 +#define CLK_VDO0_FAKE_ENG0 24 +#define CLK_VDO0_FAKE_ENG1 25 +#define CLK_VDO0_DL_ASYNC0 26 +#define CLK_VDO0_DL_ASYNC1 27 +#define CLK_VDO0_DL_ASYNC2 28 +#define CLK_VDO0_DL_ASYNC3 29 +#define CLK_VDO0_DL_ASYNC4 30 +#define CLK_VDO0_DISP_MONITOR0 31 +#define CLK_VDO0_DISP_MONITOR1 32 +#define CLK_VDO0_DISP_MONITOR2 33 +#define CLK_VDO0_DISP_MONITOR3 34 +#define CLK_VDO0_DISP_MONITOR4 35 +#define CLK_VDO0_SMI_GALS 36 +#define CLK_VDO0_SMI_COMMON 37 +#define CLK_VDO0_SMI_EMI 38 +#define CLK_VDO0_SMI_IOMMU 39 +#define CLK_VDO0_SMI_LARB 40 +#define CLK_VDO0_SMI_RSI 41 +#define CLK_VDO0_DSI0_DSI 42 +#define CLK_VDO0_DSI1_DSI 43 +#define CLK_VDO0_DP_INTF0_DP_INTF 44 +#define CLK_VDO0_NR_CLK 45 + +/* VDOSYS1 */ + +#define CLK_VDO1_SMI_LARB2 0 +#define CLK_VDO1_SMI_LARB3 1 +#define CLK_VDO1_GALS 2 +#define CLK_VDO1_FAKE_ENG0 3 +#define CLK_VDO1_FAKE_ENG 4 +#define CLK_VDO1_MDP_RDMA0 5 +#define CLK_VDO1_MDP_RDMA1 6 +#define CLK_VDO1_MDP_RDMA2 7 +#define CLK_VDO1_MDP_RDMA3 8 +#define CLK_VDO1_VPP_MERGE0 9 +#define CLK_VDO1_VPP_MERGE1 10 +#define CLK_VDO1_VPP_MERGE2 11 +#define CLK_VDO1_VPP_MERGE3 12 +#define CLK_VDO1_VPP_MERGE4 13 +#define CLK_VDO1_VPP2_TO_VDO1_DL_ASYNC 14 +#define CLK_VDO1_VPP3_TO_VDO1_DL_ASYNC 15 +#define CLK_VDO1_DISP_MUTEX 16 +#define CLK_VDO1_MDP_RDMA4 17 +#define CLK_VDO1_MDP_RDMA5 18 +#define CLK_VDO1_MDP_RDMA6 19 +#define CLK_VDO1_MDP_RDMA7 20 +#define CLK_VDO1_DP_INTF0_MM 21 +#define CLK_VDO1_DPI0_MM 22 +#define CLK_VDO1_DPI1_MM 23 +#define CLK_VDO1_DISP_MONITOR 24 +#define CLK_VDO1_MERGE0_DL_ASYNC 25 +#define CLK_VDO1_MERGE1_DL_ASYNC 26 +#define CLK_VDO1_MERGE2_DL_ASYNC 27 +#define CLK_VDO1_MERGE3_DL_ASYNC 28 +#define CLK_VDO1_MERGE4_DL_ASYNC 29 +#define CLK_VDO1_VDO0_DSC_TO_VDO1_DL_ASYNC 30 +#define CLK_VDO1_VDO0_MERGE_TO_VDO1_DL_ASYNC 31 +#define CLK_VDO1_HDR_VDO_FE0 32 +#define CLK_VDO1_HDR_GFX_FE0 33 +#define CLK_VDO1_HDR_VDO_BE 34 +#define CLK_VDO1_HDR_VDO_FE1 35 +#define CLK_VDO1_HDR_GFX_FE1 36 +#define CLK_VDO1_DISP_MIXER 37 +#define CLK_VDO1_HDR_VDO_FE0_DL_ASYNC 38 +#define CLK_VDO1_HDR_VDO_FE1_DL_ASYNC 39 +#define CLK_VDO1_HDR_GFX_FE0_DL_ASYNC 40 +#define CLK_VDO1_HDR_GFX_FE1_DL_ASYNC 41 +#define CLK_VDO1_HDR_VDO_BE_DL_ASYNC 42 +#define CLK_VDO1_DPI0 43 +#define CLK_VDO1_DISP_MONITOR_DPI0 44 +#define CLK_VDO1_DPI1 45 +#define CLK_VDO1_DISP_MONITOR_DPI1 46 +#define CLK_VDO1_DPINTF 47 +#define CLK_VDO1_DISP_MONITOR_DPINTF 48 +#define CLK_VDO1_26M_SLOW 49 +#define CLK_VDO1_DPI1_HDMI 50 +#define CLK_VDO1_NR_CLK 51 + + +#endif /* _DT_BINDINGS_CLK_MT8195_H */ diff --git a/include/dt-bindings/clock/nuvoton,npcm7xx-clock.h b/include/dt-bindings/clock/nuvoton,npcm7xx-clock.h index f21522605b94..3e0a9b68933d 100644 --- a/include/dt-bindings/clock/nuvoton,npcm7xx-clock.h +++ b/include/dt-bindings/clock/nuvoton,npcm7xx-clock.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* * Nuvoton NPCM7xx Clock Generator binding - * clock binding number for all clocks supportted by nuvoton,npcm7xx-clk + * clock binding number for all clocks supported by nuvoton,npcm7xx-clk * * Copyright (C) 2018 Nuvoton Technologies tali.perry@nuvoton.com * diff --git a/include/dt-bindings/clock/nuvoton,npcm845-clk.h b/include/dt-bindings/clock/nuvoton,npcm845-clk.h new file mode 100644 index 000000000000..e5cce08b00e1 --- /dev/null +++ b/include/dt-bindings/clock/nuvoton,npcm845-clk.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2021 Nuvoton Technologies. + * Author: Tomer Maimon <tomer.maimon@nuvoton.com> + * + * Device Tree binding constants for NPCM8XX clock controller. + */ + +#ifndef __DT_BINDINGS_CLOCK_NPCM8XX_H +#define __DT_BINDINGS_CLOCK_NPCM8XX_H + +#define NPCM8XX_CLK_CPU 0 +#define NPCM8XX_CLK_GFX_PIXEL 1 +#define NPCM8XX_CLK_MC 2 +#define NPCM8XX_CLK_ADC 3 +#define NPCM8XX_CLK_AHB 4 +#define NPCM8XX_CLK_TIMER 5 +#define NPCM8XX_CLK_UART 6 +#define NPCM8XX_CLK_UART2 7 +#define NPCM8XX_CLK_MMC 8 +#define NPCM8XX_CLK_SPI3 9 +#define NPCM8XX_CLK_PCI 10 +#define NPCM8XX_CLK_AXI 11 +#define NPCM8XX_CLK_APB4 12 +#define NPCM8XX_CLK_APB3 13 +#define NPCM8XX_CLK_APB2 14 +#define NPCM8XX_CLK_APB1 15 +#define NPCM8XX_CLK_APB5 16 +#define NPCM8XX_CLK_CLKOUT 17 +#define NPCM8XX_CLK_GFX 18 +#define NPCM8XX_CLK_SU 19 +#define NPCM8XX_CLK_SU48 20 +#define NPCM8XX_CLK_SDHC 21 +#define NPCM8XX_CLK_SPI0 22 +#define NPCM8XX_CLK_SPI1 23 +#define NPCM8XX_CLK_SPIX 24 +#define NPCM8XX_CLK_RG 25 +#define NPCM8XX_CLK_RCP 26 +#define NPCM8XX_CLK_PRE_ADC 27 +#define NPCM8XX_CLK_ATB 28 +#define NPCM8XX_CLK_PRE_CLK 29 +#define NPCM8XX_CLK_TH 30 +#define NPCM8XX_CLK_REFCLK 31 +#define NPCM8XX_CLK_SYSBYPCK 32 +#define NPCM8XX_CLK_MCBYPCK 33 + +#define NPCM8XX_NUM_CLOCKS (NPCM8XX_CLK_MCBYPCK + 1) + +#endif diff --git a/include/dt-bindings/clock/omap5.h b/include/dt-bindings/clock/omap5.h index 41775272fd27..90e0d4b00127 100644 --- a/include/dt-bindings/clock/omap5.h +++ b/include/dt-bindings/clock/omap5.h @@ -32,6 +32,8 @@ /* l3main2 clocks */ #define OMAP5_L3_MAIN_2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) +#define OMAP5_L3_MAIN_2_GPMC_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) +#define OMAP5_L3_MAIN_2_OCMC_RAM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) /* ipu clocks */ #define OMAP5_MMU_IPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) diff --git a/include/dt-bindings/clock/qcom,apss-ipq.h b/include/dt-bindings/clock/qcom,apss-ipq.h new file mode 100644 index 000000000000..77b6e05492e2 --- /dev/null +++ b/include/dt-bindings/clock/qcom,apss-ipq.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLOCK_QCA_APSS_IPQ6018_H +#define _DT_BINDINGS_CLOCK_QCA_APSS_IPQ6018_H + +#define APCS_ALIAS0_CLK_SRC 0 +#define APCS_ALIAS0_CORE_CLK 1 + +#endif diff --git a/include/dt-bindings/clock/qcom,camcc-sc7180.h b/include/dt-bindings/clock/qcom,camcc-sc7180.h new file mode 100644 index 000000000000..ef7d3a041b88 --- /dev/null +++ b/include/dt-bindings/clock/qcom,camcc-sc7180.h @@ -0,0 +1,121 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SC7180_H +#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SC7180_H + +/* CAM_CC clocks */ +#define CAM_CC_PLL2_OUT_EARLY 0 +#define CAM_CC_PLL0 1 +#define CAM_CC_PLL1 2 +#define CAM_CC_PLL2 3 +#define CAM_CC_PLL2_OUT_AUX 4 +#define CAM_CC_PLL3 5 +#define CAM_CC_CAMNOC_AXI_CLK 6 +#define CAM_CC_CCI_0_CLK 7 +#define CAM_CC_CCI_0_CLK_SRC 8 +#define CAM_CC_CCI_1_CLK 9 +#define CAM_CC_CCI_1_CLK_SRC 10 +#define CAM_CC_CORE_AHB_CLK 11 +#define CAM_CC_CPAS_AHB_CLK 12 +#define CAM_CC_CPHY_RX_CLK_SRC 13 +#define CAM_CC_CSI0PHYTIMER_CLK 14 +#define CAM_CC_CSI0PHYTIMER_CLK_SRC 15 +#define CAM_CC_CSI1PHYTIMER_CLK 16 +#define CAM_CC_CSI1PHYTIMER_CLK_SRC 17 +#define CAM_CC_CSI2PHYTIMER_CLK 18 +#define CAM_CC_CSI2PHYTIMER_CLK_SRC 19 +#define CAM_CC_CSI3PHYTIMER_CLK 20 +#define CAM_CC_CSI3PHYTIMER_CLK_SRC 21 +#define CAM_CC_CSIPHY0_CLK 22 +#define CAM_CC_CSIPHY1_CLK 23 +#define CAM_CC_CSIPHY2_CLK 24 +#define CAM_CC_CSIPHY3_CLK 25 +#define CAM_CC_FAST_AHB_CLK_SRC 26 +#define CAM_CC_ICP_APB_CLK 27 +#define CAM_CC_ICP_ATB_CLK 28 +#define CAM_CC_ICP_CLK 29 +#define CAM_CC_ICP_CLK_SRC 30 +#define CAM_CC_ICP_CTI_CLK 31 +#define CAM_CC_ICP_TS_CLK 32 +#define CAM_CC_IFE_0_AXI_CLK 33 +#define CAM_CC_IFE_0_CLK 34 +#define CAM_CC_IFE_0_CLK_SRC 35 +#define CAM_CC_IFE_0_CPHY_RX_CLK 36 +#define CAM_CC_IFE_0_CSID_CLK 37 +#define CAM_CC_IFE_0_CSID_CLK_SRC 38 +#define CAM_CC_IFE_0_DSP_CLK 39 +#define CAM_CC_IFE_1_AXI_CLK 40 +#define CAM_CC_IFE_1_CLK 41 +#define CAM_CC_IFE_1_CLK_SRC 42 +#define CAM_CC_IFE_1_CPHY_RX_CLK 43 +#define CAM_CC_IFE_1_CSID_CLK 44 +#define CAM_CC_IFE_1_CSID_CLK_SRC 45 +#define CAM_CC_IFE_1_DSP_CLK 46 +#define CAM_CC_IFE_LITE_CLK 47 +#define CAM_CC_IFE_LITE_CLK_SRC 48 +#define CAM_CC_IFE_LITE_CPHY_RX_CLK 49 +#define CAM_CC_IFE_LITE_CSID_CLK 50 +#define CAM_CC_IFE_LITE_CSID_CLK_SRC 51 +#define CAM_CC_IPE_0_AHB_CLK 52 +#define CAM_CC_IPE_0_AREG_CLK 53 +#define CAM_CC_IPE_0_AXI_CLK 54 +#define CAM_CC_IPE_0_CLK 55 +#define CAM_CC_IPE_0_CLK_SRC 56 +#define CAM_CC_JPEG_CLK 57 +#define CAM_CC_JPEG_CLK_SRC 58 +#define CAM_CC_LRME_CLK 59 +#define CAM_CC_LRME_CLK_SRC 60 +#define CAM_CC_MCLK0_CLK 61 +#define CAM_CC_MCLK0_CLK_SRC 62 +#define CAM_CC_MCLK1_CLK 63 +#define CAM_CC_MCLK1_CLK_SRC 64 +#define CAM_CC_MCLK2_CLK 65 +#define CAM_CC_MCLK2_CLK_SRC 66 +#define CAM_CC_MCLK3_CLK 67 +#define CAM_CC_MCLK3_CLK_SRC 68 +#define CAM_CC_MCLK4_CLK 69 +#define CAM_CC_MCLK4_CLK_SRC 70 +#define CAM_CC_BPS_AHB_CLK 71 +#define CAM_CC_BPS_AREG_CLK 72 +#define CAM_CC_BPS_AXI_CLK 73 +#define CAM_CC_BPS_CLK 74 +#define CAM_CC_BPS_CLK_SRC 75 +#define CAM_CC_SLOW_AHB_CLK_SRC 76 +#define CAM_CC_SOC_AHB_CLK 77 +#define CAM_CC_SYS_TMR_CLK 78 + +/* CAM_CC power domains */ +#define BPS_GDSC 0 +#define IFE_0_GDSC 1 +#define IFE_1_GDSC 2 +#define IPE_0_GDSC 3 +#define TITAN_TOP_GDSC 4 + +/* CAM_CC resets */ +#define CAM_CC_BPS_BCR 0 +#define CAM_CC_CAMNOC_BCR 1 +#define CAM_CC_CCI_0_BCR 2 +#define CAM_CC_CCI_1_BCR 3 +#define CAM_CC_CPAS_BCR 4 +#define CAM_CC_CSI0PHY_BCR 5 +#define CAM_CC_CSI1PHY_BCR 6 +#define CAM_CC_CSI2PHY_BCR 7 +#define CAM_CC_CSI3PHY_BCR 8 +#define CAM_CC_ICP_BCR 9 +#define CAM_CC_IFE_0_BCR 10 +#define CAM_CC_IFE_1_BCR 11 +#define CAM_CC_IFE_LITE_BCR 12 +#define CAM_CC_IPE_0_BCR 13 +#define CAM_CC_JPEG_BCR 14 +#define CAM_CC_LRME_BCR 15 +#define CAM_CC_MCLK0_BCR 16 +#define CAM_CC_MCLK1_BCR 17 +#define CAM_CC_MCLK2_BCR 18 +#define CAM_CC_MCLK3_BCR 19 +#define CAM_CC_MCLK4_BCR 20 +#define CAM_CC_TITAN_TOP_BCR 21 + +#endif diff --git a/include/dt-bindings/clock/qcom,camcc-sc7280.h b/include/dt-bindings/clock/qcom,camcc-sc7280.h new file mode 100644 index 000000000000..56640f407309 --- /dev/null +++ b/include/dt-bindings/clock/qcom,camcc-sc7280.h @@ -0,0 +1,127 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SC7280_H +#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SC7280_H + +/* CAM_CC clocks */ +#define CAM_CC_PLL0 0 +#define CAM_CC_PLL0_OUT_EVEN 1 +#define CAM_CC_PLL0_OUT_ODD 2 +#define CAM_CC_PLL1 3 +#define CAM_CC_PLL1_OUT_EVEN 4 +#define CAM_CC_PLL2 5 +#define CAM_CC_PLL2_OUT_AUX 6 +#define CAM_CC_PLL2_OUT_AUX2 7 +#define CAM_CC_PLL3 8 +#define CAM_CC_PLL3_OUT_EVEN 9 +#define CAM_CC_PLL4 10 +#define CAM_CC_PLL4_OUT_EVEN 11 +#define CAM_CC_PLL5 12 +#define CAM_CC_PLL5_OUT_EVEN 13 +#define CAM_CC_PLL6 14 +#define CAM_CC_PLL6_OUT_EVEN 15 +#define CAM_CC_PLL6_OUT_ODD 16 +#define CAM_CC_BPS_AHB_CLK 17 +#define CAM_CC_BPS_AREG_CLK 18 +#define CAM_CC_BPS_AXI_CLK 19 +#define CAM_CC_BPS_CLK 20 +#define CAM_CC_BPS_CLK_SRC 21 +#define CAM_CC_CAMNOC_AXI_CLK 22 +#define CAM_CC_CAMNOC_AXI_CLK_SRC 23 +#define CAM_CC_CAMNOC_DCD_XO_CLK 24 +#define CAM_CC_CCI_0_CLK 25 +#define CAM_CC_CCI_0_CLK_SRC 26 +#define CAM_CC_CCI_1_CLK 27 +#define CAM_CC_CCI_1_CLK_SRC 28 +#define CAM_CC_CORE_AHB_CLK 29 +#define CAM_CC_CPAS_AHB_CLK 30 +#define CAM_CC_CPHY_RX_CLK_SRC 31 +#define CAM_CC_CSI0PHYTIMER_CLK 32 +#define CAM_CC_CSI0PHYTIMER_CLK_SRC 33 +#define CAM_CC_CSI1PHYTIMER_CLK 34 +#define CAM_CC_CSI1PHYTIMER_CLK_SRC 35 +#define CAM_CC_CSI2PHYTIMER_CLK 36 +#define CAM_CC_CSI2PHYTIMER_CLK_SRC 37 +#define CAM_CC_CSI3PHYTIMER_CLK 38 +#define CAM_CC_CSI3PHYTIMER_CLK_SRC 39 +#define CAM_CC_CSI4PHYTIMER_CLK 40 +#define CAM_CC_CSI4PHYTIMER_CLK_SRC 41 +#define CAM_CC_CSIPHY0_CLK 42 +#define CAM_CC_CSIPHY1_CLK 43 +#define CAM_CC_CSIPHY2_CLK 44 +#define CAM_CC_CSIPHY3_CLK 45 +#define CAM_CC_CSIPHY4_CLK 46 +#define CAM_CC_FAST_AHB_CLK_SRC 47 +#define CAM_CC_GDSC_CLK 48 +#define CAM_CC_ICP_AHB_CLK 49 +#define CAM_CC_ICP_CLK 50 +#define CAM_CC_ICP_CLK_SRC 51 +#define CAM_CC_IFE_0_AXI_CLK 52 +#define CAM_CC_IFE_0_CLK 53 +#define CAM_CC_IFE_0_CLK_SRC 54 +#define CAM_CC_IFE_0_CPHY_RX_CLK 55 +#define CAM_CC_IFE_0_CSID_CLK 56 +#define CAM_CC_IFE_0_CSID_CLK_SRC 57 +#define CAM_CC_IFE_0_DSP_CLK 58 +#define CAM_CC_IFE_1_AXI_CLK 59 +#define CAM_CC_IFE_1_CLK 60 +#define CAM_CC_IFE_1_CLK_SRC 61 +#define CAM_CC_IFE_1_CPHY_RX_CLK 62 +#define CAM_CC_IFE_1_CSID_CLK 63 +#define CAM_CC_IFE_1_CSID_CLK_SRC 64 +#define CAM_CC_IFE_1_DSP_CLK 65 +#define CAM_CC_IFE_2_AXI_CLK 66 +#define CAM_CC_IFE_2_CLK 67 +#define CAM_CC_IFE_2_CLK_SRC 68 +#define CAM_CC_IFE_2_CPHY_RX_CLK 69 +#define CAM_CC_IFE_2_CSID_CLK 70 +#define CAM_CC_IFE_2_CSID_CLK_SRC 71 +#define CAM_CC_IFE_2_DSP_CLK 72 +#define CAM_CC_IFE_LITE_0_CLK 73 +#define CAM_CC_IFE_LITE_0_CLK_SRC 74 +#define CAM_CC_IFE_LITE_0_CPHY_RX_CLK 75 +#define CAM_CC_IFE_LITE_0_CSID_CLK 76 +#define CAM_CC_IFE_LITE_0_CSID_CLK_SRC 77 +#define CAM_CC_IFE_LITE_1_CLK 78 +#define CAM_CC_IFE_LITE_1_CLK_SRC 79 +#define CAM_CC_IFE_LITE_1_CPHY_RX_CLK 80 +#define CAM_CC_IFE_LITE_1_CSID_CLK 81 +#define CAM_CC_IFE_LITE_1_CSID_CLK_SRC 82 +#define CAM_CC_IPE_0_AHB_CLK 83 +#define CAM_CC_IPE_0_AREG_CLK 84 +#define CAM_CC_IPE_0_AXI_CLK 85 +#define CAM_CC_IPE_0_CLK 86 +#define CAM_CC_IPE_0_CLK_SRC 87 +#define CAM_CC_JPEG_CLK 88 +#define CAM_CC_JPEG_CLK_SRC 89 +#define CAM_CC_LRME_CLK 90 +#define CAM_CC_LRME_CLK_SRC 91 +#define CAM_CC_MCLK0_CLK 92 +#define CAM_CC_MCLK0_CLK_SRC 93 +#define CAM_CC_MCLK1_CLK 94 +#define CAM_CC_MCLK1_CLK_SRC 95 +#define CAM_CC_MCLK2_CLK 96 +#define CAM_CC_MCLK2_CLK_SRC 97 +#define CAM_CC_MCLK3_CLK 98 +#define CAM_CC_MCLK3_CLK_SRC 99 +#define CAM_CC_MCLK4_CLK 100 +#define CAM_CC_MCLK4_CLK_SRC 101 +#define CAM_CC_MCLK5_CLK 102 +#define CAM_CC_MCLK5_CLK_SRC 103 +#define CAM_CC_SLEEP_CLK 104 +#define CAM_CC_SLEEP_CLK_SRC 105 +#define CAM_CC_SLOW_AHB_CLK_SRC 106 +#define CAM_CC_XO_CLK_SRC 107 + +/* CAM_CC power domains */ +#define CAM_CC_BPS_GDSC 0 +#define CAM_CC_IFE_0_GDSC 1 +#define CAM_CC_IFE_1_GDSC 2 +#define CAM_CC_IFE_2_GDSC 3 +#define CAM_CC_IPE_0_GDSC 4 +#define CAM_CC_TITAN_TOP_GDSC 5 + +#endif diff --git a/include/dt-bindings/clock/qcom,camcc-sm8250.h b/include/dt-bindings/clock/qcom,camcc-sm8250.h new file mode 100644 index 000000000000..383ead17608d --- /dev/null +++ b/include/dt-bindings/clock/qcom,camcc-sm8250.h @@ -0,0 +1,138 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8250_H +#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8250_H + +/* CAM_CC clocks */ +#define CAM_CC_BPS_AHB_CLK 0 +#define CAM_CC_BPS_AREG_CLK 1 +#define CAM_CC_BPS_AXI_CLK 2 +#define CAM_CC_BPS_CLK 3 +#define CAM_CC_BPS_CLK_SRC 4 +#define CAM_CC_CAMNOC_AXI_CLK 5 +#define CAM_CC_CAMNOC_AXI_CLK_SRC 6 +#define CAM_CC_CAMNOC_DCD_XO_CLK 7 +#define CAM_CC_CCI_0_CLK 8 +#define CAM_CC_CCI_0_CLK_SRC 9 +#define CAM_CC_CCI_1_CLK 10 +#define CAM_CC_CCI_1_CLK_SRC 11 +#define CAM_CC_CORE_AHB_CLK 12 +#define CAM_CC_CPAS_AHB_CLK 13 +#define CAM_CC_CPHY_RX_CLK_SRC 14 +#define CAM_CC_CSI0PHYTIMER_CLK 15 +#define CAM_CC_CSI0PHYTIMER_CLK_SRC 16 +#define CAM_CC_CSI1PHYTIMER_CLK 17 +#define CAM_CC_CSI1PHYTIMER_CLK_SRC 18 +#define CAM_CC_CSI2PHYTIMER_CLK 19 +#define CAM_CC_CSI2PHYTIMER_CLK_SRC 20 +#define CAM_CC_CSI3PHYTIMER_CLK 21 +#define CAM_CC_CSI3PHYTIMER_CLK_SRC 22 +#define CAM_CC_CSI4PHYTIMER_CLK 23 +#define CAM_CC_CSI4PHYTIMER_CLK_SRC 24 +#define CAM_CC_CSI5PHYTIMER_CLK 25 +#define CAM_CC_CSI5PHYTIMER_CLK_SRC 26 +#define CAM_CC_CSIPHY0_CLK 27 +#define CAM_CC_CSIPHY1_CLK 28 +#define CAM_CC_CSIPHY2_CLK 29 +#define CAM_CC_CSIPHY3_CLK 30 +#define CAM_CC_CSIPHY4_CLK 31 +#define CAM_CC_CSIPHY5_CLK 32 +#define CAM_CC_FAST_AHB_CLK_SRC 33 +#define CAM_CC_FD_CORE_CLK 34 +#define CAM_CC_FD_CORE_CLK_SRC 35 +#define CAM_CC_FD_CORE_UAR_CLK 36 +#define CAM_CC_GDSC_CLK 37 +#define CAM_CC_ICP_AHB_CLK 38 +#define CAM_CC_ICP_CLK 39 +#define CAM_CC_ICP_CLK_SRC 40 +#define CAM_CC_IFE_0_AHB_CLK 41 +#define CAM_CC_IFE_0_AREG_CLK 42 +#define CAM_CC_IFE_0_AXI_CLK 43 +#define CAM_CC_IFE_0_CLK 44 +#define CAM_CC_IFE_0_CLK_SRC 45 +#define CAM_CC_IFE_0_CPHY_RX_CLK 46 +#define CAM_CC_IFE_0_CSID_CLK 47 +#define CAM_CC_IFE_0_CSID_CLK_SRC 48 +#define CAM_CC_IFE_0_DSP_CLK 49 +#define CAM_CC_IFE_1_AHB_CLK 50 +#define CAM_CC_IFE_1_AREG_CLK 51 +#define CAM_CC_IFE_1_AXI_CLK 52 +#define CAM_CC_IFE_1_CLK 53 +#define CAM_CC_IFE_1_CLK_SRC 54 +#define CAM_CC_IFE_1_CPHY_RX_CLK 55 +#define CAM_CC_IFE_1_CSID_CLK 56 +#define CAM_CC_IFE_1_CSID_CLK_SRC 57 +#define CAM_CC_IFE_1_DSP_CLK 58 +#define CAM_CC_IFE_LITE_AHB_CLK 59 +#define CAM_CC_IFE_LITE_AXI_CLK 60 +#define CAM_CC_IFE_LITE_CLK 61 +#define CAM_CC_IFE_LITE_CLK_SRC 62 +#define CAM_CC_IFE_LITE_CPHY_RX_CLK 63 +#define CAM_CC_IFE_LITE_CSID_CLK 64 +#define CAM_CC_IFE_LITE_CSID_CLK_SRC 65 +#define CAM_CC_IPE_0_AHB_CLK 66 +#define CAM_CC_IPE_0_AREG_CLK 67 +#define CAM_CC_IPE_0_AXI_CLK 68 +#define CAM_CC_IPE_0_CLK 69 +#define CAM_CC_IPE_0_CLK_SRC 70 +#define CAM_CC_JPEG_CLK 71 +#define CAM_CC_JPEG_CLK_SRC 72 +#define CAM_CC_MCLK0_CLK 73 +#define CAM_CC_MCLK0_CLK_SRC 74 +#define CAM_CC_MCLK1_CLK 75 +#define CAM_CC_MCLK1_CLK_SRC 76 +#define CAM_CC_MCLK2_CLK 77 +#define CAM_CC_MCLK2_CLK_SRC 78 +#define CAM_CC_MCLK3_CLK 79 +#define CAM_CC_MCLK3_CLK_SRC 80 +#define CAM_CC_MCLK4_CLK 81 +#define CAM_CC_MCLK4_CLK_SRC 82 +#define CAM_CC_MCLK5_CLK 83 +#define CAM_CC_MCLK5_CLK_SRC 84 +#define CAM_CC_MCLK6_CLK 85 +#define CAM_CC_MCLK6_CLK_SRC 86 +#define CAM_CC_PLL0 87 +#define CAM_CC_PLL0_OUT_EVEN 88 +#define CAM_CC_PLL0_OUT_ODD 89 +#define CAM_CC_PLL1 90 +#define CAM_CC_PLL1_OUT_EVEN 91 +#define CAM_CC_PLL2 92 +#define CAM_CC_PLL2_OUT_MAIN 93 +#define CAM_CC_PLL3 94 +#define CAM_CC_PLL3_OUT_EVEN 95 +#define CAM_CC_PLL4 96 +#define CAM_CC_PLL4_OUT_EVEN 97 +#define CAM_CC_SBI_AHB_CLK 98 +#define CAM_CC_SBI_AXI_CLK 99 +#define CAM_CC_SBI_CLK 100 +#define CAM_CC_SBI_CPHY_RX_CLK 101 +#define CAM_CC_SBI_CSID_CLK 102 +#define CAM_CC_SBI_CSID_CLK_SRC 103 +#define CAM_CC_SBI_DIV_CLK_SRC 104 +#define CAM_CC_SBI_IFE_0_CLK 105 +#define CAM_CC_SBI_IFE_1_CLK 106 +#define CAM_CC_SLEEP_CLK 107 +#define CAM_CC_SLEEP_CLK_SRC 108 +#define CAM_CC_SLOW_AHB_CLK_SRC 109 +#define CAM_CC_XO_CLK_SRC 110 + +/* CAM_CC resets */ +#define CAM_CC_BPS_BCR 0 +#define CAM_CC_ICP_BCR 1 +#define CAM_CC_IFE_0_BCR 2 +#define CAM_CC_IFE_1_BCR 3 +#define CAM_CC_IPE_0_BCR 4 +#define CAM_CC_SBI_BCR 5 + +/* CAM_CC GDSCRs */ +#define BPS_GDSC 0 +#define IPE_0_GDSC 1 +#define SBI_GDSC 2 +#define IFE_0_GDSC 3 +#define IFE_1_GDSC 4 +#define TITAN_TOP_GDSC 5 + +#endif diff --git a/include/dt-bindings/clock/qcom,dispcc-qcm2290.h b/include/dt-bindings/clock/qcom,dispcc-qcm2290.h new file mode 100644 index 000000000000..1db513d6b3ee --- /dev/null +++ b/include/dt-bindings/clock/qcom,dispcc-qcm2290.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_QCM2290_H +#define _DT_BINDINGS_CLK_QCOM_DISP_CC_QCM2290_H + +/* DISP_CC clocks */ +#define DISP_CC_PLL0 0 +#define DISP_CC_MDSS_AHB_CLK 1 +#define DISP_CC_MDSS_AHB_CLK_SRC 2 +#define DISP_CC_MDSS_BYTE0_CLK 3 +#define DISP_CC_MDSS_BYTE0_CLK_SRC 4 +#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 5 +#define DISP_CC_MDSS_BYTE0_INTF_CLK 6 +#define DISP_CC_MDSS_ESC0_CLK 7 +#define DISP_CC_MDSS_ESC0_CLK_SRC 8 +#define DISP_CC_MDSS_MDP_CLK 9 +#define DISP_CC_MDSS_MDP_CLK_SRC 10 +#define DISP_CC_MDSS_MDP_LUT_CLK 11 +#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 12 +#define DISP_CC_MDSS_PCLK0_CLK 13 +#define DISP_CC_MDSS_PCLK0_CLK_SRC 14 +#define DISP_CC_MDSS_VSYNC_CLK 15 +#define DISP_CC_MDSS_VSYNC_CLK_SRC 16 +#define DISP_CC_SLEEP_CLK 17 +#define DISP_CC_SLEEP_CLK_SRC 18 +#define DISP_CC_XO_CLK 19 +#define DISP_CC_XO_CLK_SRC 20 + +#define MDSS_GDSC 0 + +#endif diff --git a/include/dt-bindings/clock/qcom,dispcc-sc7280.h b/include/dt-bindings/clock/qcom,dispcc-sc7280.h new file mode 100644 index 000000000000..a4a692c20acf --- /dev/null +++ b/include/dt-bindings/clock/qcom,dispcc-sc7280.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7280_H +#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7280_H + +/* DISP_CC clocks */ +#define DISP_CC_PLL0 0 +#define DISP_CC_MDSS_AHB_CLK 1 +#define DISP_CC_MDSS_AHB_CLK_SRC 2 +#define DISP_CC_MDSS_BYTE0_CLK 3 +#define DISP_CC_MDSS_BYTE0_CLK_SRC 4 +#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 5 +#define DISP_CC_MDSS_BYTE0_INTF_CLK 6 +#define DISP_CC_MDSS_DP_AUX_CLK 7 +#define DISP_CC_MDSS_DP_AUX_CLK_SRC 8 +#define DISP_CC_MDSS_DP_CRYPTO_CLK 9 +#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 10 +#define DISP_CC_MDSS_DP_LINK_CLK 11 +#define DISP_CC_MDSS_DP_LINK_CLK_SRC 12 +#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC 13 +#define DISP_CC_MDSS_DP_LINK_INTF_CLK 14 +#define DISP_CC_MDSS_DP_PIXEL_CLK 15 +#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 16 +#define DISP_CC_MDSS_EDP_AUX_CLK 17 +#define DISP_CC_MDSS_EDP_AUX_CLK_SRC 18 +#define DISP_CC_MDSS_EDP_LINK_CLK 19 +#define DISP_CC_MDSS_EDP_LINK_CLK_SRC 20 +#define DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC 21 +#define DISP_CC_MDSS_EDP_LINK_INTF_CLK 22 +#define DISP_CC_MDSS_EDP_PIXEL_CLK 23 +#define DISP_CC_MDSS_EDP_PIXEL_CLK_SRC 24 +#define DISP_CC_MDSS_ESC0_CLK 25 +#define DISP_CC_MDSS_ESC0_CLK_SRC 26 +#define DISP_CC_MDSS_MDP_CLK 27 +#define DISP_CC_MDSS_MDP_CLK_SRC 28 +#define DISP_CC_MDSS_MDP_LUT_CLK 29 +#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 30 +#define DISP_CC_MDSS_PCLK0_CLK 31 +#define DISP_CC_MDSS_PCLK0_CLK_SRC 32 +#define DISP_CC_MDSS_ROT_CLK 33 +#define DISP_CC_MDSS_ROT_CLK_SRC 34 +#define DISP_CC_MDSS_RSCC_AHB_CLK 35 +#define DISP_CC_MDSS_RSCC_VSYNC_CLK 36 +#define DISP_CC_MDSS_VSYNC_CLK 37 +#define DISP_CC_MDSS_VSYNC_CLK_SRC 38 +#define DISP_CC_SLEEP_CLK 39 +#define DISP_CC_XO_CLK 40 + +/* DISP_CC power domains */ +#define DISP_CC_MDSS_CORE_GDSC 0 + +#endif diff --git a/include/dt-bindings/clock/qcom,dispcc-sm6125.h b/include/dt-bindings/clock/qcom,dispcc-sm6125.h new file mode 100644 index 000000000000..4ff974f4fcc3 --- /dev/null +++ b/include/dt-bindings/clock/qcom,dispcc-sm6125.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6125_H +#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6125_H + +#define DISP_CC_PLL0 0 +#define DISP_CC_MDSS_AHB_CLK 1 +#define DISP_CC_MDSS_AHB_CLK_SRC 2 +#define DISP_CC_MDSS_BYTE0_CLK 3 +#define DISP_CC_MDSS_BYTE0_CLK_SRC 4 +#define DISP_CC_MDSS_BYTE0_INTF_CLK 5 +#define DISP_CC_MDSS_DP_AUX_CLK 6 +#define DISP_CC_MDSS_DP_AUX_CLK_SRC 7 +#define DISP_CC_MDSS_DP_CRYPTO_CLK 8 +#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 9 +#define DISP_CC_MDSS_DP_LINK_CLK 10 +#define DISP_CC_MDSS_DP_LINK_CLK_SRC 11 +#define DISP_CC_MDSS_DP_LINK_INTF_CLK 12 +#define DISP_CC_MDSS_DP_PIXEL_CLK 13 +#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 14 +#define DISP_CC_MDSS_ESC0_CLK 15 +#define DISP_CC_MDSS_ESC0_CLK_SRC 16 +#define DISP_CC_MDSS_MDP_CLK 17 +#define DISP_CC_MDSS_MDP_CLK_SRC 18 +#define DISP_CC_MDSS_MDP_LUT_CLK 19 +#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 20 +#define DISP_CC_MDSS_PCLK0_CLK 21 +#define DISP_CC_MDSS_PCLK0_CLK_SRC 22 +#define DISP_CC_MDSS_ROT_CLK 23 +#define DISP_CC_MDSS_ROT_CLK_SRC 24 +#define DISP_CC_MDSS_VSYNC_CLK 25 +#define DISP_CC_MDSS_VSYNC_CLK_SRC 26 +#define DISP_CC_XO_CLK 27 + +/* DISP_CC GDSCR */ +#define MDSS_GDSC 0 + +#endif diff --git a/include/dt-bindings/clock/qcom,dispcc-sm6350.h b/include/dt-bindings/clock/qcom,dispcc-sm6350.h new file mode 100644 index 000000000000..cb54aae2723e --- /dev/null +++ b/include/dt-bindings/clock/qcom,dispcc-sm6350.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6350_H +#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6350_H + +/* DISP_CC clocks */ +#define DISP_CC_PLL0 0 +#define DISP_CC_MDSS_AHB_CLK 1 +#define DISP_CC_MDSS_AHB_CLK_SRC 2 +#define DISP_CC_MDSS_BYTE0_CLK 3 +#define DISP_CC_MDSS_BYTE0_CLK_SRC 4 +#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 5 +#define DISP_CC_MDSS_BYTE0_INTF_CLK 6 +#define DISP_CC_MDSS_DP_AUX_CLK 7 +#define DISP_CC_MDSS_DP_AUX_CLK_SRC 8 +#define DISP_CC_MDSS_DP_CRYPTO_CLK 9 +#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 10 +#define DISP_CC_MDSS_DP_LINK_CLK 11 +#define DISP_CC_MDSS_DP_LINK_CLK_SRC 12 +#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC 13 +#define DISP_CC_MDSS_DP_LINK_INTF_CLK 14 +#define DISP_CC_MDSS_DP_PIXEL_CLK 15 +#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 16 +#define DISP_CC_MDSS_ESC0_CLK 17 +#define DISP_CC_MDSS_ESC0_CLK_SRC 18 +#define DISP_CC_MDSS_MDP_CLK 19 +#define DISP_CC_MDSS_MDP_CLK_SRC 20 +#define DISP_CC_MDSS_MDP_LUT_CLK 21 +#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 22 +#define DISP_CC_MDSS_PCLK0_CLK 23 +#define DISP_CC_MDSS_PCLK0_CLK_SRC 24 +#define DISP_CC_MDSS_ROT_CLK 25 +#define DISP_CC_MDSS_ROT_CLK_SRC 26 +#define DISP_CC_MDSS_RSCC_AHB_CLK 27 +#define DISP_CC_MDSS_RSCC_VSYNC_CLK 28 +#define DISP_CC_MDSS_VSYNC_CLK 29 +#define DISP_CC_MDSS_VSYNC_CLK_SRC 30 +#define DISP_CC_SLEEP_CLK 31 +#define DISP_CC_XO_CLK 32 + +/* GDSCs */ +#define MDSS_GDSC 0 + +#endif diff --git a/include/dt-bindings/clock/qcom,dispcc-sm8150.h b/include/dt-bindings/clock/qcom,dispcc-sm8150.h new file mode 120000 index 000000000000..0312b4544acb --- /dev/null +++ b/include/dt-bindings/clock/qcom,dispcc-sm8150.h @@ -0,0 +1 @@ +qcom,dispcc-sm8250.h
\ No newline at end of file diff --git a/include/dt-bindings/clock/qcom,dispcc-sm8250.h b/include/dt-bindings/clock/qcom,dispcc-sm8250.h new file mode 100644 index 000000000000..ce001cbbc27f --- /dev/null +++ b/include/dt-bindings/clock/qcom,dispcc-sm8250.h @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8250_H +#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8250_H + +/* DISP_CC clock registers */ +#define DISP_CC_MDSS_AHB_CLK 0 +#define DISP_CC_MDSS_AHB_CLK_SRC 1 +#define DISP_CC_MDSS_BYTE0_CLK 2 +#define DISP_CC_MDSS_BYTE0_CLK_SRC 3 +#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 4 +#define DISP_CC_MDSS_BYTE0_INTF_CLK 5 +#define DISP_CC_MDSS_BYTE1_CLK 6 +#define DISP_CC_MDSS_BYTE1_CLK_SRC 7 +#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 8 +#define DISP_CC_MDSS_BYTE1_INTF_CLK 9 +#define DISP_CC_MDSS_DP_AUX1_CLK 10 +#define DISP_CC_MDSS_DP_AUX1_CLK_SRC 11 +#define DISP_CC_MDSS_DP_AUX_CLK 12 +#define DISP_CC_MDSS_DP_AUX_CLK_SRC 13 +#define DISP_CC_MDSS_DP_LINK1_CLK 14 +#define DISP_CC_MDSS_DP_LINK1_CLK_SRC 15 +#define DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC 16 +#define DISP_CC_MDSS_DP_LINK1_INTF_CLK 17 +#define DISP_CC_MDSS_DP_LINK_CLK 18 +#define DISP_CC_MDSS_DP_LINK_CLK_SRC 19 +#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC 20 +#define DISP_CC_MDSS_DP_LINK_INTF_CLK 21 +#define DISP_CC_MDSS_DP_PIXEL1_CLK 22 +#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC 23 +#define DISP_CC_MDSS_DP_PIXEL2_CLK 24 +#define DISP_CC_MDSS_DP_PIXEL2_CLK_SRC 25 +#define DISP_CC_MDSS_DP_PIXEL_CLK 26 +#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 27 +#define DISP_CC_MDSS_ESC0_CLK 28 +#define DISP_CC_MDSS_ESC0_CLK_SRC 29 +#define DISP_CC_MDSS_ESC1_CLK 30 +#define DISP_CC_MDSS_ESC1_CLK_SRC 31 +#define DISP_CC_MDSS_MDP_CLK 32 +#define DISP_CC_MDSS_MDP_CLK_SRC 33 +#define DISP_CC_MDSS_MDP_LUT_CLK 34 +#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 35 +#define DISP_CC_MDSS_PCLK0_CLK 36 +#define DISP_CC_MDSS_PCLK0_CLK_SRC 37 +#define DISP_CC_MDSS_PCLK1_CLK 38 +#define DISP_CC_MDSS_PCLK1_CLK_SRC 39 +#define DISP_CC_MDSS_ROT_CLK 40 +#define DISP_CC_MDSS_ROT_CLK_SRC 41 +#define DISP_CC_MDSS_RSCC_AHB_CLK 42 +#define DISP_CC_MDSS_RSCC_VSYNC_CLK 43 +#define DISP_CC_MDSS_VSYNC_CLK 44 +#define DISP_CC_MDSS_VSYNC_CLK_SRC 45 +#define DISP_CC_PLL0 46 +#define DISP_CC_PLL1 47 +#define DISP_CC_MDSS_EDP_AUX_CLK 48 +#define DISP_CC_MDSS_EDP_AUX_CLK_SRC 49 +#define DISP_CC_MDSS_EDP_GTC_CLK 50 +#define DISP_CC_MDSS_EDP_GTC_CLK_SRC 51 +#define DISP_CC_MDSS_EDP_LINK_CLK 52 +#define DISP_CC_MDSS_EDP_LINK_CLK_SRC 53 +#define DISP_CC_MDSS_EDP_LINK_INTF_CLK 54 +#define DISP_CC_MDSS_EDP_PIXEL_CLK 55 +#define DISP_CC_MDSS_EDP_PIXEL_CLK_SRC 56 + +/* DISP_CC Reset */ +#define DISP_CC_MDSS_CORE_BCR 0 +#define DISP_CC_MDSS_RSCC_BCR 1 + +/* DISP_CC GDSCR */ +#define MDSS_GDSC 0 + +#endif diff --git a/include/dt-bindings/clock/qcom,dispcc-sm8350.h b/include/dt-bindings/clock/qcom,dispcc-sm8350.h new file mode 120000 index 000000000000..0312b4544acb --- /dev/null +++ b/include/dt-bindings/clock/qcom,dispcc-sm8350.h @@ -0,0 +1 @@ +qcom,dispcc-sm8250.h
\ No newline at end of file diff --git a/include/dt-bindings/clock/qcom,gcc-ipq806x.h b/include/dt-bindings/clock/qcom,gcc-ipq806x.h index 7deec14a6dee..02262d2ac899 100644 --- a/include/dt-bindings/clock/qcom,gcc-ipq806x.h +++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h @@ -240,7 +240,7 @@ #define PLL14 232 #define PLL14_VOTE 233 #define PLL18 234 -#define CE5_SRC 235 +#define CE5_A_CLK 235 #define CE5_H_CLK 236 #define CE5_CORE_CLK 237 #define CE3_SLEEP_CLK 238 @@ -283,5 +283,8 @@ #define EBI2_AON_CLK 281 #define NSSTCM_CLK_SRC 282 #define NSSTCM_CLK 283 +#define CE5_A_CLK_SRC 285 +#define CE5_H_CLK_SRC 286 +#define CE5_CORE_CLK_SRC 287 #endif diff --git a/include/dt-bindings/clock/qcom,gcc-ipq8074.h b/include/dt-bindings/clock/qcom,gcc-ipq8074.h index 4de4811a3540..e4991d303708 100644 --- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h +++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h @@ -230,6 +230,10 @@ #define GCC_GP1_CLK 221 #define GCC_GP2_CLK 222 #define GCC_GP3_CLK 223 +#define GCC_PCIE0_AXI_S_BRIDGE_CLK 224 +#define GCC_PCIE0_RCHNG_CLK_SRC 225 +#define GCC_PCIE0_RCHNG_CLK 226 +#define GCC_CRYPTO_PPE_CLK 227 #define GCC_BLSP1_BCR 0 #define GCC_BLSP1_QUP1_BCR 1 @@ -362,5 +366,9 @@ #define GCC_PCIE1_AXI_SLAVE_ARES 128 #define GCC_PCIE1_AHB_ARES 129 #define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130 +#define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 131 + +#define USB0_GDSC 0 +#define USB1_GDSC 1 #endif diff --git a/include/dt-bindings/clock/qcom,gcc-mdm9607.h b/include/dt-bindings/clock/qcom,gcc-mdm9607.h new file mode 100644 index 000000000000..357a680a40da --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-mdm9607.h @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */ +/* + * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> + */ + +#ifndef _DT_BINDINGS_CLK_MSM_GCC_9607_H +#define _DT_BINDINGS_CLK_MSM_GCC_9607_H + +#define GPLL0 0 +#define GPLL0_EARLY 1 +#define GPLL1 2 +#define GPLL1_VOTE 3 +#define GPLL2 4 +#define GPLL2_EARLY 5 +#define PCNOC_BFDCD_CLK_SRC 6 +#define SYSTEM_NOC_BFDCD_CLK_SRC 7 +#define GCC_SMMU_CFG_CLK 8 +#define APSS_AHB_CLK_SRC 9 +#define GCC_QDSS_DAP_CLK 10 +#define BLSP1_QUP1_I2C_APPS_CLK_SRC 11 +#define BLSP1_QUP1_SPI_APPS_CLK_SRC 12 +#define BLSP1_QUP2_I2C_APPS_CLK_SRC 13 +#define BLSP1_QUP2_SPI_APPS_CLK_SRC 14 +#define BLSP1_QUP3_I2C_APPS_CLK_SRC 15 +#define BLSP1_QUP3_SPI_APPS_CLK_SRC 16 +#define BLSP1_QUP4_I2C_APPS_CLK_SRC 17 +#define BLSP1_QUP4_SPI_APPS_CLK_SRC 18 +#define BLSP1_QUP5_I2C_APPS_CLK_SRC 19 +#define BLSP1_QUP5_SPI_APPS_CLK_SRC 20 +#define BLSP1_QUP6_I2C_APPS_CLK_SRC 21 +#define BLSP1_QUP6_SPI_APPS_CLK_SRC 22 +#define BLSP1_UART1_APPS_CLK_SRC 23 +#define BLSP1_UART2_APPS_CLK_SRC 24 +#define CRYPTO_CLK_SRC 25 +#define GP1_CLK_SRC 26 +#define GP2_CLK_SRC 27 +#define GP3_CLK_SRC 28 +#define PDM2_CLK_SRC 29 +#define SDCC1_APPS_CLK_SRC 30 +#define SDCC2_APPS_CLK_SRC 31 +#define APSS_TCU_CLK_SRC 32 +#define USB_HS_SYSTEM_CLK_SRC 33 +#define GCC_BLSP1_AHB_CLK 34 +#define GCC_BLSP1_SLEEP_CLK 35 +#define GCC_BLSP1_QUP1_I2C_APPS_CLK 36 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK 37 +#define GCC_BLSP1_QUP2_I2C_APPS_CLK 38 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK 39 +#define GCC_BLSP1_QUP3_I2C_APPS_CLK 40 +#define GCC_BLSP1_QUP3_SPI_APPS_CLK 41 +#define GCC_BLSP1_QUP4_I2C_APPS_CLK 42 +#define GCC_BLSP1_QUP4_SPI_APPS_CLK 43 +#define GCC_BLSP1_QUP5_I2C_APPS_CLK 44 +#define GCC_BLSP1_QUP5_SPI_APPS_CLK 45 +#define GCC_BLSP1_QUP6_I2C_APPS_CLK 46 +#define GCC_BLSP1_QUP6_SPI_APPS_CLK 47 +#define GCC_BLSP1_UART1_APPS_CLK 48 +#define GCC_BLSP1_UART2_APPS_CLK 49 +#define GCC_BOOT_ROM_AHB_CLK 50 +#define GCC_CRYPTO_AHB_CLK 51 +#define GCC_CRYPTO_AXI_CLK 52 +#define GCC_CRYPTO_CLK 53 +#define GCC_GP1_CLK 54 +#define GCC_GP2_CLK 55 +#define GCC_GP3_CLK 56 +#define GCC_MSS_CFG_AHB_CLK 57 +#define GCC_PDM2_CLK 58 +#define GCC_PDM_AHB_CLK 59 +#define GCC_PRNG_AHB_CLK 60 +#define GCC_SDCC1_AHB_CLK 61 +#define GCC_SDCC1_APPS_CLK 62 +#define GCC_SDCC2_AHB_CLK 63 +#define GCC_SDCC2_APPS_CLK 64 +#define GCC_USB2A_PHY_SLEEP_CLK 65 +#define GCC_USB_HS_AHB_CLK 66 +#define GCC_USB_HS_SYSTEM_CLK 67 +#define GCC_APSS_TCU_CLK 68 +#define GCC_MSS_Q6_BIMC_AXI_CLK 69 +#define BIMC_PLL 70 +#define BIMC_PLL_VOTE 71 +#define BIMC_DDR_CLK_SRC 72 +#define BLSP1_UART3_APPS_CLK_SRC 73 +#define BLSP1_UART4_APPS_CLK_SRC 74 +#define BLSP1_UART5_APPS_CLK_SRC 75 +#define BLSP1_UART6_APPS_CLK_SRC 76 +#define GCC_BLSP1_UART3_APPS_CLK 77 +#define GCC_BLSP1_UART4_APPS_CLK 78 +#define GCC_BLSP1_UART5_APPS_CLK 79 +#define GCC_BLSP1_UART6_APPS_CLK 80 +#define GCC_APSS_AHB_CLK 81 +#define GCC_APSS_AXI_CLK 82 +#define GCC_USB_HS_PHY_CFG_AHB_CLK 83 +#define GCC_USB_HSIC_CLK_SRC 84 +#define GCC_USB_HSIC_IO_CAL_CLK_SRC 85 +#define GCC_USB_HSIC_SYSTEM_CLK_SRC 86 + +/* Resets */ +#define USB2_HS_PHY_ONLY_BCR 0 +#define QUSB2_PHY_BCR 1 +#define GCC_MSS_RESTART 2 +#define USB_HS_HSIC_BCR 3 +#define USB_HS_BCR 4 + +#endif diff --git a/include/dt-bindings/clock/qcom,gcc-msm8909.h b/include/dt-bindings/clock/qcom,gcc-msm8909.h new file mode 100644 index 000000000000..4394ba003425 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-msm8909.h @@ -0,0 +1,218 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2022 Kernkonzept GmbH. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_8909_H +#define _DT_BINDINGS_CLK_QCOM_GCC_8909_H + +/* PLLs */ +#define GPLL0_EARLY 0 +#define GPLL0 1 +#define GPLL1 2 +#define GPLL1_VOTE 3 +#define GPLL2_EARLY 4 +#define GPLL2 5 +#define BIMC_PLL_EARLY 6 +#define BIMC_PLL 7 + +/* RCGs */ +#define APSS_AHB_CLK_SRC 8 +#define BIMC_DDR_CLK_SRC 9 +#define BIMC_GPU_CLK_SRC 10 +#define BLSP1_QUP1_I2C_APPS_CLK_SRC 11 +#define BLSP1_QUP1_SPI_APPS_CLK_SRC 12 +#define BLSP1_QUP2_I2C_APPS_CLK_SRC 13 +#define BLSP1_QUP2_SPI_APPS_CLK_SRC 14 +#define BLSP1_QUP3_I2C_APPS_CLK_SRC 15 +#define BLSP1_QUP3_SPI_APPS_CLK_SRC 16 +#define BLSP1_QUP4_I2C_APPS_CLK_SRC 17 +#define BLSP1_QUP4_SPI_APPS_CLK_SRC 18 +#define BLSP1_QUP5_I2C_APPS_CLK_SRC 19 +#define BLSP1_QUP5_SPI_APPS_CLK_SRC 20 +#define BLSP1_QUP6_I2C_APPS_CLK_SRC 21 +#define BLSP1_QUP6_SPI_APPS_CLK_SRC 22 +#define BLSP1_UART1_APPS_CLK_SRC 23 +#define BLSP1_UART2_APPS_CLK_SRC 24 +#define BYTE0_CLK_SRC 25 +#define CAMSS_GP0_CLK_SRC 26 +#define CAMSS_GP1_CLK_SRC 27 +#define CAMSS_TOP_AHB_CLK_SRC 28 +#define CODEC_DIGCODEC_CLK_SRC 29 +#define CRYPTO_CLK_SRC 30 +#define CSI0_CLK_SRC 31 +#define CSI0PHYTIMER_CLK_SRC 32 +#define CSI1_CLK_SRC 33 +#define ESC0_CLK_SRC 34 +#define GFX3D_CLK_SRC 35 +#define GP1_CLK_SRC 36 +#define GP2_CLK_SRC 37 +#define GP3_CLK_SRC 38 +#define MCLK0_CLK_SRC 39 +#define MCLK1_CLK_SRC 40 +#define MDP_CLK_SRC 41 +#define PCLK0_CLK_SRC 42 +#define PCNOC_BFDCD_CLK_SRC 43 +#define PDM2_CLK_SRC 44 +#define SDCC1_APPS_CLK_SRC 45 +#define SDCC2_APPS_CLK_SRC 46 +#define SYSTEM_NOC_BFDCD_CLK_SRC 47 +#define ULTAUDIO_AHBFABRIC_CLK_SRC 48 +#define ULTAUDIO_LPAIF_AUX_I2S_CLK_SRC 49 +#define ULTAUDIO_LPAIF_PRI_I2S_CLK_SRC 50 +#define ULTAUDIO_LPAIF_SEC_I2S_CLK_SRC 51 +#define ULTAUDIO_XO_CLK_SRC 52 +#define USB_HS_SYSTEM_CLK_SRC 53 +#define VCODEC0_CLK_SRC 54 +#define VFE0_CLK_SRC 55 +#define VSYNC_CLK_SRC 56 + +/* Voteable Clocks */ +#define GCC_APSS_TCU_CLK 57 +#define GCC_BLSP1_AHB_CLK 58 +#define GCC_BLSP1_SLEEP_CLK 59 +#define GCC_BOOT_ROM_AHB_CLK 60 +#define GCC_CRYPTO_CLK 61 +#define GCC_CRYPTO_AHB_CLK 62 +#define GCC_CRYPTO_AXI_CLK 63 +#define GCC_GFX_TBU_CLK 64 +#define GCC_GFX_TCU_CLK 65 +#define GCC_GTCU_AHB_CLK 66 +#define GCC_MDP_TBU_CLK 67 +#define GCC_PRNG_AHB_CLK 68 +#define GCC_SMMU_CFG_CLK 69 +#define GCC_VENUS_TBU_CLK 70 +#define GCC_VFE_TBU_CLK 71 + +/* Branches */ +#define GCC_BIMC_GFX_CLK 72 +#define GCC_BIMC_GPU_CLK 73 +#define GCC_BLSP1_QUP1_I2C_APPS_CLK 74 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK 75 +#define GCC_BLSP1_QUP2_I2C_APPS_CLK 76 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK 77 +#define GCC_BLSP1_QUP3_I2C_APPS_CLK 78 +#define GCC_BLSP1_QUP3_SPI_APPS_CLK 79 +#define GCC_BLSP1_QUP4_I2C_APPS_CLK 80 +#define GCC_BLSP1_QUP4_SPI_APPS_CLK 81 +#define GCC_BLSP1_QUP5_I2C_APPS_CLK 82 +#define GCC_BLSP1_QUP5_SPI_APPS_CLK 83 +#define GCC_BLSP1_QUP6_I2C_APPS_CLK 84 +#define GCC_BLSP1_QUP6_SPI_APPS_CLK 85 +#define GCC_BLSP1_UART1_APPS_CLK 86 +#define GCC_BLSP1_UART2_APPS_CLK 87 +#define GCC_CAMSS_AHB_CLK 88 +#define GCC_CAMSS_CSI0_CLK 89 +#define GCC_CAMSS_CSI0_AHB_CLK 90 +#define GCC_CAMSS_CSI0PHY_CLK 91 +#define GCC_CAMSS_CSI0PHYTIMER_CLK 92 +#define GCC_CAMSS_CSI0PIX_CLK 93 +#define GCC_CAMSS_CSI0RDI_CLK 94 +#define GCC_CAMSS_CSI1_CLK 95 +#define GCC_CAMSS_CSI1_AHB_CLK 96 +#define GCC_CAMSS_CSI1PHY_CLK 97 +#define GCC_CAMSS_CSI1PIX_CLK 98 +#define GCC_CAMSS_CSI1RDI_CLK 99 +#define GCC_CAMSS_CSI_VFE0_CLK 100 +#define GCC_CAMSS_GP0_CLK 101 +#define GCC_CAMSS_GP1_CLK 102 +#define GCC_CAMSS_ISPIF_AHB_CLK 103 +#define GCC_CAMSS_MCLK0_CLK 104 +#define GCC_CAMSS_MCLK1_CLK 105 +#define GCC_CAMSS_TOP_AHB_CLK 106 +#define GCC_CAMSS_VFE0_CLK 107 +#define GCC_CAMSS_VFE_AHB_CLK 108 +#define GCC_CAMSS_VFE_AXI_CLK 109 +#define GCC_CODEC_DIGCODEC_CLK 110 +#define GCC_GP1_CLK 111 +#define GCC_GP2_CLK 112 +#define GCC_GP3_CLK 113 +#define GCC_MDSS_AHB_CLK 114 +#define GCC_MDSS_AXI_CLK 115 +#define GCC_MDSS_BYTE0_CLK 116 +#define GCC_MDSS_ESC0_CLK 117 +#define GCC_MDSS_MDP_CLK 118 +#define GCC_MDSS_PCLK0_CLK 119 +#define GCC_MDSS_VSYNC_CLK 120 +#define GCC_MSS_CFG_AHB_CLK 121 +#define GCC_MSS_Q6_BIMC_AXI_CLK 122 +#define GCC_OXILI_AHB_CLK 123 +#define GCC_OXILI_GFX3D_CLK 124 +#define GCC_PDM2_CLK 125 +#define GCC_PDM_AHB_CLK 126 +#define GCC_SDCC1_AHB_CLK 127 +#define GCC_SDCC1_APPS_CLK 128 +#define GCC_SDCC2_AHB_CLK 129 +#define GCC_SDCC2_APPS_CLK 130 +#define GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK 131 +#define GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CLK 132 +#define GCC_ULTAUDIO_AVSYNC_XO_CLK 133 +#define GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK 134 +#define GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK 135 +#define GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK 136 +#define GCC_ULTAUDIO_PCNOC_MPORT_CLK 137 +#define GCC_ULTAUDIO_PCNOC_SWAY_CLK 138 +#define GCC_ULTAUDIO_STC_XO_CLK 139 +#define GCC_USB2A_PHY_SLEEP_CLK 140 +#define GCC_USB_HS_AHB_CLK 141 +#define GCC_USB_HS_PHY_CFG_AHB_CLK 142 +#define GCC_USB_HS_SYSTEM_CLK 143 +#define GCC_VENUS0_AHB_CLK 144 +#define GCC_VENUS0_AXI_CLK 145 +#define GCC_VENUS0_CORE0_VCODEC0_CLK 146 +#define GCC_VENUS0_VCODEC0_CLK 147 + +/* Resets */ +#define GCC_AUDIO_CORE_BCR 0 +#define GCC_BLSP1_BCR 1 +#define GCC_BLSP1_QUP1_BCR 2 +#define GCC_BLSP1_QUP2_BCR 3 +#define GCC_BLSP1_QUP3_BCR 4 +#define GCC_BLSP1_QUP4_BCR 5 +#define GCC_BLSP1_QUP5_BCR 6 +#define GCC_BLSP1_QUP6_BCR 7 +#define GCC_BLSP1_UART1_BCR 8 +#define GCC_BLSP1_UART2_BCR 9 +#define GCC_CAMSS_CSI0_BCR 10 +#define GCC_CAMSS_CSI0PHY_BCR 11 +#define GCC_CAMSS_CSI0PIX_BCR 12 +#define GCC_CAMSS_CSI0RDI_BCR 13 +#define GCC_CAMSS_CSI1_BCR 14 +#define GCC_CAMSS_CSI1PHY_BCR 15 +#define GCC_CAMSS_CSI1PIX_BCR 16 +#define GCC_CAMSS_CSI1RDI_BCR 17 +#define GCC_CAMSS_CSI_VFE0_BCR 18 +#define GCC_CAMSS_GP0_BCR 19 +#define GCC_CAMSS_GP1_BCR 20 +#define GCC_CAMSS_ISPIF_BCR 21 +#define GCC_CAMSS_MCLK0_BCR 22 +#define GCC_CAMSS_MCLK1_BCR 23 +#define GCC_CAMSS_PHY0_BCR 24 +#define GCC_CAMSS_TOP_BCR 25 +#define GCC_CAMSS_TOP_AHB_BCR 26 +#define GCC_CAMSS_VFE_BCR 27 +#define GCC_CRYPTO_BCR 28 +#define GCC_MDSS_BCR 29 +#define GCC_OXILI_BCR 30 +#define GCC_PDM_BCR 31 +#define GCC_PRNG_BCR 32 +#define GCC_QUSB2_PHY_BCR 33 +#define GCC_SDCC1_BCR 34 +#define GCC_SDCC2_BCR 35 +#define GCC_ULT_AUDIO_BCR 36 +#define GCC_USB2A_PHY_BCR 37 +#define GCC_USB2_HS_PHY_ONLY_BCR 38 +#define GCC_USB_HS_BCR 39 +#define GCC_VENUS0_BCR 40 + +/* Subsystem Restart */ +#define GCC_MSS_RESTART 41 + +/* Power Domains */ +#define MDSS_GDSC 0 +#define OXILI_GDSC 1 +#define VENUS_GDSC 2 +#define VENUS_CORE0_GDSC 3 +#define VFE_GDSC 4 + +#endif diff --git a/include/dt-bindings/clock/qcom,gcc-msm8939.h b/include/dt-bindings/clock/qcom,gcc-msm8939.h new file mode 100644 index 000000000000..2d545ed0d35a --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-msm8939.h @@ -0,0 +1,207 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2020 Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_MSM_GCC_8939_H +#define _DT_BINDINGS_CLK_MSM_GCC_8939_H + +#define GPLL0 0 +#define GPLL0_VOTE 1 +#define BIMC_PLL 2 +#define BIMC_PLL_VOTE 3 +#define GPLL1 4 +#define GPLL1_VOTE 5 +#define GPLL2 6 +#define GPLL2_VOTE 7 +#define PCNOC_BFDCD_CLK_SRC 8 +#define SYSTEM_NOC_BFDCD_CLK_SRC 9 +#define CAMSS_AHB_CLK_SRC 10 +#define APSS_AHB_CLK_SRC 11 +#define CSI0_CLK_SRC 12 +#define CSI1_CLK_SRC 13 +#define GFX3D_CLK_SRC 14 +#define VFE0_CLK_SRC 15 +#define BLSP1_QUP1_I2C_APPS_CLK_SRC 16 +#define BLSP1_QUP1_SPI_APPS_CLK_SRC 17 +#define BLSP1_QUP2_I2C_APPS_CLK_SRC 18 +#define BLSP1_QUP2_SPI_APPS_CLK_SRC 19 +#define BLSP1_QUP3_I2C_APPS_CLK_SRC 20 +#define BLSP1_QUP3_SPI_APPS_CLK_SRC 21 +#define BLSP1_QUP4_I2C_APPS_CLK_SRC 22 +#define BLSP1_QUP4_SPI_APPS_CLK_SRC 23 +#define BLSP1_QUP5_I2C_APPS_CLK_SRC 24 +#define BLSP1_QUP5_SPI_APPS_CLK_SRC 25 +#define BLSP1_QUP6_I2C_APPS_CLK_SRC 26 +#define BLSP1_QUP6_SPI_APPS_CLK_SRC 27 +#define BLSP1_UART1_APPS_CLK_SRC 28 +#define BLSP1_UART2_APPS_CLK_SRC 29 +#define CCI_CLK_SRC 30 +#define CAMSS_GP0_CLK_SRC 31 +#define CAMSS_GP1_CLK_SRC 32 +#define JPEG0_CLK_SRC 33 +#define MCLK0_CLK_SRC 34 +#define MCLK1_CLK_SRC 35 +#define CSI0PHYTIMER_CLK_SRC 36 +#define CSI1PHYTIMER_CLK_SRC 37 +#define CPP_CLK_SRC 38 +#define CRYPTO_CLK_SRC 39 +#define GP1_CLK_SRC 40 +#define GP2_CLK_SRC 41 +#define GP3_CLK_SRC 42 +#define BYTE0_CLK_SRC 43 +#define ESC0_CLK_SRC 44 +#define MDP_CLK_SRC 45 +#define PCLK0_CLK_SRC 46 +#define VSYNC_CLK_SRC 47 +#define PDM2_CLK_SRC 48 +#define SDCC1_APPS_CLK_SRC 49 +#define SDCC2_APPS_CLK_SRC 50 +#define APSS_TCU_CLK_SRC 51 +#define USB_HS_SYSTEM_CLK_SRC 52 +#define VCODEC0_CLK_SRC 53 +#define GCC_BLSP1_AHB_CLK 54 +#define GCC_BLSP1_SLEEP_CLK 55 +#define GCC_BLSP1_QUP1_I2C_APPS_CLK 56 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK 57 +#define GCC_BLSP1_QUP2_I2C_APPS_CLK 58 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK 59 +#define GCC_BLSP1_QUP3_I2C_APPS_CLK 60 +#define GCC_BLSP1_QUP3_SPI_APPS_CLK 61 +#define GCC_BLSP1_QUP4_I2C_APPS_CLK 62 +#define GCC_BLSP1_QUP4_SPI_APPS_CLK 63 +#define GCC_BLSP1_QUP5_I2C_APPS_CLK 64 +#define GCC_BLSP1_QUP5_SPI_APPS_CLK 65 +#define GCC_BLSP1_QUP6_I2C_APPS_CLK 66 +#define GCC_BLSP1_QUP6_SPI_APPS_CLK 67 +#define GCC_BLSP1_UART1_APPS_CLK 68 +#define GCC_BLSP1_UART2_APPS_CLK 69 +#define GCC_BOOT_ROM_AHB_CLK 70 +#define GCC_CAMSS_CCI_AHB_CLK 71 +#define GCC_CAMSS_CCI_CLK 72 +#define GCC_CAMSS_CSI0_AHB_CLK 73 +#define GCC_CAMSS_CSI0_CLK 74 +#define GCC_CAMSS_CSI0PHY_CLK 75 +#define GCC_CAMSS_CSI0PIX_CLK 76 +#define GCC_CAMSS_CSI0RDI_CLK 77 +#define GCC_CAMSS_CSI1_AHB_CLK 78 +#define GCC_CAMSS_CSI1_CLK 79 +#define GCC_CAMSS_CSI1PHY_CLK 80 +#define GCC_CAMSS_CSI1PIX_CLK 81 +#define GCC_CAMSS_CSI1RDI_CLK 82 +#define GCC_CAMSS_CSI_VFE0_CLK 83 +#define GCC_CAMSS_GP0_CLK 84 +#define GCC_CAMSS_GP1_CLK 85 +#define GCC_CAMSS_ISPIF_AHB_CLK 86 +#define GCC_CAMSS_JPEG0_CLK 87 +#define GCC_CAMSS_JPEG_AHB_CLK 88 +#define GCC_CAMSS_JPEG_AXI_CLK 89 +#define GCC_CAMSS_MCLK0_CLK 90 +#define GCC_CAMSS_MCLK1_CLK 91 +#define GCC_CAMSS_MICRO_AHB_CLK 92 +#define GCC_CAMSS_CSI0PHYTIMER_CLK 93 +#define GCC_CAMSS_CSI1PHYTIMER_CLK 94 +#define GCC_CAMSS_AHB_CLK 95 +#define GCC_CAMSS_TOP_AHB_CLK 96 +#define GCC_CAMSS_CPP_AHB_CLK 97 +#define GCC_CAMSS_CPP_CLK 98 +#define GCC_CAMSS_VFE0_CLK 99 +#define GCC_CAMSS_VFE_AHB_CLK 100 +#define GCC_CAMSS_VFE_AXI_CLK 101 +#define GCC_CRYPTO_AHB_CLK 102 +#define GCC_CRYPTO_AXI_CLK 103 +#define GCC_CRYPTO_CLK 104 +#define GCC_OXILI_GMEM_CLK 105 +#define GCC_GP1_CLK 106 +#define GCC_GP2_CLK 107 +#define GCC_GP3_CLK 108 +#define GCC_MDSS_AHB_CLK 109 +#define GCC_MDSS_AXI_CLK 110 +#define GCC_MDSS_BYTE0_CLK 111 +#define GCC_MDSS_ESC0_CLK 112 +#define GCC_MDSS_MDP_CLK 113 +#define GCC_MDSS_PCLK0_CLK 114 +#define GCC_MDSS_VSYNC_CLK 115 +#define GCC_MSS_CFG_AHB_CLK 116 +#define GCC_OXILI_AHB_CLK 117 +#define GCC_OXILI_GFX3D_CLK 118 +#define GCC_PDM2_CLK 119 +#define GCC_PDM_AHB_CLK 120 +#define GCC_PRNG_AHB_CLK 121 +#define GCC_SDCC1_AHB_CLK 122 +#define GCC_SDCC1_APPS_CLK 123 +#define GCC_SDCC2_AHB_CLK 124 +#define GCC_SDCC2_APPS_CLK 125 +#define GCC_GTCU_AHB_CLK 126 +#define GCC_JPEG_TBU_CLK 127 +#define GCC_MDP_TBU_CLK 128 +#define GCC_SMMU_CFG_CLK 129 +#define GCC_VENUS_TBU_CLK 130 +#define GCC_VFE_TBU_CLK 131 +#define GCC_USB2A_PHY_SLEEP_CLK 132 +#define GCC_USB_HS_AHB_CLK 133 +#define GCC_USB_HS_SYSTEM_CLK 134 +#define GCC_VENUS0_AHB_CLK 135 +#define GCC_VENUS0_AXI_CLK 136 +#define GCC_VENUS0_VCODEC0_CLK 137 +#define BIMC_DDR_CLK_SRC 138 +#define GCC_APSS_TCU_CLK 139 +#define GCC_GFX_TCU_CLK 140 +#define BIMC_GPU_CLK_SRC 141 +#define GCC_BIMC_GFX_CLK 142 +#define GCC_BIMC_GPU_CLK 143 +#define ULTAUDIO_LPAIF_PRI_I2S_CLK_SRC 144 +#define ULTAUDIO_LPAIF_SEC_I2S_CLK_SRC 145 +#define ULTAUDIO_LPAIF_AUX_I2S_CLK_SRC 146 +#define ULTAUDIO_XO_CLK_SRC 147 +#define ULTAUDIO_AHBFABRIC_CLK_SRC 148 +#define CODEC_DIGCODEC_CLK_SRC 149 +#define GCC_ULTAUDIO_PCNOC_MPORT_CLK 150 +#define GCC_ULTAUDIO_PCNOC_SWAY_CLK 151 +#define GCC_ULTAUDIO_AVSYNC_XO_CLK 152 +#define GCC_ULTAUDIO_STC_XO_CLK 153 +#define GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK 154 +#define GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CLK 155 +#define GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK 156 +#define GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK 157 +#define GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK 158 +#define GCC_CODEC_DIGCODEC_CLK 159 +#define GCC_MSS_Q6_BIMC_AXI_CLK 160 +#define GPLL3 161 +#define GPLL3_VOTE 162 +#define GPLL4 163 +#define GPLL4_VOTE 164 +#define GPLL5 165 +#define GPLL5_VOTE 166 +#define GPLL6 167 +#define GPLL6_VOTE 168 +#define BYTE1_CLK_SRC 169 +#define GCC_MDSS_BYTE1_CLK 170 +#define ESC1_CLK_SRC 171 +#define GCC_MDSS_ESC1_CLK 172 +#define PCLK1_CLK_SRC 173 +#define GCC_MDSS_PCLK1_CLK 174 +#define GCC_GFX_TBU_CLK 175 +#define GCC_CPP_TBU_CLK 176 +#define GCC_MDP_RT_TBU_CLK 177 +#define USB_FS_SYSTEM_CLK_SRC 178 +#define USB_FS_IC_CLK_SRC 179 +#define GCC_USB_FS_AHB_CLK 180 +#define GCC_USB_FS_IC_CLK 181 +#define GCC_USB_FS_SYSTEM_CLK 182 +#define GCC_VENUS0_CORE0_VCODEC0_CLK 183 +#define GCC_VENUS0_CORE1_VCODEC0_CLK 184 +#define GCC_OXILI_TIMER_CLK 185 +#define SYSTEM_MM_NOC_BFDCD_CLK_SRC 186 + +/* Indexes for GDSCs */ +#define BIMC_GDSC 0 +#define VENUS_GDSC 1 +#define MDSS_GDSC 2 +#define JPEG_GDSC 3 +#define VFE_GDSC 4 +#define OXILI_GDSC 5 +#define VENUS_CORE0_GDSC 6 +#define VENUS_CORE1_GDSC 7 + +#endif diff --git a/include/dt-bindings/clock/qcom,gcc-msm8953.h b/include/dt-bindings/clock/qcom,gcc-msm8953.h new file mode 100644 index 000000000000..783162da6148 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-msm8953.h @@ -0,0 +1,234 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLK_MSM_GCC_8953_H +#define _DT_BINDINGS_CLK_MSM_GCC_8953_H + +/* Clocks */ +#define APC0_DROOP_DETECTOR_CLK_SRC 0 +#define APC1_DROOP_DETECTOR_CLK_SRC 1 +#define APSS_AHB_CLK_SRC 2 +#define BLSP1_QUP1_I2C_APPS_CLK_SRC 3 +#define BLSP1_QUP1_SPI_APPS_CLK_SRC 4 +#define BLSP1_QUP2_I2C_APPS_CLK_SRC 5 +#define BLSP1_QUP2_SPI_APPS_CLK_SRC 6 +#define BLSP1_QUP3_I2C_APPS_CLK_SRC 7 +#define BLSP1_QUP3_SPI_APPS_CLK_SRC 8 +#define BLSP1_QUP4_I2C_APPS_CLK_SRC 9 +#define BLSP1_QUP4_SPI_APPS_CLK_SRC 10 +#define BLSP1_UART1_APPS_CLK_SRC 11 +#define BLSP1_UART2_APPS_CLK_SRC 12 +#define BLSP2_QUP1_I2C_APPS_CLK_SRC 13 +#define BLSP2_QUP1_SPI_APPS_CLK_SRC 14 +#define BLSP2_QUP2_I2C_APPS_CLK_SRC 15 +#define BLSP2_QUP2_SPI_APPS_CLK_SRC 16 +#define BLSP2_QUP3_I2C_APPS_CLK_SRC 17 +#define BLSP2_QUP3_SPI_APPS_CLK_SRC 18 +#define BLSP2_QUP4_I2C_APPS_CLK_SRC 19 +#define BLSP2_QUP4_SPI_APPS_CLK_SRC 20 +#define BLSP2_UART1_APPS_CLK_SRC 21 +#define BLSP2_UART2_APPS_CLK_SRC 22 +#define BYTE0_CLK_SRC 23 +#define BYTE1_CLK_SRC 24 +#define CAMSS_GP0_CLK_SRC 25 +#define CAMSS_GP1_CLK_SRC 26 +#define CAMSS_TOP_AHB_CLK_SRC 27 +#define CCI_CLK_SRC 28 +#define CPP_CLK_SRC 29 +#define CRYPTO_CLK_SRC 30 +#define CSI0PHYTIMER_CLK_SRC 31 +#define CSI0P_CLK_SRC 32 +#define CSI0_CLK_SRC 33 +#define CSI1PHYTIMER_CLK_SRC 34 +#define CSI1P_CLK_SRC 35 +#define CSI1_CLK_SRC 36 +#define CSI2PHYTIMER_CLK_SRC 37 +#define CSI2P_CLK_SRC 38 +#define CSI2_CLK_SRC 39 +#define ESC0_CLK_SRC 40 +#define ESC1_CLK_SRC 41 +#define GCC_APC0_DROOP_DETECTOR_GPLL0_CLK 42 +#define GCC_APC1_DROOP_DETECTOR_GPLL0_CLK 43 +#define GCC_APSS_AHB_CLK 44 +#define GCC_APSS_AXI_CLK 45 +#define GCC_APSS_TCU_ASYNC_CLK 46 +#define GCC_BIMC_GFX_CLK 47 +#define GCC_BIMC_GPU_CLK 48 +#define GCC_BLSP1_AHB_CLK 49 +#define GCC_BLSP1_QUP1_I2C_APPS_CLK 50 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK 51 +#define GCC_BLSP1_QUP2_I2C_APPS_CLK 52 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK 53 +#define GCC_BLSP1_QUP3_I2C_APPS_CLK 54 +#define GCC_BLSP1_QUP3_SPI_APPS_CLK 55 +#define GCC_BLSP1_QUP4_I2C_APPS_CLK 56 +#define GCC_BLSP1_QUP4_SPI_APPS_CLK 57 +#define GCC_BLSP1_UART1_APPS_CLK 58 +#define GCC_BLSP1_UART2_APPS_CLK 59 +#define GCC_BLSP2_AHB_CLK 60 +#define GCC_BLSP2_QUP1_I2C_APPS_CLK 61 +#define GCC_BLSP2_QUP1_SPI_APPS_CLK 62 +#define GCC_BLSP2_QUP2_I2C_APPS_CLK 63 +#define GCC_BLSP2_QUP2_SPI_APPS_CLK 64 +#define GCC_BLSP2_QUP3_I2C_APPS_CLK 65 +#define GCC_BLSP2_QUP3_SPI_APPS_CLK 66 +#define GCC_BLSP2_QUP4_I2C_APPS_CLK 67 +#define GCC_BLSP2_QUP4_SPI_APPS_CLK 68 +#define GCC_BLSP2_UART1_APPS_CLK 69 +#define GCC_BLSP2_UART2_APPS_CLK 70 +#define GCC_BOOT_ROM_AHB_CLK 71 +#define GCC_CAMSS_AHB_CLK 72 +#define GCC_CAMSS_CCI_AHB_CLK 73 +#define GCC_CAMSS_CCI_CLK 74 +#define GCC_CAMSS_CPP_AHB_CLK 75 +#define GCC_CAMSS_CPP_AXI_CLK 76 +#define GCC_CAMSS_CPP_CLK 77 +#define GCC_CAMSS_CSI0PHYTIMER_CLK 78 +#define GCC_CAMSS_CSI0PHY_CLK 79 +#define GCC_CAMSS_CSI0PIX_CLK 80 +#define GCC_CAMSS_CSI0RDI_CLK 81 +#define GCC_CAMSS_CSI0_AHB_CLK 82 +#define GCC_CAMSS_CSI0_CLK 83 +#define GCC_CAMSS_CSI0_CSIPHY_3P_CLK 84 +#define GCC_CAMSS_CSI1PHYTIMER_CLK 85 +#define GCC_CAMSS_CSI1PHY_CLK 86 +#define GCC_CAMSS_CSI1PIX_CLK 87 +#define GCC_CAMSS_CSI1RDI_CLK 88 +#define GCC_CAMSS_CSI1_AHB_CLK 89 +#define GCC_CAMSS_CSI1_CLK 90 +#define GCC_CAMSS_CSI1_CSIPHY_3P_CLK 91 +#define GCC_CAMSS_CSI2PHYTIMER_CLK 92 +#define GCC_CAMSS_CSI2PHY_CLK 93 +#define GCC_CAMSS_CSI2PIX_CLK 94 +#define GCC_CAMSS_CSI2RDI_CLK 95 +#define GCC_CAMSS_CSI2_AHB_CLK 96 +#define GCC_CAMSS_CSI2_CLK 97 +#define GCC_CAMSS_CSI2_CSIPHY_3P_CLK 98 +#define GCC_CAMSS_CSI_VFE0_CLK 99 +#define GCC_CAMSS_CSI_VFE1_CLK 100 +#define GCC_CAMSS_GP0_CLK 101 +#define GCC_CAMSS_GP1_CLK 102 +#define GCC_CAMSS_ISPIF_AHB_CLK 103 +#define GCC_CAMSS_JPEG0_CLK 104 +#define GCC_CAMSS_JPEG_AHB_CLK 105 +#define GCC_CAMSS_JPEG_AXI_CLK 106 +#define GCC_CAMSS_MCLK0_CLK 107 +#define GCC_CAMSS_MCLK1_CLK 108 +#define GCC_CAMSS_MCLK2_CLK 109 +#define GCC_CAMSS_MCLK3_CLK 110 +#define GCC_CAMSS_MICRO_AHB_CLK 111 +#define GCC_CAMSS_TOP_AHB_CLK 112 +#define GCC_CAMSS_VFE0_AHB_CLK 113 +#define GCC_CAMSS_VFE0_AXI_CLK 114 +#define GCC_CAMSS_VFE0_CLK 115 +#define GCC_CAMSS_VFE1_AHB_CLK 116 +#define GCC_CAMSS_VFE1_AXI_CLK 117 +#define GCC_CAMSS_VFE1_CLK 118 +#define GCC_CPP_TBU_CLK 119 +#define GCC_CRYPTO_AHB_CLK 120 +#define GCC_CRYPTO_AXI_CLK 121 +#define GCC_CRYPTO_CLK 122 +#define GCC_DCC_CLK 123 +#define GCC_GP1_CLK 124 +#define GCC_GP2_CLK 125 +#define GCC_GP3_CLK 126 +#define GCC_JPEG_TBU_CLK 127 +#define GCC_MDP_TBU_CLK 128 +#define GCC_MDSS_AHB_CLK 129 +#define GCC_MDSS_AXI_CLK 130 +#define GCC_MDSS_BYTE0_CLK 131 +#define GCC_MDSS_BYTE1_CLK 132 +#define GCC_MDSS_ESC0_CLK 133 +#define GCC_MDSS_ESC1_CLK 134 +#define GCC_MDSS_MDP_CLK 135 +#define GCC_MDSS_PCLK0_CLK 136 +#define GCC_MDSS_PCLK1_CLK 137 +#define GCC_MDSS_VSYNC_CLK 138 +#define GCC_MSS_CFG_AHB_CLK 139 +#define GCC_MSS_Q6_BIMC_AXI_CLK 140 +#define GCC_OXILI_AHB_CLK 141 +#define GCC_OXILI_AON_CLK 142 +#define GCC_OXILI_GFX3D_CLK 143 +#define GCC_OXILI_TIMER_CLK 144 +#define GCC_PCNOC_USB3_AXI_CLK 145 +#define GCC_PDM2_CLK 146 +#define GCC_PDM_AHB_CLK 147 +#define GCC_PRNG_AHB_CLK 148 +#define GCC_QDSS_DAP_CLK 149 +#define GCC_QUSB_REF_CLK 150 +#define GCC_RBCPR_GFX_CLK 151 +#define GCC_SDCC1_AHB_CLK 152 +#define GCC_SDCC1_APPS_CLK 153 +#define GCC_SDCC1_ICE_CORE_CLK 154 +#define GCC_SDCC2_AHB_CLK 155 +#define GCC_SDCC2_APPS_CLK 156 +#define GCC_SMMU_CFG_CLK 157 +#define GCC_USB30_MASTER_CLK 158 +#define GCC_USB30_MOCK_UTMI_CLK 159 +#define GCC_USB30_SLEEP_CLK 160 +#define GCC_USB3_AUX_CLK 161 +#define GCC_USB3_PIPE_CLK 162 +#define GCC_USB_PHY_CFG_AHB_CLK 163 +#define GCC_USB_SS_REF_CLK 164 +#define GCC_VENUS0_AHB_CLK 165 +#define GCC_VENUS0_AXI_CLK 166 +#define GCC_VENUS0_CORE0_VCODEC0_CLK 167 +#define GCC_VENUS0_VCODEC0_CLK 168 +#define GCC_VENUS_TBU_CLK 169 +#define GCC_VFE1_TBU_CLK 170 +#define GCC_VFE_TBU_CLK 171 +#define GFX3D_CLK_SRC 172 +#define GP1_CLK_SRC 173 +#define GP2_CLK_SRC 174 +#define GP3_CLK_SRC 175 +#define GPLL0 176 +#define GPLL0_EARLY 177 +#define GPLL2 178 +#define GPLL2_EARLY 179 +#define GPLL3 180 +#define GPLL3_EARLY 181 +#define GPLL4 182 +#define GPLL4_EARLY 183 +#define GPLL6 184 +#define GPLL6_EARLY 185 +#define JPEG0_CLK_SRC 186 +#define MCLK0_CLK_SRC 187 +#define MCLK1_CLK_SRC 188 +#define MCLK2_CLK_SRC 189 +#define MCLK3_CLK_SRC 190 +#define MDP_CLK_SRC 191 +#define PCLK0_CLK_SRC 192 +#define PCLK1_CLK_SRC 193 +#define PDM2_CLK_SRC 194 +#define RBCPR_GFX_CLK_SRC 195 +#define SDCC1_APPS_CLK_SRC 196 +#define SDCC1_ICE_CORE_CLK_SRC 197 +#define SDCC2_APPS_CLK_SRC 198 +#define USB30_MASTER_CLK_SRC 199 +#define USB30_MOCK_UTMI_CLK_SRC 200 +#define USB3_AUX_CLK_SRC 201 +#define VCODEC0_CLK_SRC 202 +#define VFE0_CLK_SRC 203 +#define VFE1_CLK_SRC 204 +#define VSYNC_CLK_SRC 205 + +/* GCC block resets */ +#define GCC_CAMSS_MICRO_BCR 0 +#define GCC_MSS_BCR 1 +#define GCC_QUSB2_PHY_BCR 2 +#define GCC_USB3PHY_PHY_BCR 3 +#define GCC_USB3_PHY_BCR 4 +#define GCC_USB_30_BCR 5 + +/* GDSCs */ +#define CPP_GDSC 0 +#define JPEG_GDSC 1 +#define MDSS_GDSC 2 +#define OXILI_CX_GDSC 3 +#define OXILI_GX_GDSC 4 +#define USB30_GDSC 5 +#define VENUS_CORE0_GDSC 6 +#define VENUS_GDSC 7 +#define VFE0_GDSC 8 +#define VFE1_GDSC 9 + +#endif diff --git a/include/dt-bindings/clock/qcom,gcc-msm8976.h b/include/dt-bindings/clock/qcom,gcc-msm8976.h new file mode 100644 index 000000000000..5351f48b2068 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-msm8976.h @@ -0,0 +1,241 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2016, The Linux Foundation. All rights reserved. + * Copyright (C) 2016-2021, AngeloGioacchino Del Regno + * <angelogioacchino.delregno@somainline.org> + */ + +#ifndef _DT_BINDINGS_CLK_MSM_GCC_8976_H +#define _DT_BINDINGS_CLK_MSM_GCC_8976_H + +#define GPLL0 0 +#define GPLL2 1 +#define GPLL3 2 +#define GPLL4 3 +#define GPLL6 4 +#define GPLL0_CLK_SRC 5 +#define GPLL2_CLK_SRC 6 +#define GPLL3_CLK_SRC 7 +#define GPLL4_CLK_SRC 8 +#define GPLL6_CLK_SRC 9 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK 10 +#define GCC_BLSP1_QUP1_I2C_APPS_CLK 11 +#define GCC_BLSP1_QUP2_I2C_APPS_CLK 12 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK 13 +#define GCC_BLSP1_QUP3_I2C_APPS_CLK 14 +#define GCC_BLSP1_QUP3_SPI_APPS_CLK 15 +#define GCC_BLSP1_QUP4_I2C_APPS_CLK 16 +#define GCC_BLSP1_QUP4_SPI_APPS_CLK 17 +#define GCC_BLSP1_UART1_APPS_CLK 18 +#define GCC_BLSP1_UART2_APPS_CLK 19 +#define GCC_BLSP2_QUP1_I2C_APPS_CLK 20 +#define GCC_BLSP2_QUP1_SPI_APPS_CLK 21 +#define GCC_BLSP2_QUP2_I2C_APPS_CLK 22 +#define GCC_BLSP2_QUP2_SPI_APPS_CLK 23 +#define GCC_BLSP2_QUP3_I2C_APPS_CLK 24 +#define GCC_BLSP2_QUP3_SPI_APPS_CLK 25 +#define GCC_BLSP2_QUP4_I2C_APPS_CLK 26 +#define GCC_BLSP2_QUP4_SPI_APPS_CLK 27 +#define GCC_BLSP2_UART1_APPS_CLK 28 +#define GCC_BLSP2_UART2_APPS_CLK 29 +#define GCC_CAMSS_CCI_AHB_CLK 30 +#define GCC_CAMSS_CCI_CLK 31 +#define GCC_CAMSS_CPP_AHB_CLK 32 +#define GCC_CAMSS_CPP_AXI_CLK 33 +#define GCC_CAMSS_CPP_CLK 34 +#define GCC_CAMSS_CSI0_AHB_CLK 35 +#define GCC_CAMSS_CSI0_CLK 36 +#define GCC_CAMSS_CSI0PHY_CLK 37 +#define GCC_CAMSS_CSI0PIX_CLK 38 +#define GCC_CAMSS_CSI0RDI_CLK 39 +#define GCC_CAMSS_CSI1_AHB_CLK 40 +#define GCC_CAMSS_CSI1_CLK 41 +#define GCC_CAMSS_CSI1PHY_CLK 42 +#define GCC_CAMSS_CSI1PIX_CLK 43 +#define GCC_CAMSS_CSI1RDI_CLK 44 +#define GCC_CAMSS_CSI2_AHB_CLK 45 +#define GCC_CAMSS_CSI2_CLK 46 +#define GCC_CAMSS_CSI2PHY_CLK 47 +#define GCC_CAMSS_CSI2PIX_CLK 48 +#define GCC_CAMSS_CSI2RDI_CLK 49 +#define GCC_CAMSS_CSI_VFE0_CLK 50 +#define GCC_CAMSS_CSI_VFE1_CLK 51 +#define GCC_CAMSS_GP0_CLK 52 +#define GCC_CAMSS_GP1_CLK 53 +#define GCC_CAMSS_ISPIF_AHB_CLK 54 +#define GCC_CAMSS_JPEG0_CLK 55 +#define GCC_CAMSS_JPEG_AHB_CLK 56 +#define GCC_CAMSS_JPEG_AXI_CLK 57 +#define GCC_CAMSS_MCLK0_CLK 58 +#define GCC_CAMSS_MCLK1_CLK 59 +#define GCC_CAMSS_MCLK2_CLK 60 +#define GCC_CAMSS_MICRO_AHB_CLK 61 +#define GCC_CAMSS_CSI0PHYTIMER_CLK 62 +#define GCC_CAMSS_CSI1PHYTIMER_CLK 63 +#define GCC_CAMSS_AHB_CLK 64 +#define GCC_CAMSS_TOP_AHB_CLK 65 +#define GCC_CAMSS_VFE0_CLK 66 +#define GCC_CAMSS_VFE_AHB_CLK 67 +#define GCC_CAMSS_VFE_AXI_CLK 68 +#define GCC_CAMSS_VFE1_AHB_CLK 69 +#define GCC_CAMSS_VFE1_AXI_CLK 70 +#define GCC_CAMSS_VFE1_CLK 71 +#define GCC_DCC_CLK 72 +#define GCC_GP1_CLK 73 +#define GCC_GP2_CLK 74 +#define GCC_GP3_CLK 75 +#define GCC_MDSS_AHB_CLK 76 +#define GCC_MDSS_AXI_CLK 77 +#define GCC_MDSS_ESC0_CLK 78 +#define GCC_MDSS_ESC1_CLK 79 +#define GCC_MDSS_MDP_CLK 80 +#define GCC_MDSS_VSYNC_CLK 81 +#define GCC_MSS_CFG_AHB_CLK 82 +#define GCC_MSS_Q6_BIMC_AXI_CLK 83 +#define GCC_PDM2_CLK 84 +#define GCC_PRNG_AHB_CLK 85 +#define GCC_PDM_AHB_CLK 86 +#define GCC_RBCPR_GFX_AHB_CLK 87 +#define GCC_RBCPR_GFX_CLK 88 +#define GCC_SDCC1_AHB_CLK 89 +#define GCC_SDCC1_APPS_CLK 90 +#define GCC_SDCC1_ICE_CORE_CLK 91 +#define GCC_SDCC2_AHB_CLK 92 +#define GCC_SDCC2_APPS_CLK 93 +#define GCC_SDCC3_AHB_CLK 94 +#define GCC_SDCC3_APPS_CLK 95 +#define GCC_USB2A_PHY_SLEEP_CLK 96 +#define GCC_USB_HS_PHY_CFG_AHB_CLK 97 +#define GCC_USB_FS_AHB_CLK 98 +#define GCC_USB_FS_IC_CLK 99 +#define GCC_USB_FS_SYSTEM_CLK 100 +#define GCC_USB_HS_AHB_CLK 101 +#define GCC_USB_HS_SYSTEM_CLK 102 +#define GCC_VENUS0_AHB_CLK 103 +#define GCC_VENUS0_AXI_CLK 104 +#define GCC_VENUS0_CORE0_VCODEC0_CLK 105 +#define GCC_VENUS0_CORE1_VCODEC0_CLK 106 +#define GCC_VENUS0_VCODEC0_CLK 107 +#define GCC_APSS_AHB_CLK 108 +#define GCC_APSS_AXI_CLK 109 +#define GCC_BLSP1_AHB_CLK 110 +#define GCC_BLSP2_AHB_CLK 111 +#define GCC_BOOT_ROM_AHB_CLK 112 +#define GCC_CRYPTO_AHB_CLK 113 +#define GCC_CRYPTO_AXI_CLK 114 +#define GCC_CRYPTO_CLK 115 +#define GCC_CPP_TBU_CLK 116 +#define GCC_APSS_TCU_CLK 117 +#define GCC_JPEG_TBU_CLK 118 +#define GCC_MDP_RT_TBU_CLK 119 +#define GCC_MDP_TBU_CLK 120 +#define GCC_SMMU_CFG_CLK 121 +#define GCC_VENUS_1_TBU_CLK 122 +#define GCC_VENUS_TBU_CLK 123 +#define GCC_VFE1_TBU_CLK 124 +#define GCC_VFE_TBU_CLK 125 +#define GCC_APS_0_CLK 126 +#define GCC_APS_1_CLK 127 +#define APS_0_CLK_SRC 128 +#define APS_1_CLK_SRC 129 +#define APSS_AHB_CLK_SRC 130 +#define BLSP1_QUP1_I2C_APPS_CLK_SRC 131 +#define BLSP1_QUP1_SPI_APPS_CLK_SRC 132 +#define BLSP1_QUP2_I2C_APPS_CLK_SRC 133 +#define BLSP1_QUP2_SPI_APPS_CLK_SRC 134 +#define BLSP1_QUP3_I2C_APPS_CLK_SRC 135 +#define BLSP1_QUP3_SPI_APPS_CLK_SRC 136 +#define BLSP1_QUP4_I2C_APPS_CLK_SRC 137 +#define BLSP1_QUP4_SPI_APPS_CLK_SRC 138 +#define BLSP1_UART1_APPS_CLK_SRC 139 +#define BLSP1_UART2_APPS_CLK_SRC 140 +#define BLSP2_QUP1_I2C_APPS_CLK_SRC 141 +#define BLSP2_QUP1_SPI_APPS_CLK_SRC 142 +#define BLSP2_QUP2_I2C_APPS_CLK_SRC 143 +#define BLSP2_QUP2_SPI_APPS_CLK_SRC 144 +#define BLSP2_QUP3_I2C_APPS_CLK_SRC 145 +#define BLSP2_QUP3_SPI_APPS_CLK_SRC 146 +#define BLSP2_QUP4_I2C_APPS_CLK_SRC 147 +#define BLSP2_QUP4_SPI_APPS_CLK_SRC 148 +#define BLSP2_UART1_APPS_CLK_SRC 149 +#define BLSP2_UART2_APPS_CLK_SRC 150 +#define CCI_CLK_SRC 151 +#define CPP_CLK_SRC 152 +#define CSI0_CLK_SRC 153 +#define CSI1_CLK_SRC 154 +#define CSI2_CLK_SRC 155 +#define CAMSS_GP0_CLK_SRC 156 +#define CAMSS_GP1_CLK_SRC 157 +#define JPEG0_CLK_SRC 158 +#define MCLK0_CLK_SRC 159 +#define MCLK1_CLK_SRC 160 +#define MCLK2_CLK_SRC 161 +#define CSI0PHYTIMER_CLK_SRC 162 +#define CSI1PHYTIMER_CLK_SRC 163 +#define CAMSS_TOP_AHB_CLK_SRC 164 +#define VFE0_CLK_SRC 165 +#define VFE1_CLK_SRC 166 +#define CRYPTO_CLK_SRC 167 +#define GP1_CLK_SRC 168 +#define GP2_CLK_SRC 169 +#define GP3_CLK_SRC 170 +#define ESC0_CLK_SRC 171 +#define ESC1_CLK_SRC 172 +#define MDP_CLK_SRC 173 +#define VSYNC_CLK_SRC 174 +#define PDM2_CLK_SRC 175 +#define RBCPR_GFX_CLK_SRC 176 +#define SDCC1_APPS_CLK_SRC 177 +#define SDCC1_ICE_CORE_CLK_SRC 178 +#define SDCC2_APPS_CLK_SRC 179 +#define SDCC3_APPS_CLK_SRC 180 +#define USB_FS_IC_CLK_SRC 181 +#define USB_FS_SYSTEM_CLK_SRC 182 +#define USB_HS_SYSTEM_CLK_SRC 183 +#define VCODEC0_CLK_SRC 184 +#define GCC_MDSS_BYTE0_CLK_SRC 185 +#define GCC_MDSS_BYTE1_CLK_SRC 186 +#define GCC_MDSS_BYTE0_CLK 187 +#define GCC_MDSS_BYTE1_CLK 188 +#define GCC_MDSS_PCLK0_CLK_SRC 189 +#define GCC_MDSS_PCLK1_CLK_SRC 190 +#define GCC_MDSS_PCLK0_CLK 191 +#define GCC_MDSS_PCLK1_CLK 192 +#define GCC_GFX3D_CLK_SRC 193 +#define GCC_GFX3D_OXILI_CLK 194 +#define GCC_GFX3D_BIMC_CLK 195 +#define GCC_GFX3D_OXILI_AHB_CLK 196 +#define GCC_GFX3D_OXILI_AON_CLK 197 +#define GCC_GFX3D_OXILI_GMEM_CLK 198 +#define GCC_GFX3D_OXILI_TIMER_CLK 199 +#define GCC_GFX3D_TBU0_CLK 200 +#define GCC_GFX3D_TBU1_CLK 201 +#define GCC_GFX3D_TCU_CLK 202 +#define GCC_GFX3D_GTCU_AHB_CLK 203 + +/* GCC block resets */ +#define RST_CAMSS_MICRO_BCR 0 +#define RST_USB_HS_BCR 1 +#define RST_QUSB2_PHY_BCR 2 +#define RST_USB2_HS_PHY_ONLY_BCR 3 +#define RST_USB_HS_PHY_CFG_AHB_BCR 4 +#define RST_USB_FS_BCR 5 +#define RST_CAMSS_CSI1PIX_BCR 6 +#define RST_CAMSS_CSI_VFE1_BCR 7 +#define RST_CAMSS_VFE1_BCR 8 +#define RST_CAMSS_CPP_BCR 9 +#define RST_MSS_BCR 10 + +/* GDSCs */ +#define VENUS_GDSC 0 +#define VENUS_CORE0_GDSC 1 +#define VENUS_CORE1_GDSC 2 +#define MDSS_GDSC 3 +#define JPEG_GDSC 4 +#define VFE0_GDSC 5 +#define VFE1_GDSC 6 +#define CPP_GDSC 7 +#define OXILI_GX_GDSC 8 +#define OXILI_CX_GDSC 9 + +#endif /* _DT_BINDINGS_CLK_MSM_GCC_8976_H */ diff --git a/include/dt-bindings/clock/qcom,gcc-msm8994.h b/include/dt-bindings/clock/qcom,gcc-msm8994.h index 938969309e00..f6836f430bb5 100644 --- a/include/dt-bindings/clock/qcom,gcc-msm8994.h +++ b/include/dt-bindings/clock/qcom,gcc-msm8994.h @@ -126,5 +126,54 @@ #define GCC_USB3_PHY_AUX_CLK 116 #define GCC_USB_HS_SYSTEM_CLK 117 #define GCC_SDCC1_AHB_CLK 118 +#define GCC_LPASS_Q6_AXI_CLK 119 +#define GCC_MSS_Q6_BIMC_AXI_CLK 120 +#define GCC_PCIE_0_CFG_AHB_CLK 121 +#define GCC_PCIE_0_MSTR_AXI_CLK 122 +#define GCC_PCIE_0_SLV_AXI_CLK 123 +#define GCC_PCIE_1_CFG_AHB_CLK 124 +#define GCC_PCIE_1_MSTR_AXI_CLK 125 +#define GCC_PCIE_1_SLV_AXI_CLK 126 +#define GCC_PDM_AHB_CLK 127 +#define GCC_SDCC2_AHB_CLK 128 +#define GCC_SDCC3_AHB_CLK 129 +#define GCC_SDCC4_AHB_CLK 130 +#define GCC_TSIF_AHB_CLK 131 +#define GCC_UFS_AHB_CLK 132 +#define GCC_UFS_RX_SYMBOL_0_CLK 133 +#define GCC_UFS_RX_SYMBOL_1_CLK 134 +#define GCC_UFS_TX_SYMBOL_0_CLK 135 +#define GCC_UFS_TX_SYMBOL_1_CLK 136 +#define GCC_USB2_HS_PHY_SLEEP_CLK 137 +#define GCC_USB30_SLEEP_CLK 138 +#define GCC_USB_HS_AHB_CLK 139 +#define GCC_USB_PHY_CFG_AHB2PHY_CLK 140 +#define CONFIG_NOC_CLK_SRC 141 +#define PERIPH_NOC_CLK_SRC 142 +#define SYSTEM_NOC_CLK_SRC 143 +#define GPLL0_OUT_MMSSCC 144 +#define GPLL0_OUT_MSSCC 145 +#define PCIE_0_PHY_LDO 146 +#define PCIE_1_PHY_LDO 147 +#define UFS_PHY_LDO 148 +#define USB_SS_PHY_LDO 149 +#define GCC_BOOT_ROM_AHB_CLK 150 +#define GCC_PRNG_AHB_CLK 151 +#define GCC_USB3_PHY_PIPE_CLK 152 + +/* GDSCs */ +#define PCIE_GDSC 0 +#define PCIE_0_GDSC 1 +#define PCIE_1_GDSC 2 +#define USB30_GDSC 3 +#define UFS_GDSC 4 + +/* Resets */ +#define USB3_PHY_RESET 0 +#define USB3PHY_PHY_RESET 1 +#define PCIE_PHY_0_RESET 2 +#define PCIE_PHY_1_RESET 3 +#define QUSB2_PHY_RESET 4 +#define MSS_RESET 5 #endif diff --git a/include/dt-bindings/clock/qcom,gcc-msm8998.h b/include/dt-bindings/clock/qcom,gcc-msm8998.h index 63e02dc32a0b..1badb4f9c58f 100644 --- a/include/dt-bindings/clock/qcom,gcc-msm8998.h +++ b/include/dt-bindings/clock/qcom,gcc-msm8998.h @@ -183,6 +183,13 @@ #define GCC_MSS_SNOC_AXI_CLK 174 #define GCC_MSS_MNOC_BIMC_AXI_CLK 175 #define GCC_BIMC_GFX_CLK 176 +#define UFS_UNIPRO_CORE_CLK_SRC 177 +#define GCC_MMSS_GPLL0_CLK 178 +#define HMSS_GPLL0_CLK_SRC 179 +#define GCC_IM_SLEEP 180 +#define AGGRE2_SNOC_NORTH_AXI 181 +#define SSC_XO 182 +#define SSC_CNOC_AHBS_CLK 183 #define PCIE_0_GDSC 0 #define UFS_GDSC 1 diff --git a/include/dt-bindings/clock/qcom,gcc-qcm2290.h b/include/dt-bindings/clock/qcom,gcc-qcm2290.h new file mode 100644 index 000000000000..8d907035f9e4 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-qcm2290.h @@ -0,0 +1,188 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_QCM2290_H +#define _DT_BINDINGS_CLK_QCOM_GCC_QCM2290_H + +/* GCC clocks */ +#define GPLL0 0 +#define GPLL0_OUT_AUX2 1 +#define GPLL1 2 +#define GPLL10 3 +#define GPLL11 4 +#define GPLL3 5 +#define GPLL3_OUT_MAIN 6 +#define GPLL4 7 +#define GPLL5 8 +#define GPLL6 9 +#define GPLL6_OUT_MAIN 10 +#define GPLL7 11 +#define GPLL8 12 +#define GPLL8_OUT_MAIN 13 +#define GPLL9 14 +#define GPLL9_OUT_MAIN 15 +#define GCC_AHB2PHY_CSI_CLK 16 +#define GCC_AHB2PHY_USB_CLK 17 +#define GCC_APC_VS_CLK 18 +#define GCC_BIMC_GPU_AXI_CLK 19 +#define GCC_BOOT_ROM_AHB_CLK 20 +#define GCC_CAM_THROTTLE_NRT_CLK 21 +#define GCC_CAM_THROTTLE_RT_CLK 22 +#define GCC_CAMERA_AHB_CLK 23 +#define GCC_CAMERA_XO_CLK 24 +#define GCC_CAMSS_AXI_CLK 25 +#define GCC_CAMSS_AXI_CLK_SRC 26 +#define GCC_CAMSS_CAMNOC_ATB_CLK 27 +#define GCC_CAMSS_CAMNOC_NTS_XO_CLK 28 +#define GCC_CAMSS_CCI_0_CLK 29 +#define GCC_CAMSS_CCI_CLK_SRC 30 +#define GCC_CAMSS_CPHY_0_CLK 31 +#define GCC_CAMSS_CPHY_1_CLK 32 +#define GCC_CAMSS_CSI0PHYTIMER_CLK 33 +#define GCC_CAMSS_CSI0PHYTIMER_CLK_SRC 34 +#define GCC_CAMSS_CSI1PHYTIMER_CLK 35 +#define GCC_CAMSS_CSI1PHYTIMER_CLK_SRC 36 +#define GCC_CAMSS_MCLK0_CLK 37 +#define GCC_CAMSS_MCLK0_CLK_SRC 38 +#define GCC_CAMSS_MCLK1_CLK 39 +#define GCC_CAMSS_MCLK1_CLK_SRC 40 +#define GCC_CAMSS_MCLK2_CLK 41 +#define GCC_CAMSS_MCLK2_CLK_SRC 42 +#define GCC_CAMSS_MCLK3_CLK 43 +#define GCC_CAMSS_MCLK3_CLK_SRC 44 +#define GCC_CAMSS_NRT_AXI_CLK 45 +#define GCC_CAMSS_OPE_AHB_CLK 46 +#define GCC_CAMSS_OPE_AHB_CLK_SRC 47 +#define GCC_CAMSS_OPE_CLK 48 +#define GCC_CAMSS_OPE_CLK_SRC 49 +#define GCC_CAMSS_RT_AXI_CLK 50 +#define GCC_CAMSS_TFE_0_CLK 51 +#define GCC_CAMSS_TFE_0_CLK_SRC 52 +#define GCC_CAMSS_TFE_0_CPHY_RX_CLK 53 +#define GCC_CAMSS_TFE_0_CSID_CLK 54 +#define GCC_CAMSS_TFE_0_CSID_CLK_SRC 55 +#define GCC_CAMSS_TFE_1_CLK 56 +#define GCC_CAMSS_TFE_1_CLK_SRC 57 +#define GCC_CAMSS_TFE_1_CPHY_RX_CLK 58 +#define GCC_CAMSS_TFE_1_CSID_CLK 59 +#define GCC_CAMSS_TFE_1_CSID_CLK_SRC 60 +#define GCC_CAMSS_TFE_CPHY_RX_CLK_SRC 61 +#define GCC_CAMSS_TOP_AHB_CLK 62 +#define GCC_CAMSS_TOP_AHB_CLK_SRC 63 +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 64 +#define GCC_CPUSS_AHB_CLK 65 +#define GCC_CPUSS_AHB_CLK_SRC 66 +#define GCC_CPUSS_AHB_POSTDIV_CLK_SRC 67 +#define GCC_CPUSS_GNOC_CLK 68 +#define GCC_CPUSS_THROTTLE_CORE_CLK 69 +#define GCC_CPUSS_THROTTLE_XO_CLK 70 +#define GCC_DISP_AHB_CLK 71 +#define GCC_DISP_GPLL0_CLK_SRC 72 +#define GCC_DISP_GPLL0_DIV_CLK_SRC 73 +#define GCC_DISP_HF_AXI_CLK 74 +#define GCC_DISP_THROTTLE_CORE_CLK 75 +#define GCC_DISP_XO_CLK 76 +#define GCC_GP1_CLK 77 +#define GCC_GP1_CLK_SRC 78 +#define GCC_GP2_CLK 79 +#define GCC_GP2_CLK_SRC 80 +#define GCC_GP3_CLK 81 +#define GCC_GP3_CLK_SRC 82 +#define GCC_GPU_CFG_AHB_CLK 83 +#define GCC_GPU_GPLL0_CLK_SRC 84 +#define GCC_GPU_GPLL0_DIV_CLK_SRC 85 +#define GCC_GPU_IREF_CLK 86 +#define GCC_GPU_MEMNOC_GFX_CLK 87 +#define GCC_GPU_SNOC_DVM_GFX_CLK 88 +#define GCC_GPU_THROTTLE_CORE_CLK 89 +#define GCC_GPU_THROTTLE_XO_CLK 90 +#define GCC_PDM2_CLK 91 +#define GCC_PDM2_CLK_SRC 92 +#define GCC_PDM_AHB_CLK 93 +#define GCC_PDM_XO4_CLK 94 +#define GCC_PWM0_XO512_CLK 95 +#define GCC_QMIP_CAMERA_NRT_AHB_CLK 96 +#define GCC_QMIP_CAMERA_RT_AHB_CLK 97 +#define GCC_QMIP_CPUSS_CFG_AHB_CLK 98 +#define GCC_QMIP_DISP_AHB_CLK 99 +#define GCC_QMIP_GPU_CFG_AHB_CLK 100 +#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 101 +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 102 +#define GCC_QUPV3_WRAP0_CORE_CLK 103 +#define GCC_QUPV3_WRAP0_S0_CLK 104 +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 105 +#define GCC_QUPV3_WRAP0_S1_CLK 106 +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 107 +#define GCC_QUPV3_WRAP0_S2_CLK 108 +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 109 +#define GCC_QUPV3_WRAP0_S3_CLK 110 +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 111 +#define GCC_QUPV3_WRAP0_S4_CLK 112 +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 113 +#define GCC_QUPV3_WRAP0_S5_CLK 114 +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 115 +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 116 +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 117 +#define GCC_SDCC1_AHB_CLK 118 +#define GCC_SDCC1_APPS_CLK 119 +#define GCC_SDCC1_APPS_CLK_SRC 120 +#define GCC_SDCC1_ICE_CORE_CLK 121 +#define GCC_SDCC1_ICE_CORE_CLK_SRC 122 +#define GCC_SDCC2_AHB_CLK 123 +#define GCC_SDCC2_APPS_CLK 124 +#define GCC_SDCC2_APPS_CLK_SRC 125 +#define GCC_SYS_NOC_CPUSS_AHB_CLK 126 +#define GCC_SYS_NOC_USB3_PRIM_AXI_CLK 127 +#define GCC_USB30_PRIM_MASTER_CLK 128 +#define GCC_USB30_PRIM_MASTER_CLK_SRC 129 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 130 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 131 +#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV 132 +#define GCC_USB30_PRIM_SLEEP_CLK 133 +#define GCC_USB3_PRIM_CLKREF_CLK 134 +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 135 +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 136 +#define GCC_USB3_PRIM_PHY_PIPE_CLK 137 +#define GCC_VCODEC0_AXI_CLK 138 +#define GCC_VENUS_AHB_CLK 139 +#define GCC_VENUS_CTL_AXI_CLK 140 +#define GCC_VIDEO_AHB_CLK 141 +#define GCC_VIDEO_AXI0_CLK 142 +#define GCC_VIDEO_THROTTLE_CORE_CLK 143 +#define GCC_VIDEO_VCODEC0_SYS_CLK 144 +#define GCC_VIDEO_VENUS_CLK_SRC 145 +#define GCC_VIDEO_VENUS_CTL_CLK 146 +#define GCC_VIDEO_XO_CLK 147 + +/* GCC resets */ +#define GCC_CAMSS_OPE_BCR 0 +#define GCC_CAMSS_TFE_BCR 1 +#define GCC_CAMSS_TOP_BCR 2 +#define GCC_GPU_BCR 3 +#define GCC_MMSS_BCR 4 +#define GCC_PDM_BCR 5 +#define GCC_QUPV3_WRAPPER_0_BCR 6 +#define GCC_SDCC1_BCR 7 +#define GCC_SDCC2_BCR 8 +#define GCC_USB30_PRIM_BCR 9 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 10 +#define GCC_VCODEC0_BCR 11 +#define GCC_VENUS_BCR 12 +#define GCC_VIDEO_INTERFACE_BCR 13 +#define GCC_QUSB2PHY_PRIM_BCR 14 +#define GCC_USB3_PHY_PRIM_SP0_BCR 15 +#define GCC_USB3PHY_PHY_PRIM_SP0_BCR 16 + +/* Indexes for GDSCs */ +#define GCC_CAMSS_TOP_GDSC 0 +#define GCC_USB30_PRIM_GDSC 1 +#define GCC_VCODEC0_GDSC 2 +#define GCC_VENUS_GDSC 3 +#define HLOS1_VOTE_TURING_MMU_TBU1_GDSC 4 +#define HLOS1_VOTE_TURING_MMU_TBU0_GDSC 5 +#define HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC 6 +#define HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC 7 + +#endif diff --git a/include/dt-bindings/clock/qcom,gcc-sc7180.h b/include/dt-bindings/clock/qcom,gcc-sc7180.h index e8029b2e92d7..bdf43adc7897 100644 --- a/include/dt-bindings/clock/qcom,gcc-sc7180.h +++ b/include/dt-bindings/clock/qcom,gcc-sc7180.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. */ #ifndef _DT_BINDINGS_CLK_QCOM_GCC_SC7180_H @@ -132,6 +132,13 @@ #define GCC_VIDEO_GPLL0_DIV_CLK_SRC 122 #define GCC_VIDEO_THROTTLE_AXI_CLK 123 #define GCC_VIDEO_XO_CLK 124 +#define GCC_MSS_CFG_AHB_CLK 125 +#define GCC_MSS_MFAB_AXIS_CLK 126 +#define GCC_MSS_NAV_AXI_CLK 127 +#define GCC_MSS_Q6_MEMNOC_AXI_CLK 128 +#define GCC_MSS_SNOC_AXI_CLK 129 +#define GCC_SEC_CTRL_CLK_SRC 130 +#define GCC_LPASS_CFG_NOC_SWAY_CLK 131 /* GCC resets */ #define GCC_QUSB2PHY_PRIM_BCR 0 diff --git a/include/dt-bindings/clock/qcom,gcc-sc7280.h b/include/dt-bindings/clock/qcom,gcc-sc7280.h new file mode 100644 index 000000000000..3d5724b79bff --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-sc7280.h @@ -0,0 +1,226 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SC7280_H +#define _DT_BINDINGS_CLK_QCOM_GCC_SC7280_H + +/* GCC clocks */ +#define GCC_GPLL0 0 +#define GCC_GPLL0_OUT_EVEN 1 +#define GCC_GPLL0_OUT_ODD 2 +#define GCC_GPLL1 3 +#define GCC_GPLL10 4 +#define GCC_GPLL4 5 +#define GCC_GPLL9 6 +#define GCC_AGGRE_NOC_PCIE_0_AXI_CLK 7 +#define GCC_AGGRE_NOC_PCIE_1_AXI_CLK 8 +#define GCC_AGGRE_UFS_PHY_AXI_CLK 9 +#define GCC_AGGRE_USB3_PRIM_AXI_CLK 10 +#define GCC_CAMERA_AHB_CLK 11 +#define GCC_CAMERA_HF_AXI_CLK 12 +#define GCC_CAMERA_SF_AXI_CLK 13 +#define GCC_CAMERA_XO_CLK 14 +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 15 +#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 16 +#define GCC_CPUSS_AHB_CLK 17 +#define GCC_CPUSS_AHB_CLK_SRC 18 +#define GCC_CPUSS_AHB_POSTDIV_CLK_SRC 19 +#define GCC_DDRSS_GPU_AXI_CLK 20 +#define GCC_DDRSS_PCIE_SF_CLK 21 +#define GCC_DISP_AHB_CLK 22 +#define GCC_DISP_GPLL0_CLK_SRC 23 +#define GCC_DISP_HF_AXI_CLK 24 +#define GCC_DISP_SF_AXI_CLK 25 +#define GCC_DISP_XO_CLK 26 +#define GCC_GP1_CLK 27 +#define GCC_GP1_CLK_SRC 28 +#define GCC_GP2_CLK 29 +#define GCC_GP2_CLK_SRC 30 +#define GCC_GP3_CLK 31 +#define GCC_GP3_CLK_SRC 32 +#define GCC_GPU_CFG_AHB_CLK 33 +#define GCC_GPU_GPLL0_CLK_SRC 34 +#define GCC_GPU_GPLL0_DIV_CLK_SRC 35 +#define GCC_GPU_IREF_EN 36 +#define GCC_GPU_MEMNOC_GFX_CLK 37 +#define GCC_GPU_SNOC_DVM_GFX_CLK 38 +#define GCC_PCIE0_PHY_RCHNG_CLK 39 +#define GCC_PCIE1_PHY_RCHNG_CLK 40 +#define GCC_PCIE_0_AUX_CLK 41 +#define GCC_PCIE_0_AUX_CLK_SRC 42 +#define GCC_PCIE_0_CFG_AHB_CLK 43 +#define GCC_PCIE_0_MSTR_AXI_CLK 44 +#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 45 +#define GCC_PCIE_0_PIPE_CLK 46 +#define GCC_PCIE_0_PIPE_CLK_SRC 47 +#define GCC_PCIE_0_SLV_AXI_CLK 48 +#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 49 +#define GCC_PCIE_1_AUX_CLK 50 +#define GCC_PCIE_1_AUX_CLK_SRC 51 +#define GCC_PCIE_1_CFG_AHB_CLK 52 +#define GCC_PCIE_1_MSTR_AXI_CLK 53 +#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 54 +#define GCC_PCIE_1_PIPE_CLK 55 +#define GCC_PCIE_1_PIPE_CLK_SRC 56 +#define GCC_PCIE_1_SLV_AXI_CLK 57 +#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 58 +#define GCC_PCIE_THROTTLE_CORE_CLK 59 +#define GCC_PDM2_CLK 60 +#define GCC_PDM2_CLK_SRC 61 +#define GCC_PDM_AHB_CLK 62 +#define GCC_PDM_XO4_CLK 63 +#define GCC_QMIP_CAMERA_NRT_AHB_CLK 64 +#define GCC_QMIP_CAMERA_RT_AHB_CLK 65 +#define GCC_QMIP_DISP_AHB_CLK 66 +#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 67 +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 68 +#define GCC_QUPV3_WRAP0_CORE_CLK 69 +#define GCC_QUPV3_WRAP0_S0_CLK 70 +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 71 +#define GCC_QUPV3_WRAP0_S1_CLK 72 +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 73 +#define GCC_QUPV3_WRAP0_S2_CLK 74 +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 75 +#define GCC_QUPV3_WRAP0_S3_CLK 76 +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 77 +#define GCC_QUPV3_WRAP0_S4_CLK 78 +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 79 +#define GCC_QUPV3_WRAP0_S5_CLK 80 +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 81 +#define GCC_QUPV3_WRAP0_S6_CLK 82 +#define GCC_QUPV3_WRAP0_S6_CLK_SRC 83 +#define GCC_QUPV3_WRAP0_S7_CLK 84 +#define GCC_QUPV3_WRAP0_S7_CLK_SRC 85 +#define GCC_QUPV3_WRAP1_CORE_2X_CLK 86 +#define GCC_QUPV3_WRAP1_CORE_CLK 87 +#define GCC_QUPV3_WRAP1_S0_CLK 88 +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 89 +#define GCC_QUPV3_WRAP1_S1_CLK 90 +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 91 +#define GCC_QUPV3_WRAP1_S2_CLK 92 +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 93 +#define GCC_QUPV3_WRAP1_S3_CLK 94 +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 95 +#define GCC_QUPV3_WRAP1_S4_CLK 96 +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 97 +#define GCC_QUPV3_WRAP1_S5_CLK 98 +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 99 +#define GCC_QUPV3_WRAP1_S6_CLK 100 +#define GCC_QUPV3_WRAP1_S6_CLK_SRC 101 +#define GCC_QUPV3_WRAP1_S7_CLK 102 +#define GCC_QUPV3_WRAP1_S7_CLK_SRC 103 +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 104 +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 105 +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 106 +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 107 +#define GCC_SDCC1_AHB_CLK 108 +#define GCC_SDCC1_APPS_CLK 109 +#define GCC_SDCC1_APPS_CLK_SRC 110 +#define GCC_SDCC1_ICE_CORE_CLK 111 +#define GCC_SDCC1_ICE_CORE_CLK_SRC 112 +#define GCC_SDCC2_AHB_CLK 113 +#define GCC_SDCC2_APPS_CLK 114 +#define GCC_SDCC2_APPS_CLK_SRC 115 +#define GCC_SDCC4_AHB_CLK 116 +#define GCC_SDCC4_APPS_CLK 117 +#define GCC_SDCC4_APPS_CLK_SRC 118 +#define GCC_SYS_NOC_CPUSS_AHB_CLK 119 +#define GCC_THROTTLE_PCIE_AHB_CLK 120 +#define GCC_TITAN_NRT_THROTTLE_CORE_CLK 121 +#define GCC_TITAN_RT_THROTTLE_CORE_CLK 122 +#define GCC_UFS_1_CLKREF_EN 123 +#define GCC_UFS_PHY_AHB_CLK 124 +#define GCC_UFS_PHY_AXI_CLK 125 +#define GCC_UFS_PHY_AXI_CLK_SRC 126 +#define GCC_UFS_PHY_ICE_CORE_CLK 127 +#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 128 +#define GCC_UFS_PHY_PHY_AUX_CLK 129 +#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 130 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 131 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 132 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 133 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 134 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 135 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 136 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK 137 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 138 +#define GCC_USB30_PRIM_MASTER_CLK 139 +#define GCC_USB30_PRIM_MASTER_CLK_SRC 140 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 141 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 142 +#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 143 +#define GCC_USB30_PRIM_SLEEP_CLK 144 +#define GCC_USB30_SEC_MASTER_CLK 145 +#define GCC_USB30_SEC_MASTER_CLK_SRC 146 +#define GCC_USB30_SEC_MOCK_UTMI_CLK 147 +#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 148 +#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 149 +#define GCC_USB30_SEC_SLEEP_CLK 150 +#define GCC_USB3_PRIM_PHY_AUX_CLK 151 +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 152 +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 153 +#define GCC_USB3_PRIM_PHY_PIPE_CLK 154 +#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 155 +#define GCC_USB3_SEC_PHY_AUX_CLK 156 +#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 157 +#define GCC_USB3_SEC_PHY_COM_AUX_CLK 158 +#define GCC_USB3_SEC_PHY_PIPE_CLK 159 +#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 160 +#define GCC_VIDEO_AHB_CLK 161 +#define GCC_VIDEO_AXI0_CLK 162 +#define GCC_VIDEO_MVP_THROTTLE_CORE_CLK 163 +#define GCC_VIDEO_XO_CLK 164 +#define GCC_GPLL0_MAIN_DIV_CDIV 165 +#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 166 +#define GCC_QSPI_CORE_CLK 167 +#define GCC_QSPI_CORE_CLK_SRC 168 +#define GCC_CFG_NOC_LPASS_CLK 169 +#define GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC 170 +#define GCC_MSS_CFG_AHB_CLK 171 +#define GCC_MSS_OFFLINE_AXI_CLK 172 +#define GCC_MSS_SNOC_AXI_CLK 173 +#define GCC_MSS_Q6_MEMNOC_AXI_CLK 174 +#define GCC_MSS_Q6SS_BOOT_CLK_SRC 175 +#define GCC_AGGRE_USB3_SEC_AXI_CLK 176 +#define GCC_AGGRE_NOC_PCIE_TBU_CLK 177 +#define GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK 178 +#define GCC_PCIE_CLKREF_EN 179 +#define GCC_WPSS_AHB_CLK 180 +#define GCC_WPSS_AHB_BDG_MST_CLK 181 +#define GCC_WPSS_RSCP_CLK 182 +#define GCC_EDP_CLKREF_EN 183 +#define GCC_SEC_CTRL_CLK_SRC 184 + +/* GCC power domains */ +#define GCC_PCIE_0_GDSC 0 +#define GCC_PCIE_1_GDSC 1 +#define GCC_UFS_PHY_GDSC 2 +#define GCC_USB30_PRIM_GDSC 3 +#define GCC_USB30_SEC_GDSC 4 +#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 5 +#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 6 +#define HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC 7 +#define HLOS1_VOTE_TURING_MMU_TBU0_GDSC 8 +#define HLOS1_VOTE_TURING_MMU_TBU1_GDSC 9 + +/* GCC resets */ +#define GCC_PCIE_0_BCR 0 +#define GCC_PCIE_0_PHY_BCR 1 +#define GCC_PCIE_1_BCR 2 +#define GCC_PCIE_1_PHY_BCR 3 +#define GCC_QUSB2PHY_PRIM_BCR 4 +#define GCC_QUSB2PHY_SEC_BCR 5 +#define GCC_SDCC1_BCR 6 +#define GCC_SDCC2_BCR 7 +#define GCC_SDCC4_BCR 8 +#define GCC_UFS_PHY_BCR 9 +#define GCC_USB30_PRIM_BCR 10 +#define GCC_USB30_SEC_BCR 11 +#define GCC_USB3_DP_PHY_PRIM_BCR 12 +#define GCC_USB3_PHY_PRIM_BCR 13 +#define GCC_USB3PHY_PHY_PRIM_BCR 14 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 15 + +#endif diff --git a/include/dt-bindings/clock/qcom,gcc-sc8180x.h b/include/dt-bindings/clock/qcom,gcc-sc8180x.h new file mode 100644 index 000000000000..e893415ae13d --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-sc8180x.h @@ -0,0 +1,309 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2021, Linaro Ltd. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SC8180X_H +#define _DT_BINDINGS_CLK_QCOM_GCC_SC8180X_H + +#define GCC_AGGRE_NOC_PCIE_TBU_CLK 0 +#define GCC_AGGRE_UFS_CARD_AXI_CLK 1 +#define GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK 2 +#define GCC_AGGRE_UFS_PHY_AXI_CLK 3 +#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 4 +#define GCC_AGGRE_USB3_MP_AXI_CLK 5 +#define GCC_AGGRE_USB3_PRIM_AXI_CLK 6 +#define GCC_AGGRE_USB3_SEC_AXI_CLK 7 +#define GCC_BOOT_ROM_AHB_CLK 8 +#define GCC_CAMERA_HF_AXI_CLK 9 +#define GCC_CAMERA_SF_AXI_CLK 10 +#define GCC_CFG_NOC_USB3_MP_AXI_CLK 11 +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 12 +#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 13 +#define GCC_CPUSS_AHB_CLK 14 +#define GCC_CPUSS_AHB_CLK_SRC 15 +#define GCC_CPUSS_RBCPR_CLK 16 +#define GCC_DDRSS_GPU_AXI_CLK 17 +#define GCC_DISP_HF_AXI_CLK 18 +#define GCC_DISP_SF_AXI_CLK 19 +#define GCC_EMAC_AXI_CLK 20 +#define GCC_EMAC_PTP_CLK 21 +#define GCC_EMAC_PTP_CLK_SRC 22 +#define GCC_EMAC_RGMII_CLK 23 +#define GCC_EMAC_RGMII_CLK_SRC 24 +#define GCC_EMAC_SLV_AHB_CLK 25 +#define GCC_GP1_CLK 26 +#define GCC_GP1_CLK_SRC 27 +#define GCC_GP2_CLK 28 +#define GCC_GP2_CLK_SRC 29 +#define GCC_GP3_CLK 30 +#define GCC_GP3_CLK_SRC 31 +#define GCC_GP4_CLK 32 +#define GCC_GP4_CLK_SRC 33 +#define GCC_GP5_CLK 34 +#define GCC_GP5_CLK_SRC 35 +#define GCC_GPU_GPLL0_CLK_SRC 36 +#define GCC_GPU_GPLL0_DIV_CLK_SRC 37 +#define GCC_GPU_MEMNOC_GFX_CLK 38 +#define GCC_GPU_SNOC_DVM_GFX_CLK 39 +#define GCC_NPU_AT_CLK 40 +#define GCC_NPU_AXI_CLK 41 +#define GCC_NPU_AXI_CLK_SRC 42 +#define GCC_NPU_GPLL0_CLK_SRC 43 +#define GCC_NPU_GPLL0_DIV_CLK_SRC 44 +#define GCC_NPU_TRIG_CLK 45 +#define GCC_PCIE0_PHY_REFGEN_CLK 46 +#define GCC_PCIE1_PHY_REFGEN_CLK 47 +#define GCC_PCIE2_PHY_REFGEN_CLK 48 +#define GCC_PCIE3_PHY_REFGEN_CLK 49 +#define GCC_PCIE_0_AUX_CLK 50 +#define GCC_PCIE_0_AUX_CLK_SRC 51 +#define GCC_PCIE_0_CFG_AHB_CLK 52 +#define GCC_PCIE_0_MSTR_AXI_CLK 53 +#define GCC_PCIE_0_PIPE_CLK 54 +#define GCC_PCIE_0_SLV_AXI_CLK 55 +#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 56 +#define GCC_PCIE_1_AUX_CLK 57 +#define GCC_PCIE_1_AUX_CLK_SRC 58 +#define GCC_PCIE_1_CFG_AHB_CLK 59 +#define GCC_PCIE_1_MSTR_AXI_CLK 60 +#define GCC_PCIE_1_PIPE_CLK 61 +#define GCC_PCIE_1_SLV_AXI_CLK 62 +#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 63 +#define GCC_PCIE_2_AUX_CLK 64 +#define GCC_PCIE_2_AUX_CLK_SRC 65 +#define GCC_PCIE_2_CFG_AHB_CLK 66 +#define GCC_PCIE_2_MSTR_AXI_CLK 67 +#define GCC_PCIE_2_PIPE_CLK 68 +#define GCC_PCIE_2_SLV_AXI_CLK 69 +#define GCC_PCIE_2_SLV_Q2A_AXI_CLK 70 +#define GCC_PCIE_3_AUX_CLK 71 +#define GCC_PCIE_3_AUX_CLK_SRC 72 +#define GCC_PCIE_3_CFG_AHB_CLK 73 +#define GCC_PCIE_3_MSTR_AXI_CLK 74 +#define GCC_PCIE_3_PIPE_CLK 75 +#define GCC_PCIE_3_SLV_AXI_CLK 76 +#define GCC_PCIE_3_SLV_Q2A_AXI_CLK 77 +#define GCC_PCIE_PHY_AUX_CLK 78 +#define GCC_PCIE_PHY_REFGEN_CLK_SRC 79 +#define GCC_PDM2_CLK 80 +#define GCC_PDM2_CLK_SRC 81 +#define GCC_PDM_AHB_CLK 82 +#define GCC_PDM_XO4_CLK 83 +#define GCC_PRNG_AHB_CLK 84 +#define GCC_QMIP_CAMERA_NRT_AHB_CLK 85 +#define GCC_QMIP_CAMERA_RT_AHB_CLK 86 +#define GCC_QMIP_DISP_AHB_CLK 87 +#define GCC_QMIP_VIDEO_CVP_AHB_CLK 88 +#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 89 +#define GCC_QSPI_1_CNOC_PERIPH_AHB_CLK 90 +#define GCC_QSPI_1_CORE_CLK 91 +#define GCC_QSPI_1_CORE_CLK_SRC 92 +#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 93 +#define GCC_QSPI_CORE_CLK 94 +#define GCC_QSPI_CORE_CLK_SRC 95 +#define GCC_QUPV3_WRAP0_S0_CLK 96 +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 97 +#define GCC_QUPV3_WRAP0_S1_CLK 98 +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 99 +#define GCC_QUPV3_WRAP0_S2_CLK 100 +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 101 +#define GCC_QUPV3_WRAP0_S3_CLK 102 +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 103 +#define GCC_QUPV3_WRAP0_S4_CLK 104 +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 105 +#define GCC_QUPV3_WRAP0_S5_CLK 106 +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 107 +#define GCC_QUPV3_WRAP0_S6_CLK 108 +#define GCC_QUPV3_WRAP0_S6_CLK_SRC 109 +#define GCC_QUPV3_WRAP0_S7_CLK 110 +#define GCC_QUPV3_WRAP0_S7_CLK_SRC 111 +#define GCC_QUPV3_WRAP1_S0_CLK 112 +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 113 +#define GCC_QUPV3_WRAP1_S1_CLK 114 +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 115 +#define GCC_QUPV3_WRAP1_S2_CLK 116 +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 117 +#define GCC_QUPV3_WRAP1_S3_CLK 118 +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 119 +#define GCC_QUPV3_WRAP1_S4_CLK 120 +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 121 +#define GCC_QUPV3_WRAP1_S5_CLK 122 +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 123 +#define GCC_QUPV3_WRAP2_S0_CLK 124 +#define GCC_QUPV3_WRAP2_S0_CLK_SRC 125 +#define GCC_QUPV3_WRAP2_S1_CLK 126 +#define GCC_QUPV3_WRAP2_S1_CLK_SRC 127 +#define GCC_QUPV3_WRAP2_S2_CLK 128 +#define GCC_QUPV3_WRAP2_S2_CLK_SRC 129 +#define GCC_QUPV3_WRAP2_S3_CLK 130 +#define GCC_QUPV3_WRAP2_S3_CLK_SRC 131 +#define GCC_QUPV3_WRAP2_S4_CLK 132 +#define GCC_QUPV3_WRAP2_S4_CLK_SRC 133 +#define GCC_QUPV3_WRAP2_S5_CLK 134 +#define GCC_QUPV3_WRAP2_S5_CLK_SRC 135 +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 136 +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 137 +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 138 +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 139 +#define GCC_QUPV3_WRAP_2_M_AHB_CLK 140 +#define GCC_QUPV3_WRAP_2_S_AHB_CLK 141 +#define GCC_SDCC2_AHB_CLK 142 +#define GCC_SDCC2_APPS_CLK 143 +#define GCC_SDCC2_APPS_CLK_SRC 144 +#define GCC_SDCC4_AHB_CLK 145 +#define GCC_SDCC4_APPS_CLK 146 +#define GCC_SDCC4_APPS_CLK_SRC 147 +#define GCC_SYS_NOC_CPUSS_AHB_CLK 148 +#define GCC_TSIF_AHB_CLK 149 +#define GCC_TSIF_INACTIVITY_TIMERS_CLK 150 +#define GCC_TSIF_REF_CLK 151 +#define GCC_TSIF_REF_CLK_SRC 152 +#define GCC_UFS_CARD_2_AHB_CLK 153 +#define GCC_UFS_CARD_2_AXI_CLK 154 +#define GCC_UFS_CARD_2_AXI_CLK_SRC 155 +#define GCC_UFS_CARD_2_ICE_CORE_CLK 156 +#define GCC_UFS_CARD_2_ICE_CORE_CLK_SRC 157 +#define GCC_UFS_CARD_2_PHY_AUX_CLK 158 +#define GCC_UFS_CARD_2_PHY_AUX_CLK_SRC 159 +#define GCC_UFS_CARD_2_RX_SYMBOL_0_CLK 160 +#define GCC_UFS_CARD_2_RX_SYMBOL_1_CLK 161 +#define GCC_UFS_CARD_2_TX_SYMBOL_0_CLK 162 +#define GCC_UFS_CARD_2_UNIPRO_CORE_CLK 163 +#define GCC_UFS_CARD_2_UNIPRO_CORE_CLK_SRC 164 +#define GCC_UFS_CARD_AHB_CLK 165 +#define GCC_UFS_CARD_AXI_CLK 166 +#define GCC_UFS_CARD_AXI_CLK_SRC 167 +#define GCC_UFS_CARD_AXI_HW_CTL_CLK 168 +#define GCC_UFS_CARD_ICE_CORE_CLK 169 +#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 170 +#define GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK 171 +#define GCC_UFS_CARD_PHY_AUX_CLK 172 +#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 173 +#define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK 174 +#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 175 +#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 176 +#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 177 +#define GCC_UFS_CARD_UNIPRO_CORE_CLK 178 +#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 179 +#define GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK 180 +#define GCC_UFS_PHY_AHB_CLK 181 +#define GCC_UFS_PHY_AXI_CLK 182 +#define GCC_UFS_PHY_AXI_CLK_SRC 183 +#define GCC_UFS_PHY_AXI_HW_CTL_CLK 184 +#define GCC_UFS_PHY_ICE_CORE_CLK 185 +#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 186 +#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 187 +#define GCC_UFS_PHY_PHY_AUX_CLK 188 +#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 189 +#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 190 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 191 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 192 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 193 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK 194 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 195 +#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 196 +#define GCC_USB30_MP_MASTER_CLK 197 +#define GCC_USB30_MP_MASTER_CLK_SRC 198 +#define GCC_USB30_MP_MOCK_UTMI_CLK 199 +#define GCC_USB30_MP_MOCK_UTMI_CLK_SRC 200 +#define GCC_USB30_MP_SLEEP_CLK 201 +#define GCC_USB30_PRIM_MASTER_CLK 202 +#define GCC_USB30_PRIM_MASTER_CLK_SRC 203 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 204 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 205 +#define GCC_USB30_PRIM_SLEEP_CLK 206 +#define GCC_USB30_SEC_MASTER_CLK 207 +#define GCC_USB30_SEC_MASTER_CLK_SRC 208 +#define GCC_USB30_SEC_MOCK_UTMI_CLK 209 +#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 210 +#define GCC_USB30_SEC_SLEEP_CLK 211 +#define GCC_USB3_MP_PHY_AUX_CLK 212 +#define GCC_USB3_MP_PHY_AUX_CLK_SRC 213 +#define GCC_USB3_MP_PHY_COM_AUX_CLK 214 +#define GCC_USB3_MP_PHY_PIPE_0_CLK 215 +#define GCC_USB3_MP_PHY_PIPE_1_CLK 216 +#define GCC_USB3_PRIM_PHY_AUX_CLK 217 +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 218 +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 219 +#define GCC_USB3_PRIM_PHY_PIPE_CLK 220 +#define GCC_USB3_SEC_PHY_AUX_CLK 221 +#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 222 +#define GCC_USB3_SEC_PHY_COM_AUX_CLK 223 +#define GCC_USB3_SEC_PHY_PIPE_CLK 224 +#define GCC_VIDEO_AXI0_CLK 225 +#define GCC_VIDEO_AXI1_CLK 226 +#define GCC_VIDEO_AXIC_CLK 227 +#define GPLL0 228 +#define GPLL0_OUT_EVEN 229 +#define GPLL1 230 +#define GPLL4 231 +#define GPLL7 232 +#define GCC_PCIE_0_CLKREF_CLK 233 +#define GCC_PCIE_1_CLKREF_CLK 234 +#define GCC_PCIE_2_CLKREF_CLK 235 +#define GCC_PCIE_3_CLKREF_CLK 236 +#define GCC_USB3_PRIM_CLKREF_CLK 237 +#define GCC_USB3_SEC_CLKREF_CLK 238 + +#define GCC_EMAC_BCR 0 +#define GCC_GPU_BCR 1 +#define GCC_MMSS_BCR 2 +#define GCC_NPU_BCR 3 +#define GCC_PCIE_0_BCR 4 +#define GCC_PCIE_0_PHY_BCR 5 +#define GCC_PCIE_1_BCR 6 +#define GCC_PCIE_1_PHY_BCR 7 +#define GCC_PCIE_2_BCR 8 +#define GCC_PCIE_2_PHY_BCR 9 +#define GCC_PCIE_3_BCR 10 +#define GCC_PCIE_3_PHY_BCR 11 +#define GCC_PCIE_PHY_BCR 12 +#define GCC_PDM_BCR 13 +#define GCC_PRNG_BCR 14 +#define GCC_QSPI_1_BCR 15 +#define GCC_QSPI_BCR 16 +#define GCC_QUPV3_WRAPPER_0_BCR 17 +#define GCC_QUPV3_WRAPPER_1_BCR 18 +#define GCC_QUPV3_WRAPPER_2_BCR 19 +#define GCC_QUSB2PHY_5_BCR 20 +#define GCC_QUSB2PHY_MP0_BCR 21 +#define GCC_QUSB2PHY_MP1_BCR 22 +#define GCC_QUSB2PHY_PRIM_BCR 23 +#define GCC_QUSB2PHY_SEC_BCR 24 +#define GCC_USB3_PHY_PRIM_SP0_BCR 25 +#define GCC_USB3_PHY_PRIM_SP1_BCR 26 +#define GCC_USB3_DP_PHY_PRIM_SP0_BCR 27 +#define GCC_USB3_DP_PHY_PRIM_SP1_BCR 28 +#define GCC_USB3_PHY_SEC_BCR 29 +#define GCC_USB3PHY_PHY_SEC_BCR 30 +#define GCC_SDCC2_BCR 31 +#define GCC_SDCC4_BCR 32 +#define GCC_TSIF_BCR 33 +#define GCC_UFS_CARD_2_BCR 34 +#define GCC_UFS_CARD_BCR 35 +#define GCC_UFS_PHY_BCR 36 +#define GCC_USB30_MP_BCR 37 +#define GCC_USB30_PRIM_BCR 38 +#define GCC_USB30_SEC_BCR 39 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 40 +#define GCC_VIDEO_AXIC_CLK_BCR 41 +#define GCC_VIDEO_AXI0_CLK_BCR 42 +#define GCC_VIDEO_AXI1_CLK_BCR 43 +#define GCC_USB3_DP_PHY_SEC_BCR 44 + +/* GCC GDSCRs */ +#define EMAC_GDSC 0 +#define PCIE_0_GDSC 1 +#define PCIE_1_GDSC 2 +#define PCIE_2_GDSC 3 +#define PCIE_3_GDSC 4 +#define UFS_CARD_2_GDSC 5 +#define UFS_CARD_GDSC 6 +#define UFS_PHY_GDSC 7 +#define USB30_MP_GDSC 8 +#define USB30_PRIM_GDSC 9 +#define USB30_SEC_GDSC 10 + +#endif diff --git a/include/dt-bindings/clock/qcom,gcc-sc8280xp.h b/include/dt-bindings/clock/qcom,gcc-sc8280xp.h new file mode 100644 index 000000000000..cb2fb638825c --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-sc8280xp.h @@ -0,0 +1,496 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Linaro Ltd. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_DIREWOLF_H +#define _DT_BINDINGS_CLK_QCOM_GCC_DIREWOLF_H + +/* GCC clocks */ +#define GCC_GPLL0 0 +#define GCC_GPLL0_OUT_EVEN 1 +#define GCC_GPLL2 2 +#define GCC_GPLL4 3 +#define GCC_GPLL7 4 +#define GCC_GPLL8 5 +#define GCC_GPLL9 6 +#define GCC_AGGRE_NOC_PCIE0_TUNNEL_AXI_CLK 7 +#define GCC_AGGRE_NOC_PCIE1_TUNNEL_AXI_CLK 8 +#define GCC_AGGRE_NOC_PCIE_4_AXI_CLK 9 +#define GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK 10 +#define GCC_AGGRE_UFS_CARD_AXI_CLK 11 +#define GCC_AGGRE_UFS_PHY_AXI_CLK 12 +#define GCC_AGGRE_USB3_MP_AXI_CLK 13 +#define GCC_AGGRE_USB3_PRIM_AXI_CLK 14 +#define GCC_AGGRE_USB3_SEC_AXI_CLK 15 +#define GCC_AGGRE_USB4_1_AXI_CLK 16 +#define GCC_AGGRE_USB4_AXI_CLK 17 +#define GCC_AGGRE_USB_NOC_AXI_CLK 18 +#define GCC_AGGRE_USB_NOC_NORTH_AXI_CLK 19 +#define GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK 20 +#define GCC_AHB2PHY0_CLK 21 +#define GCC_AHB2PHY2_CLK 22 +#define GCC_BOOT_ROM_AHB_CLK 23 +#define GCC_CAMERA_AHB_CLK 24 +#define GCC_CAMERA_HF_AXI_CLK 25 +#define GCC_CAMERA_SF_AXI_CLK 26 +#define GCC_CAMERA_THROTTLE_NRT_AXI_CLK 27 +#define GCC_CAMERA_THROTTLE_RT_AXI_CLK 28 +#define GCC_CAMERA_THROTTLE_XO_CLK 29 +#define GCC_CAMERA_XO_CLK 30 +#define GCC_CFG_NOC_USB3_MP_AXI_CLK 31 +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 32 +#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 33 +#define GCC_CNOC_PCIE0_TUNNEL_CLK 34 +#define GCC_CNOC_PCIE1_TUNNEL_CLK 35 +#define GCC_CNOC_PCIE4_QX_CLK 36 +#define GCC_DDRSS_GPU_AXI_CLK 37 +#define GCC_DDRSS_PCIE_SF_TBU_CLK 38 +#define GCC_DISP1_AHB_CLK 39 +#define GCC_DISP1_HF_AXI_CLK 40 +#define GCC_DISP1_SF_AXI_CLK 41 +#define GCC_DISP1_THROTTLE_NRT_AXI_CLK 42 +#define GCC_DISP1_THROTTLE_RT_AXI_CLK 43 +#define GCC_DISP1_XO_CLK 44 +#define GCC_DISP_AHB_CLK 45 +#define GCC_DISP_HF_AXI_CLK 46 +#define GCC_DISP_SF_AXI_CLK 47 +#define GCC_DISP_THROTTLE_NRT_AXI_CLK 48 +#define GCC_DISP_THROTTLE_RT_AXI_CLK 49 +#define GCC_DISP_XO_CLK 50 +#define GCC_EMAC0_AXI_CLK 51 +#define GCC_EMAC0_PTP_CLK 52 +#define GCC_EMAC0_PTP_CLK_SRC 53 +#define GCC_EMAC0_RGMII_CLK 54 +#define GCC_EMAC0_RGMII_CLK_SRC 55 +#define GCC_EMAC0_SLV_AHB_CLK 56 +#define GCC_EMAC1_AXI_CLK 57 +#define GCC_EMAC1_PTP_CLK 58 +#define GCC_EMAC1_PTP_CLK_SRC 59 +#define GCC_EMAC1_RGMII_CLK 60 +#define GCC_EMAC1_RGMII_CLK_SRC 61 +#define GCC_EMAC1_SLV_AHB_CLK 62 +#define GCC_GP1_CLK 63 +#define GCC_GP1_CLK_SRC 64 +#define GCC_GP2_CLK 65 +#define GCC_GP2_CLK_SRC 66 +#define GCC_GP3_CLK 67 +#define GCC_GP3_CLK_SRC 68 +#define GCC_GP4_CLK 69 +#define GCC_GP4_CLK_SRC 70 +#define GCC_GP5_CLK 71 +#define GCC_GP5_CLK_SRC 72 +#define GCC_GPU_CFG_AHB_CLK 73 +#define GCC_GPU_GPLL0_CLK_SRC 74 +#define GCC_GPU_GPLL0_DIV_CLK_SRC 75 +#define GCC_GPU_IREF_EN 76 +#define GCC_GPU_MEMNOC_GFX_CLK 77 +#define GCC_GPU_SNOC_DVM_GFX_CLK 78 +#define GCC_GPU_TCU_THROTTLE_AHB_CLK 79 +#define GCC_GPU_TCU_THROTTLE_CLK 80 +#define GCC_PCIE0_PHY_RCHNG_CLK 81 +#define GCC_PCIE1_PHY_RCHNG_CLK 82 +#define GCC_PCIE2A_PHY_RCHNG_CLK 83 +#define GCC_PCIE2B_PHY_RCHNG_CLK 84 +#define GCC_PCIE3A_PHY_RCHNG_CLK 85 +#define GCC_PCIE3B_PHY_RCHNG_CLK 86 +#define GCC_PCIE4_PHY_RCHNG_CLK 87 +#define GCC_PCIE_0_AUX_CLK 88 +#define GCC_PCIE_0_AUX_CLK_SRC 89 +#define GCC_PCIE_0_CFG_AHB_CLK 90 +#define GCC_PCIE_0_MSTR_AXI_CLK 91 +#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 92 +#define GCC_PCIE_0_PIPE_CLK 93 +#define GCC_PCIE_0_SLV_AXI_CLK 94 +#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 95 +#define GCC_PCIE_1_AUX_CLK 96 +#define GCC_PCIE_1_AUX_CLK_SRC 97 +#define GCC_PCIE_1_CFG_AHB_CLK 98 +#define GCC_PCIE_1_MSTR_AXI_CLK 99 +#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 100 +#define GCC_PCIE_1_PIPE_CLK 101 +#define GCC_PCIE_1_SLV_AXI_CLK 102 +#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 103 +#define GCC_PCIE_2A2B_CLKREF_CLK 104 +#define GCC_PCIE_2A_AUX_CLK 105 +#define GCC_PCIE_2A_AUX_CLK_SRC 106 +#define GCC_PCIE_2A_CFG_AHB_CLK 107 +#define GCC_PCIE_2A_MSTR_AXI_CLK 108 +#define GCC_PCIE_2A_PHY_RCHNG_CLK_SRC 109 +#define GCC_PCIE_2A_PIPE_CLK 110 +#define GCC_PCIE_2A_PIPE_CLK_SRC 111 +#define GCC_PCIE_2A_PIPE_DIV_CLK_SRC 112 +#define GCC_PCIE_2A_PIPEDIV2_CLK 113 +#define GCC_PCIE_2A_SLV_AXI_CLK 114 +#define GCC_PCIE_2A_SLV_Q2A_AXI_CLK 115 +#define GCC_PCIE_2B_AUX_CLK 116 +#define GCC_PCIE_2B_AUX_CLK_SRC 117 +#define GCC_PCIE_2B_CFG_AHB_CLK 118 +#define GCC_PCIE_2B_MSTR_AXI_CLK 119 +#define GCC_PCIE_2B_PHY_RCHNG_CLK_SRC 120 +#define GCC_PCIE_2B_PIPE_CLK 121 +#define GCC_PCIE_2B_PIPE_CLK_SRC 122 +#define GCC_PCIE_2B_PIPE_DIV_CLK_SRC 123 +#define GCC_PCIE_2B_PIPEDIV2_CLK 124 +#define GCC_PCIE_2B_SLV_AXI_CLK 125 +#define GCC_PCIE_2B_SLV_Q2A_AXI_CLK 126 +#define GCC_PCIE_3A3B_CLKREF_CLK 127 +#define GCC_PCIE_3A_AUX_CLK 128 +#define GCC_PCIE_3A_AUX_CLK_SRC 129 +#define GCC_PCIE_3A_CFG_AHB_CLK 130 +#define GCC_PCIE_3A_MSTR_AXI_CLK 131 +#define GCC_PCIE_3A_PHY_RCHNG_CLK_SRC 132 +#define GCC_PCIE_3A_PIPE_CLK 133 +#define GCC_PCIE_3A_PIPE_CLK_SRC 134 +#define GCC_PCIE_3A_PIPE_DIV_CLK_SRC 135 +#define GCC_PCIE_3A_PIPEDIV2_CLK 136 +#define GCC_PCIE_3A_SLV_AXI_CLK 137 +#define GCC_PCIE_3A_SLV_Q2A_AXI_CLK 138 +#define GCC_PCIE_3B_AUX_CLK 139 +#define GCC_PCIE_3B_AUX_CLK_SRC 140 +#define GCC_PCIE_3B_CFG_AHB_CLK 141 +#define GCC_PCIE_3B_MSTR_AXI_CLK 142 +#define GCC_PCIE_3B_PHY_RCHNG_CLK_SRC 143 +#define GCC_PCIE_3B_PIPE_CLK 144 +#define GCC_PCIE_3B_PIPE_CLK_SRC 145 +#define GCC_PCIE_3B_PIPE_DIV_CLK_SRC 146 +#define GCC_PCIE_3B_PIPEDIV2_CLK 147 +#define GCC_PCIE_3B_SLV_AXI_CLK 148 +#define GCC_PCIE_3B_SLV_Q2A_AXI_CLK 149 +#define GCC_PCIE_4_AUX_CLK 150 +#define GCC_PCIE_4_AUX_CLK_SRC 151 +#define GCC_PCIE_4_CFG_AHB_CLK 152 +#define GCC_PCIE_4_CLKREF_CLK 153 +#define GCC_PCIE_4_MSTR_AXI_CLK 154 +#define GCC_PCIE_4_PHY_RCHNG_CLK_SRC 155 +#define GCC_PCIE_4_PIPE_CLK 156 +#define GCC_PCIE_4_PIPE_CLK_SRC 157 +#define GCC_PCIE_4_PIPE_DIV_CLK_SRC 158 +#define GCC_PCIE_4_PIPEDIV2_CLK 159 +#define GCC_PCIE_4_SLV_AXI_CLK 160 +#define GCC_PCIE_4_SLV_Q2A_AXI_CLK 161 +#define GCC_PCIE_RSCC_AHB_CLK 162 +#define GCC_PCIE_RSCC_XO_CLK 163 +#define GCC_PCIE_RSCC_XO_CLK_SRC 164 +#define GCC_PCIE_THROTTLE_CFG_CLK 165 +#define GCC_PDM2_CLK 166 +#define GCC_PDM2_CLK_SRC 167 +#define GCC_PDM_AHB_CLK 168 +#define GCC_PDM_XO4_CLK 169 +#define GCC_QMIP_CAMERA_NRT_AHB_CLK 170 +#define GCC_QMIP_CAMERA_RT_AHB_CLK 171 +#define GCC_QMIP_DISP1_AHB_CLK 172 +#define GCC_QMIP_DISP1_ROT_AHB_CLK 173 +#define GCC_QMIP_DISP_AHB_CLK 174 +#define GCC_QMIP_DISP_ROT_AHB_CLK 175 +#define GCC_QMIP_VIDEO_CVP_AHB_CLK 176 +#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 177 +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 178 +#define GCC_QUPV3_WRAP0_CORE_CLK 179 +#define GCC_QUPV3_WRAP0_QSPI0_CLK 180 +#define GCC_QUPV3_WRAP0_S0_CLK 181 +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 182 +#define GCC_QUPV3_WRAP0_S1_CLK 183 +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 184 +#define GCC_QUPV3_WRAP0_S2_CLK 185 +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 186 +#define GCC_QUPV3_WRAP0_S3_CLK 187 +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 188 +#define GCC_QUPV3_WRAP0_S4_CLK 189 +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 190 +#define GCC_QUPV3_WRAP0_S4_DIV_CLK_SRC 191 +#define GCC_QUPV3_WRAP0_S5_CLK 192 +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 193 +#define GCC_QUPV3_WRAP0_S6_CLK 194 +#define GCC_QUPV3_WRAP0_S6_CLK_SRC 195 +#define GCC_QUPV3_WRAP0_S7_CLK 196 +#define GCC_QUPV3_WRAP0_S7_CLK_SRC 197 +#define GCC_QUPV3_WRAP1_CORE_2X_CLK 198 +#define GCC_QUPV3_WRAP1_CORE_CLK 199 +#define GCC_QUPV3_WRAP1_QSPI0_CLK 200 +#define GCC_QUPV3_WRAP1_S0_CLK 201 +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 202 +#define GCC_QUPV3_WRAP1_S1_CLK 203 +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 204 +#define GCC_QUPV3_WRAP1_S2_CLK 205 +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 206 +#define GCC_QUPV3_WRAP1_S3_CLK 207 +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 208 +#define GCC_QUPV3_WRAP1_S4_CLK 209 +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 210 +#define GCC_QUPV3_WRAP1_S4_DIV_CLK_SRC 211 +#define GCC_QUPV3_WRAP1_S5_CLK 212 +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 213 +#define GCC_QUPV3_WRAP1_S6_CLK 214 +#define GCC_QUPV3_WRAP1_S6_CLK_SRC 215 +#define GCC_QUPV3_WRAP1_S7_CLK 216 +#define GCC_QUPV3_WRAP1_S7_CLK_SRC 217 +#define GCC_QUPV3_WRAP2_CORE_2X_CLK 218 +#define GCC_QUPV3_WRAP2_CORE_CLK 219 +#define GCC_QUPV3_WRAP2_QSPI0_CLK 220 +#define GCC_QUPV3_WRAP2_S0_CLK 221 +#define GCC_QUPV3_WRAP2_S0_CLK_SRC 222 +#define GCC_QUPV3_WRAP2_S1_CLK 223 +#define GCC_QUPV3_WRAP2_S1_CLK_SRC 224 +#define GCC_QUPV3_WRAP2_S2_CLK 225 +#define GCC_QUPV3_WRAP2_S2_CLK_SRC 226 +#define GCC_QUPV3_WRAP2_S3_CLK 227 +#define GCC_QUPV3_WRAP2_S3_CLK_SRC 228 +#define GCC_QUPV3_WRAP2_S4_CLK 229 +#define GCC_QUPV3_WRAP2_S4_CLK_SRC 230 +#define GCC_QUPV3_WRAP2_S4_DIV_CLK_SRC 231 +#define GCC_QUPV3_WRAP2_S5_CLK 232 +#define GCC_QUPV3_WRAP2_S5_CLK_SRC 233 +#define GCC_QUPV3_WRAP2_S6_CLK 234 +#define GCC_QUPV3_WRAP2_S6_CLK_SRC 235 +#define GCC_QUPV3_WRAP2_S7_CLK 236 +#define GCC_QUPV3_WRAP2_S7_CLK_SRC 237 +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 238 +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 239 +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 240 +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 241 +#define GCC_QUPV3_WRAP_2_M_AHB_CLK 242 +#define GCC_QUPV3_WRAP_2_S_AHB_CLK 243 +#define GCC_SDCC2_AHB_CLK 244 +#define GCC_SDCC2_APPS_CLK 245 +#define GCC_SDCC2_APPS_CLK_SRC 246 +#define GCC_SDCC4_AHB_CLK 247 +#define GCC_SDCC4_APPS_CLK 248 +#define GCC_SDCC4_APPS_CLK_SRC 249 +#define GCC_SYS_NOC_USB_AXI_CLK 250 +#define GCC_UFS_1_CARD_CLKREF_CLK 251 +#define GCC_UFS_CARD_AHB_CLK 252 +#define GCC_UFS_CARD_AXI_CLK 253 +#define GCC_UFS_CARD_AXI_CLK_SRC 254 +#define GCC_UFS_CARD_CLKREF_CLK 255 +#define GCC_UFS_CARD_ICE_CORE_CLK 256 +#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 257 +#define GCC_UFS_CARD_PHY_AUX_CLK 258 +#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 259 +#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 260 +#define GCC_UFS_CARD_RX_SYMBOL_0_CLK_SRC 261 +#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 262 +#define GCC_UFS_CARD_RX_SYMBOL_1_CLK_SRC 263 +#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 264 +#define GCC_UFS_CARD_TX_SYMBOL_0_CLK_SRC 265 +#define GCC_UFS_CARD_UNIPRO_CORE_CLK 266 +#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 267 +#define GCC_UFS_PHY_AHB_CLK 268 +#define GCC_UFS_PHY_AXI_CLK 269 +#define GCC_UFS_PHY_AXI_CLK_SRC 270 +#define GCC_UFS_PHY_ICE_CORE_CLK 271 +#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 272 +#define GCC_UFS_PHY_PHY_AUX_CLK 273 +#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 274 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 275 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 276 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 277 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 278 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 279 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 280 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK 281 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 282 +#define GCC_UFS_REF_CLKREF_CLK 283 +#define GCC_USB2_HS0_CLKREF_CLK 284 +#define GCC_USB2_HS1_CLKREF_CLK 285 +#define GCC_USB2_HS2_CLKREF_CLK 286 +#define GCC_USB2_HS3_CLKREF_CLK 287 +#define GCC_USB30_MP_MASTER_CLK 288 +#define GCC_USB30_MP_MASTER_CLK_SRC 289 +#define GCC_USB30_MP_MOCK_UTMI_CLK 290 +#define GCC_USB30_MP_MOCK_UTMI_CLK_SRC 291 +#define GCC_USB30_MP_MOCK_UTMI_POSTDIV_CLK_SRC 292 +#define GCC_USB30_MP_SLEEP_CLK 293 +#define GCC_USB30_PRIM_MASTER_CLK 294 +#define GCC_USB30_PRIM_MASTER_CLK_SRC 295 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 296 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 297 +#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 298 +#define GCC_USB30_PRIM_SLEEP_CLK 299 +#define GCC_USB30_SEC_MASTER_CLK 300 +#define GCC_USB30_SEC_MASTER_CLK_SRC 301 +#define GCC_USB30_SEC_MOCK_UTMI_CLK 302 +#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 303 +#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 304 +#define GCC_USB30_SEC_SLEEP_CLK 305 +#define GCC_USB34_PRIM_PHY_PIPE_CLK_SRC 306 +#define GCC_USB34_SEC_PHY_PIPE_CLK_SRC 307 +#define GCC_USB3_MP0_CLKREF_CLK 308 +#define GCC_USB3_MP1_CLKREF_CLK 309 +#define GCC_USB3_MP_PHY_AUX_CLK 310 +#define GCC_USB3_MP_PHY_AUX_CLK_SRC 311 +#define GCC_USB3_MP_PHY_COM_AUX_CLK 312 +#define GCC_USB3_MP_PHY_PIPE_0_CLK 313 +#define GCC_USB3_MP_PHY_PIPE_0_CLK_SRC 314 +#define GCC_USB3_MP_PHY_PIPE_1_CLK 315 +#define GCC_USB3_MP_PHY_PIPE_1_CLK_SRC 316 +#define GCC_USB3_PRIM_PHY_AUX_CLK 317 +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 318 +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 319 +#define GCC_USB3_PRIM_PHY_PIPE_CLK 320 +#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 321 +#define GCC_USB3_SEC_PHY_AUX_CLK 322 +#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 323 +#define GCC_USB3_SEC_PHY_COM_AUX_CLK 324 +#define GCC_USB3_SEC_PHY_PIPE_CLK 325 +#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 326 +#define GCC_USB4_1_CFG_AHB_CLK 327 +#define GCC_USB4_1_DP_CLK 328 +#define GCC_USB4_1_MASTER_CLK 329 +#define GCC_USB4_1_MASTER_CLK_SRC 330 +#define GCC_USB4_1_PHY_DP_CLK_SRC 331 +#define GCC_USB4_1_PHY_P2RR2P_PIPE_CLK 332 +#define GCC_USB4_1_PHY_P2RR2P_PIPE_CLK_SRC 333 +#define GCC_USB4_1_PHY_PCIE_PIPE_CLK 334 +#define GCC_USB4_1_PHY_PCIE_PIPE_CLK_SRC 335 +#define GCC_USB4_1_PHY_PCIE_PIPE_MUX_CLK_SRC 336 +#define GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC 337 +#define GCC_USB4_1_PHY_RX0_CLK 338 +#define GCC_USB4_1_PHY_RX0_CLK_SRC 339 +#define GCC_USB4_1_PHY_RX1_CLK 340 +#define GCC_USB4_1_PHY_RX1_CLK_SRC 341 +#define GCC_USB4_1_PHY_SYS_CLK_SRC 342 +#define GCC_USB4_1_PHY_USB_PIPE_CLK 343 +#define GCC_USB4_1_SB_IF_CLK 344 +#define GCC_USB4_1_SB_IF_CLK_SRC 345 +#define GCC_USB4_1_SYS_CLK 346 +#define GCC_USB4_1_TMU_CLK 347 +#define GCC_USB4_1_TMU_CLK_SRC 348 +#define GCC_USB4_CFG_AHB_CLK 349 +#define GCC_USB4_CLKREF_CLK 350 +#define GCC_USB4_DP_CLK 351 +#define GCC_USB4_EUD_CLKREF_CLK 352 +#define GCC_USB4_MASTER_CLK 353 +#define GCC_USB4_MASTER_CLK_SRC 354 +#define GCC_USB4_PHY_DP_CLK_SRC 355 +#define GCC_USB4_PHY_P2RR2P_PIPE_CLK 356 +#define GCC_USB4_PHY_P2RR2P_PIPE_CLK_SRC 357 +#define GCC_USB4_PHY_PCIE_PIPE_CLK 358 +#define GCC_USB4_PHY_PCIE_PIPE_CLK_SRC 359 +#define GCC_USB4_PHY_PCIE_PIPE_MUX_CLK_SRC 360 +#define GCC_USB4_PHY_PCIE_PIPEGMUX_CLK_SRC 361 +#define GCC_USB4_PHY_RX0_CLK 362 +#define GCC_USB4_PHY_RX0_CLK_SRC 363 +#define GCC_USB4_PHY_RX1_CLK 364 +#define GCC_USB4_PHY_RX1_CLK_SRC 365 +#define GCC_USB4_PHY_SYS_CLK_SRC 366 +#define GCC_USB4_PHY_USB_PIPE_CLK 367 +#define GCC_USB4_SB_IF_CLK 368 +#define GCC_USB4_SB_IF_CLK_SRC 369 +#define GCC_USB4_SYS_CLK 370 +#define GCC_USB4_TMU_CLK 371 +#define GCC_USB4_TMU_CLK_SRC 372 +#define GCC_VIDEO_AHB_CLK 373 +#define GCC_VIDEO_AXI0_CLK 374 +#define GCC_VIDEO_AXI1_CLK 375 +#define GCC_VIDEO_CVP_THROTTLE_CLK 376 +#define GCC_VIDEO_VCODEC_THROTTLE_CLK 377 +#define GCC_VIDEO_XO_CLK 378 +#define GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK 379 +#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 380 +#define GCC_UFS_CARD_AXI_HW_CTL_CLK 381 +#define GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK 382 +#define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK 383 +#define GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK 384 +#define GCC_UFS_PHY_AXI_HW_CTL_CLK 385 +#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 386 +#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 387 +#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 388 + +/* GCC resets */ +#define GCC_EMAC0_BCR 0 +#define GCC_EMAC1_BCR 1 +#define GCC_PCIE_0_LINK_DOWN_BCR 2 +#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 3 +#define GCC_PCIE_0_PHY_BCR 4 +#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 5 +#define GCC_PCIE_0_TUNNEL_BCR 6 +#define GCC_PCIE_1_LINK_DOWN_BCR 7 +#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 8 +#define GCC_PCIE_1_PHY_BCR 9 +#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 10 +#define GCC_PCIE_1_TUNNEL_BCR 11 +#define GCC_PCIE_2A_BCR 12 +#define GCC_PCIE_2A_LINK_DOWN_BCR 13 +#define GCC_PCIE_2A_NOCSR_COM_PHY_BCR 14 +#define GCC_PCIE_2A_PHY_BCR 15 +#define GCC_PCIE_2A_PHY_NOCSR_COM_PHY_BCR 16 +#define GCC_PCIE_2B_BCR 17 +#define GCC_PCIE_2B_LINK_DOWN_BCR 18 +#define GCC_PCIE_2B_NOCSR_COM_PHY_BCR 19 +#define GCC_PCIE_2B_PHY_BCR 20 +#define GCC_PCIE_2B_PHY_NOCSR_COM_PHY_BCR 21 +#define GCC_PCIE_3A_BCR 22 +#define GCC_PCIE_3A_LINK_DOWN_BCR 23 +#define GCC_PCIE_3A_NOCSR_COM_PHY_BCR 24 +#define GCC_PCIE_3A_PHY_BCR 25 +#define GCC_PCIE_3A_PHY_NOCSR_COM_PHY_BCR 26 +#define GCC_PCIE_3B_BCR 27 +#define GCC_PCIE_3B_LINK_DOWN_BCR 28 +#define GCC_PCIE_3B_NOCSR_COM_PHY_BCR 29 +#define GCC_PCIE_3B_PHY_BCR 30 +#define GCC_PCIE_3B_PHY_NOCSR_COM_PHY_BCR 31 +#define GCC_PCIE_4_BCR 32 +#define GCC_PCIE_4_LINK_DOWN_BCR 33 +#define GCC_PCIE_4_NOCSR_COM_PHY_BCR 34 +#define GCC_PCIE_4_PHY_BCR 35 +#define GCC_PCIE_4_PHY_NOCSR_COM_PHY_BCR 36 +#define GCC_PCIE_PHY_CFG_AHB_BCR 37 +#define GCC_PCIE_PHY_COM_BCR 38 +#define GCC_PCIE_RSCC_BCR 39 +#define GCC_QUSB2PHY_HS0_MP_BCR 40 +#define GCC_QUSB2PHY_HS1_MP_BCR 41 +#define GCC_QUSB2PHY_HS2_MP_BCR 42 +#define GCC_QUSB2PHY_HS3_MP_BCR 43 +#define GCC_QUSB2PHY_PRIM_BCR 44 +#define GCC_QUSB2PHY_SEC_BCR 45 +#define GCC_SDCC2_BCR 46 +#define GCC_SDCC4_BCR 47 +#define GCC_UFS_CARD_BCR 48 +#define GCC_UFS_PHY_BCR 49 +#define GCC_USB2_PHY_PRIM_BCR 50 +#define GCC_USB2_PHY_SEC_BCR 51 +#define GCC_USB30_MP_BCR 52 +#define GCC_USB30_PRIM_BCR 53 +#define GCC_USB30_SEC_BCR 54 +#define GCC_USB3_DP_PHY_PRIM_BCR 55 +#define GCC_USB3_DP_PHY_SEC_BCR 56 +#define GCC_USB3_PHY_PRIM_BCR 57 +#define GCC_USB3_PHY_SEC_BCR 58 +#define GCC_USB3_UNIPHY_MP0_BCR 59 +#define GCC_USB3_UNIPHY_MP1_BCR 60 +#define GCC_USB3PHY_PHY_PRIM_BCR 61 +#define GCC_USB3PHY_PHY_SEC_BCR 62 +#define GCC_USB3UNIPHY_PHY_MP0_BCR 63 +#define GCC_USB3UNIPHY_PHY_MP1_BCR 64 +#define GCC_USB4_1_BCR 65 +#define GCC_USB4_1_DP_PHY_PRIM_BCR 66 +#define GCC_USB4_1_DPPHY_AUX_BCR 67 +#define GCC_USB4_1_PHY_PRIM_BCR 68 +#define GCC_USB4_BCR 69 +#define GCC_USB4_DP_PHY_PRIM_BCR 70 +#define GCC_USB4_DPPHY_AUX_BCR 71 +#define GCC_USB4_PHY_PRIM_BCR 72 +#define GCC_USB4PHY_1_PHY_PRIM_BCR 73 +#define GCC_USB4PHY_PHY_PRIM_BCR 74 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 75 +#define GCC_VIDEO_BCR 76 +#define GCC_VIDEO_AXI0_CLK_ARES 77 +#define GCC_VIDEO_AXI1_CLK_ARES 78 + +/* GCC GDSCs */ +#define PCIE_0_TUNNEL_GDSC 0 +#define PCIE_1_TUNNEL_GDSC 1 +#define PCIE_2A_GDSC 2 +#define PCIE_2B_GDSC 3 +#define PCIE_3A_GDSC 4 +#define PCIE_3B_GDSC 5 +#define PCIE_4_GDSC 6 +#define UFS_CARD_GDSC 7 +#define UFS_PHY_GDSC 8 +#define USB30_MP_GDSC 9 +#define USB30_PRIM_GDSC 10 +#define USB30_SEC_GDSC 11 + +#endif diff --git a/include/dt-bindings/clock/qcom,gcc-sdm660.h b/include/dt-bindings/clock/qcom,gcc-sdm660.h index 468302282913..df8a6f3d367e 100644 --- a/include/dt-bindings/clock/qcom,gcc-sdm660.h +++ b/include/dt-bindings/clock/qcom,gcc-sdm660.h @@ -152,5 +152,6 @@ #define GCC_USB_20_BCR 6 #define GCC_USB_30_BCR 7 #define GCC_USB_PHY_CFG_AHB2PHY_BCR 8 +#define GCC_MSS_RESTART 9 #endif diff --git a/include/dt-bindings/clock/qcom,gcc-sdm845.h b/include/dt-bindings/clock/qcom,gcc-sdm845.h index 968fa65b9c42..d78b899263a2 100644 --- a/include/dt-bindings/clock/qcom,gcc-sdm845.h +++ b/include/dt-bindings/clock/qcom,gcc-sdm845.h @@ -199,6 +199,7 @@ #define GCC_QSPI_CNOC_PERIPH_AHB_CLK 189 #define GCC_LPASS_Q6_AXI_CLK 190 #define GCC_LPASS_SWAY_CLK 191 +#define GPLL6 192 /* GCC Resets */ #define GCC_MMSS_BCR 0 diff --git a/include/dt-bindings/clock/qcom,gcc-sdx55.h b/include/dt-bindings/clock/qcom,gcc-sdx55.h new file mode 100644 index 000000000000..fb9a5942f793 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-sdx55.h @@ -0,0 +1,117 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2020, Linaro Ltd. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SDX55_H +#define _DT_BINDINGS_CLK_QCOM_GCC_SDX55_H + +#define GPLL0 3 +#define GPLL0_OUT_EVEN 4 +#define GPLL4 5 +#define GPLL4_OUT_EVEN 6 +#define GPLL5 7 +#define GCC_AHB_PCIE_LINK_CLK 8 +#define GCC_BLSP1_AHB_CLK 9 +#define GCC_BLSP1_QUP1_I2C_APPS_CLK 10 +#define GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC 11 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK 12 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC 13 +#define GCC_BLSP1_QUP2_I2C_APPS_CLK 14 +#define GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC 15 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK 16 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC 17 +#define GCC_BLSP1_QUP3_I2C_APPS_CLK 18 +#define GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC 19 +#define GCC_BLSP1_QUP3_SPI_APPS_CLK 20 +#define GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC 21 +#define GCC_BLSP1_QUP4_I2C_APPS_CLK 22 +#define GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC 23 +#define GCC_BLSP1_QUP4_SPI_APPS_CLK 24 +#define GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC 25 +#define GCC_BLSP1_UART1_APPS_CLK 26 +#define GCC_BLSP1_UART1_APPS_CLK_SRC 27 +#define GCC_BLSP1_UART2_APPS_CLK 28 +#define GCC_BLSP1_UART2_APPS_CLK_SRC 29 +#define GCC_BLSP1_UART3_APPS_CLK 30 +#define GCC_BLSP1_UART3_APPS_CLK_SRC 31 +#define GCC_BLSP1_UART4_APPS_CLK 32 +#define GCC_BLSP1_UART4_APPS_CLK_SRC 33 +#define GCC_BOOT_ROM_AHB_CLK 34 +#define GCC_CE1_AHB_CLK 35 +#define GCC_CE1_AXI_CLK 36 +#define GCC_CE1_CLK 37 +#define GCC_CPUSS_AHB_CLK 38 +#define GCC_CPUSS_AHB_CLK_SRC 39 +#define GCC_CPUSS_GNOC_CLK 40 +#define GCC_CPUSS_RBCPR_CLK 41 +#define GCC_CPUSS_RBCPR_CLK_SRC 42 +#define GCC_EMAC_CLK_SRC 43 +#define GCC_EMAC_PTP_CLK_SRC 44 +#define GCC_ETH_AXI_CLK 45 +#define GCC_ETH_PTP_CLK 46 +#define GCC_ETH_RGMII_CLK 47 +#define GCC_ETH_SLAVE_AHB_CLK 48 +#define GCC_GP1_CLK 49 +#define GCC_GP1_CLK_SRC 50 +#define GCC_GP2_CLK 51 +#define GCC_GP2_CLK_SRC 52 +#define GCC_GP3_CLK 53 +#define GCC_GP3_CLK_SRC 54 +#define GCC_PCIE_0_CLKREF_CLK 55 +#define GCC_PCIE_AUX_CLK 56 +#define GCC_PCIE_AUX_PHY_CLK_SRC 57 +#define GCC_PCIE_CFG_AHB_CLK 58 +#define GCC_PCIE_MSTR_AXI_CLK 59 +#define GCC_PCIE_PIPE_CLK 60 +#define GCC_PCIE_RCHNG_PHY_CLK 61 +#define GCC_PCIE_RCHNG_PHY_CLK_SRC 62 +#define GCC_PCIE_SLEEP_CLK 63 +#define GCC_PCIE_SLV_AXI_CLK 64 +#define GCC_PCIE_SLV_Q2A_AXI_CLK 65 +#define GCC_PDM2_CLK 66 +#define GCC_PDM2_CLK_SRC 67 +#define GCC_PDM_AHB_CLK 68 +#define GCC_PDM_XO4_CLK 69 +#define GCC_SDCC1_AHB_CLK 70 +#define GCC_SDCC1_APPS_CLK 71 +#define GCC_SDCC1_APPS_CLK_SRC 72 +#define GCC_SYS_NOC_CPUSS_AHB_CLK 73 +#define GCC_USB30_MASTER_CLK 74 +#define GCC_USB30_MASTER_CLK_SRC 75 +#define GCC_USB30_MOCK_UTMI_CLK 76 +#define GCC_USB30_MOCK_UTMI_CLK_SRC 77 +#define GCC_USB30_MSTR_AXI_CLK 78 +#define GCC_USB30_SLEEP_CLK 79 +#define GCC_USB30_SLV_AHB_CLK 80 +#define GCC_USB3_PHY_AUX_CLK 81 +#define GCC_USB3_PHY_AUX_CLK_SRC 82 +#define GCC_USB3_PHY_PIPE_CLK 83 +#define GCC_USB3_PRIM_CLKREF_CLK 84 +#define GCC_USB_PHY_CFG_AHB2PHY_CLK 85 +#define GCC_XO_DIV4_CLK 86 +#define GCC_XO_PCIE_LINK_CLK 87 + +#define GCC_EMAC_BCR 0 +#define GCC_PCIE_BCR 1 +#define GCC_PCIE_LINK_DOWN_BCR 2 +#define GCC_PCIE_NOCSR_COM_PHY_BCR 3 +#define GCC_PCIE_PHY_BCR 4 +#define GCC_PCIE_PHY_CFG_AHB_BCR 5 +#define GCC_PCIE_PHY_COM_BCR 6 +#define GCC_PCIE_PHY_NOCSR_COM_PHY_BCR 7 +#define GCC_PDM_BCR 8 +#define GCC_QUSB2PHY_BCR 9 +#define GCC_TCSR_PCIE_BCR 10 +#define GCC_USB30_BCR 11 +#define GCC_USB3_PHY_BCR 12 +#define GCC_USB3PHY_PHY_BCR 13 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 14 + +/* GCC power domains */ +#define USB30_GDSC 0 +#define PCIE_GDSC 1 +#define EMAC_GDSC 2 + +#endif diff --git a/include/dt-bindings/clock/qcom,gcc-sdx65.h b/include/dt-bindings/clock/qcom,gcc-sdx65.h new file mode 100644 index 000000000000..75ecc9237d8f --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-sdx65.h @@ -0,0 +1,122 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SDX65_H +#define _DT_BINDINGS_CLK_QCOM_GCC_SDX65_H + +/* GCC clocks */ +#define GPLL0 0 +#define GPLL0_OUT_EVEN 1 +#define GCC_AHB_PCIE_LINK_CLK 2 +#define GCC_BLSP1_AHB_CLK 3 +#define GCC_BLSP1_QUP1_I2C_APPS_CLK 4 +#define GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC 5 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK 6 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC 7 +#define GCC_BLSP1_QUP2_I2C_APPS_CLK 8 +#define GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC 9 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK 10 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC 11 +#define GCC_BLSP1_QUP3_I2C_APPS_CLK 12 +#define GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC 13 +#define GCC_BLSP1_QUP3_SPI_APPS_CLK 14 +#define GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC 15 +#define GCC_BLSP1_QUP4_I2C_APPS_CLK 16 +#define GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC 17 +#define GCC_BLSP1_QUP4_SPI_APPS_CLK 18 +#define GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC 19 +#define GCC_BLSP1_SLEEP_CLK 20 +#define GCC_BLSP1_UART1_APPS_CLK 21 +#define GCC_BLSP1_UART1_APPS_CLK_SRC 22 +#define GCC_BLSP1_UART2_APPS_CLK 23 +#define GCC_BLSP1_UART2_APPS_CLK_SRC 24 +#define GCC_BLSP1_UART3_APPS_CLK 25 +#define GCC_BLSP1_UART3_APPS_CLK_SRC 26 +#define GCC_BLSP1_UART4_APPS_CLK 27 +#define GCC_BLSP1_UART4_APPS_CLK_SRC 28 +#define GCC_BOOT_ROM_AHB_CLK 29 +#define GCC_CPUSS_AHB_CLK 30 +#define GCC_CPUSS_AHB_CLK_SRC 31 +#define GCC_CPUSS_AHB_POSTDIV_CLK_SRC 32 +#define GCC_CPUSS_GNOC_CLK 33 +#define GCC_GP1_CLK 34 +#define GCC_GP1_CLK_SRC 35 +#define GCC_GP2_CLK 36 +#define GCC_GP2_CLK_SRC 37 +#define GCC_GP3_CLK 38 +#define GCC_GP3_CLK_SRC 39 +#define GCC_PCIE_0_CLKREF_EN 40 +#define GCC_PCIE_AUX_CLK 41 +#define GCC_PCIE_AUX_CLK_SRC 42 +#define GCC_PCIE_AUX_PHY_CLK_SRC 43 +#define GCC_PCIE_CFG_AHB_CLK 44 +#define GCC_PCIE_MSTR_AXI_CLK 45 +#define GCC_PCIE_PIPE_CLK 46 +#define GCC_PCIE_PIPE_CLK_SRC 47 +#define GCC_PCIE_RCHNG_PHY_CLK 48 +#define GCC_PCIE_RCHNG_PHY_CLK_SRC 49 +#define GCC_PCIE_SLEEP_CLK 50 +#define GCC_PCIE_SLV_AXI_CLK 51 +#define GCC_PCIE_SLV_Q2A_AXI_CLK 52 +#define GCC_PDM2_CLK 53 +#define GCC_PDM2_CLK_SRC 54 +#define GCC_PDM_AHB_CLK 55 +#define GCC_PDM_XO4_CLK 56 +#define GCC_RX1_USB2_CLKREF_EN 57 +#define GCC_SDCC1_AHB_CLK 58 +#define GCC_SDCC1_APPS_CLK 59 +#define GCC_SDCC1_APPS_CLK_SRC 60 +#define GCC_SPMI_FETCHER_AHB_CLK 61 +#define GCC_SPMI_FETCHER_CLK 62 +#define GCC_SPMI_FETCHER_CLK_SRC 63 +#define GCC_SYS_NOC_CPUSS_AHB_CLK 64 +#define GCC_USB30_MASTER_CLK 65 +#define GCC_USB30_MASTER_CLK_SRC 66 +#define GCC_USB30_MOCK_UTMI_CLK 67 +#define GCC_USB30_MOCK_UTMI_CLK_SRC 68 +#define GCC_USB30_MOCK_UTMI_POSTDIV_CLK_SRC 69 +#define GCC_USB30_MSTR_AXI_CLK 70 +#define GCC_USB30_SLEEP_CLK 71 +#define GCC_USB30_SLV_AHB_CLK 72 +#define GCC_USB3_PHY_AUX_CLK 73 +#define GCC_USB3_PHY_AUX_CLK_SRC 74 +#define GCC_USB3_PHY_PIPE_CLK 75 +#define GCC_USB3_PHY_PIPE_CLK_SRC 76 +#define GCC_USB3_PRIM_CLKREF_EN 77 +#define GCC_USB_PHY_CFG_AHB2PHY_CLK 78 +#define GCC_XO_DIV4_CLK 79 +#define GCC_XO_PCIE_LINK_CLK 80 + +/* GCC resets */ +#define GCC_BLSP1_QUP1_BCR 0 +#define GCC_BLSP1_QUP2_BCR 1 +#define GCC_BLSP1_QUP3_BCR 2 +#define GCC_BLSP1_QUP4_BCR 3 +#define GCC_BLSP1_UART1_BCR 4 +#define GCC_BLSP1_UART2_BCR 5 +#define GCC_BLSP1_UART3_BCR 6 +#define GCC_BLSP1_UART4_BCR 7 +#define GCC_PCIE_BCR 8 +#define GCC_PCIE_LINK_DOWN_BCR 9 +#define GCC_PCIE_NOCSR_COM_PHY_BCR 10 +#define GCC_PCIE_PHY_BCR 11 +#define GCC_PCIE_PHY_CFG_AHB_BCR 12 +#define GCC_PCIE_PHY_COM_BCR 13 +#define GCC_PCIE_PHY_NOCSR_COM_PHY_BCR 14 +#define GCC_PDM_BCR 15 +#define GCC_QUSB2PHY_BCR 16 +#define GCC_SDCC1_BCR 17 +#define GCC_SPMI_FETCHER_BCR 18 +#define GCC_TCSR_PCIE_BCR 19 +#define GCC_USB30_BCR 20 +#define GCC_USB3_PHY_BCR 21 +#define GCC_USB3PHY_PHY_BCR 22 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 23 + +/* GCC power domains */ +#define USB30_GDSC 0 +#define PCIE_GDSC 1 + +#endif diff --git a/include/dt-bindings/clock/qcom,gcc-sm6115.h b/include/dt-bindings/clock/qcom,gcc-sm6115.h new file mode 100644 index 000000000000..b91a7b460433 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-sm6115.h @@ -0,0 +1,201 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM6115_H +#define _DT_BINDINGS_CLK_QCOM_GCC_SM6115_H + +/* GCC clocks */ +#define GPLL0 0 +#define GPLL0_OUT_AUX2 1 +#define GPLL0_OUT_MAIN 2 +#define GPLL10 3 +#define GPLL10_OUT_MAIN 4 +#define GPLL11 5 +#define GPLL11_OUT_MAIN 6 +#define GPLL3 7 +#define GPLL4 8 +#define GPLL4_OUT_MAIN 9 +#define GPLL6 10 +#define GPLL6_OUT_MAIN 11 +#define GPLL7 12 +#define GPLL7_OUT_MAIN 13 +#define GPLL8 14 +#define GPLL8_OUT_MAIN 15 +#define GPLL9 16 +#define GPLL9_OUT_MAIN 17 +#define GCC_CAMSS_CSI0PHYTIMER_CLK 18 +#define GCC_CAMSS_CSI0PHYTIMER_CLK_SRC 19 +#define GCC_CAMSS_CSI1PHYTIMER_CLK 20 +#define GCC_CAMSS_CSI1PHYTIMER_CLK_SRC 21 +#define GCC_CAMSS_CSI2PHYTIMER_CLK 22 +#define GCC_CAMSS_CSI2PHYTIMER_CLK_SRC 23 +#define GCC_CAMSS_MCLK0_CLK 24 +#define GCC_CAMSS_MCLK0_CLK_SRC 25 +#define GCC_CAMSS_MCLK1_CLK 26 +#define GCC_CAMSS_MCLK1_CLK_SRC 27 +#define GCC_CAMSS_MCLK2_CLK 28 +#define GCC_CAMSS_MCLK2_CLK_SRC 29 +#define GCC_CAMSS_MCLK3_CLK 30 +#define GCC_CAMSS_MCLK3_CLK_SRC 31 +#define GCC_CAMSS_NRT_AXI_CLK 32 +#define GCC_CAMSS_OPE_AHB_CLK 33 +#define GCC_CAMSS_OPE_AHB_CLK_SRC 34 +#define GCC_CAMSS_OPE_CLK 35 +#define GCC_CAMSS_OPE_CLK_SRC 36 +#define GCC_CAMSS_RT_AXI_CLK 37 +#define GCC_CAMSS_TFE_0_CLK 38 +#define GCC_CAMSS_TFE_0_CLK_SRC 39 +#define GCC_CAMSS_TFE_0_CPHY_RX_CLK 40 +#define GCC_CAMSS_TFE_0_CSID_CLK 41 +#define GCC_CAMSS_TFE_0_CSID_CLK_SRC 42 +#define GCC_CAMSS_TFE_1_CLK 43 +#define GCC_CAMSS_TFE_1_CLK_SRC 44 +#define GCC_CAMSS_TFE_1_CPHY_RX_CLK 45 +#define GCC_CAMSS_TFE_1_CSID_CLK 46 +#define GCC_CAMSS_TFE_1_CSID_CLK_SRC 47 +#define GCC_CAMSS_TFE_2_CLK 48 +#define GCC_CAMSS_TFE_2_CLK_SRC 49 +#define GCC_CAMSS_TFE_2_CPHY_RX_CLK 50 +#define GCC_CAMSS_TFE_2_CSID_CLK 51 +#define GCC_CAMSS_TFE_2_CSID_CLK_SRC 52 +#define GCC_CAMSS_TFE_CPHY_RX_CLK_SRC 53 +#define GCC_CAMSS_TOP_AHB_CLK 54 +#define GCC_CAMSS_TOP_AHB_CLK_SRC 55 +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 56 +#define GCC_CPUSS_AHB_CLK 57 +#define GCC_CPUSS_GNOC_CLK 60 +#define GCC_DISP_AHB_CLK 61 +#define GCC_DISP_GPLL0_DIV_CLK_SRC 62 +#define GCC_DISP_HF_AXI_CLK 63 +#define GCC_DISP_THROTTLE_CORE_CLK 64 +#define GCC_DISP_XO_CLK 65 +#define GCC_GP1_CLK 66 +#define GCC_GP1_CLK_SRC 67 +#define GCC_GP2_CLK 68 +#define GCC_GP2_CLK_SRC 69 +#define GCC_GP3_CLK 70 +#define GCC_GP3_CLK_SRC 71 +#define GCC_GPU_CFG_AHB_CLK 72 +#define GCC_GPU_GPLL0_CLK_SRC 73 +#define GCC_GPU_GPLL0_DIV_CLK_SRC 74 +#define GCC_GPU_IREF_CLK 75 +#define GCC_GPU_MEMNOC_GFX_CLK 76 +#define GCC_GPU_SNOC_DVM_GFX_CLK 77 +#define GCC_GPU_THROTTLE_CORE_CLK 78 +#define GCC_GPU_THROTTLE_XO_CLK 79 +#define GCC_PDM2_CLK 80 +#define GCC_PDM2_CLK_SRC 81 +#define GCC_PDM_AHB_CLK 82 +#define GCC_PDM_XO4_CLK 83 +#define GCC_PRNG_AHB_CLK 84 +#define GCC_QMIP_CAMERA_NRT_AHB_CLK 85 +#define GCC_QMIP_CAMERA_RT_AHB_CLK 86 +#define GCC_QMIP_DISP_AHB_CLK 87 +#define GCC_QMIP_GPU_CFG_AHB_CLK 88 +#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 89 +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 90 +#define GCC_QUPV3_WRAP0_CORE_CLK 91 +#define GCC_QUPV3_WRAP0_S0_CLK 92 +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 93 +#define GCC_QUPV3_WRAP0_S1_CLK 94 +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 95 +#define GCC_QUPV3_WRAP0_S2_CLK 96 +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 97 +#define GCC_QUPV3_WRAP0_S3_CLK 98 +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 99 +#define GCC_QUPV3_WRAP0_S4_CLK 100 +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 101 +#define GCC_QUPV3_WRAP0_S5_CLK 102 +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 103 +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 104 +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 105 +#define GCC_SDCC1_AHB_CLK 106 +#define GCC_SDCC1_APPS_CLK 107 +#define GCC_SDCC1_APPS_CLK_SRC 108 +#define GCC_SDCC1_ICE_CORE_CLK 109 +#define GCC_SDCC1_ICE_CORE_CLK_SRC 110 +#define GCC_SDCC2_AHB_CLK 111 +#define GCC_SDCC2_APPS_CLK 112 +#define GCC_SDCC2_APPS_CLK_SRC 113 +#define GCC_SYS_NOC_CPUSS_AHB_CLK 114 +#define GCC_SYS_NOC_UFS_PHY_AXI_CLK 115 +#define GCC_SYS_NOC_USB3_PRIM_AXI_CLK 116 +#define GCC_UFS_PHY_AHB_CLK 117 +#define GCC_UFS_PHY_AXI_CLK 118 +#define GCC_UFS_PHY_AXI_CLK_SRC 119 +#define GCC_UFS_PHY_ICE_CORE_CLK 120 +#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 121 +#define GCC_UFS_PHY_PHY_AUX_CLK 122 +#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 123 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 124 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 125 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK 126 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 127 +#define GCC_USB30_PRIM_MASTER_CLK 128 +#define GCC_USB30_PRIM_MASTER_CLK_SRC 129 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 130 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 131 +#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 132 +#define GCC_USB30_PRIM_SLEEP_CLK 133 +#define GCC_USB3_PRIM_CLKREF_CLK 134 +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 135 +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 136 +#define GCC_USB3_PRIM_PHY_PIPE_CLK 137 +#define GCC_VCODEC0_AXI_CLK 138 +#define GCC_VENUS_AHB_CLK 139 +#define GCC_VENUS_CTL_AXI_CLK 140 +#define GCC_VIDEO_AHB_CLK 141 +#define GCC_VIDEO_AXI0_CLK 142 +#define GCC_VIDEO_THROTTLE_CORE_CLK 143 +#define GCC_VIDEO_VCODEC0_SYS_CLK 144 +#define GCC_VIDEO_VENUS_CLK_SRC 145 +#define GCC_VIDEO_VENUS_CTL_CLK 146 +#define GCC_VIDEO_XO_CLK 147 +#define GCC_AHB2PHY_CSI_CLK 148 +#define GCC_AHB2PHY_USB_CLK 149 +#define GCC_BIMC_GPU_AXI_CLK 150 +#define GCC_BOOT_ROM_AHB_CLK 151 +#define GCC_CAM_THROTTLE_NRT_CLK 152 +#define GCC_CAM_THROTTLE_RT_CLK 153 +#define GCC_CAMERA_AHB_CLK 154 +#define GCC_CAMERA_XO_CLK 155 +#define GCC_CAMSS_AXI_CLK 156 +#define GCC_CAMSS_AXI_CLK_SRC 157 +#define GCC_CAMSS_CAMNOC_ATB_CLK 158 +#define GCC_CAMSS_CAMNOC_NTS_XO_CLK 159 +#define GCC_CAMSS_CCI_0_CLK 160 +#define GCC_CAMSS_CCI_CLK_SRC 161 +#define GCC_CAMSS_CPHY_0_CLK 162 +#define GCC_CAMSS_CPHY_1_CLK 163 +#define GCC_CAMSS_CPHY_2_CLK 164 +#define GCC_UFS_CLKREF_CLK 165 +#define GCC_DISP_GPLL0_CLK_SRC 166 + +/* GCC resets */ +#define GCC_QUSB2PHY_PRIM_BCR 0 +#define GCC_QUSB2PHY_SEC_BCR 1 +#define GCC_SDCC1_BCR 2 +#define GCC_UFS_PHY_BCR 3 +#define GCC_USB30_PRIM_BCR 4 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 5 +#define GCC_VCODEC0_BCR 6 +#define GCC_VENUS_BCR 7 +#define GCC_VIDEO_INTERFACE_BCR 8 +#define GCC_USB3PHY_PHY_PRIM_SP0_BCR 9 +#define GCC_USB3_PHY_PRIM_SP0_BCR 10 +#define GCC_SDCC2_BCR 11 + +/* Indexes for GDSCs */ +#define GCC_CAMSS_TOP_GDSC 0 +#define GCC_UFS_PHY_GDSC 1 +#define GCC_USB30_PRIM_GDSC 2 +#define GCC_VCODEC0_GDSC 3 +#define GCC_VENUS_GDSC 4 +#define HLOS1_VOTE_TURING_MMU_TBU1_GDSC 5 +#define HLOS1_VOTE_TURING_MMU_TBU0_GDSC 6 +#define HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC 7 +#define HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC 8 + +#endif diff --git a/include/dt-bindings/clock/qcom,gcc-sm6125.h b/include/dt-bindings/clock/qcom,gcc-sm6125.h new file mode 100644 index 000000000000..08ea18086824 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-sm6125.h @@ -0,0 +1,240 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM6125_H +#define _DT_BINDINGS_CLK_QCOM_GCC_SM6125_H + +#define GPLL0_OUT_AUX2 0 +#define GPLL0_OUT_MAIN 1 +#define GPLL6_OUT_MAIN 2 +#define GPLL7_OUT_MAIN 3 +#define GPLL8_OUT_MAIN 4 +#define GPLL9_OUT_MAIN 5 +#define GPLL0_OUT_EARLY 6 +#define GPLL3_OUT_EARLY 7 +#define GPLL4_OUT_MAIN 8 +#define GPLL5_OUT_MAIN 9 +#define GPLL6_OUT_EARLY 10 +#define GPLL7_OUT_EARLY 11 +#define GPLL8_OUT_EARLY 12 +#define GPLL9_OUT_EARLY 13 +#define GCC_AHB2PHY_CSI_CLK 14 +#define GCC_AHB2PHY_USB_CLK 15 +#define GCC_APC_VS_CLK 16 +#define GCC_BOOT_ROM_AHB_CLK 17 +#define GCC_CAMERA_AHB_CLK 18 +#define GCC_CAMERA_XO_CLK 19 +#define GCC_CAMSS_AHB_CLK_SRC 20 +#define GCC_CAMSS_CCI_AHB_CLK 21 +#define GCC_CAMSS_CCI_CLK 22 +#define GCC_CAMSS_CCI_CLK_SRC 23 +#define GCC_CAMSS_CPHY_CSID0_CLK 24 +#define GCC_CAMSS_CPHY_CSID1_CLK 25 +#define GCC_CAMSS_CPHY_CSID2_CLK 26 +#define GCC_CAMSS_CPHY_CSID3_CLK 27 +#define GCC_CAMSS_CPP_AHB_CLK 28 +#define GCC_CAMSS_CPP_AXI_CLK 29 +#define GCC_CAMSS_CPP_CLK 30 +#define GCC_CAMSS_CPP_CLK_SRC 31 +#define GCC_CAMSS_CPP_VBIF_AHB_CLK 32 +#define GCC_CAMSS_CSI0_AHB_CLK 33 +#define GCC_CAMSS_CSI0_CLK 34 +#define GCC_CAMSS_CSI0_CLK_SRC 35 +#define GCC_CAMSS_CSI0PHYTIMER_CLK 36 +#define GCC_CAMSS_CSI0PHYTIMER_CLK_SRC 37 +#define GCC_CAMSS_CSI0PIX_CLK 38 +#define GCC_CAMSS_CSI0RDI_CLK 39 +#define GCC_CAMSS_CSI1_AHB_CLK 40 +#define GCC_CAMSS_CSI1_CLK 41 +#define GCC_CAMSS_CSI1_CLK_SRC 42 +#define GCC_CAMSS_CSI1PHYTIMER_CLK 43 +#define GCC_CAMSS_CSI1PHYTIMER_CLK_SRC 44 +#define GCC_CAMSS_CSI1PIX_CLK 45 +#define GCC_CAMSS_CSI1RDI_CLK 46 +#define GCC_CAMSS_CSI2_AHB_CLK 47 +#define GCC_CAMSS_CSI2_CLK 48 +#define GCC_CAMSS_CSI2_CLK_SRC 49 +#define GCC_CAMSS_CSI2PHYTIMER_CLK 50 +#define GCC_CAMSS_CSI2PHYTIMER_CLK_SRC 51 +#define GCC_CAMSS_CSI2PIX_CLK 52 +#define GCC_CAMSS_CSI2RDI_CLK 53 +#define GCC_CAMSS_CSI3_AHB_CLK 54 +#define GCC_CAMSS_CSI3_CLK 55 +#define GCC_CAMSS_CSI3_CLK_SRC 56 +#define GCC_CAMSS_CSI3PIX_CLK 57 +#define GCC_CAMSS_CSI3RDI_CLK 58 +#define GCC_CAMSS_CSI_VFE0_CLK 59 +#define GCC_CAMSS_CSI_VFE1_CLK 60 +#define GCC_CAMSS_CSIPHY0_CLK 61 +#define GCC_CAMSS_CSIPHY1_CLK 62 +#define GCC_CAMSS_CSIPHY2_CLK 63 +#define GCC_CAMSS_CSIPHY_CLK_SRC 64 +#define GCC_CAMSS_GP0_CLK 65 +#define GCC_CAMSS_GP0_CLK_SRC 66 +#define GCC_CAMSS_GP1_CLK 67 +#define GCC_CAMSS_GP1_CLK_SRC 68 +#define GCC_CAMSS_ISPIF_AHB_CLK 69 +#define GCC_CAMSS_JPEG_AHB_CLK 70 +#define GCC_CAMSS_JPEG_AXI_CLK 71 +#define GCC_CAMSS_JPEG_CLK 72 +#define GCC_CAMSS_JPEG_CLK_SRC 73 +#define GCC_CAMSS_MCLK0_CLK 74 +#define GCC_CAMSS_MCLK0_CLK_SRC 75 +#define GCC_CAMSS_MCLK1_CLK 76 +#define GCC_CAMSS_MCLK1_CLK_SRC 77 +#define GCC_CAMSS_MCLK2_CLK 78 +#define GCC_CAMSS_MCLK2_CLK_SRC 79 +#define GCC_CAMSS_MCLK3_CLK 80 +#define GCC_CAMSS_MCLK3_CLK_SRC 81 +#define GCC_CAMSS_MICRO_AHB_CLK 82 +#define GCC_CAMSS_THROTTLE_NRT_AXI_CLK 83 +#define GCC_CAMSS_THROTTLE_RT_AXI_CLK 84 +#define GCC_CAMSS_TOP_AHB_CLK 85 +#define GCC_CAMSS_VFE0_AHB_CLK 86 +#define GCC_CAMSS_VFE0_CLK 87 +#define GCC_CAMSS_VFE0_CLK_SRC 88 +#define GCC_CAMSS_VFE0_STREAM_CLK 89 +#define GCC_CAMSS_VFE1_AHB_CLK 90 +#define GCC_CAMSS_VFE1_CLK 91 +#define GCC_CAMSS_VFE1_CLK_SRC 92 +#define GCC_CAMSS_VFE1_STREAM_CLK 93 +#define GCC_CAMSS_VFE_TSCTR_CLK 94 +#define GCC_CAMSS_VFE_VBIF_AHB_CLK 95 +#define GCC_CAMSS_VFE_VBIF_AXI_CLK 96 +#define GCC_CE1_AHB_CLK 97 +#define GCC_CE1_AXI_CLK 98 +#define GCC_CE1_CLK 99 +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 100 +#define GCC_CPUSS_GNOC_CLK 101 +#define GCC_DISP_AHB_CLK 102 +#define GCC_DISP_GPLL0_DIV_CLK_SRC 103 +#define GCC_DISP_HF_AXI_CLK 104 +#define GCC_DISP_THROTTLE_CORE_CLK 105 +#define GCC_DISP_XO_CLK 106 +#define GCC_GP1_CLK 107 +#define GCC_GP1_CLK_SRC 108 +#define GCC_GP2_CLK 109 +#define GCC_GP2_CLK_SRC 110 +#define GCC_GP3_CLK 111 +#define GCC_GP3_CLK_SRC 112 +#define GCC_GPU_CFG_AHB_CLK 113 +#define GCC_GPU_GPLL0_CLK_SRC 114 +#define GCC_GPU_GPLL0_DIV_CLK_SRC 115 +#define GCC_GPU_MEMNOC_GFX_CLK 116 +#define GCC_GPU_SNOC_DVM_GFX_CLK 117 +#define GCC_GPU_THROTTLE_CORE_CLK 118 +#define GCC_GPU_THROTTLE_XO_CLK 119 +#define GCC_MSS_VS_CLK 120 +#define GCC_PDM2_CLK 121 +#define GCC_PDM2_CLK_SRC 122 +#define GCC_PDM_AHB_CLK 123 +#define GCC_PDM_XO4_CLK 124 +#define GCC_PRNG_AHB_CLK 125 +#define GCC_QMIP_CAMERA_NRT_AHB_CLK 126 +#define GCC_QMIP_CAMERA_RT_AHB_CLK 127 +#define GCC_QMIP_DISP_AHB_CLK 128 +#define GCC_QMIP_GPU_CFG_AHB_CLK 129 +#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 130 +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 131 +#define GCC_QUPV3_WRAP0_CORE_CLK 132 +#define GCC_QUPV3_WRAP0_S0_CLK 133 +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 134 +#define GCC_QUPV3_WRAP0_S1_CLK 135 +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 136 +#define GCC_QUPV3_WRAP0_S2_CLK 137 +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 138 +#define GCC_QUPV3_WRAP0_S3_CLK 139 +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 140 +#define GCC_QUPV3_WRAP0_S4_CLK 141 +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 142 +#define GCC_QUPV3_WRAP0_S5_CLK 143 +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 144 +#define GCC_QUPV3_WRAP1_CORE_2X_CLK 145 +#define GCC_QUPV3_WRAP1_CORE_CLK 146 +#define GCC_QUPV3_WRAP1_S0_CLK 147 +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 148 +#define GCC_QUPV3_WRAP1_S1_CLK 149 +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 150 +#define GCC_QUPV3_WRAP1_S2_CLK 151 +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 152 +#define GCC_QUPV3_WRAP1_S3_CLK 153 +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 154 +#define GCC_QUPV3_WRAP1_S4_CLK 155 +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 156 +#define GCC_QUPV3_WRAP1_S5_CLK 157 +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 158 +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 159 +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 160 +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 161 +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 162 +#define GCC_SDCC1_AHB_CLK 163 +#define GCC_SDCC1_APPS_CLK 164 +#define GCC_SDCC1_APPS_CLK_SRC 165 +#define GCC_SDCC1_ICE_CORE_CLK 166 +#define GCC_SDCC1_ICE_CORE_CLK_SRC 167 +#define GCC_SDCC2_AHB_CLK 168 +#define GCC_SDCC2_APPS_CLK 169 +#define GCC_SDCC2_APPS_CLK_SRC 170 +#define GCC_SYS_NOC_CPUSS_AHB_CLK 171 +#define GCC_SYS_NOC_UFS_PHY_AXI_CLK 172 +#define GCC_SYS_NOC_USB3_PRIM_AXI_CLK 173 +#define GCC_UFS_PHY_AHB_CLK 174 +#define GCC_UFS_PHY_AXI_CLK 175 +#define GCC_UFS_PHY_AXI_CLK_SRC 176 +#define GCC_UFS_PHY_ICE_CORE_CLK 177 +#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 178 +#define GCC_UFS_PHY_PHY_AUX_CLK 179 +#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 180 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 181 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 182 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK 183 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 184 +#define GCC_USB30_PRIM_MASTER_CLK 185 +#define GCC_USB30_PRIM_MASTER_CLK_SRC 186 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 187 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 188 +#define GCC_USB30_PRIM_SLEEP_CLK 189 +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 190 +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 191 +#define GCC_USB3_PRIM_PHY_PIPE_CLK 192 +#define GCC_VDDA_VS_CLK 193 +#define GCC_VDDCX_VS_CLK 194 +#define GCC_VDDMX_VS_CLK 195 +#define GCC_VIDEO_AHB_CLK 196 +#define GCC_VIDEO_AXI0_CLK 197 +#define GCC_VIDEO_THROTTLE_CORE_CLK 198 +#define GCC_VIDEO_XO_CLK 199 +#define GCC_VS_CTRL_AHB_CLK 200 +#define GCC_VS_CTRL_CLK 201 +#define GCC_VS_CTRL_CLK_SRC 202 +#define GCC_VSENSOR_CLK_SRC 203 +#define GCC_WCSS_VS_CLK 204 +#define GCC_USB3_PRIM_CLKREF_CLK 205 +#define GCC_SYS_NOC_COMPUTE_SF_AXI_CLK 206 +#define GCC_BIMC_GPU_AXI_CLK 207 +#define GCC_UFS_MEM_CLKREF_CLK 208 + +/* GDSCs */ +#define USB30_PRIM_GDSC 0 +#define UFS_PHY_GDSC 1 +#define CAMSS_VFE0_GDSC 2 +#define CAMSS_VFE1_GDSC 3 +#define CAMSS_TOP_GDSC 4 +#define CAM_CPP_GDSC 5 +#define HLOS1_VOTE_TURING_MMU_TBU1_GDSC 6 +#define HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC 7 +#define HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC 8 +#define HLOS1_VOTE_TURING_MMU_TBU0_GDSC 9 + +#define GCC_QUSB2PHY_PRIM_BCR 0 +#define GCC_QUSB2PHY_SEC_BCR 1 +#define GCC_UFS_PHY_BCR 2 +#define GCC_USB30_PRIM_BCR 3 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 4 +#define GCC_USB3_PHY_PRIM_SP0_BCR 5 +#define GCC_USB3PHY_PHY_PRIM_SP0_BCR 6 +#define GCC_CAMSS_MICRO_BCR 7 + +#endif diff --git a/include/dt-bindings/clock/qcom,gcc-sm6350.h b/include/dt-bindings/clock/qcom,gcc-sm6350.h new file mode 100644 index 000000000000..ba584ca33c39 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-sm6350.h @@ -0,0 +1,178 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM6350_H +#define _DT_BINDINGS_CLK_QCOM_GCC_SM6350_H + +/* GCC clocks */ +#define GPLL0 0 +#define GPLL0_OUT_EVEN 1 +#define GPLL0_OUT_ODD 2 +#define GPLL6 3 +#define GPLL6_OUT_EVEN 4 +#define GPLL7 5 +#define GCC_AGGRE_CNOC_PERIPH_CENTER_AHB_CLK 6 +#define GCC_AGGRE_NOC_CENTER_AHB_CLK 7 +#define GCC_AGGRE_NOC_PCIE_SF_AXI_CLK 8 +#define GCC_AGGRE_NOC_PCIE_TBU_CLK 9 +#define GCC_AGGRE_NOC_WLAN_AXI_CLK 10 +#define GCC_AGGRE_UFS_PHY_AXI_CLK 11 +#define GCC_AGGRE_USB3_PRIM_AXI_CLK 12 +#define GCC_BOOT_ROM_AHB_CLK 13 +#define GCC_CAMERA_AHB_CLK 14 +#define GCC_CAMERA_AXI_CLK 15 +#define GCC_CAMERA_THROTTLE_NRT_AXI_CLK 16 +#define GCC_CAMERA_THROTTLE_RT_AXI_CLK 17 +#define GCC_CAMERA_XO_CLK 18 +#define GCC_CE1_AHB_CLK 19 +#define GCC_CE1_AXI_CLK 20 +#define GCC_CE1_CLK 21 +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 22 +#define GCC_CPUSS_AHB_CLK 23 +#define GCC_CPUSS_AHB_CLK_SRC 24 +#define GCC_CPUSS_AHB_DIV_CLK_SRC 25 +#define GCC_CPUSS_GNOC_CLK 26 +#define GCC_CPUSS_RBCPR_CLK 27 +#define GCC_DDRSS_GPU_AXI_CLK 28 +#define GCC_DISP_AHB_CLK 29 +#define GCC_DISP_AXI_CLK 30 +#define GCC_DISP_CC_SLEEP_CLK 31 +#define GCC_DISP_CC_XO_CLK 32 +#define GCC_DISP_GPLL0_CLK 33 +#define GCC_DISP_THROTTLE_AXI_CLK 34 +#define GCC_DISP_XO_CLK 35 +#define GCC_GP1_CLK 36 +#define GCC_GP1_CLK_SRC 37 +#define GCC_GP2_CLK 38 +#define GCC_GP2_CLK_SRC 39 +#define GCC_GP3_CLK 40 +#define GCC_GP3_CLK_SRC 41 +#define GCC_GPU_CFG_AHB_CLK 42 +#define GCC_GPU_GPLL0_CLK 43 +#define GCC_GPU_GPLL0_DIV_CLK 44 +#define GCC_GPU_MEMNOC_GFX_CLK 45 +#define GCC_GPU_SNOC_DVM_GFX_CLK 46 +#define GCC_NPU_AXI_CLK 47 +#define GCC_NPU_BWMON_AXI_CLK 48 +#define GCC_NPU_BWMON_DMA_CFG_AHB_CLK 49 +#define GCC_NPU_BWMON_DSP_CFG_AHB_CLK 50 +#define GCC_NPU_CFG_AHB_CLK 51 +#define GCC_NPU_DMA_CLK 52 +#define GCC_NPU_GPLL0_CLK 53 +#define GCC_NPU_GPLL0_DIV_CLK 54 +#define GCC_PCIE_0_AUX_CLK 55 +#define GCC_PCIE_0_AUX_CLK_SRC 56 +#define GCC_PCIE_0_CFG_AHB_CLK 57 +#define GCC_PCIE_0_MSTR_AXI_CLK 58 +#define GCC_PCIE_0_PIPE_CLK 59 +#define GCC_PCIE_0_SLV_AXI_CLK 60 +#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 61 +#define GCC_PCIE_PHY_RCHNG_CLK 62 +#define GCC_PCIE_PHY_RCHNG_CLK_SRC 63 +#define GCC_PDM2_CLK 64 +#define GCC_PDM2_CLK_SRC 65 +#define GCC_PDM_AHB_CLK 66 +#define GCC_PDM_XO4_CLK 67 +#define GCC_PRNG_AHB_CLK 68 +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 69 +#define GCC_QUPV3_WRAP0_CORE_CLK 70 +#define GCC_QUPV3_WRAP0_S0_CLK 71 +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 72 +#define GCC_QUPV3_WRAP0_S1_CLK 73 +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 74 +#define GCC_QUPV3_WRAP0_S2_CLK 75 +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 76 +#define GCC_QUPV3_WRAP0_S3_CLK 77 +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 78 +#define GCC_QUPV3_WRAP0_S4_CLK 79 +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 80 +#define GCC_QUPV3_WRAP0_S5_CLK 81 +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 82 +#define GCC_QUPV3_WRAP1_CORE_2X_CLK 83 +#define GCC_QUPV3_WRAP1_CORE_CLK 84 +#define GCC_QUPV3_WRAP1_S0_CLK 85 +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 86 +#define GCC_QUPV3_WRAP1_S1_CLK 87 +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 88 +#define GCC_QUPV3_WRAP1_S2_CLK 89 +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 90 +#define GCC_QUPV3_WRAP1_S3_CLK 91 +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 92 +#define GCC_QUPV3_WRAP1_S4_CLK 93 +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 94 +#define GCC_QUPV3_WRAP1_S5_CLK 95 +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 96 +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 97 +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 98 +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 99 +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 100 +#define GCC_SDCC1_AHB_CLK 101 +#define GCC_SDCC1_APPS_CLK 102 +#define GCC_SDCC1_APPS_CLK_SRC 103 +#define GCC_SDCC1_ICE_CORE_CLK 104 +#define GCC_SDCC1_ICE_CORE_CLK_SRC 105 +#define GCC_SDCC2_AHB_CLK 106 +#define GCC_SDCC2_APPS_CLK 107 +#define GCC_SDCC2_APPS_CLK_SRC 108 +#define GCC_SYS_NOC_CPUSS_AHB_CLK 109 +#define GCC_UFS_MEM_CLKREF_CLK 110 +#define GCC_UFS_PHY_AHB_CLK 111 +#define GCC_UFS_PHY_AXI_CLK 112 +#define GCC_UFS_PHY_AXI_CLK_SRC 113 +#define GCC_UFS_PHY_ICE_CORE_CLK 114 +#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 115 +#define GCC_UFS_PHY_PHY_AUX_CLK 116 +#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 117 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 118 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 119 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 120 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK 121 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 122 +#define GCC_USB30_PRIM_MASTER_CLK 123 +#define GCC_USB30_PRIM_MASTER_CLK_SRC 124 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 125 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 126 +#define GCC_USB30_PRIM_MOCK_UTMI_DIV_CLK_SRC 127 +#define GCC_USB3_PRIM_CLKREF_CLK 128 +#define GCC_USB30_PRIM_SLEEP_CLK 129 +#define GCC_USB3_PRIM_PHY_AUX_CLK 130 +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 131 +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 132 +#define GCC_USB3_PRIM_PHY_PIPE_CLK 133 +#define GCC_VIDEO_AHB_CLK 134 +#define GCC_VIDEO_AXI_CLK 135 +#define GCC_VIDEO_THROTTLE_AXI_CLK 136 +#define GCC_VIDEO_XO_CLK 137 +#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 138 +#define GCC_UFS_PHY_AXI_HW_CTL_CLK 139 +#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 140 +#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 141 +#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 142 +#define GCC_RX5_PCIE_CLKREF_CLK 143 +#define GCC_GPU_GPLL0_MAIN_DIV_CLK_SRC 144 +#define GCC_NPU_PLL0_MAIN_DIV_CLK_SRC 145 + +/* GCC resets */ +#define GCC_QUSB2PHY_PRIM_BCR 0 +#define GCC_QUSB2PHY_SEC_BCR 1 +#define GCC_SDCC1_BCR 2 +#define GCC_SDCC2_BCR 3 +#define GCC_UFS_PHY_BCR 4 +#define GCC_USB30_PRIM_BCR 5 +#define GCC_PCIE_0_BCR 6 +#define GCC_PCIE_0_PHY_BCR 7 +#define GCC_QUPV3_WRAPPER_0_BCR 8 +#define GCC_QUPV3_WRAPPER_1_BCR 9 +#define GCC_USB3_PHY_PRIM_BCR 10 +#define GCC_USB3_DP_PHY_PRIM_BCR 11 + +/* GCC GDSCs */ +#define USB30_PRIM_GDSC 0 +#define UFS_PHY_GDSC 1 +#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 2 +#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 3 + +#endif diff --git a/include/dt-bindings/clock/qcom,gcc-sm8150.h b/include/dt-bindings/clock/qcom,gcc-sm8150.h index 90d60ef94c64..dfefd5e8bf6e 100644 --- a/include/dt-bindings/clock/qcom,gcc-sm8150.h +++ b/include/dt-bindings/clock/qcom,gcc-sm8150.h @@ -240,4 +240,13 @@ #define GCC_USB30_SEC_BCR 27 #define GCC_USB_PHY_CFG_AHB2PHY_BCR 28 +/* GCC GDSCRs */ +#define PCIE_0_GDSC 0 +#define PCIE_1_GDSC 1 +#define UFS_CARD_GDSC 2 +#define UFS_PHY_GDSC 3 +#define USB30_PRIM_GDSC 4 +#define USB30_SEC_GDSC 5 +#define EMAC_GDSC 6 + #endif diff --git a/include/dt-bindings/clock/qcom,gcc-sm8250.h b/include/dt-bindings/clock/qcom,gcc-sm8250.h new file mode 100644 index 000000000000..7b7abe327e37 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-sm8250.h @@ -0,0 +1,271 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM8250_H +#define _DT_BINDINGS_CLK_QCOM_GCC_SM8250_H + +/* GCC clocks */ +#define GPLL0 0 +#define GPLL0_OUT_EVEN 1 +#define GPLL4 2 +#define GPLL9 3 +#define GCC_AGGRE_NOC_PCIE_TBU_CLK 4 +#define GCC_AGGRE_UFS_CARD_AXI_CLK 5 +#define GCC_AGGRE_UFS_PHY_AXI_CLK 6 +#define GCC_AGGRE_USB3_PRIM_AXI_CLK 7 +#define GCC_AGGRE_USB3_SEC_AXI_CLK 8 +#define GCC_BOOT_ROM_AHB_CLK 9 +#define GCC_CAMERA_AHB_CLK 10 +#define GCC_CAMERA_HF_AXI_CLK 11 +#define GCC_CAMERA_SF_AXI_CLK 12 +#define GCC_CAMERA_XO_CLK 13 +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 14 +#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 15 +#define GCC_CPUSS_AHB_CLK 16 +#define GCC_CPUSS_AHB_CLK_SRC 17 +#define GCC_CPUSS_AHB_POSTDIV_CLK_SRC 18 +#define GCC_CPUSS_DVM_BUS_CLK 19 +#define GCC_CPUSS_RBCPR_CLK 20 +#define GCC_DDRSS_GPU_AXI_CLK 21 +#define GCC_DDRSS_PCIE_SF_TBU_CLK 22 +#define GCC_DISP_AHB_CLK 23 +#define GCC_DISP_HF_AXI_CLK 24 +#define GCC_DISP_SF_AXI_CLK 25 +#define GCC_DISP_XO_CLK 26 +#define GCC_GP1_CLK 27 +#define GCC_GP1_CLK_SRC 28 +#define GCC_GP2_CLK 29 +#define GCC_GP2_CLK_SRC 30 +#define GCC_GP3_CLK 31 +#define GCC_GP3_CLK_SRC 32 +#define GCC_GPU_CFG_AHB_CLK 33 +#define GCC_GPU_GPLL0_CLK_SRC 34 +#define GCC_GPU_GPLL0_DIV_CLK_SRC 35 +#define GCC_GPU_IREF_EN 36 +#define GCC_GPU_MEMNOC_GFX_CLK 37 +#define GCC_GPU_SNOC_DVM_GFX_CLK 38 +#define GCC_NPU_AXI_CLK 39 +#define GCC_NPU_BWMON_AXI_CLK 40 +#define GCC_NPU_BWMON_CFG_AHB_CLK 41 +#define GCC_NPU_CFG_AHB_CLK 42 +#define GCC_NPU_DMA_CLK 43 +#define GCC_NPU_GPLL0_CLK_SRC 44 +#define GCC_NPU_GPLL0_DIV_CLK_SRC 45 +#define GCC_PCIE0_PHY_REFGEN_CLK 46 +#define GCC_PCIE1_PHY_REFGEN_CLK 47 +#define GCC_PCIE2_PHY_REFGEN_CLK 48 +#define GCC_PCIE_0_AUX_CLK 49 +#define GCC_PCIE_0_AUX_CLK_SRC 50 +#define GCC_PCIE_0_CFG_AHB_CLK 51 +#define GCC_PCIE_0_MSTR_AXI_CLK 52 +#define GCC_PCIE_0_PIPE_CLK 53 +#define GCC_PCIE_0_SLV_AXI_CLK 54 +#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 55 +#define GCC_PCIE_1_AUX_CLK 56 +#define GCC_PCIE_1_AUX_CLK_SRC 57 +#define GCC_PCIE_1_CFG_AHB_CLK 58 +#define GCC_PCIE_1_MSTR_AXI_CLK 59 +#define GCC_PCIE_1_PIPE_CLK 60 +#define GCC_PCIE_1_SLV_AXI_CLK 61 +#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 62 +#define GCC_PCIE_2_AUX_CLK 63 +#define GCC_PCIE_2_AUX_CLK_SRC 64 +#define GCC_PCIE_2_CFG_AHB_CLK 65 +#define GCC_PCIE_2_MSTR_AXI_CLK 66 +#define GCC_PCIE_2_PIPE_CLK 67 +#define GCC_PCIE_2_SLV_AXI_CLK 68 +#define GCC_PCIE_2_SLV_Q2A_AXI_CLK 69 +#define GCC_PCIE_MDM_CLKREF_EN 70 +#define GCC_PCIE_PHY_AUX_CLK 71 +#define GCC_PCIE_PHY_REFGEN_CLK_SRC 72 +#define GCC_PCIE_WIFI_CLKREF_EN 73 +#define GCC_PCIE_WIGIG_CLKREF_EN 74 +#define GCC_PDM2_CLK 75 +#define GCC_PDM2_CLK_SRC 76 +#define GCC_PDM_AHB_CLK 77 +#define GCC_PDM_XO4_CLK 78 +#define GCC_PRNG_AHB_CLK 79 +#define GCC_QMIP_CAMERA_NRT_AHB_CLK 80 +#define GCC_QMIP_CAMERA_RT_AHB_CLK 81 +#define GCC_QMIP_DISP_AHB_CLK 82 +#define GCC_QMIP_VIDEO_CVP_AHB_CLK 83 +#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 84 +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 85 +#define GCC_QUPV3_WRAP0_CORE_CLK 86 +#define GCC_QUPV3_WRAP0_S0_CLK 87 +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 88 +#define GCC_QUPV3_WRAP0_S1_CLK 89 +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 90 +#define GCC_QUPV3_WRAP0_S2_CLK 91 +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 92 +#define GCC_QUPV3_WRAP0_S3_CLK 93 +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 94 +#define GCC_QUPV3_WRAP0_S4_CLK 95 +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 96 +#define GCC_QUPV3_WRAP0_S5_CLK 97 +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 98 +#define GCC_QUPV3_WRAP0_S6_CLK 99 +#define GCC_QUPV3_WRAP0_S6_CLK_SRC 100 +#define GCC_QUPV3_WRAP0_S7_CLK 101 +#define GCC_QUPV3_WRAP0_S7_CLK_SRC 102 +#define GCC_QUPV3_WRAP1_CORE_2X_CLK 103 +#define GCC_QUPV3_WRAP1_CORE_CLK 104 +#define GCC_QUPV3_WRAP1_S0_CLK 105 +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 106 +#define GCC_QUPV3_WRAP1_S1_CLK 107 +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 108 +#define GCC_QUPV3_WRAP1_S2_CLK 109 +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 110 +#define GCC_QUPV3_WRAP1_S3_CLK 111 +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 112 +#define GCC_QUPV3_WRAP1_S4_CLK 113 +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 114 +#define GCC_QUPV3_WRAP1_S5_CLK 115 +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 116 +#define GCC_QUPV3_WRAP2_CORE_2X_CLK 117 +#define GCC_QUPV3_WRAP2_CORE_CLK 118 +#define GCC_QUPV3_WRAP2_S0_CLK 119 +#define GCC_QUPV3_WRAP2_S0_CLK_SRC 120 +#define GCC_QUPV3_WRAP2_S1_CLK 121 +#define GCC_QUPV3_WRAP2_S1_CLK_SRC 122 +#define GCC_QUPV3_WRAP2_S2_CLK 123 +#define GCC_QUPV3_WRAP2_S2_CLK_SRC 124 +#define GCC_QUPV3_WRAP2_S3_CLK 125 +#define GCC_QUPV3_WRAP2_S3_CLK_SRC 126 +#define GCC_QUPV3_WRAP2_S4_CLK 127 +#define GCC_QUPV3_WRAP2_S4_CLK_SRC 128 +#define GCC_QUPV3_WRAP2_S5_CLK 129 +#define GCC_QUPV3_WRAP2_S5_CLK_SRC 130 +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 131 +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 132 +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 133 +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 134 +#define GCC_QUPV3_WRAP_2_M_AHB_CLK 135 +#define GCC_QUPV3_WRAP_2_S_AHB_CLK 136 +#define GCC_SDCC2_AHB_CLK 137 +#define GCC_SDCC2_APPS_CLK 138 +#define GCC_SDCC2_APPS_CLK_SRC 139 +#define GCC_SDCC4_AHB_CLK 140 +#define GCC_SDCC4_APPS_CLK 141 +#define GCC_SDCC4_APPS_CLK_SRC 142 +#define GCC_SYS_NOC_CPUSS_AHB_CLK 143 +#define GCC_TSIF_AHB_CLK 144 +#define GCC_TSIF_INACTIVITY_TIMERS_CLK 145 +#define GCC_TSIF_REF_CLK 146 +#define GCC_TSIF_REF_CLK_SRC 147 +#define GCC_UFS_1X_CLKREF_EN 148 +#define GCC_UFS_CARD_AHB_CLK 149 +#define GCC_UFS_CARD_AXI_CLK 150 +#define GCC_UFS_CARD_AXI_CLK_SRC 151 +#define GCC_UFS_CARD_ICE_CORE_CLK 152 +#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 153 +#define GCC_UFS_CARD_PHY_AUX_CLK 154 +#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 155 +#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 156 +#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 157 +#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 158 +#define GCC_UFS_CARD_UNIPRO_CORE_CLK 159 +#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 160 +#define GCC_UFS_PHY_AHB_CLK 161 +#define GCC_UFS_PHY_AXI_CLK 162 +#define GCC_UFS_PHY_AXI_CLK_SRC 163 +#define GCC_UFS_PHY_ICE_CORE_CLK 164 +#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 165 +#define GCC_UFS_PHY_PHY_AUX_CLK 166 +#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 167 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 168 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 169 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 170 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK 171 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 172 +#define GCC_USB30_PRIM_MASTER_CLK 173 +#define GCC_USB30_PRIM_MASTER_CLK_SRC 174 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 175 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 176 +#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 177 +#define GCC_USB30_PRIM_SLEEP_CLK 178 +#define GCC_USB30_SEC_MASTER_CLK 179 +#define GCC_USB30_SEC_MASTER_CLK_SRC 180 +#define GCC_USB30_SEC_MOCK_UTMI_CLK 181 +#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 182 +#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 183 +#define GCC_USB30_SEC_SLEEP_CLK 184 +#define GCC_USB3_PRIM_PHY_AUX_CLK 185 +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 186 +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 187 +#define GCC_USB3_PRIM_PHY_PIPE_CLK 188 +#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 189 +#define GCC_USB3_SEC_CLKREF_EN 190 +#define GCC_USB3_SEC_PHY_AUX_CLK 191 +#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 192 +#define GCC_USB3_SEC_PHY_COM_AUX_CLK 193 +#define GCC_USB3_SEC_PHY_PIPE_CLK 194 +#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 195 +#define GCC_VIDEO_AHB_CLK 196 +#define GCC_VIDEO_AXI0_CLK 197 +#define GCC_VIDEO_AXI1_CLK 198 +#define GCC_VIDEO_XO_CLK 199 + +/* GCC resets */ +#define GCC_GPU_BCR 0 +#define GCC_MMSS_BCR 1 +#define GCC_NPU_BWMON_BCR 2 +#define GCC_NPU_BCR 3 +#define GCC_PCIE_0_BCR 4 +#define GCC_PCIE_0_LINK_DOWN_BCR 5 +#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 6 +#define GCC_PCIE_0_PHY_BCR 7 +#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 8 +#define GCC_PCIE_1_BCR 9 +#define GCC_PCIE_1_LINK_DOWN_BCR 10 +#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 11 +#define GCC_PCIE_1_PHY_BCR 12 +#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 13 +#define GCC_PCIE_2_BCR 14 +#define GCC_PCIE_2_LINK_DOWN_BCR 15 +#define GCC_PCIE_2_NOCSR_COM_PHY_BCR 16 +#define GCC_PCIE_2_PHY_BCR 17 +#define GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR 18 +#define GCC_PCIE_PHY_BCR 19 +#define GCC_PCIE_PHY_CFG_AHB_BCR 20 +#define GCC_PCIE_PHY_COM_BCR 21 +#define GCC_PDM_BCR 22 +#define GCC_PRNG_BCR 23 +#define GCC_QUPV3_WRAPPER_0_BCR 24 +#define GCC_QUPV3_WRAPPER_1_BCR 25 +#define GCC_QUPV3_WRAPPER_2_BCR 26 +#define GCC_QUSB2PHY_PRIM_BCR 27 +#define GCC_QUSB2PHY_SEC_BCR 28 +#define GCC_SDCC2_BCR 29 +#define GCC_SDCC4_BCR 30 +#define GCC_TSIF_BCR 31 +#define GCC_UFS_CARD_BCR 32 +#define GCC_UFS_PHY_BCR 33 +#define GCC_USB30_PRIM_BCR 34 +#define GCC_USB30_SEC_BCR 35 +#define GCC_USB3_DP_PHY_PRIM_BCR 36 +#define GCC_USB3_DP_PHY_SEC_BCR 37 +#define GCC_USB3_PHY_PRIM_BCR 38 +#define GCC_USB3_PHY_SEC_BCR 39 +#define GCC_USB3PHY_PHY_PRIM_BCR 40 +#define GCC_USB3PHY_PHY_SEC_BCR 41 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 42 +#define GCC_VIDEO_AXI0_CLK_ARES 43 +#define GCC_VIDEO_AXI1_CLK_ARES 44 + +/* GCC power domains */ +#define PCIE_0_GDSC 0 +#define PCIE_1_GDSC 1 +#define PCIE_2_GDSC 2 +#define UFS_CARD_GDSC 3 +#define UFS_PHY_GDSC 4 +#define USB30_PRIM_GDSC 5 +#define USB30_SEC_GDSC 6 +#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 7 +#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 8 +#define HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC 9 +#define HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDSC 10 + +#endif diff --git a/include/dt-bindings/clock/qcom,gcc-sm8350.h b/include/dt-bindings/clock/qcom,gcc-sm8350.h new file mode 100644 index 000000000000..f6be3da5f781 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-sm8350.h @@ -0,0 +1,266 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2020-2021, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM8350_H +#define _DT_BINDINGS_CLK_QCOM_GCC_SM8350_H + +/* GCC HW clocks */ +#define CORE_BI_PLL_TEST_SE 0 +#define PCIE_0_PIPE_CLK 1 +#define PCIE_1_PIPE_CLK 2 +#define UFS_CARD_RX_SYMBOL_0_CLK 3 +#define UFS_CARD_RX_SYMBOL_1_CLK 4 +#define UFS_CARD_TX_SYMBOL_0_CLK 5 +#define UFS_PHY_RX_SYMBOL_0_CLK 6 +#define UFS_PHY_RX_SYMBOL_1_CLK 7 +#define UFS_PHY_TX_SYMBOL_0_CLK 8 +#define USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK 9 +#define USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK 10 + +/* GCC clocks */ +#define GCC_AGGRE_NOC_PCIE_0_AXI_CLK 11 +#define GCC_AGGRE_NOC_PCIE_1_AXI_CLK 12 +#define GCC_AGGRE_NOC_PCIE_TBU_CLK 13 +#define GCC_AGGRE_UFS_CARD_AXI_CLK 14 +#define GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK 15 +#define GCC_AGGRE_UFS_PHY_AXI_CLK 16 +#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 17 +#define GCC_AGGRE_USB3_PRIM_AXI_CLK 18 +#define GCC_AGGRE_USB3_SEC_AXI_CLK 19 +#define GCC_BOOT_ROM_AHB_CLK 20 +#define GCC_CAMERA_HF_AXI_CLK 21 +#define GCC_CAMERA_SF_AXI_CLK 22 +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 23 +#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 24 +#define GCC_DDRSS_GPU_AXI_CLK 25 +#define GCC_DDRSS_PCIE_SF_TBU_CLK 26 +#define GCC_DISP_HF_AXI_CLK 27 +#define GCC_DISP_SF_AXI_CLK 28 +#define GCC_GP1_CLK 29 +#define GCC_GP1_CLK_SRC 30 +#define GCC_GP2_CLK 31 +#define GCC_GP2_CLK_SRC 32 +#define GCC_GP3_CLK 33 +#define GCC_GP3_CLK_SRC 34 +#define GCC_GPLL0 35 +#define GCC_GPLL0_OUT_EVEN 36 +#define GCC_GPLL4 37 +#define GCC_GPLL9 38 +#define GCC_GPU_GPLL0_CLK_SRC 39 +#define GCC_GPU_GPLL0_DIV_CLK_SRC 40 +#define GCC_GPU_IREF_EN 41 +#define GCC_GPU_MEMNOC_GFX_CLK 42 +#define GCC_GPU_SNOC_DVM_GFX_CLK 43 +#define GCC_PCIE0_PHY_RCHNG_CLK 44 +#define GCC_PCIE1_PHY_RCHNG_CLK 45 +#define GCC_PCIE_0_AUX_CLK 46 +#define GCC_PCIE_0_AUX_CLK_SRC 47 +#define GCC_PCIE_0_CFG_AHB_CLK 48 +#define GCC_PCIE_0_CLKREF_EN 49 +#define GCC_PCIE_0_MSTR_AXI_CLK 50 +#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 51 +#define GCC_PCIE_0_PIPE_CLK 52 +#define GCC_PCIE_0_PIPE_CLK_SRC 53 +#define GCC_PCIE_0_SLV_AXI_CLK 54 +#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 55 +#define GCC_PCIE_1_AUX_CLK 56 +#define GCC_PCIE_1_AUX_CLK_SRC 57 +#define GCC_PCIE_1_CFG_AHB_CLK 58 +#define GCC_PCIE_1_CLKREF_EN 59 +#define GCC_PCIE_1_MSTR_AXI_CLK 60 +#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 61 +#define GCC_PCIE_1_PIPE_CLK 62 +#define GCC_PCIE_1_PIPE_CLK_SRC 63 +#define GCC_PCIE_1_SLV_AXI_CLK 64 +#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 65 +#define GCC_PDM2_CLK 66 +#define GCC_PDM2_CLK_SRC 67 +#define GCC_PDM_AHB_CLK 68 +#define GCC_PDM_XO4_CLK 69 +#define GCC_QMIP_CAMERA_NRT_AHB_CLK 70 +#define GCC_QMIP_CAMERA_RT_AHB_CLK 71 +#define GCC_QMIP_DISP_AHB_CLK 72 +#define GCC_QMIP_VIDEO_CVP_AHB_CLK 73 +#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 74 +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 75 +#define GCC_QUPV3_WRAP0_CORE_CLK 76 +#define GCC_QUPV3_WRAP0_S0_CLK 77 +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 78 +#define GCC_QUPV3_WRAP0_S1_CLK 79 +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 80 +#define GCC_QUPV3_WRAP0_S2_CLK 81 +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 82 +#define GCC_QUPV3_WRAP0_S3_CLK 83 +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 84 +#define GCC_QUPV3_WRAP0_S4_CLK 85 +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 86 +#define GCC_QUPV3_WRAP0_S5_CLK 87 +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 88 +#define GCC_QUPV3_WRAP0_S6_CLK 89 +#define GCC_QUPV3_WRAP0_S6_CLK_SRC 90 +#define GCC_QUPV3_WRAP0_S7_CLK 91 +#define GCC_QUPV3_WRAP0_S7_CLK_SRC 92 +#define GCC_QUPV3_WRAP1_CORE_2X_CLK 93 +#define GCC_QUPV3_WRAP1_CORE_CLK 94 +#define GCC_QUPV3_WRAP1_S0_CLK 95 +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 96 +#define GCC_QUPV3_WRAP1_S1_CLK 97 +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 98 +#define GCC_QUPV3_WRAP1_S2_CLK 99 +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 100 +#define GCC_QUPV3_WRAP1_S3_CLK 101 +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 102 +#define GCC_QUPV3_WRAP1_S4_CLK 103 +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 104 +#define GCC_QUPV3_WRAP1_S5_CLK 105 +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 106 +#define GCC_QUPV3_WRAP2_CORE_2X_CLK 107 +#define GCC_QUPV3_WRAP2_CORE_CLK 108 +#define GCC_QUPV3_WRAP2_S0_CLK 109 +#define GCC_QUPV3_WRAP2_S0_CLK_SRC 110 +#define GCC_QUPV3_WRAP2_S1_CLK 111 +#define GCC_QUPV3_WRAP2_S1_CLK_SRC 112 +#define GCC_QUPV3_WRAP2_S2_CLK 113 +#define GCC_QUPV3_WRAP2_S2_CLK_SRC 114 +#define GCC_QUPV3_WRAP2_S3_CLK 115 +#define GCC_QUPV3_WRAP2_S3_CLK_SRC 116 +#define GCC_QUPV3_WRAP2_S4_CLK 117 +#define GCC_QUPV3_WRAP2_S4_CLK_SRC 118 +#define GCC_QUPV3_WRAP2_S5_CLK 119 +#define GCC_QUPV3_WRAP2_S5_CLK_SRC 120 +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 121 +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 122 +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 123 +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 124 +#define GCC_QUPV3_WRAP_2_M_AHB_CLK 125 +#define GCC_QUPV3_WRAP_2_S_AHB_CLK 126 +#define GCC_SDCC2_AHB_CLK 127 +#define GCC_SDCC2_APPS_CLK 128 +#define GCC_SDCC2_APPS_CLK_SRC 129 +#define GCC_SDCC4_AHB_CLK 130 +#define GCC_SDCC4_APPS_CLK 131 +#define GCC_SDCC4_APPS_CLK_SRC 132 +#define GCC_THROTTLE_PCIE_AHB_CLK 133 +#define GCC_UFS_1_CLKREF_EN 134 +#define GCC_UFS_CARD_AHB_CLK 135 +#define GCC_UFS_CARD_AXI_CLK 136 +#define GCC_UFS_CARD_AXI_CLK_SRC 137 +#define GCC_UFS_CARD_AXI_HW_CTL_CLK 138 +#define GCC_UFS_CARD_ICE_CORE_CLK 139 +#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 140 +#define GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK 141 +#define GCC_UFS_CARD_PHY_AUX_CLK 142 +#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 143 +#define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK 144 +#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 145 +#define GCC_UFS_CARD_RX_SYMBOL_0_CLK_SRC 146 +#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 147 +#define GCC_UFS_CARD_RX_SYMBOL_1_CLK_SRC 148 +#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 149 +#define GCC_UFS_CARD_TX_SYMBOL_0_CLK_SRC 150 +#define GCC_UFS_CARD_UNIPRO_CORE_CLK 151 +#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 152 +#define GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK 153 +#define GCC_UFS_PHY_AHB_CLK 154 +#define GCC_UFS_PHY_AXI_CLK 155 +#define GCC_UFS_PHY_AXI_CLK_SRC 156 +#define GCC_UFS_PHY_AXI_HW_CTL_CLK 157 +#define GCC_UFS_PHY_ICE_CORE_CLK 158 +#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 159 +#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 160 +#define GCC_UFS_PHY_PHY_AUX_CLK 161 +#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 162 +#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 163 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 164 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 165 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 166 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 167 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 168 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 169 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK 170 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 171 +#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 172 +#define GCC_USB30_PRIM_MASTER_CLK 173 +#define GCC_USB30_PRIM_MASTER_CLK__FORCE_MEM_CORE_ON 174 +#define GCC_USB30_PRIM_MASTER_CLK_SRC 175 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 176 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 177 +#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 178 +#define GCC_USB30_PRIM_SLEEP_CLK 179 +#define GCC_USB30_SEC_MASTER_CLK 180 +#define GCC_USB30_SEC_MASTER_CLK__FORCE_MEM_CORE_ON 181 +#define GCC_USB30_SEC_MASTER_CLK_SRC 182 +#define GCC_USB30_SEC_MOCK_UTMI_CLK 183 +#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 184 +#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 185 +#define GCC_USB30_SEC_SLEEP_CLK 186 +#define GCC_USB3_PRIM_PHY_AUX_CLK 187 +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 188 +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 189 +#define GCC_USB3_PRIM_PHY_PIPE_CLK 190 +#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 191 +#define GCC_USB3_SEC_CLKREF_EN 192 +#define GCC_USB3_SEC_PHY_AUX_CLK 193 +#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 194 +#define GCC_USB3_SEC_PHY_COM_AUX_CLK 195 +#define GCC_USB3_SEC_PHY_PIPE_CLK 196 +#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 197 +#define GCC_VIDEO_AXI0_CLK 198 +#define GCC_VIDEO_AXI1_CLK 199 + +/* GCC resets */ +#define GCC_CAMERA_BCR 0 +#define GCC_DISPLAY_BCR 1 +#define GCC_GPU_BCR 2 +#define GCC_MMSS_BCR 3 +#define GCC_PCIE_0_BCR 4 +#define GCC_PCIE_0_LINK_DOWN_BCR 5 +#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 6 +#define GCC_PCIE_0_PHY_BCR 7 +#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 8 +#define GCC_PCIE_1_BCR 9 +#define GCC_PCIE_1_LINK_DOWN_BCR 10 +#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 11 +#define GCC_PCIE_1_PHY_BCR 12 +#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 13 +#define GCC_PCIE_PHY_CFG_AHB_BCR 14 +#define GCC_PCIE_PHY_COM_BCR 15 +#define GCC_PDM_BCR 16 +#define GCC_QUPV3_WRAPPER_0_BCR 17 +#define GCC_QUPV3_WRAPPER_1_BCR 18 +#define GCC_QUPV3_WRAPPER_2_BCR 19 +#define GCC_QUSB2PHY_PRIM_BCR 20 +#define GCC_QUSB2PHY_SEC_BCR 21 +#define GCC_SDCC2_BCR 22 +#define GCC_SDCC4_BCR 23 +#define GCC_UFS_CARD_BCR 24 +#define GCC_UFS_PHY_BCR 25 +#define GCC_USB30_PRIM_BCR 26 +#define GCC_USB30_SEC_BCR 27 +#define GCC_USB3_DP_PHY_PRIM_BCR 28 +#define GCC_USB3_DP_PHY_SEC_BCR 29 +#define GCC_USB3_PHY_PRIM_BCR 30 +#define GCC_USB3_PHY_SEC_BCR 31 +#define GCC_USB3PHY_PHY_PRIM_BCR 32 +#define GCC_USB3PHY_PHY_SEC_BCR 33 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 34 +#define GCC_VIDEO_AXI0_CLK_ARES 35 +#define GCC_VIDEO_AXI1_CLK_ARES 36 +#define GCC_VIDEO_BCR 37 + +/* GCC power domains */ +#define PCIE_0_GDSC 0 +#define PCIE_1_GDSC 1 +#define UFS_CARD_GDSC 2 +#define UFS_PHY_GDSC 3 +#define USB30_PRIM_GDSC 4 +#define USB30_SEC_GDSC 5 +#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 6 +#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 7 +#define HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC 8 +#define HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDSC 9 + +#endif diff --git a/include/dt-bindings/clock/qcom,gcc-sm8450.h b/include/dt-bindings/clock/qcom,gcc-sm8450.h new file mode 100644 index 000000000000..cf1469312c4c --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-sm8450.h @@ -0,0 +1,244 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2021, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM8450_H +#define _DT_BINDINGS_CLK_QCOM_GCC_SM8450_H + +/* GCC HW clocks */ +#define CORE_BI_PLL_TEST_SE 0 +#define PCIE_0_PIPE_CLK 1 +#define PCIE_1_PHY_AUX_CLK 2 +#define PCIE_1_PIPE_CLK 3 +#define UFS_PHY_RX_SYMBOL_0_CLK 4 +#define UFS_PHY_RX_SYMBOL_1_CLK 5 +#define UFS_PHY_TX_SYMBOL_0_CLK 6 +#define USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK 7 + +/* GCC clocks */ +#define GCC_AGGRE_NOC_PCIE_0_AXI_CLK 8 +#define GCC_AGGRE_NOC_PCIE_1_AXI_CLK 9 +#define GCC_AGGRE_UFS_PHY_AXI_CLK 10 +#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 11 +#define GCC_AGGRE_USB3_PRIM_AXI_CLK 12 +#define GCC_ANOC_PCIE_PWRCTL_CLK 13 +#define GCC_BOOT_ROM_AHB_CLK 14 +#define GCC_CAMERA_AHB_CLK 15 +#define GCC_CAMERA_HF_AXI_CLK 16 +#define GCC_CAMERA_SF_AXI_CLK 17 +#define GCC_CAMERA_XO_CLK 18 +#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 19 +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 20 +#define GCC_CPUSS_AHB_CLK 21 +#define GCC_CPUSS_AHB_CLK_SRC 22 +#define GCC_CPUSS_AHB_POSTDIV_CLK_SRC 23 +#define GCC_CPUSS_CONFIG_NOC_SF_CLK 24 +#define GCC_DDRSS_GPU_AXI_CLK 25 +#define GCC_DDRSS_PCIE_SF_TBU_CLK 26 +#define GCC_DISP_AHB_CLK 27 +#define GCC_DISP_HF_AXI_CLK 28 +#define GCC_DISP_SF_AXI_CLK 29 +#define GCC_DISP_XO_CLK 30 +#define GCC_EUSB3_0_CLKREF_EN 31 +#define GCC_GP1_CLK 32 +#define GCC_GP1_CLK_SRC 33 +#define GCC_GP2_CLK 34 +#define GCC_GP2_CLK_SRC 35 +#define GCC_GP3_CLK 36 +#define GCC_GP3_CLK_SRC 37 +#define GCC_GPLL0 38 +#define GCC_GPLL0_OUT_EVEN 39 +#define GCC_GPLL4 40 +#define GCC_GPLL9 41 +#define GCC_GPU_CFG_AHB_CLK 42 +#define GCC_GPU_GPLL0_CLK_SRC 43 +#define GCC_GPU_GPLL0_DIV_CLK_SRC 44 +#define GCC_GPU_MEMNOC_GFX_CLK 45 +#define GCC_GPU_SNOC_DVM_GFX_CLK 46 +#define GCC_PCIE_0_AUX_CLK 47 +#define GCC_PCIE_0_AUX_CLK_SRC 48 +#define GCC_PCIE_0_CFG_AHB_CLK 49 +#define GCC_PCIE_0_CLKREF_EN 50 +#define GCC_PCIE_0_MSTR_AXI_CLK 51 +#define GCC_PCIE_0_PHY_RCHNG_CLK 52 +#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 53 +#define GCC_PCIE_0_PIPE_CLK 54 +#define GCC_PCIE_0_PIPE_CLK_SRC 55 +#define GCC_PCIE_0_SLV_AXI_CLK 56 +#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 57 +#define GCC_PCIE_1_AUX_CLK 58 +#define GCC_PCIE_1_AUX_CLK_SRC 59 +#define GCC_PCIE_1_CFG_AHB_CLK 60 +#define GCC_PCIE_1_CLKREF_EN 61 +#define GCC_PCIE_1_MSTR_AXI_CLK 62 +#define GCC_PCIE_1_PHY_AUX_CLK 63 +#define GCC_PCIE_1_PHY_AUX_CLK_SRC 64 +#define GCC_PCIE_1_PHY_RCHNG_CLK 65 +#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 66 +#define GCC_PCIE_1_PIPE_CLK 67 +#define GCC_PCIE_1_PIPE_CLK_SRC 68 +#define GCC_PCIE_1_SLV_AXI_CLK 69 +#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 70 +#define GCC_PDM2_CLK 71 +#define GCC_PDM2_CLK_SRC 72 +#define GCC_PDM_AHB_CLK 73 +#define GCC_PDM_XO4_CLK 74 +#define GCC_QMIP_CAMERA_NRT_AHB_CLK 75 +#define GCC_QMIP_CAMERA_RT_AHB_CLK 76 +#define GCC_QMIP_DISP_AHB_CLK 77 +#define GCC_QMIP_GPU_AHB_CLK 78 +#define GCC_QMIP_PCIE_AHB_CLK 79 +#define GCC_QMIP_VIDEO_CV_CPU_AHB_CLK 80 +#define GCC_QMIP_VIDEO_CVP_AHB_CLK 81 +#define GCC_QMIP_VIDEO_V_CPU_AHB_CLK 82 +#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 83 +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 84 +#define GCC_QUPV3_WRAP0_CORE_CLK 85 +#define GCC_QUPV3_WRAP0_S0_CLK 86 +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 87 +#define GCC_QUPV3_WRAP0_S1_CLK 88 +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 89 +#define GCC_QUPV3_WRAP0_S2_CLK 90 +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 91 +#define GCC_QUPV3_WRAP0_S3_CLK 92 +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 93 +#define GCC_QUPV3_WRAP0_S4_CLK 94 +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 95 +#define GCC_QUPV3_WRAP0_S5_CLK 96 +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 97 +#define GCC_QUPV3_WRAP0_S6_CLK 98 +#define GCC_QUPV3_WRAP0_S6_CLK_SRC 99 +#define GCC_QUPV3_WRAP0_S7_CLK 100 +#define GCC_QUPV3_WRAP0_S7_CLK_SRC 101 +#define GCC_QUPV3_WRAP1_CORE_2X_CLK 102 +#define GCC_QUPV3_WRAP1_CORE_CLK 103 +#define GCC_QUPV3_WRAP1_S0_CLK 104 +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 105 +#define GCC_QUPV3_WRAP1_S1_CLK 106 +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 107 +#define GCC_QUPV3_WRAP1_S2_CLK 108 +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 109 +#define GCC_QUPV3_WRAP1_S3_CLK 110 +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 111 +#define GCC_QUPV3_WRAP1_S4_CLK 112 +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 113 +#define GCC_QUPV3_WRAP1_S5_CLK 114 +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 115 +#define GCC_QUPV3_WRAP1_S6_CLK 116 +#define GCC_QUPV3_WRAP1_S6_CLK_SRC 117 +#define GCC_QUPV3_WRAP2_CORE_2X_CLK 118 +#define GCC_QUPV3_WRAP2_CORE_CLK 119 +#define GCC_QUPV3_WRAP2_S0_CLK 120 +#define GCC_QUPV3_WRAP2_S0_CLK_SRC 121 +#define GCC_QUPV3_WRAP2_S1_CLK 122 +#define GCC_QUPV3_WRAP2_S1_CLK_SRC 123 +#define GCC_QUPV3_WRAP2_S2_CLK 124 +#define GCC_QUPV3_WRAP2_S2_CLK_SRC 125 +#define GCC_QUPV3_WRAP2_S3_CLK 126 +#define GCC_QUPV3_WRAP2_S3_CLK_SRC 127 +#define GCC_QUPV3_WRAP2_S4_CLK 128 +#define GCC_QUPV3_WRAP2_S4_CLK_SRC 129 +#define GCC_QUPV3_WRAP2_S5_CLK 130 +#define GCC_QUPV3_WRAP2_S5_CLK_SRC 131 +#define GCC_QUPV3_WRAP2_S6_CLK 132 +#define GCC_QUPV3_WRAP2_S6_CLK_SRC 133 +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 134 +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 135 +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 136 +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 137 +#define GCC_QUPV3_WRAP_2_M_AHB_CLK 138 +#define GCC_QUPV3_WRAP_2_S_AHB_CLK 139 +#define GCC_SDCC2_AHB_CLK 140 +#define GCC_SDCC2_APPS_CLK 141 +#define GCC_SDCC2_APPS_CLK_SRC 142 +#define GCC_SDCC2_AT_CLK 143 +#define GCC_SDCC4_AHB_CLK 144 +#define GCC_SDCC4_APPS_CLK 145 +#define GCC_SDCC4_APPS_CLK_SRC 146 +#define GCC_SDCC4_AT_CLK 147 +#define GCC_SYS_NOC_CPUSS_AHB_CLK 148 +#define GCC_UFS_0_CLKREF_EN 149 +#define GCC_UFS_PHY_AHB_CLK 150 +#define GCC_UFS_PHY_AXI_CLK 151 +#define GCC_UFS_PHY_AXI_CLK_SRC 152 +#define GCC_UFS_PHY_AXI_HW_CTL_CLK 153 +#define GCC_UFS_PHY_ICE_CORE_CLK 154 +#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 155 +#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 156 +#define GCC_UFS_PHY_PHY_AUX_CLK 157 +#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 158 +#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 159 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 160 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 161 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 162 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 163 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 164 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 165 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK 166 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 167 +#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 168 +#define GCC_USB30_PRIM_MASTER_CLK 169 +#define GCC_USB30_PRIM_MASTER_CLK_SRC 170 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 171 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 172 +#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 173 +#define GCC_USB30_PRIM_SLEEP_CLK 174 +#define GCC_USB3_0_CLKREF_EN 175 +#define GCC_USB3_PRIM_PHY_AUX_CLK 176 +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 177 +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 178 +#define GCC_USB3_PRIM_PHY_PIPE_CLK 179 +#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 180 +#define GCC_VIDEO_AHB_CLK 181 +#define GCC_VIDEO_AXI0_CLK 182 +#define GCC_VIDEO_AXI1_CLK 183 +#define GCC_VIDEO_XO_CLK 184 + +/* GCC resets */ +#define GCC_CAMERA_BCR 0 +#define GCC_DISPLAY_BCR 1 +#define GCC_GPU_BCR 2 +#define GCC_MMSS_BCR 3 +#define GCC_PCIE_0_BCR 4 +#define GCC_PCIE_0_LINK_DOWN_BCR 5 +#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 6 +#define GCC_PCIE_0_PHY_BCR 7 +#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 8 +#define GCC_PCIE_1_BCR 9 +#define GCC_PCIE_1_LINK_DOWN_BCR 10 +#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 11 +#define GCC_PCIE_1_PHY_BCR 12 +#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 13 +#define GCC_PCIE_PHY_BCR 14 +#define GCC_PCIE_PHY_CFG_AHB_BCR 15 +#define GCC_PCIE_PHY_COM_BCR 16 +#define GCC_PDM_BCR 17 +#define GCC_QUPV3_WRAPPER_0_BCR 18 +#define GCC_QUPV3_WRAPPER_1_BCR 19 +#define GCC_QUPV3_WRAPPER_2_BCR 20 +#define GCC_QUSB2PHY_PRIM_BCR 21 +#define GCC_QUSB2PHY_SEC_BCR 22 +#define GCC_SDCC2_BCR 23 +#define GCC_SDCC4_BCR 24 +#define GCC_UFS_PHY_BCR 25 +#define GCC_USB30_PRIM_BCR 26 +#define GCC_USB3_DP_PHY_PRIM_BCR 27 +#define GCC_USB3_DP_PHY_SEC_BCR 28 +#define GCC_USB3_PHY_PRIM_BCR 29 +#define GCC_USB3_PHY_SEC_BCR 30 +#define GCC_USB3PHY_PHY_PRIM_BCR 31 +#define GCC_USB3PHY_PHY_SEC_BCR 32 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 33 +#define GCC_VIDEO_AXI0_CLK_ARES 34 +#define GCC_VIDEO_AXI1_CLK_ARES 35 +#define GCC_VIDEO_BCR 36 + +/* GCC power domains */ +#define PCIE_0_GDSC 0 +#define PCIE_1_GDSC 1 +#define UFS_PHY_GDSC 2 +#define USB30_PRIM_GDSC 3 + +#endif diff --git a/include/dt-bindings/clock/qcom,gpucc-sc7180.h b/include/dt-bindings/clock/qcom,gpucc-sc7180.h index 0e4643b08b49..65e706d7d9c6 100644 --- a/include/dt-bindings/clock/qcom,gpucc-sc7180.h +++ b/include/dt-bindings/clock/qcom,gpucc-sc7180.h @@ -15,7 +15,8 @@ #define GPU_CC_CXO_CLK 6 #define GPU_CC_GMU_CLK_SRC 7 -/* CAM_CC GDSCRs */ +/* GPU_CC GDSCRs */ #define CX_GDSC 0 +#define GX_GDSC 1 #endif diff --git a/include/dt-bindings/clock/qcom,gpucc-sc7280.h b/include/dt-bindings/clock/qcom,gpucc-sc7280.h new file mode 100644 index 000000000000..669b23b606ba --- /dev/null +++ b/include/dt-bindings/clock/qcom,gpucc-sc7280.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SC7280_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SC7280_H + +/* GPU_CC clocks */ +#define GPU_CC_PLL0 0 +#define GPU_CC_PLL1 1 +#define GPU_CC_AHB_CLK 2 +#define GPU_CC_CB_CLK 3 +#define GPU_CC_CRC_AHB_CLK 4 +#define GPU_CC_CX_GMU_CLK 5 +#define GPU_CC_CX_SNOC_DVM_CLK 6 +#define GPU_CC_CXO_AON_CLK 7 +#define GPU_CC_CXO_CLK 8 +#define GPU_CC_GMU_CLK_SRC 9 +#define GPU_CC_GX_GMU_CLK 10 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 11 +#define GPU_CC_HUB_AHB_DIV_CLK_SRC 12 +#define GPU_CC_HUB_AON_CLK 13 +#define GPU_CC_HUB_CLK_SRC 14 +#define GPU_CC_HUB_CX_INT_CLK 15 +#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC 16 +#define GPU_CC_MND1X_0_GFX3D_CLK 17 +#define GPU_CC_MND1X_1_GFX3D_CLK 18 +#define GPU_CC_SLEEP_CLK 19 + +/* GPU_CC power domains */ +#define GPU_CC_CX_GDSC 0 +#define GPU_CC_GX_GDSC 1 + +#endif diff --git a/include/dt-bindings/clock/qcom,gpucc-sc8280xp.h b/include/dt-bindings/clock/qcom,gpucc-sc8280xp.h new file mode 100644 index 000000000000..bb7da46333b0 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gpucc-sc8280xp.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SC8280XP_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SC8280XP_H + +/* GPU_CC clocks */ +#define GPU_CC_PLL0 0 +#define GPU_CC_PLL1 1 +#define GPU_CC_AHB_CLK 2 +#define GPU_CC_CB_CLK 3 +#define GPU_CC_CRC_AHB_CLK 4 +#define GPU_CC_CX_GMU_CLK 5 +#define GPU_CC_CX_SNOC_DVM_CLK 6 +#define GPU_CC_CXO_AON_CLK 7 +#define GPU_CC_CXO_CLK 8 +#define GPU_CC_FREQ_MEASURE_CLK 9 +#define GPU_CC_GMU_CLK_SRC 10 +#define GPU_CC_GX_GMU_CLK 11 +#define GPU_CC_GX_VSENSE_CLK 12 +#define GPU_CC_HUB_AHB_DIV_CLK_SRC 13 +#define GPU_CC_HUB_AON_CLK 14 +#define GPU_CC_HUB_CLK_SRC 15 +#define GPU_CC_HUB_CX_INT_CLK 16 +#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC 17 +#define GPU_CC_SLEEP_CLK 18 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 19 + +/* GPU_CC power domains */ +#define GPU_CC_CX_GDSC 0 +#define GPU_CC_GX_GDSC 1 + +#endif diff --git a/include/dt-bindings/clock/qcom,gpucc-sdm660.h b/include/dt-bindings/clock/qcom,gpucc-sdm660.h new file mode 100644 index 000000000000..7ea3e53df58c --- /dev/null +++ b/include/dt-bindings/clock/qcom,gpucc-sdm660.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2020, AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> + */ + +#ifndef _DT_BINDINGS_CLK_SDM_GPUCC_660_H +#define _DT_BINDINGS_CLK_SDM_GPUCC_660_H + +#define GPUCC_CXO_CLK 0 +#define GPU_PLL0_PLL 1 +#define GPU_PLL1_PLL 2 +#define GFX3D_CLK_SRC 3 +#define RBCPR_CLK_SRC 4 +#define RBBMTIMER_CLK_SRC 5 +#define GPUCC_RBCPR_CLK 6 +#define GPUCC_GFX3D_CLK 7 +#define GPUCC_RBBMTIMER_CLK 8 + +#define GPU_CX_GDSC 0 +#define GPU_GX_GDSC 1 + +#define GPU_CX_BCR 0 +#define GPU_GX_BCR 1 +#define RBCPR_BCR 2 +#define SPDM_BCR 3 + +#endif diff --git a/include/dt-bindings/clock/qcom,gpucc-sm6350.h b/include/dt-bindings/clock/qcom,gpucc-sm6350.h new file mode 100644 index 000000000000..68e814fc8acd --- /dev/null +++ b/include/dt-bindings/clock/qcom,gpucc-sm6350.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6350_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6350_H + +/* GPU_CC clocks */ +#define GPU_CC_PLL0 0 +#define GPU_CC_PLL1 1 +#define GPU_CC_ACD_AHB_CLK 2 +#define GPU_CC_ACD_CXO_CLK 3 +#define GPU_CC_AHB_CLK 4 +#define GPU_CC_CRC_AHB_CLK 5 +#define GPU_CC_CX_GFX3D_CLK 6 +#define GPU_CC_CX_GFX3D_SLV_CLK 7 +#define GPU_CC_CX_GMU_CLK 8 +#define GPU_CC_CX_SNOC_DVM_CLK 9 +#define GPU_CC_CXO_AON_CLK 10 +#define GPU_CC_CXO_CLK 11 +#define GPU_CC_GMU_CLK_SRC 12 +#define GPU_CC_GX_CXO_CLK 13 +#define GPU_CC_GX_GFX3D_CLK 14 +#define GPU_CC_GX_GFX3D_CLK_SRC 15 +#define GPU_CC_GX_GMU_CLK 16 +#define GPU_CC_GX_VSENSE_CLK 17 + +/* CLK_HW */ +#define GPU_CC_CRC_DIV 0 + +/* GDSCs */ +#define GPU_CX_GDSC 0 +#define GPU_GX_GDSC 1 + +#endif diff --git a/include/dt-bindings/clock/qcom,gpucc-sm8150.h b/include/dt-bindings/clock/qcom,gpucc-sm8150.h new file mode 100644 index 000000000000..c5b70aad7770 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gpucc-sm8150.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8150_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8150_H + +/* GPU_CC clock registers */ +#define GPU_CC_AHB_CLK 0 +#define GPU_CC_CRC_AHB_CLK 1 +#define GPU_CC_CX_APB_CLK 2 +#define GPU_CC_CX_GMU_CLK 3 +#define GPU_CC_CX_SNOC_DVM_CLK 4 +#define GPU_CC_CXO_AON_CLK 5 +#define GPU_CC_CXO_CLK 6 +#define GPU_CC_GMU_CLK_SRC 7 +#define GPU_CC_GX_GMU_CLK 8 +#define GPU_CC_PLL1 9 + +/* GPU_CC Resets */ +#define GPUCC_GPU_CC_CX_BCR 0 +#define GPUCC_GPU_CC_GFX3D_AON_BCR 1 +#define GPUCC_GPU_CC_GMU_BCR 2 +#define GPUCC_GPU_CC_GX_BCR 3 +#define GPUCC_GPU_CC_SPDM_BCR 4 +#define GPUCC_GPU_CC_XO_BCR 5 + +/* GPU_CC GDSCRs */ +#define GPU_CX_GDSC 0 +#define GPU_GX_GDSC 1 + +#endif diff --git a/include/dt-bindings/clock/qcom,gpucc-sm8250.h b/include/dt-bindings/clock/qcom,gpucc-sm8250.h new file mode 100644 index 000000000000..dc8e387c48ad --- /dev/null +++ b/include/dt-bindings/clock/qcom,gpucc-sm8250.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8250_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8250_H + +/* GPU_CC clock registers */ +#define GPU_CC_AHB_CLK 0 +#define GPU_CC_CRC_AHB_CLK 1 +#define GPU_CC_CX_APB_CLK 2 +#define GPU_CC_CX_GMU_CLK 3 +#define GPU_CC_CX_SNOC_DVM_CLK 4 +#define GPU_CC_CXO_AON_CLK 5 +#define GPU_CC_CXO_CLK 6 +#define GPU_CC_GMU_CLK_SRC 7 +#define GPU_CC_GX_GMU_CLK 8 +#define GPU_CC_PLL1 9 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 10 + +/* GPU_CC Resets */ +#define GPUCC_GPU_CC_ACD_BCR 0 +#define GPUCC_GPU_CC_CX_BCR 1 +#define GPUCC_GPU_CC_GFX3D_AON_BCR 2 +#define GPUCC_GPU_CC_GMU_BCR 3 +#define GPUCC_GPU_CC_GX_BCR 4 +#define GPUCC_GPU_CC_XO_BCR 5 + +/* GPU_CC GDSCRs */ +#define GPU_CX_GDSC 0 +#define GPU_GX_GDSC 1 + +#endif diff --git a/include/dt-bindings/clock/qcom,gpucc-sm8350.h b/include/dt-bindings/clock/qcom,gpucc-sm8350.h new file mode 100644 index 000000000000..2ca857f5bfd2 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gpucc-sm8350.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8350_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8350_H + +/* GPU_CC clocks */ +#define GPU_CC_AHB_CLK 0 +#define GPU_CC_CB_CLK 1 +#define GPU_CC_CRC_AHB_CLK 2 +#define GPU_CC_CX_APB_CLK 3 +#define GPU_CC_CX_GMU_CLK 4 +#define GPU_CC_CX_QDSS_AT_CLK 5 +#define GPU_CC_CX_QDSS_TRIG_CLK 6 +#define GPU_CC_CX_QDSS_TSCTR_CLK 7 +#define GPU_CC_CX_SNOC_DVM_CLK 8 +#define GPU_CC_CXO_AON_CLK 9 +#define GPU_CC_CXO_CLK 10 +#define GPU_CC_FREQ_MEASURE_CLK 11 +#define GPU_CC_GMU_CLK_SRC 12 +#define GPU_CC_GX_GMU_CLK 13 +#define GPU_CC_GX_QDSS_TSCTR_CLK 14 +#define GPU_CC_GX_VSENSE_CLK 15 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 16 +#define GPU_CC_HUB_AHB_DIV_CLK_SRC 17 +#define GPU_CC_HUB_AON_CLK 18 +#define GPU_CC_HUB_CLK_SRC 19 +#define GPU_CC_HUB_CX_INT_CLK 20 +#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC 21 +#define GPU_CC_MND1X_0_GFX3D_CLK 22 +#define GPU_CC_MND1X_1_GFX3D_CLK 23 +#define GPU_CC_PLL0 24 +#define GPU_CC_PLL1 25 +#define GPU_CC_SLEEP_CLK 26 + +/* GPU_CC resets */ +#define GPUCC_GPU_CC_ACD_BCR 0 +#define GPUCC_GPU_CC_CB_BCR 1 +#define GPUCC_GPU_CC_CX_BCR 2 +#define GPUCC_GPU_CC_FAST_HUB_BCR 3 +#define GPUCC_GPU_CC_GFX3D_AON_BCR 4 +#define GPUCC_GPU_CC_GMU_BCR 5 +#define GPUCC_GPU_CC_GX_BCR 6 +#define GPUCC_GPU_CC_XO_BCR 7 + +/* GPU_CC GDSCRs */ +#define GPU_CX_GDSC 0 +#define GPU_GX_GDSC 1 + +#endif diff --git a/include/dt-bindings/clock/qcom,lcc-ipq806x.h b/include/dt-bindings/clock/qcom,lcc-ipq806x.h index 25b92bbf0ab4..e0fb4acf4ba8 100644 --- a/include/dt-bindings/clock/qcom,lcc-ipq806x.h +++ b/include/dt-bindings/clock/qcom,lcc-ipq806x.h @@ -19,4 +19,6 @@ #define SPDIF_CLK 10 #define AHBIX_CLK 11 +#define LCC_PCM_RESET 0 + #endif diff --git a/include/dt-bindings/clock/qcom,lpass-sc7280.h b/include/dt-bindings/clock/qcom,lpass-sc7280.h new file mode 100644 index 000000000000..e71ccac3a375 --- /dev/null +++ b/include/dt-bindings/clock/qcom,lpass-sc7280.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_LPASS_SC7280_H +#define _DT_BINDINGS_CLK_QCOM_LPASS_SC7280_H + +#define LPASS_Q6SS_AHBM_CLK 0 +#define LPASS_Q6SS_AHBS_CLK 1 +#define LPASS_TOP_CC_LPI_Q6_AXIM_HS_CLK 2 +#define LPASS_QDSP6SS_XO_CLK 3 +#define LPASS_QDSP6SS_SLEEP_CLK 4 +#define LPASS_QDSP6SS_CORE_CLK 5 + +#endif diff --git a/include/dt-bindings/clock/qcom,lpassaudiocc-sc7280.h b/include/dt-bindings/clock/qcom,lpassaudiocc-sc7280.h new file mode 100644 index 000000000000..22dcd47d4513 --- /dev/null +++ b/include/dt-bindings/clock/qcom,lpassaudiocc-sc7280.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_LPASS_AUDIO_CC_SC7280_H +#define _DT_BINDINGS_CLK_QCOM_LPASS_AUDIO_CC_SC7280_H + +/* LPASS_AUDIO_CC clocks */ +#define LPASS_AUDIO_CC_PLL 0 +#define LPASS_AUDIO_CC_PLL_OUT_AUX2 1 +#define LPASS_AUDIO_CC_PLL_OUT_AUX2_DIV_CLK_SRC 2 +#define LPASS_AUDIO_CC_PLL_OUT_MAIN_DIV_CLK_SRC 3 +#define LPASS_AUDIO_CC_CDIV_RX_MCLK_DIV_CLK_SRC 4 +#define LPASS_AUDIO_CC_CODEC_MEM0_CLK 5 +#define LPASS_AUDIO_CC_CODEC_MEM1_CLK 6 +#define LPASS_AUDIO_CC_CODEC_MEM2_CLK 7 +#define LPASS_AUDIO_CC_CODEC_MEM_CLK 8 +#define LPASS_AUDIO_CC_EXT_MCLK0_CLK 9 +#define LPASS_AUDIO_CC_EXT_MCLK0_CLK_SRC 10 +#define LPASS_AUDIO_CC_EXT_MCLK1_CLK 11 +#define LPASS_AUDIO_CC_EXT_MCLK1_CLK_SRC 12 +#define LPASS_AUDIO_CC_RX_MCLK_2X_CLK 13 +#define LPASS_AUDIO_CC_RX_MCLK_CLK 14 +#define LPASS_AUDIO_CC_RX_MCLK_CLK_SRC 15 + +/* LPASS AUDIO CC CSR */ +#define LPASS_AUDIO_SWR_RX_CGCR 0 +#define LPASS_AUDIO_SWR_TX_CGCR 1 +#define LPASS_AUDIO_SWR_WSA_CGCR 2 + +/* LPASS_AON_CC clocks */ +#define LPASS_AON_CC_PLL 0 +#define LPASS_AON_CC_PLL_OUT_EVEN 1 +#define LPASS_AON_CC_PLL_OUT_MAIN_CDIV_DIV_CLK_SRC 2 +#define LPASS_AON_CC_PLL_OUT_ODD 3 +#define LPASS_AON_CC_AUDIO_HM_H_CLK 4 +#define LPASS_AON_CC_CDIV_TX_MCLK_DIV_CLK_SRC 5 +#define LPASS_AON_CC_MAIN_RCG_CLK_SRC 6 +#define LPASS_AON_CC_TX_MCLK_2X_CLK 7 +#define LPASS_AON_CC_TX_MCLK_CLK 8 +#define LPASS_AON_CC_TX_MCLK_RCG_CLK_SRC 9 +#define LPASS_AON_CC_VA_MEM0_CLK 10 + +/* LPASS_AON_CC power domains */ +#define LPASS_AON_CC_LPASS_AUDIO_HM_GDSC 0 + +#endif diff --git a/include/dt-bindings/clock/qcom,lpasscorecc-sc7180.h b/include/dt-bindings/clock/qcom,lpasscorecc-sc7180.h new file mode 100644 index 000000000000..a55d01db2b20 --- /dev/null +++ b/include/dt-bindings/clock/qcom,lpasscorecc-sc7180.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_LPASS_CORE_CC_SC7180_H +#define _DT_BINDINGS_CLK_QCOM_LPASS_CORE_CC_SC7180_H + +/* LPASS_CORE_CC clocks */ +#define LPASS_LPAAUDIO_DIG_PLL 0 +#define LPASS_LPAAUDIO_DIG_PLL_OUT_ODD 1 +#define CORE_CLK_SRC 2 +#define EXT_MCLK0_CLK_SRC 3 +#define LPAIF_PRI_CLK_SRC 4 +#define LPAIF_SEC_CLK_SRC 5 +#define LPASS_AUDIO_CORE_CORE_CLK 6 +#define LPASS_AUDIO_CORE_EXT_MCLK0_CLK 7 +#define LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK 8 +#define LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK 9 +#define LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK 10 + +/* LPASS Core power domains */ +#define LPASS_CORE_HM_GDSCR 0 + +/* LPASS Audio power domains */ +#define LPASS_AUDIO_HM_GDSCR 0 +#define LPASS_PDC_HM_GDSCR 1 + +#endif diff --git a/include/dt-bindings/clock/qcom,lpasscorecc-sc7280.h b/include/dt-bindings/clock/qcom,lpasscorecc-sc7280.h new file mode 100644 index 000000000000..0324c69ce968 --- /dev/null +++ b/include/dt-bindings/clock/qcom,lpasscorecc-sc7280.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_LPASS_CORE_CC_SC7280_H +#define _DT_BINDINGS_CLK_QCOM_LPASS_CORE_CC_SC7280_H + +/* LPASS_CORE_CC clocks */ +#define LPASS_CORE_CC_DIG_PLL 0 +#define LPASS_CORE_CC_DIG_PLL_OUT_MAIN_DIV_CLK_SRC 1 +#define LPASS_CORE_CC_DIG_PLL_OUT_ODD 2 +#define LPASS_CORE_CC_CORE_CLK 3 +#define LPASS_CORE_CC_CORE_CLK_SRC 4 +#define LPASS_CORE_CC_EXT_IF0_CLK_SRC 5 +#define LPASS_CORE_CC_EXT_IF0_IBIT_CLK 6 +#define LPASS_CORE_CC_EXT_IF1_CLK_SRC 7 +#define LPASS_CORE_CC_EXT_IF1_IBIT_CLK 8 +#define LPASS_CORE_CC_LPM_CORE_CLK 9 +#define LPASS_CORE_CC_LPM_MEM0_CORE_CLK 10 +#define LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK 11 +#define LPASS_CORE_CC_EXT_MCLK0_CLK 12 +#define LPASS_CORE_CC_EXT_MCLK0_CLK_SRC 13 + +/* LPASS_CORE_CC power domains */ +#define LPASS_CORE_CC_LPASS_CORE_HM_GDSC 0 + +#endif diff --git a/include/dt-bindings/clock/qcom,mmcc-msm8994.h b/include/dt-bindings/clock/qcom,mmcc-msm8994.h new file mode 100644 index 000000000000..4b289092f5a2 --- /dev/null +++ b/include/dt-bindings/clock/qcom,mmcc-msm8994.h @@ -0,0 +1,155 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020, Konrad Dybcio + */ + +#ifndef _DT_BINDINGS_CLK_MSM_MMCC_8994_H +#define _DT_BINDINGS_CLK_MSM_MMCC_8994_H + +/* Clocks */ +#define MMPLL0_EARLY 0 +#define MMPLL0_PLL 1 +#define MMPLL1_EARLY 2 +#define MMPLL1_PLL 3 +#define MMPLL3_EARLY 4 +#define MMPLL3_PLL 5 +#define MMPLL4_EARLY 6 +#define MMPLL4_PLL 7 +#define MMPLL5_EARLY 8 +#define MMPLL5_PLL 9 +#define AXI_CLK_SRC 10 +#define RBBMTIMER_CLK_SRC 11 +#define PCLK0_CLK_SRC 12 +#define PCLK1_CLK_SRC 13 +#define MDP_CLK_SRC 14 +#define VSYNC_CLK_SRC 15 +#define BYTE0_CLK_SRC 16 +#define BYTE1_CLK_SRC 17 +#define ESC0_CLK_SRC 18 +#define ESC1_CLK_SRC 19 +#define MDSS_AHB_CLK 20 +#define MDSS_PCLK0_CLK 21 +#define MDSS_PCLK1_CLK 22 +#define MDSS_VSYNC_CLK 23 +#define MDSS_BYTE0_CLK 24 +#define MDSS_BYTE1_CLK 25 +#define MDSS_ESC0_CLK 26 +#define MDSS_ESC1_CLK 27 +#define CSI0_CLK_SRC 28 +#define CSI1_CLK_SRC 29 +#define CSI2_CLK_SRC 30 +#define CSI3_CLK_SRC 31 +#define VFE0_CLK_SRC 32 +#define VFE1_CLK_SRC 33 +#define CPP_CLK_SRC 34 +#define JPEG0_CLK_SRC 35 +#define JPEG1_CLK_SRC 36 +#define JPEG2_CLK_SRC 37 +#define CSI2PHYTIMER_CLK_SRC 38 +#define FD_CORE_CLK_SRC 39 +#define OCMEMNOC_CLK_SRC 40 +#define CCI_CLK_SRC 41 +#define MMSS_GP0_CLK_SRC 42 +#define MMSS_GP1_CLK_SRC 43 +#define JPEG_DMA_CLK_SRC 44 +#define MCLK0_CLK_SRC 45 +#define MCLK1_CLK_SRC 46 +#define MCLK2_CLK_SRC 47 +#define MCLK3_CLK_SRC 48 +#define CSI0PHYTIMER_CLK_SRC 49 +#define CSI1PHYTIMER_CLK_SRC 50 +#define EXTPCLK_CLK_SRC 51 +#define HDMI_CLK_SRC 52 +#define CAMSS_AHB_CLK 53 +#define CAMSS_CCI_CCI_AHB_CLK 54 +#define CAMSS_CCI_CCI_CLK 55 +#define CAMSS_VFE_CPP_AHB_CLK 56 +#define CAMSS_VFE_CPP_AXI_CLK 57 +#define CAMSS_VFE_CPP_CLK 58 +#define CAMSS_CSI0_AHB_CLK 59 +#define CAMSS_CSI0_CLK 60 +#define CAMSS_CSI0PHY_CLK 61 +#define CAMSS_CSI0PIX_CLK 62 +#define CAMSS_CSI0RDI_CLK 63 +#define CAMSS_CSI1_AHB_CLK 64 +#define CAMSS_CSI1_CLK 65 +#define CAMSS_CSI1PHY_CLK 66 +#define CAMSS_CSI1PIX_CLK 67 +#define CAMSS_CSI1RDI_CLK 68 +#define CAMSS_CSI2_AHB_CLK 69 +#define CAMSS_CSI2_CLK 70 +#define CAMSS_CSI2PHY_CLK 71 +#define CAMSS_CSI2PIX_CLK 72 +#define CAMSS_CSI2RDI_CLK 73 +#define CAMSS_CSI3_AHB_CLK 74 +#define CAMSS_CSI3_CLK 75 +#define CAMSS_CSI3PHY_CLK 76 +#define CAMSS_CSI3PIX_CLK 77 +#define CAMSS_CSI3RDI_CLK 78 +#define CAMSS_CSI_VFE0_CLK 79 +#define CAMSS_CSI_VFE1_CLK 80 +#define CAMSS_GP0_CLK 81 +#define CAMSS_GP1_CLK 82 +#define CAMSS_ISPIF_AHB_CLK 83 +#define CAMSS_JPEG_DMA_CLK 84 +#define CAMSS_JPEG_JPEG0_CLK 85 +#define CAMSS_JPEG_JPEG1_CLK 86 +#define CAMSS_JPEG_JPEG2_CLK 87 +#define CAMSS_JPEG_JPEG_AHB_CLK 88 +#define CAMSS_JPEG_JPEG_AXI_CLK 89 +#define CAMSS_MCLK0_CLK 90 +#define CAMSS_MCLK1_CLK 91 +#define CAMSS_MCLK2_CLK 92 +#define CAMSS_MCLK3_CLK 93 +#define CAMSS_MICRO_AHB_CLK 94 +#define CAMSS_PHY0_CSI0PHYTIMER_CLK 95 +#define CAMSS_PHY1_CSI1PHYTIMER_CLK 96 +#define CAMSS_PHY2_CSI2PHYTIMER_CLK 97 +#define CAMSS_TOP_AHB_CLK 98 +#define CAMSS_VFE_VFE0_CLK 99 +#define CAMSS_VFE_VFE1_CLK 100 +#define CAMSS_VFE_VFE_AHB_CLK 101 +#define CAMSS_VFE_VFE_AXI_CLK 102 +#define FD_AXI_CLK 103 +#define FD_CORE_CLK 104 +#define FD_CORE_UAR_CLK 105 +#define MDSS_AXI_CLK 106 +#define MDSS_EXTPCLK_CLK 107 +#define MDSS_HDMI_AHB_CLK 108 +#define MDSS_HDMI_CLK 109 +#define MDSS_MDP_CLK 110 +#define MMSS_MISC_AHB_CLK 111 +#define MMSS_MMSSNOC_AXI_CLK 112 +#define MMSS_S0_AXI_CLK 113 +#define OCMEMCX_OCMEMNOC_CLK 114 +#define OXILI_GFX3D_CLK 115 +#define OXILI_RBBMTIMER_CLK 116 +#define OXILICX_AHB_CLK 117 +#define VENUS0_AHB_CLK 118 +#define VENUS0_AXI_CLK 119 +#define VENUS0_OCMEMNOC_CLK 120 +#define VENUS0_VCODEC0_CLK 121 +#define VENUS0_CORE0_VCODEC_CLK 122 +#define VENUS0_CORE1_VCODEC_CLK 123 +#define VENUS0_CORE2_VCODEC_CLK 124 +#define AHB_CLK_SRC 125 +#define FD_AHB_CLK 126 + +/* GDSCs */ +#define VENUS_GDSC 0 +#define VENUS_CORE0_GDSC 1 +#define VENUS_CORE1_GDSC 2 +#define VENUS_CORE2_GDSC 3 +#define CAMSS_TOP_GDSC 4 +#define MDSS_GDSC 5 +#define JPEG_GDSC 6 +#define VFE_GDSC 7 +#define CPP_GDSC 8 +#define OXILI_GX_GDSC 9 +#define OXILI_CX_GDSC 10 +#define FD_GDSC 11 + +/* Resets */ +#define CAMSS_MICRO_BCR 0 + +#endif diff --git a/include/dt-bindings/clock/qcom,mmcc-sdm660.h b/include/dt-bindings/clock/qcom,mmcc-sdm660.h new file mode 100644 index 000000000000..f9dbc21cb5c7 --- /dev/null +++ b/include/dt-bindings/clock/qcom,mmcc-sdm660.h @@ -0,0 +1,162 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_MSM_MMCC_660_H +#define _DT_BINDINGS_CLK_MSM_MMCC_660_H + +#define AHB_CLK_SRC 0 +#define BYTE0_CLK_SRC 1 +#define BYTE1_CLK_SRC 2 +#define CAMSS_GP0_CLK_SRC 3 +#define CAMSS_GP1_CLK_SRC 4 +#define CCI_CLK_SRC 5 +#define CPP_CLK_SRC 6 +#define CSI0_CLK_SRC 7 +#define CSI0PHYTIMER_CLK_SRC 8 +#define CSI1_CLK_SRC 9 +#define CSI1PHYTIMER_CLK_SRC 10 +#define CSI2_CLK_SRC 11 +#define CSI2PHYTIMER_CLK_SRC 12 +#define CSI3_CLK_SRC 13 +#define CSIPHY_CLK_SRC 14 +#define DP_AUX_CLK_SRC 15 +#define DP_CRYPTO_CLK_SRC 16 +#define DP_GTC_CLK_SRC 17 +#define DP_LINK_CLK_SRC 18 +#define DP_PIXEL_CLK_SRC 19 +#define ESC0_CLK_SRC 20 +#define ESC1_CLK_SRC 21 +#define JPEG0_CLK_SRC 22 +#define MCLK0_CLK_SRC 23 +#define MCLK1_CLK_SRC 24 +#define MCLK2_CLK_SRC 25 +#define MCLK3_CLK_SRC 26 +#define MDP_CLK_SRC 27 +#define MMPLL0_PLL 28 +#define MMPLL10_PLL 29 +#define MMPLL1_PLL 30 +#define MMPLL3_PLL 31 +#define MMPLL4_PLL 32 +#define MMPLL5_PLL 33 +#define MMPLL6_PLL 34 +#define MMPLL7_PLL 35 +#define MMPLL8_PLL 36 +#define BIMC_SMMU_AHB_CLK 37 +#define BIMC_SMMU_AXI_CLK 38 +#define CAMSS_AHB_CLK 39 +#define CAMSS_CCI_AHB_CLK 40 +#define CAMSS_CCI_CLK 41 +#define CAMSS_CPHY_CSID0_CLK 42 +#define CAMSS_CPHY_CSID1_CLK 43 +#define CAMSS_CPHY_CSID2_CLK 44 +#define CAMSS_CPHY_CSID3_CLK 45 +#define CAMSS_CPP_AHB_CLK 46 +#define CAMSS_CPP_AXI_CLK 47 +#define CAMSS_CPP_CLK 48 +#define CAMSS_CPP_VBIF_AHB_CLK 49 +#define CAMSS_CSI0_AHB_CLK 50 +#define CAMSS_CSI0_CLK 51 +#define CAMSS_CSI0PHYTIMER_CLK 52 +#define CAMSS_CSI0PIX_CLK 53 +#define CAMSS_CSI0RDI_CLK 54 +#define CAMSS_CSI1_AHB_CLK 55 +#define CAMSS_CSI1_CLK 56 +#define CAMSS_CSI1PHYTIMER_CLK 57 +#define CAMSS_CSI1PIX_CLK 58 +#define CAMSS_CSI1RDI_CLK 59 +#define CAMSS_CSI2_AHB_CLK 60 +#define CAMSS_CSI2_CLK 61 +#define CAMSS_CSI2PHYTIMER_CLK 62 +#define CAMSS_CSI2PIX_CLK 63 +#define CAMSS_CSI2RDI_CLK 64 +#define CAMSS_CSI3_AHB_CLK 65 +#define CAMSS_CSI3_CLK 66 +#define CAMSS_CSI3PIX_CLK 67 +#define CAMSS_CSI3RDI_CLK 68 +#define CAMSS_CSI_VFE0_CLK 69 +#define CAMSS_CSI_VFE1_CLK 70 +#define CAMSS_CSIPHY0_CLK 71 +#define CAMSS_CSIPHY1_CLK 72 +#define CAMSS_CSIPHY2_CLK 73 +#define CAMSS_GP0_CLK 74 +#define CAMSS_GP1_CLK 75 +#define CAMSS_ISPIF_AHB_CLK 76 +#define CAMSS_JPEG0_CLK 77 +#define CAMSS_JPEG_AHB_CLK 78 +#define CAMSS_JPEG_AXI_CLK 79 +#define CAMSS_MCLK0_CLK 80 +#define CAMSS_MCLK1_CLK 81 +#define CAMSS_MCLK2_CLK 82 +#define CAMSS_MCLK3_CLK 83 +#define CAMSS_MICRO_AHB_CLK 84 +#define CAMSS_TOP_AHB_CLK 85 +#define CAMSS_VFE0_AHB_CLK 86 +#define CAMSS_VFE0_CLK 87 +#define CAMSS_VFE0_STREAM_CLK 88 +#define CAMSS_VFE1_AHB_CLK 89 +#define CAMSS_VFE1_CLK 90 +#define CAMSS_VFE1_STREAM_CLK 91 +#define CAMSS_VFE_VBIF_AHB_CLK 92 +#define CAMSS_VFE_VBIF_AXI_CLK 93 +#define CSIPHY_AHB2CRIF_CLK 94 +#define CXO_CLK 95 +#define MDSS_AHB_CLK 96 +#define MDSS_AXI_CLK 97 +#define MDSS_BYTE0_CLK 98 +#define MDSS_BYTE0_INTF_CLK 99 +#define MDSS_BYTE0_INTF_DIV_CLK 100 +#define MDSS_BYTE1_CLK 101 +#define MDSS_BYTE1_INTF_CLK 102 +#define MDSS_DP_AUX_CLK 103 +#define MDSS_DP_CRYPTO_CLK 104 +#define MDSS_DP_GTC_CLK 105 +#define MDSS_DP_LINK_CLK 106 +#define MDSS_DP_LINK_INTF_CLK 107 +#define MDSS_DP_PIXEL_CLK 108 +#define MDSS_ESC0_CLK 109 +#define MDSS_ESC1_CLK 110 +#define MDSS_HDMI_DP_AHB_CLK 111 +#define MDSS_MDP_CLK 112 +#define MDSS_PCLK0_CLK 113 +#define MDSS_PCLK1_CLK 114 +#define MDSS_ROT_CLK 115 +#define MDSS_VSYNC_CLK 116 +#define MISC_AHB_CLK 117 +#define MISC_CXO_CLK 118 +#define MNOC_AHB_CLK 119 +#define SNOC_DVM_AXI_CLK 120 +#define THROTTLE_CAMSS_AHB_CLK 121 +#define THROTTLE_CAMSS_AXI_CLK 122 +#define THROTTLE_MDSS_AHB_CLK 123 +#define THROTTLE_MDSS_AXI_CLK 124 +#define THROTTLE_VIDEO_AHB_CLK 125 +#define THROTTLE_VIDEO_AXI_CLK 126 +#define VIDEO_AHB_CLK 127 +#define VIDEO_AXI_CLK 128 +#define VIDEO_CORE_CLK 129 +#define VIDEO_SUBCORE0_CLK 130 +#define PCLK0_CLK_SRC 131 +#define PCLK1_CLK_SRC 132 +#define ROT_CLK_SRC 133 +#define VFE0_CLK_SRC 134 +#define VFE1_CLK_SRC 135 +#define VIDEO_CORE_CLK_SRC 136 +#define VSYNC_CLK_SRC 137 +#define MDSS_BYTE1_INTF_DIV_CLK 138 +#define AXI_CLK_SRC 139 + +#define VENUS_GDSC 0 +#define VENUS_CORE0_GDSC 1 +#define MDSS_GDSC 2 +#define CAMSS_TOP_GDSC 3 +#define CAMSS_VFE0_GDSC 4 +#define CAMSS_VFE1_GDSC 5 +#define CAMSS_CPP_GDSC 6 +#define BIMC_SMMU_GDSC 7 + +#define CAMSS_MICRO_BCR 0 + +#endif + diff --git a/include/dt-bindings/clock/qcom,mss-sc7180.h b/include/dt-bindings/clock/qcom,mss-sc7180.h new file mode 100644 index 000000000000..f15a9ded2961 --- /dev/null +++ b/include/dt-bindings/clock/qcom,mss-sc7180.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_MSS_SC7180_H +#define _DT_BINDINGS_CLK_QCOM_MSS_SC7180_H + +#define MSS_AXI_CRYPTO_CLK 0 +#define MSS_AXI_NAV_CLK 1 + +#endif diff --git a/include/dt-bindings/clock/qcom,rpmcc.h b/include/dt-bindings/clock/qcom,rpmcc.h index 8e3095720552..c0ad624e930e 100644 --- a/include/dt-bindings/clock/qcom,rpmcc.h +++ b/include/dt-bindings/clock/qcom,rpmcc.h @@ -37,6 +37,10 @@ #define RPM_XO_A0 27 #define RPM_XO_A1 28 #define RPM_XO_A2 29 +#define RPM_NSS_FABRIC_0_CLK 30 +#define RPM_NSS_FABRIC_0_A_CLK 31 +#define RPM_NSS_FABRIC_1_CLK 32 +#define RPM_NSS_FABRIC_1_A_CLK 33 /* SMD RPM clocks */ #define RPM_SMD_XO_CLK_SRC 0 @@ -129,5 +133,40 @@ #define RPM_SMD_RF_CLK3_A 87 #define RPM_SMD_RF_CLK3_PIN 88 #define RPM_SMD_RF_CLK3_A_PIN 89 +#define RPM_SMD_MMSSNOC_AXI_CLK 90 +#define RPM_SMD_MMSSNOC_AXI_CLK_A 91 +#define RPM_SMD_CNOC_PERIPH_CLK 92 +#define RPM_SMD_CNOC_PERIPH_A_CLK 93 +#define RPM_SMD_LN_BB_CLK3 94 +#define RPM_SMD_LN_BB_CLK3_A 95 +#define RPM_SMD_LN_BB_CLK1_PIN 96 +#define RPM_SMD_LN_BB_CLK1_A_PIN 97 +#define RPM_SMD_LN_BB_CLK2_PIN 98 +#define RPM_SMD_LN_BB_CLK2_A_PIN 99 +#define RPM_SMD_SYSMMNOC_CLK 100 +#define RPM_SMD_SYSMMNOC_A_CLK 101 +#define RPM_SMD_CE2_CLK 102 +#define RPM_SMD_CE2_A_CLK 103 +#define RPM_SMD_CE3_CLK 104 +#define RPM_SMD_CE3_A_CLK 105 +#define RPM_SMD_QUP_CLK 106 +#define RPM_SMD_QUP_A_CLK 107 +#define RPM_SMD_MMRT_CLK 108 +#define RPM_SMD_MMRT_A_CLK 109 +#define RPM_SMD_MMNRT_CLK 110 +#define RPM_SMD_MMNRT_A_CLK 111 +#define RPM_SMD_SNOC_PERIPH_CLK 112 +#define RPM_SMD_SNOC_PERIPH_A_CLK 113 +#define RPM_SMD_SNOC_LPASS_CLK 114 +#define RPM_SMD_SNOC_LPASS_A_CLK 115 +#define RPM_SMD_HWKM_CLK 116 +#define RPM_SMD_HWKM_A_CLK 117 +#define RPM_SMD_PKA_CLK 118 +#define RPM_SMD_PKA_A_CLK 119 +#define RPM_SMD_CPUSS_GNOC_CLK 120 +#define RPM_SMD_CPUSS_GNOC_A_CLK 121 +#define RPM_SMD_MSS_CFG_AHB_CLK 122 +#define RPM_SMD_MSS_CFG_AHB_A_CLK 123 +#define RPM_SMD_BIMC_FREQ_LOG 124 #endif diff --git a/include/dt-bindings/clock/qcom,rpmh.h b/include/dt-bindings/clock/qcom,rpmh.h index edcab3f7b7d3..0a7d1be0d124 100644 --- a/include/dt-bindings/clock/qcom,rpmh.h +++ b/include/dt-bindings/clock/qcom,rpmh.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0 */ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */ +/* Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved. */ #ifndef _DT_BINDINGS_CLK_MSM_RPMH_H @@ -19,5 +19,19 @@ #define RPMH_RF_CLK3 10 #define RPMH_RF_CLK3_A 11 #define RPMH_IPA_CLK 12 +#define RPMH_LN_BB_CLK1 13 +#define RPMH_LN_BB_CLK1_A 14 +#define RPMH_CE_CLK 15 +#define RPMH_QPIC_CLK 16 +#define RPMH_DIV_CLK1 17 +#define RPMH_DIV_CLK1_A 18 +#define RPMH_RF_CLK4 19 +#define RPMH_RF_CLK4_A 20 +#define RPMH_RF_CLK5 21 +#define RPMH_RF_CLK5_A 22 +#define RPMH_PKA_CLK 23 +#define RPMH_HWKM_CLK 24 +#define RPMH_QLINK_CLK 25 +#define RPMH_QLINK_CLK_A 26 #endif diff --git a/include/dt-bindings/clock/qcom,sm6115-dispcc.h b/include/dt-bindings/clock/qcom,sm6115-dispcc.h new file mode 100644 index 000000000000..d1a6c45b5029 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm6115-dispcc.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6115_H +#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6115_H + +/* DISP_CC clocks */ +#define DISP_CC_PLL0 0 +#define DISP_CC_PLL0_OUT_MAIN 1 +#define DISP_CC_MDSS_AHB_CLK 2 +#define DISP_CC_MDSS_AHB_CLK_SRC 3 +#define DISP_CC_MDSS_BYTE0_CLK 4 +#define DISP_CC_MDSS_BYTE0_CLK_SRC 5 +#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 6 +#define DISP_CC_MDSS_BYTE0_INTF_CLK 7 +#define DISP_CC_MDSS_ESC0_CLK 8 +#define DISP_CC_MDSS_ESC0_CLK_SRC 9 +#define DISP_CC_MDSS_MDP_CLK 10 +#define DISP_CC_MDSS_MDP_CLK_SRC 11 +#define DISP_CC_MDSS_MDP_LUT_CLK 12 +#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 13 +#define DISP_CC_MDSS_PCLK0_CLK 14 +#define DISP_CC_MDSS_PCLK0_CLK_SRC 15 +#define DISP_CC_MDSS_ROT_CLK 16 +#define DISP_CC_MDSS_ROT_CLK_SRC 17 +#define DISP_CC_MDSS_VSYNC_CLK 18 +#define DISP_CC_MDSS_VSYNC_CLK_SRC 19 +#define DISP_CC_SLEEP_CLK 20 +#define DISP_CC_SLEEP_CLK_SRC 21 + +/* DISP_CC GDSCR */ +#define MDSS_GDSC 0 + +#endif diff --git a/include/dt-bindings/clock/qcom,sm6375-gcc.h b/include/dt-bindings/clock/qcom,sm6375-gcc.h new file mode 100644 index 000000000000..1e9801e1cedf --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm6375-gcc.h @@ -0,0 +1,234 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Konrad Dybcio <konrad.dybcio@somainline.org> + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM6375_H +#define _DT_BINDINGS_CLK_QCOM_GCC_SM6375_H + +/* Clocks */ +#define GPLL0 0 +#define GPLL0_OUT_EVEN 1 +#define GPLL0_OUT_ODD 2 +#define GPLL1 3 +#define GPLL10 4 +#define GPLL11 5 +#define GPLL3 6 +#define GPLL3_OUT_EVEN 7 +#define GPLL4 8 +#define GPLL5 9 +#define GPLL6 10 +#define GPLL6_OUT_EVEN 11 +#define GPLL7 12 +#define GPLL8 13 +#define GPLL8_OUT_EVEN 14 +#define GPLL9 15 +#define GPLL9_OUT_MAIN 16 +#define GCC_AHB2PHY_CSI_CLK 17 +#define GCC_AHB2PHY_USB_CLK 18 +#define GCC_BIMC_GPU_AXI_CLK 19 +#define GCC_BOOT_ROM_AHB_CLK 20 +#define GCC_CAM_THROTTLE_NRT_CLK 21 +#define GCC_CAM_THROTTLE_RT_CLK 22 +#define GCC_CAMERA_AHB_CLK 23 +#define GCC_CAMERA_XO_CLK 24 +#define GCC_CAMSS_AXI_CLK 25 +#define GCC_CAMSS_AXI_CLK_SRC 26 +#define GCC_CAMSS_CAMNOC_ATB_CLK 27 +#define GCC_CAMSS_CAMNOC_NTS_XO_CLK 28 +#define GCC_CAMSS_CCI_0_CLK 29 +#define GCC_CAMSS_CCI_0_CLK_SRC 30 +#define GCC_CAMSS_CCI_1_CLK 31 +#define GCC_CAMSS_CCI_1_CLK_SRC 32 +#define GCC_CAMSS_CPHY_0_CLK 33 +#define GCC_CAMSS_CPHY_1_CLK 34 +#define GCC_CAMSS_CPHY_2_CLK 35 +#define GCC_CAMSS_CPHY_3_CLK 36 +#define GCC_CAMSS_CSI0PHYTIMER_CLK 37 +#define GCC_CAMSS_CSI0PHYTIMER_CLK_SRC 38 +#define GCC_CAMSS_CSI1PHYTIMER_CLK 39 +#define GCC_CAMSS_CSI1PHYTIMER_CLK_SRC 40 +#define GCC_CAMSS_CSI2PHYTIMER_CLK 41 +#define GCC_CAMSS_CSI2PHYTIMER_CLK_SRC 42 +#define GCC_CAMSS_CSI3PHYTIMER_CLK 43 +#define GCC_CAMSS_CSI3PHYTIMER_CLK_SRC 44 +#define GCC_CAMSS_MCLK0_CLK 45 +#define GCC_CAMSS_MCLK0_CLK_SRC 46 +#define GCC_CAMSS_MCLK1_CLK 47 +#define GCC_CAMSS_MCLK1_CLK_SRC 48 +#define GCC_CAMSS_MCLK2_CLK 49 +#define GCC_CAMSS_MCLK2_CLK_SRC 50 +#define GCC_CAMSS_MCLK3_CLK 51 +#define GCC_CAMSS_MCLK3_CLK_SRC 52 +#define GCC_CAMSS_MCLK4_CLK 53 +#define GCC_CAMSS_MCLK4_CLK_SRC 54 +#define GCC_CAMSS_NRT_AXI_CLK 55 +#define GCC_CAMSS_OPE_AHB_CLK 56 +#define GCC_CAMSS_OPE_AHB_CLK_SRC 57 +#define GCC_CAMSS_OPE_CLK 58 +#define GCC_CAMSS_OPE_CLK_SRC 59 +#define GCC_CAMSS_RT_AXI_CLK 60 +#define GCC_CAMSS_TFE_0_CLK 61 +#define GCC_CAMSS_TFE_0_CLK_SRC 62 +#define GCC_CAMSS_TFE_0_CPHY_RX_CLK 63 +#define GCC_CAMSS_TFE_0_CSID_CLK 64 +#define GCC_CAMSS_TFE_0_CSID_CLK_SRC 65 +#define GCC_CAMSS_TFE_1_CLK 66 +#define GCC_CAMSS_TFE_1_CLK_SRC 67 +#define GCC_CAMSS_TFE_1_CPHY_RX_CLK 68 +#define GCC_CAMSS_TFE_1_CSID_CLK 69 +#define GCC_CAMSS_TFE_1_CSID_CLK_SRC 70 +#define GCC_CAMSS_TFE_2_CLK 71 +#define GCC_CAMSS_TFE_2_CLK_SRC 72 +#define GCC_CAMSS_TFE_2_CPHY_RX_CLK 73 +#define GCC_CAMSS_TFE_2_CSID_CLK 74 +#define GCC_CAMSS_TFE_2_CSID_CLK_SRC 75 +#define GCC_CAMSS_TFE_CPHY_RX_CLK_SRC 76 +#define GCC_CAMSS_TOP_AHB_CLK 77 +#define GCC_CAMSS_TOP_AHB_CLK_SRC 78 +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 79 +#define GCC_CPUSS_AHB_CLK_SRC 80 +#define GCC_CPUSS_AHB_POSTDIV_CLK_SRC 81 +#define GCC_CPUSS_GNOC_CLK 82 +#define GCC_DISP_AHB_CLK 83 +#define GCC_DISP_GPLL0_CLK_SRC 84 +#define GCC_DISP_GPLL0_DIV_CLK_SRC 85 +#define GCC_DISP_HF_AXI_CLK 86 +#define GCC_DISP_SLEEP_CLK 87 +#define GCC_DISP_THROTTLE_CORE_CLK 88 +#define GCC_DISP_XO_CLK 89 +#define GCC_GP1_CLK 90 +#define GCC_GP1_CLK_SRC 91 +#define GCC_GP2_CLK 92 +#define GCC_GP2_CLK_SRC 93 +#define GCC_GP3_CLK 94 +#define GCC_GP3_CLK_SRC 95 +#define GCC_GPU_CFG_AHB_CLK 96 +#define GCC_GPU_GPLL0_CLK_SRC 97 +#define GCC_GPU_GPLL0_DIV_CLK_SRC 98 +#define GCC_GPU_MEMNOC_GFX_CLK 99 +#define GCC_GPU_SNOC_DVM_GFX_CLK 100 +#define GCC_GPU_THROTTLE_CORE_CLK 101 +#define GCC_PDM2_CLK 102 +#define GCC_PDM2_CLK_SRC 103 +#define GCC_PDM_AHB_CLK 104 +#define GCC_PDM_XO4_CLK 105 +#define GCC_PRNG_AHB_CLK 106 +#define GCC_QMIP_CAMERA_NRT_AHB_CLK 107 +#define GCC_QMIP_CAMERA_RT_AHB_CLK 108 +#define GCC_QMIP_DISP_AHB_CLK 109 +#define GCC_QMIP_GPU_CFG_AHB_CLK 110 +#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 111 +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 112 +#define GCC_QUPV3_WRAP0_CORE_CLK 113 +#define GCC_QUPV3_WRAP0_S0_CLK 114 +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 115 +#define GCC_QUPV3_WRAP0_S1_CLK 116 +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 117 +#define GCC_QUPV3_WRAP0_S2_CLK 118 +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 119 +#define GCC_QUPV3_WRAP0_S3_CLK 120 +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 121 +#define GCC_QUPV3_WRAP0_S4_CLK 122 +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 123 +#define GCC_QUPV3_WRAP0_S5_CLK 124 +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 125 +#define GCC_QUPV3_WRAP1_CORE_2X_CLK 126 +#define GCC_QUPV3_WRAP1_CORE_CLK 127 +#define GCC_QUPV3_WRAP1_S0_CLK 128 +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 129 +#define GCC_QUPV3_WRAP1_S1_CLK 130 +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 131 +#define GCC_QUPV3_WRAP1_S2_CLK 132 +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 133 +#define GCC_QUPV3_WRAP1_S3_CLK 134 +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 135 +#define GCC_QUPV3_WRAP1_S4_CLK 136 +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 137 +#define GCC_QUPV3_WRAP1_S5_CLK 138 +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 139 +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 140 +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 141 +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 142 +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 143 +#define GCC_RX5_PCIE_CLKREF_EN_CLK 144 +#define GCC_SDCC1_AHB_CLK 145 +#define GCC_SDCC1_APPS_CLK 146 +#define GCC_SDCC1_APPS_CLK_SRC 147 +#define GCC_SDCC1_ICE_CORE_CLK 148 +#define GCC_SDCC1_ICE_CORE_CLK_SRC 149 +#define GCC_SDCC2_AHB_CLK 150 +#define GCC_SDCC2_APPS_CLK 151 +#define GCC_SDCC2_APPS_CLK_SRC 152 +#define GCC_SYS_NOC_CPUSS_AHB_CLK 153 +#define GCC_SYS_NOC_UFS_PHY_AXI_CLK 154 +#define GCC_SYS_NOC_USB3_PRIM_AXI_CLK 155 +#define GCC_UFS_MEM_CLKREF_CLK 156 +#define GCC_UFS_PHY_AHB_CLK 157 +#define GCC_UFS_PHY_AXI_CLK 158 +#define GCC_UFS_PHY_AXI_CLK_SRC 159 +#define GCC_UFS_PHY_ICE_CORE_CLK 160 +#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 161 +#define GCC_UFS_PHY_PHY_AUX_CLK 162 +#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 163 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 164 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 165 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK 166 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 167 +#define GCC_USB30_PRIM_MASTER_CLK 168 +#define GCC_USB30_PRIM_MASTER_CLK_SRC 169 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 170 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 171 +#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 172 +#define GCC_USB30_PRIM_SLEEP_CLK 173 +#define GCC_USB3_PRIM_CLKREF_CLK 174 +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 175 +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 176 +#define GCC_USB3_PRIM_PHY_PIPE_CLK 177 +#define GCC_VCODEC0_AXI_CLK 178 +#define GCC_VENUS_AHB_CLK 179 +#define GCC_VENUS_CTL_AXI_CLK 180 +#define GCC_VIDEO_AHB_CLK 181 +#define GCC_VIDEO_AXI0_CLK 182 +#define GCC_VIDEO_THROTTLE_CORE_CLK 183 +#define GCC_VIDEO_VCODEC0_SYS_CLK 184 +#define GCC_VIDEO_VENUS_CLK_SRC 185 +#define GCC_VIDEO_VENUS_CTL_CLK 186 +#define GCC_VIDEO_XO_CLK 187 + +/* Resets */ +#define GCC_CAMSS_OPE_BCR 0 +#define GCC_CAMSS_TFE_BCR 1 +#define GCC_CAMSS_TOP_BCR 2 +#define GCC_GPU_BCR 3 +#define GCC_MMSS_BCR 4 +#define GCC_PDM_BCR 5 +#define GCC_PRNG_BCR 6 +#define GCC_QUPV3_WRAPPER_0_BCR 7 +#define GCC_QUPV3_WRAPPER_1_BCR 8 +#define GCC_QUSB2PHY_PRIM_BCR 9 +#define GCC_QUSB2PHY_SEC_BCR 10 +#define GCC_SDCC1_BCR 11 +#define GCC_SDCC2_BCR 12 +#define GCC_UFS_PHY_BCR 13 +#define GCC_USB30_PRIM_BCR 14 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 15 +#define GCC_VCODEC0_BCR 16 +#define GCC_VENUS_BCR 17 +#define GCC_VIDEO_INTERFACE_BCR 18 +#define GCC_USB3_DP_PHY_PRIM_BCR 19 +#define GCC_USB3_PHY_PRIM_SP0_BCR 20 + +/* GDSCs */ +#define USB30_PRIM_GDSC 0 +#define UFS_PHY_GDSC 1 +#define CAMSS_TOP_GDSC 2 +#define VENUS_GDSC 3 +#define VCODEC0_GDSC 4 +#define HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC 5 +#define HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC 6 +#define HLOS1_VOTE_TURING_MMU_TBU0_GDSC 7 +#define HLOS1_VOTE_TURING_MMU_TBU1_GDSC 8 + +#endif diff --git a/include/dt-bindings/clock/qcom,sm8250-lpass-aoncc.h b/include/dt-bindings/clock/qcom,sm8250-lpass-aoncc.h new file mode 100644 index 000000000000..f5a1cfac8612 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8250-lpass-aoncc.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef _DT_BINDINGS_CLK_LPASS_AONCC_SM8250_H +#define _DT_BINDINGS_CLK_LPASS_AONCC_SM8250_H + +/* from AOCC */ +#define LPASS_CDC_VA_MCLK 0 +#define LPASS_CDC_TX_NPL 1 +#define LPASS_CDC_TX_MCLK 2 + +#endif /* _DT_BINDINGS_CLK_LPASS_AONCC_SM8250_H */ diff --git a/include/dt-bindings/clock/qcom,sm8250-lpass-audiocc.h b/include/dt-bindings/clock/qcom,sm8250-lpass-audiocc.h new file mode 100644 index 000000000000..a1aa6cb5d840 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8250-lpass-audiocc.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef _DT_BINDINGS_CLK_LPASS_AUDIOCC_SM8250_H +#define _DT_BINDINGS_CLK_LPASS_AUDIOCC_SM8250_H + +/* From AudioCC */ +#define LPASS_CDC_WSA_NPL 0 +#define LPASS_CDC_WSA_MCLK 1 +#define LPASS_CDC_RX_MCLK 2 +#define LPASS_CDC_RX_NPL 3 +#define LPASS_CDC_RX_MCLK_MCLK2 4 + +#endif /* _DT_BINDINGS_CLK_LPASS_AUDIOCC_SM8250_H */ diff --git a/include/dt-bindings/clock/qcom,sm8450-camcc.h b/include/dt-bindings/clock/qcom,sm8450-camcc.h new file mode 100644 index 000000000000..7ff67acf301a --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8450-camcc.h @@ -0,0 +1,159 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8450_H +#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8450_H + +/* CAM_CC clocks */ +#define CAM_CC_BPS_AHB_CLK 0 +#define CAM_CC_BPS_CLK 1 +#define CAM_CC_BPS_CLK_SRC 2 +#define CAM_CC_BPS_FAST_AHB_CLK 3 +#define CAM_CC_CAMNOC_AXI_CLK 4 +#define CAM_CC_CAMNOC_AXI_CLK_SRC 5 +#define CAM_CC_CAMNOC_DCD_XO_CLK 6 +#define CAM_CC_CCI_0_CLK 7 +#define CAM_CC_CCI_0_CLK_SRC 8 +#define CAM_CC_CCI_1_CLK 9 +#define CAM_CC_CCI_1_CLK_SRC 10 +#define CAM_CC_CORE_AHB_CLK 11 +#define CAM_CC_CPAS_AHB_CLK 12 +#define CAM_CC_CPAS_BPS_CLK 13 +#define CAM_CC_CPAS_FAST_AHB_CLK 14 +#define CAM_CC_CPAS_IFE_0_CLK 15 +#define CAM_CC_CPAS_IFE_1_CLK 16 +#define CAM_CC_CPAS_IFE_2_CLK 17 +#define CAM_CC_CPAS_IFE_LITE_CLK 18 +#define CAM_CC_CPAS_IPE_NPS_CLK 19 +#define CAM_CC_CPAS_SBI_CLK 20 +#define CAM_CC_CPAS_SFE_0_CLK 21 +#define CAM_CC_CPAS_SFE_1_CLK 22 +#define CAM_CC_CPHY_RX_CLK_SRC 23 +#define CAM_CC_CSI0PHYTIMER_CLK 24 +#define CAM_CC_CSI0PHYTIMER_CLK_SRC 25 +#define CAM_CC_CSI1PHYTIMER_CLK 26 +#define CAM_CC_CSI1PHYTIMER_CLK_SRC 27 +#define CAM_CC_CSI2PHYTIMER_CLK 28 +#define CAM_CC_CSI2PHYTIMER_CLK_SRC 29 +#define CAM_CC_CSI3PHYTIMER_CLK 30 +#define CAM_CC_CSI3PHYTIMER_CLK_SRC 31 +#define CAM_CC_CSI4PHYTIMER_CLK 32 +#define CAM_CC_CSI4PHYTIMER_CLK_SRC 33 +#define CAM_CC_CSI5PHYTIMER_CLK 34 +#define CAM_CC_CSI5PHYTIMER_CLK_SRC 35 +#define CAM_CC_CSID_CLK 36 +#define CAM_CC_CSID_CLK_SRC 37 +#define CAM_CC_CSID_CSIPHY_RX_CLK 38 +#define CAM_CC_CSIPHY0_CLK 39 +#define CAM_CC_CSIPHY1_CLK 40 +#define CAM_CC_CSIPHY2_CLK 41 +#define CAM_CC_CSIPHY3_CLK 42 +#define CAM_CC_CSIPHY4_CLK 43 +#define CAM_CC_CSIPHY5_CLK 44 +#define CAM_CC_FAST_AHB_CLK_SRC 45 +#define CAM_CC_GDSC_CLK 46 +#define CAM_CC_ICP_AHB_CLK 47 +#define CAM_CC_ICP_CLK 48 +#define CAM_CC_ICP_CLK_SRC 49 +#define CAM_CC_IFE_0_CLK 50 +#define CAM_CC_IFE_0_CLK_SRC 51 +#define CAM_CC_IFE_0_DSP_CLK 52 +#define CAM_CC_IFE_0_FAST_AHB_CLK 53 +#define CAM_CC_IFE_1_CLK 54 +#define CAM_CC_IFE_1_CLK_SRC 55 +#define CAM_CC_IFE_1_DSP_CLK 56 +#define CAM_CC_IFE_1_FAST_AHB_CLK 57 +#define CAM_CC_IFE_2_CLK 58 +#define CAM_CC_IFE_2_CLK_SRC 59 +#define CAM_CC_IFE_2_DSP_CLK 60 +#define CAM_CC_IFE_2_FAST_AHB_CLK 61 +#define CAM_CC_IFE_LITE_AHB_CLK 62 +#define CAM_CC_IFE_LITE_CLK 63 +#define CAM_CC_IFE_LITE_CLK_SRC 64 +#define CAM_CC_IFE_LITE_CPHY_RX_CLK 65 +#define CAM_CC_IFE_LITE_CSID_CLK 66 +#define CAM_CC_IFE_LITE_CSID_CLK_SRC 67 +#define CAM_CC_IPE_NPS_AHB_CLK 68 +#define CAM_CC_IPE_NPS_CLK 69 +#define CAM_CC_IPE_NPS_CLK_SRC 70 +#define CAM_CC_IPE_NPS_FAST_AHB_CLK 71 +#define CAM_CC_IPE_PPS_CLK 72 +#define CAM_CC_IPE_PPS_FAST_AHB_CLK 73 +#define CAM_CC_JPEG_CLK 74 +#define CAM_CC_JPEG_CLK_SRC 75 +#define CAM_CC_MCLK0_CLK 76 +#define CAM_CC_MCLK0_CLK_SRC 77 +#define CAM_CC_MCLK1_CLK 78 +#define CAM_CC_MCLK1_CLK_SRC 79 +#define CAM_CC_MCLK2_CLK 80 +#define CAM_CC_MCLK2_CLK_SRC 81 +#define CAM_CC_MCLK3_CLK 82 +#define CAM_CC_MCLK3_CLK_SRC 83 +#define CAM_CC_MCLK4_CLK 84 +#define CAM_CC_MCLK4_CLK_SRC 85 +#define CAM_CC_MCLK5_CLK 86 +#define CAM_CC_MCLK5_CLK_SRC 87 +#define CAM_CC_MCLK6_CLK 88 +#define CAM_CC_MCLK6_CLK_SRC 89 +#define CAM_CC_MCLK7_CLK 90 +#define CAM_CC_MCLK7_CLK_SRC 91 +#define CAM_CC_PLL0 92 +#define CAM_CC_PLL0_OUT_EVEN 93 +#define CAM_CC_PLL0_OUT_ODD 94 +#define CAM_CC_PLL1 95 +#define CAM_CC_PLL1_OUT_EVEN 96 +#define CAM_CC_PLL2 97 +#define CAM_CC_PLL3 98 +#define CAM_CC_PLL3_OUT_EVEN 99 +#define CAM_CC_PLL4 100 +#define CAM_CC_PLL4_OUT_EVEN 101 +#define CAM_CC_PLL5 102 +#define CAM_CC_PLL5_OUT_EVEN 103 +#define CAM_CC_PLL6 104 +#define CAM_CC_PLL6_OUT_EVEN 105 +#define CAM_CC_PLL7 106 +#define CAM_CC_PLL7_OUT_EVEN 107 +#define CAM_CC_PLL8 108 +#define CAM_CC_PLL8_OUT_EVEN 109 +#define CAM_CC_QDSS_DEBUG_CLK 110 +#define CAM_CC_QDSS_DEBUG_CLK_SRC 111 +#define CAM_CC_QDSS_DEBUG_XO_CLK 112 +#define CAM_CC_SBI_AHB_CLK 113 +#define CAM_CC_SBI_CLK 114 +#define CAM_CC_SFE_0_CLK 115 +#define CAM_CC_SFE_0_CLK_SRC 116 +#define CAM_CC_SFE_0_FAST_AHB_CLK 117 +#define CAM_CC_SFE_1_CLK 118 +#define CAM_CC_SFE_1_CLK_SRC 119 +#define CAM_CC_SFE_1_FAST_AHB_CLK 120 +#define CAM_CC_SLEEP_CLK 121 +#define CAM_CC_SLEEP_CLK_SRC 122 +#define CAM_CC_SLOW_AHB_CLK_SRC 123 +#define CAM_CC_XO_CLK_SRC 124 + +/* CAM_CC resets */ +#define CAM_CC_BPS_BCR 0 +#define CAM_CC_ICP_BCR 1 +#define CAM_CC_IFE_0_BCR 2 +#define CAM_CC_IFE_1_BCR 3 +#define CAM_CC_IFE_2_BCR 4 +#define CAM_CC_IPE_0_BCR 5 +#define CAM_CC_QDSS_DEBUG_BCR 6 +#define CAM_CC_SBI_BCR 7 +#define CAM_CC_SFE_0_BCR 8 +#define CAM_CC_SFE_1_BCR 9 + +/* CAM_CC GDSCRs */ +#define BPS_GDSC 0 +#define IPE_0_GDSC 1 +#define SBI_GDSC 2 +#define IFE_0_GDSC 3 +#define IFE_1_GDSC 4 +#define IFE_2_GDSC 5 +#define SFE_0_GDSC 6 +#define SFE_1_GDSC 7 +#define TITAN_TOP_GDSC 8 + +#endif diff --git a/include/dt-bindings/clock/qcom,sm8450-dispcc.h b/include/dt-bindings/clock/qcom,sm8450-dispcc.h new file mode 100644 index 000000000000..fd16ca894971 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8450-dispcc.h @@ -0,0 +1,103 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8450_H +#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8450_H + +/* DISP_CC clocks */ +#define DISP_CC_MDSS_AHB1_CLK 0 +#define DISP_CC_MDSS_AHB_CLK 1 +#define DISP_CC_MDSS_AHB_CLK_SRC 2 +#define DISP_CC_MDSS_BYTE0_CLK 3 +#define DISP_CC_MDSS_BYTE0_CLK_SRC 4 +#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 5 +#define DISP_CC_MDSS_BYTE0_INTF_CLK 6 +#define DISP_CC_MDSS_BYTE1_CLK 7 +#define DISP_CC_MDSS_BYTE1_CLK_SRC 8 +#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 9 +#define DISP_CC_MDSS_BYTE1_INTF_CLK 10 +#define DISP_CC_MDSS_DPTX0_AUX_CLK 11 +#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 12 +#define DISP_CC_MDSS_DPTX0_CRYPTO_CLK 13 +#define DISP_CC_MDSS_DPTX0_LINK_CLK 14 +#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 15 +#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 16 +#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 17 +#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK 18 +#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 19 +#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK 20 +#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 21 +#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 22 +#define DISP_CC_MDSS_DPTX1_AUX_CLK 23 +#define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 24 +#define DISP_CC_MDSS_DPTX1_CRYPTO_CLK 25 +#define DISP_CC_MDSS_DPTX1_LINK_CLK 26 +#define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 27 +#define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 28 +#define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 29 +#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK 30 +#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 31 +#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK 32 +#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 33 +#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 34 +#define DISP_CC_MDSS_DPTX2_AUX_CLK 35 +#define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC 36 +#define DISP_CC_MDSS_DPTX2_CRYPTO_CLK 37 +#define DISP_CC_MDSS_DPTX2_LINK_CLK 38 +#define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC 39 +#define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC 40 +#define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK 41 +#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK 42 +#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC 43 +#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK 44 +#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC 45 +#define DISP_CC_MDSS_DPTX3_AUX_CLK 46 +#define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC 47 +#define DISP_CC_MDSS_DPTX3_CRYPTO_CLK 48 +#define DISP_CC_MDSS_DPTX3_LINK_CLK 49 +#define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC 50 +#define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC 51 +#define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK 52 +#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK 53 +#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC 54 +#define DISP_CC_MDSS_ESC0_CLK 55 +#define DISP_CC_MDSS_ESC0_CLK_SRC 56 +#define DISP_CC_MDSS_ESC1_CLK 57 +#define DISP_CC_MDSS_ESC1_CLK_SRC 58 +#define DISP_CC_MDSS_MDP1_CLK 59 +#define DISP_CC_MDSS_MDP_CLK 60 +#define DISP_CC_MDSS_MDP_CLK_SRC 61 +#define DISP_CC_MDSS_MDP_LUT1_CLK 62 +#define DISP_CC_MDSS_MDP_LUT_CLK 63 +#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 64 +#define DISP_CC_MDSS_PCLK0_CLK 65 +#define DISP_CC_MDSS_PCLK0_CLK_SRC 66 +#define DISP_CC_MDSS_PCLK1_CLK 67 +#define DISP_CC_MDSS_PCLK1_CLK_SRC 68 +#define DISP_CC_MDSS_ROT1_CLK 69 +#define DISP_CC_MDSS_ROT_CLK 70 +#define DISP_CC_MDSS_ROT_CLK_SRC 71 +#define DISP_CC_MDSS_RSCC_AHB_CLK 72 +#define DISP_CC_MDSS_RSCC_VSYNC_CLK 73 +#define DISP_CC_MDSS_VSYNC1_CLK 74 +#define DISP_CC_MDSS_VSYNC_CLK 75 +#define DISP_CC_MDSS_VSYNC_CLK_SRC 76 +#define DISP_CC_PLL0 77 +#define DISP_CC_PLL1 78 +#define DISP_CC_SLEEP_CLK 79 +#define DISP_CC_SLEEP_CLK_SRC 80 +#define DISP_CC_XO_CLK 81 +#define DISP_CC_XO_CLK_SRC 82 + +/* DISP_CC resets */ +#define DISP_CC_MDSS_CORE_BCR 0 +#define DISP_CC_MDSS_CORE_INT2_BCR 1 +#define DISP_CC_MDSS_RSCC_BCR 2 + +/* DISP_CC GDSCR */ +#define MDSS_GDSC 0 +#define MDSS_INT2_GDSC 1 + +#endif diff --git a/include/dt-bindings/clock/qcom,videocc-sc7280.h b/include/dt-bindings/clock/qcom,videocc-sc7280.h new file mode 100644 index 000000000000..9e00c3a5f75e --- /dev/null +++ b/include/dt-bindings/clock/qcom,videocc-sc7280.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SC7280_H +#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SC7280_H + +/* VIDEO_CC clocks */ +#define VIDEO_PLL0 0 +#define VIDEO_CC_IRIS_AHB_CLK 1 +#define VIDEO_CC_IRIS_CLK_SRC 2 +#define VIDEO_CC_MVS0_AXI_CLK 3 +#define VIDEO_CC_MVS0_CORE_CLK 4 +#define VIDEO_CC_MVSC_CORE_CLK 5 +#define VIDEO_CC_MVSC_CTL_AXI_CLK 6 +#define VIDEO_CC_SLEEP_CLK 7 +#define VIDEO_CC_SLEEP_CLK_SRC 8 +#define VIDEO_CC_VENUS_AHB_CLK 9 +#define VIDEO_CC_XO_CLK 10 +#define VIDEO_CC_XO_CLK_SRC 11 + +/* VIDEO_CC power domains */ +#define MVS0_GDSC 0 +#define MVSC_GDSC 1 + +#endif diff --git a/include/dt-bindings/clock/qcom,videocc-sm8150.h b/include/dt-bindings/clock/qcom,videocc-sm8150.h new file mode 100644 index 000000000000..e24ee840cfdb --- /dev/null +++ b/include/dt-bindings/clock/qcom,videocc-sm8150.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8150_H +#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8150_H + +/* VIDEO_CC clocks */ +#define VIDEO_CC_IRIS_AHB_CLK 0 +#define VIDEO_CC_IRIS_CLK_SRC 1 +#define VIDEO_CC_MVS0_CORE_CLK 2 +#define VIDEO_CC_MVS1_CORE_CLK 3 +#define VIDEO_CC_MVSC_CORE_CLK 4 +#define VIDEO_CC_PLL0 5 + +/* VIDEO_CC Resets */ +#define VIDEO_CC_MVSC_CORE_CLK_BCR 0 + +/* VIDEO_CC GDSCRs */ +#define VENUS_GDSC 0 +#define VCODEC0_GDSC 1 +#define VCODEC1_GDSC 2 + +#endif diff --git a/include/dt-bindings/clock/qcom,videocc-sm8250.h b/include/dt-bindings/clock/qcom,videocc-sm8250.h new file mode 100644 index 000000000000..8d321ac3b1fa --- /dev/null +++ b/include/dt-bindings/clock/qcom,videocc-sm8250.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8250_H +#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8250_H + +/* VIDEO_CC clocks */ +#define VIDEO_CC_MVS0_CLK_SRC 0 +#define VIDEO_CC_MVS0C_CLK 1 +#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 2 +#define VIDEO_CC_MVS1_CLK_SRC 3 +#define VIDEO_CC_MVS1_DIV2_CLK 4 +#define VIDEO_CC_MVS1C_CLK 5 +#define VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC 6 +#define VIDEO_CC_PLL0 7 +#define VIDEO_CC_PLL1 8 +#define VIDEO_CC_MVS0_DIV_CLK_SRC 9 +#define VIDEO_CC_MVS0_CLK 10 + +/* VIDEO_CC resets */ +#define VIDEO_CC_CVP_INTERFACE_BCR 0 +#define VIDEO_CC_CVP_MVS0_BCR 1 +#define VIDEO_CC_MVS0C_CLK_ARES 2 +#define VIDEO_CC_CVP_MVS0C_BCR 3 +#define VIDEO_CC_CVP_MVS1_BCR 4 +#define VIDEO_CC_MVS1C_CLK_ARES 5 +#define VIDEO_CC_CVP_MVS1C_BCR 6 + +#define MVS0C_GDSC 0 +#define MVS1C_GDSC 1 +#define MVS0_GDSC 2 +#define MVS1_GDSC 3 + +#endif diff --git a/include/dt-bindings/clock/r8a7742-cpg-mssr.h b/include/dt-bindings/clock/r8a7742-cpg-mssr.h new file mode 100644 index 000000000000..e68191c24881 --- /dev/null +++ b/include/dt-bindings/clock/r8a7742-cpg-mssr.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__ + +#include <dt-bindings/clock/renesas-cpg-mssr.h> + +/* r8a7742 CPG Core Clocks */ +#define R8A7742_CLK_Z 0 +#define R8A7742_CLK_Z2 1 +#define R8A7742_CLK_ZG 2 +#define R8A7742_CLK_ZTR 3 +#define R8A7742_CLK_ZTRD2 4 +#define R8A7742_CLK_ZT 5 +#define R8A7742_CLK_ZX 6 +#define R8A7742_CLK_ZS 7 +#define R8A7742_CLK_HP 8 +#define R8A7742_CLK_B 9 +#define R8A7742_CLK_LB 10 +#define R8A7742_CLK_P 11 +#define R8A7742_CLK_CL 12 +#define R8A7742_CLK_M2 13 +#define R8A7742_CLK_ZB3 14 +#define R8A7742_CLK_ZB3D2 15 +#define R8A7742_CLK_DDR 16 +#define R8A7742_CLK_SDH 17 +#define R8A7742_CLK_SD0 18 +#define R8A7742_CLK_SD1 19 +#define R8A7742_CLK_SD2 20 +#define R8A7742_CLK_SD3 21 +#define R8A7742_CLK_MMC0 22 +#define R8A7742_CLK_MMC1 23 +#define R8A7742_CLK_MP 24 +#define R8A7742_CLK_QSPI 25 +#define R8A7742_CLK_CP 26 +#define R8A7742_CLK_RCAN 27 +#define R8A7742_CLK_R 28 +#define R8A7742_CLK_OSC 29 + +#endif /* __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/clock/r8a774e1-cpg-mssr.h b/include/dt-bindings/clock/r8a774e1-cpg-mssr.h new file mode 100644 index 000000000000..b2fc1d1c3c47 --- /dev/null +++ b/include/dt-bindings/clock/r8a774e1-cpg-mssr.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__ + +#include <dt-bindings/clock/renesas-cpg-mssr.h> + +/* R8A774E1 CPG Core Clocks */ +#define R8A774E1_CLK_Z 0 +#define R8A774E1_CLK_Z2 1 +#define R8A774E1_CLK_ZG 2 +#define R8A774E1_CLK_ZTR 3 +#define R8A774E1_CLK_ZTRD2 4 +#define R8A774E1_CLK_ZT 5 +#define R8A774E1_CLK_ZX 6 +#define R8A774E1_CLK_S0D1 7 +#define R8A774E1_CLK_S0D2 8 +#define R8A774E1_CLK_S0D3 9 +#define R8A774E1_CLK_S0D4 10 +#define R8A774E1_CLK_S0D6 11 +#define R8A774E1_CLK_S0D8 12 +#define R8A774E1_CLK_S0D12 13 +#define R8A774E1_CLK_S1D2 14 +#define R8A774E1_CLK_S1D4 15 +#define R8A774E1_CLK_S2D1 16 +#define R8A774E1_CLK_S2D2 17 +#define R8A774E1_CLK_S2D4 18 +#define R8A774E1_CLK_S3D1 19 +#define R8A774E1_CLK_S3D2 20 +#define R8A774E1_CLK_S3D4 21 +#define R8A774E1_CLK_LB 22 +#define R8A774E1_CLK_CL 23 +#define R8A774E1_CLK_ZB3 24 +#define R8A774E1_CLK_ZB3D2 25 +#define R8A774E1_CLK_ZB3D4 26 +#define R8A774E1_CLK_CR 27 +#define R8A774E1_CLK_CRD2 28 +#define R8A774E1_CLK_SD0H 29 +#define R8A774E1_CLK_SD0 30 +#define R8A774E1_CLK_SD1H 31 +#define R8A774E1_CLK_SD1 32 +#define R8A774E1_CLK_SD2H 33 +#define R8A774E1_CLK_SD2 34 +#define R8A774E1_CLK_SD3H 35 +#define R8A774E1_CLK_SD3 36 +#define R8A774E1_CLK_RPC 37 +#define R8A774E1_CLK_RPCD2 38 +#define R8A774E1_CLK_MSO 39 +#define R8A774E1_CLK_HDMI 40 +#define R8A774E1_CLK_CSI0 41 +#define R8A774E1_CLK_CP 42 +#define R8A774E1_CLK_CPEX 43 +#define R8A774E1_CLK_R 44 +#define R8A774E1_CLK_OSC 45 +#define R8A774E1_CLK_CANFD 46 + +#endif /* __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/clock/r8a779a0-cpg-mssr.h b/include/dt-bindings/clock/r8a779a0-cpg-mssr.h new file mode 100644 index 000000000000..f1d737ca7ca1 --- /dev/null +++ b/include/dt-bindings/clock/r8a779a0-cpg-mssr.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2020 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__ + +#include <dt-bindings/clock/renesas-cpg-mssr.h> + +/* r8a779A0 CPG Core Clocks */ +#define R8A779A0_CLK_Z0 0 +#define R8A779A0_CLK_ZX 1 +#define R8A779A0_CLK_Z1 2 +#define R8A779A0_CLK_ZR 3 +#define R8A779A0_CLK_ZS 4 +#define R8A779A0_CLK_ZT 5 +#define R8A779A0_CLK_ZTR 6 +#define R8A779A0_CLK_S1D1 7 +#define R8A779A0_CLK_S1D2 8 +#define R8A779A0_CLK_S1D4 9 +#define R8A779A0_CLK_S1D8 10 +#define R8A779A0_CLK_S1D12 11 +#define R8A779A0_CLK_S3D1 12 +#define R8A779A0_CLK_S3D2 13 +#define R8A779A0_CLK_S3D4 14 +#define R8A779A0_CLK_LB 15 +#define R8A779A0_CLK_CP 16 +#define R8A779A0_CLK_CL 17 +#define R8A779A0_CLK_CL16MCK 18 +#define R8A779A0_CLK_ZB30 19 +#define R8A779A0_CLK_ZB30D2 20 +#define R8A779A0_CLK_ZB30D4 21 +#define R8A779A0_CLK_ZB31 22 +#define R8A779A0_CLK_ZB31D2 23 +#define R8A779A0_CLK_ZB31D4 24 +#define R8A779A0_CLK_SD0H 25 +#define R8A779A0_CLK_SD0 26 +#define R8A779A0_CLK_RPC 27 +#define R8A779A0_CLK_RPCD2 28 +#define R8A779A0_CLK_MSO 29 +#define R8A779A0_CLK_CANFD 30 +#define R8A779A0_CLK_CSI0 31 +#define R8A779A0_CLK_FRAY 32 +#define R8A779A0_CLK_DSI 33 +#define R8A779A0_CLK_VIP 34 +#define R8A779A0_CLK_ADGH 35 +#define R8A779A0_CLK_CNNDSP 36 +#define R8A779A0_CLK_ICU 37 +#define R8A779A0_CLK_ICUD2 38 +#define R8A779A0_CLK_VCBUS 39 +#define R8A779A0_CLK_CBFUSA 40 +#define R8A779A0_CLK_R 41 +#define R8A779A0_CLK_OSC 42 + +#endif /* __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/clock/r8a779f0-cpg-mssr.h b/include/dt-bindings/clock/r8a779f0-cpg-mssr.h new file mode 100644 index 000000000000..f2ae1c6a82dd --- /dev/null +++ b/include/dt-bindings/clock/r8a779f0-cpg-mssr.h @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: (GPL-2.0 or MIT) */ +/* + * Copyright (C) 2021 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__ + +#include <dt-bindings/clock/renesas-cpg-mssr.h> + +/* r8a779f0 CPG Core Clocks */ + +#define R8A779F0_CLK_ZX 0 +#define R8A779F0_CLK_ZS 1 +#define R8A779F0_CLK_ZT 2 +#define R8A779F0_CLK_ZTR 3 +#define R8A779F0_CLK_S0D2 4 +#define R8A779F0_CLK_S0D3 5 +#define R8A779F0_CLK_S0D4 6 +#define R8A779F0_CLK_S0D2_MM 7 +#define R8A779F0_CLK_S0D3_MM 8 +#define R8A779F0_CLK_S0D4_MM 9 +#define R8A779F0_CLK_S0D2_RT 10 +#define R8A779F0_CLK_S0D3_RT 11 +#define R8A779F0_CLK_S0D4_RT 12 +#define R8A779F0_CLK_S0D6_RT 13 +#define R8A779F0_CLK_S0D3_PER 14 +#define R8A779F0_CLK_S0D6_PER 15 +#define R8A779F0_CLK_S0D12_PER 16 +#define R8A779F0_CLK_S0D24_PER 17 +#define R8A779F0_CLK_S0D2_HSC 18 +#define R8A779F0_CLK_S0D3_HSC 19 +#define R8A779F0_CLK_S0D4_HSC 20 +#define R8A779F0_CLK_S0D6_HSC 21 +#define R8A779F0_CLK_S0D12_HSC 22 +#define R8A779F0_CLK_S0D2_CC 23 +#define R8A779F0_CLK_CL 24 +#define R8A779F0_CLK_CL16M 25 +#define R8A779F0_CLK_CL16M_MM 26 +#define R8A779F0_CLK_CL16M_RT 27 +#define R8A779F0_CLK_CL16M_PER 28 +#define R8A779F0_CLK_CL16M_HSC 29 +#define R8A779F0_CLK_Z0 30 +#define R8A779F0_CLK_Z1 31 +#define R8A779F0_CLK_ZB3 32 +#define R8A779F0_CLK_ZB3D2 33 +#define R8A779F0_CLK_ZB3D4 34 +#define R8A779F0_CLK_SD0H 35 +#define R8A779F0_CLK_SD0 36 +#define R8A779F0_CLK_RPC 37 +#define R8A779F0_CLK_RPCD2 38 +#define R8A779F0_CLK_MSO 39 +#define R8A779F0_CLK_SASYNCRT 40 +#define R8A779F0_CLK_SASYNCPERD1 41 +#define R8A779F0_CLK_SASYNCPERD2 42 +#define R8A779F0_CLK_SASYNCPERD4 43 +#define R8A779F0_CLK_DBGSOC_HSC 44 +#define R8A779F0_CLK_RSW2 45 +#define R8A779F0_CLK_OSC 46 +#define R8A779F0_CLK_ZR 47 +#define R8A779F0_CLK_CPEX 48 +#define R8A779F0_CLK_CBFUSA 49 +#define R8A779F0_CLK_R 50 + +#endif /* __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/clock/r8a779g0-cpg-mssr.h b/include/dt-bindings/clock/r8a779g0-cpg-mssr.h new file mode 100644 index 000000000000..754c54a6eb06 --- /dev/null +++ b/include/dt-bindings/clock/r8a779g0-cpg-mssr.h @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2022 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__ + +#include <dt-bindings/clock/renesas-cpg-mssr.h> + +/* r8a779g0 CPG Core Clocks */ + +#define R8A779G0_CLK_ZX 0 +#define R8A779G0_CLK_ZS 1 +#define R8A779G0_CLK_ZT 2 +#define R8A779G0_CLK_ZTR 3 +#define R8A779G0_CLK_S0D2 4 +#define R8A779G0_CLK_S0D3 5 +#define R8A779G0_CLK_S0D4 6 +#define R8A779G0_CLK_S0D1_VIO 7 +#define R8A779G0_CLK_S0D2_VIO 8 +#define R8A779G0_CLK_S0D4_VIO 9 +#define R8A779G0_CLK_S0D8_VIO 10 +#define R8A779G0_CLK_S0D1_VC 11 +#define R8A779G0_CLK_S0D2_VC 12 +#define R8A779G0_CLK_S0D4_VC 13 +#define R8A779G0_CLK_S0D2_MM 14 +#define R8A779G0_CLK_S0D4_MM 15 +#define R8A779G0_CLK_S0D2_U3DG 16 +#define R8A779G0_CLK_S0D4_U3DG 17 +#define R8A779G0_CLK_S0D2_RT 18 +#define R8A779G0_CLK_S0D3_RT 19 +#define R8A779G0_CLK_S0D4_RT 20 +#define R8A779G0_CLK_S0D6_RT 21 +#define R8A779G0_CLK_S0D24_RT 22 +#define R8A779G0_CLK_S0D2_PER 23 +#define R8A779G0_CLK_S0D3_PER 24 +#define R8A779G0_CLK_S0D4_PER 25 +#define R8A779G0_CLK_S0D6_PER 26 +#define R8A779G0_CLK_S0D12_PER 27 +#define R8A779G0_CLK_S0D24_PER 28 +#define R8A779G0_CLK_S0D1_HSC 29 +#define R8A779G0_CLK_S0D2_HSC 30 +#define R8A779G0_CLK_S0D4_HSC 31 +#define R8A779G0_CLK_S0D2_CC 32 +#define R8A779G0_CLK_SVD1_IR 33 +#define R8A779G0_CLK_SVD2_IR 34 +#define R8A779G0_CLK_SVD1_VIP 35 +#define R8A779G0_CLK_SVD2_VIP 36 +#define R8A779G0_CLK_CL 37 +#define R8A779G0_CLK_CL16M 38 +#define R8A779G0_CLK_CL16M_MM 39 +#define R8A779G0_CLK_CL16M_RT 40 +#define R8A779G0_CLK_CL16M_PER 41 +#define R8A779G0_CLK_CL16M_HSC 42 +#define R8A779G0_CLK_Z0 43 +#define R8A779G0_CLK_ZB3 44 +#define R8A779G0_CLK_ZB3D2 45 +#define R8A779G0_CLK_ZB3D4 46 +#define R8A779G0_CLK_ZG 47 +#define R8A779G0_CLK_SD0H 48 +#define R8A779G0_CLK_SD0 49 +#define R8A779G0_CLK_RPC 50 +#define R8A779G0_CLK_RPCD2 51 +#define R8A779G0_CLK_MSO 52 +#define R8A779G0_CLK_CANFD 53 +#define R8A779G0_CLK_CSI 54 +#define R8A779G0_CLK_FRAY 55 +#define R8A779G0_CLK_IPC 56 +#define R8A779G0_CLK_SASYNCRT 57 +#define R8A779G0_CLK_SASYNCPERD1 58 +#define R8A779G0_CLK_SASYNCPERD2 59 +#define R8A779G0_CLK_SASYNCPERD4 60 +#define R8A779G0_CLK_VIOBUS 61 +#define R8A779G0_CLK_VIOBUSD2 62 +#define R8A779G0_CLK_VCBUS 63 +#define R8A779G0_CLK_VCBUSD2 64 +#define R8A779G0_CLK_DSIEXT 65 +#define R8A779G0_CLK_DSIREF 66 +#define R8A779G0_CLK_ADGH 67 +#define R8A779G0_CLK_OSC 68 +#define R8A779G0_CLK_ZR0 69 +#define R8A779G0_CLK_ZR1 70 +#define R8A779G0_CLK_ZR2 71 +#define R8A779G0_CLK_IMPA 72 +#define R8A779G0_CLK_IMPAD4 73 +#define R8A779G0_CLK_CPEX 74 +#define R8A779G0_CLK_CBFUSA 75 +#define R8A779G0_CLK_R 76 + +#endif /* __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/clock/r9a06g032-sysctrl.h b/include/dt-bindings/clock/r9a06g032-sysctrl.h index 90c0f3dc1ba1..d9d7b8b4f426 100644 --- a/include/dt-bindings/clock/r9a06g032-sysctrl.h +++ b/include/dt-bindings/clock/r9a06g032-sysctrl.h @@ -74,6 +74,7 @@ #define R9A06G032_CLK_DDRPHY_PCLK 81 /* AKA CLK_REF_SYNC_D4 */ #define R9A06G032_CLK_FW 81 /* AKA CLK_REF_SYNC_D4 */ #define R9A06G032_CLK_CRYPTO 81 /* AKA CLK_REF_SYNC_D4 */ +#define R9A06G032_CLK_WATCHDOG 82 /* AKA CLK_REF_SYNC_D8 */ #define R9A06G032_CLK_A7MP 84 /* AKA DIV_CA7 */ #define R9A06G032_HCLK_CAN0 85 #define R9A06G032_HCLK_CAN1 86 diff --git a/include/dt-bindings/clock/r9a07g043-cpg.h b/include/dt-bindings/clock/r9a07g043-cpg.h new file mode 100644 index 000000000000..77cde8effdc7 --- /dev/null +++ b/include/dt-bindings/clock/r9a07g043-cpg.h @@ -0,0 +1,204 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__ +#define __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__ + +#include <dt-bindings/clock/renesas-cpg-mssr.h> + +/* R9A07G043 CPG Core Clocks */ +#define R9A07G043_CLK_I 0 +#define R9A07G043_CLK_I2 1 +#define R9A07G043_CLK_S0 2 +#define R9A07G043_CLK_SPI0 3 +#define R9A07G043_CLK_SPI1 4 +#define R9A07G043_CLK_SD0 5 +#define R9A07G043_CLK_SD1 6 +#define R9A07G043_CLK_M0 7 +#define R9A07G043_CLK_M2 8 +#define R9A07G043_CLK_M3 9 +#define R9A07G043_CLK_HP 10 +#define R9A07G043_CLK_TSU 11 +#define R9A07G043_CLK_ZT 12 +#define R9A07G043_CLK_P0 13 +#define R9A07G043_CLK_P1 14 +#define R9A07G043_CLK_P2 15 +#define R9A07G043_CLK_AT 16 +#define R9A07G043_OSCCLK 17 +#define R9A07G043_CLK_P0_DIV2 18 + +/* R9A07G043 Module Clocks */ +#define R9A07G043_CA55_SCLK 0 /* RZ/G2UL Only */ +#define R9A07G043_CA55_PCLK 1 /* RZ/G2UL Only */ +#define R9A07G043_CA55_ATCLK 2 /* RZ/G2UL Only */ +#define R9A07G043_CA55_GICCLK 3 /* RZ/G2UL Only */ +#define R9A07G043_CA55_PERICLK 4 /* RZ/G2UL Only */ +#define R9A07G043_CA55_ACLK 5 /* RZ/G2UL Only */ +#define R9A07G043_CA55_TSCLK 6 /* RZ/G2UL Only */ +#define R9A07G043_GIC600_GICCLK 7 /* RZ/G2UL Only */ +#define R9A07G043_IA55_CLK 8 /* RZ/G2UL Only */ +#define R9A07G043_IA55_PCLK 9 /* RZ/G2UL Only */ +#define R9A07G043_MHU_PCLK 10 /* RZ/G2UL Only */ +#define R9A07G043_SYC_CNT_CLK 11 +#define R9A07G043_DMAC_ACLK 12 +#define R9A07G043_DMAC_PCLK 13 +#define R9A07G043_OSTM0_PCLK 14 +#define R9A07G043_OSTM1_PCLK 15 +#define R9A07G043_OSTM2_PCLK 16 +#define R9A07G043_MTU_X_MCK_MTU3 17 +#define R9A07G043_POE3_CLKM_POE 18 +#define R9A07G043_WDT0_PCLK 19 +#define R9A07G043_WDT0_CLK 20 +#define R9A07G043_WDT2_PCLK 21 /* RZ/G2UL Only */ +#define R9A07G043_WDT2_CLK 22 /* RZ/G2UL Only */ +#define R9A07G043_SPI_CLK2 23 +#define R9A07G043_SPI_CLK 24 +#define R9A07G043_SDHI0_IMCLK 25 +#define R9A07G043_SDHI0_IMCLK2 26 +#define R9A07G043_SDHI0_CLK_HS 27 +#define R9A07G043_SDHI0_ACLK 28 +#define R9A07G043_SDHI1_IMCLK 29 +#define R9A07G043_SDHI1_IMCLK2 30 +#define R9A07G043_SDHI1_CLK_HS 31 +#define R9A07G043_SDHI1_ACLK 32 +#define R9A07G043_ISU_ACLK 33 /* RZ/G2UL Only */ +#define R9A07G043_ISU_PCLK 34 /* RZ/G2UL Only */ +#define R9A07G043_CRU_SYSCLK 35 /* RZ/G2UL Only */ +#define R9A07G043_CRU_VCLK 36 /* RZ/G2UL Only */ +#define R9A07G043_CRU_PCLK 37 /* RZ/G2UL Only */ +#define R9A07G043_CRU_ACLK 38 /* RZ/G2UL Only */ +#define R9A07G043_LCDC_CLK_A 39 /* RZ/G2UL Only */ +#define R9A07G043_LCDC_CLK_P 40 /* RZ/G2UL Only */ +#define R9A07G043_LCDC_CLK_D 41 /* RZ/G2UL Only */ +#define R9A07G043_SSI0_PCLK2 42 +#define R9A07G043_SSI0_PCLK_SFR 43 +#define R9A07G043_SSI1_PCLK2 44 +#define R9A07G043_SSI1_PCLK_SFR 45 +#define R9A07G043_SSI2_PCLK2 46 +#define R9A07G043_SSI2_PCLK_SFR 47 +#define R9A07G043_SSI3_PCLK2 48 +#define R9A07G043_SSI3_PCLK_SFR 49 +#define R9A07G043_SRC_CLKP 50 /* RZ/G2UL Only */ +#define R9A07G043_USB_U2H0_HCLK 51 +#define R9A07G043_USB_U2H1_HCLK 52 +#define R9A07G043_USB_U2P_EXR_CPUCLK 53 +#define R9A07G043_USB_PCLK 54 +#define R9A07G043_ETH0_CLK_AXI 55 +#define R9A07G043_ETH0_CLK_CHI 56 +#define R9A07G043_ETH1_CLK_AXI 57 +#define R9A07G043_ETH1_CLK_CHI 58 +#define R9A07G043_I2C0_PCLK 59 +#define R9A07G043_I2C1_PCLK 60 +#define R9A07G043_I2C2_PCLK 61 +#define R9A07G043_I2C3_PCLK 62 +#define R9A07G043_SCIF0_CLK_PCK 63 +#define R9A07G043_SCIF1_CLK_PCK 64 +#define R9A07G043_SCIF2_CLK_PCK 65 +#define R9A07G043_SCIF3_CLK_PCK 66 +#define R9A07G043_SCIF4_CLK_PCK 67 +#define R9A07G043_SCI0_CLKP 68 +#define R9A07G043_SCI1_CLKP 69 +#define R9A07G043_IRDA_CLKP 70 +#define R9A07G043_RSPI0_CLKB 71 +#define R9A07G043_RSPI1_CLKB 72 +#define R9A07G043_RSPI2_CLKB 73 +#define R9A07G043_CANFD_PCLK 74 +#define R9A07G043_GPIO_HCLK 75 +#define R9A07G043_ADC_ADCLK 76 +#define R9A07G043_ADC_PCLK 77 +#define R9A07G043_TSU_PCLK 78 +#define R9A07G043_NCEPLDM_DM_CLK 79 /* RZ/Five Only */ +#define R9A07G043_NCEPLDM_ACLK 80 /* RZ/Five Only */ +#define R9A07G043_NCEPLDM_TCK 81 /* RZ/Five Only */ +#define R9A07G043_NCEPLMT_ACLK 82 /* RZ/Five Only */ +#define R9A07G043_NCEPLIC_ACLK 83 /* RZ/Five Only */ +#define R9A07G043_AX45MP_CORE0_CLK 84 /* RZ/Five Only */ +#define R9A07G043_AX45MP_ACLK 85 /* RZ/Five Only */ +#define R9A07G043_IAX45_CLK 86 /* RZ/Five Only */ +#define R9A07G043_IAX45_PCLK 87 /* RZ/Five Only */ + +/* R9A07G043 Resets */ +#define R9A07G043_CA55_RST_1_0 0 /* RZ/G2UL Only */ +#define R9A07G043_CA55_RST_1_1 1 /* RZ/G2UL Only */ +#define R9A07G043_CA55_RST_3_0 2 /* RZ/G2UL Only */ +#define R9A07G043_CA55_RST_3_1 3 /* RZ/G2UL Only */ +#define R9A07G043_CA55_RST_4 4 /* RZ/G2UL Only */ +#define R9A07G043_CA55_RST_5 5 /* RZ/G2UL Only */ +#define R9A07G043_CA55_RST_6 6 /* RZ/G2UL Only */ +#define R9A07G043_CA55_RST_7 7 /* RZ/G2UL Only */ +#define R9A07G043_CA55_RST_8 8 /* RZ/G2UL Only */ +#define R9A07G043_CA55_RST_9 9 /* RZ/G2UL Only */ +#define R9A07G043_CA55_RST_10 10 /* RZ/G2UL Only */ +#define R9A07G043_CA55_RST_11 11 /* RZ/G2UL Only */ +#define R9A07G043_CA55_RST_12 12 /* RZ/G2UL Only */ +#define R9A07G043_GIC600_GICRESET_N 13 /* RZ/G2UL Only */ +#define R9A07G043_GIC600_DBG_GICRESET_N 14 /* RZ/G2UL Only */ +#define R9A07G043_IA55_RESETN 15 /* RZ/G2UL Only */ +#define R9A07G043_MHU_RESETN 16 /* RZ/G2UL Only */ +#define R9A07G043_DMAC_ARESETN 17 +#define R9A07G043_DMAC_RST_ASYNC 18 +#define R9A07G043_SYC_RESETN 19 +#define R9A07G043_OSTM0_PRESETZ 20 +#define R9A07G043_OSTM1_PRESETZ 21 +#define R9A07G043_OSTM2_PRESETZ 22 +#define R9A07G043_MTU_X_PRESET_MTU3 23 +#define R9A07G043_POE3_RST_M_REG 24 +#define R9A07G043_WDT0_PRESETN 25 +#define R9A07G043_WDT2_PRESETN 26 /* RZ/G2UL Only */ +#define R9A07G043_SPI_RST 27 +#define R9A07G043_SDHI0_IXRST 28 +#define R9A07G043_SDHI1_IXRST 29 +#define R9A07G043_ISU_ARESETN 30 /* RZ/G2UL Only */ +#define R9A07G043_ISU_PRESETN 31 /* RZ/G2UL Only */ +#define R9A07G043_CRU_CMN_RSTB 32 /* RZ/G2UL Only */ +#define R9A07G043_CRU_PRESETN 33 /* RZ/G2UL Only */ +#define R9A07G043_CRU_ARESETN 34 /* RZ/G2UL Only */ +#define R9A07G043_LCDC_RESET_N 35 /* RZ/G2UL Only */ +#define R9A07G043_SSI0_RST_M2_REG 36 +#define R9A07G043_SSI1_RST_M2_REG 37 +#define R9A07G043_SSI2_RST_M2_REG 38 +#define R9A07G043_SSI3_RST_M2_REG 39 +#define R9A07G043_SRC_RST 40 /* RZ/G2UL Only */ +#define R9A07G043_USB_U2H0_HRESETN 41 +#define R9A07G043_USB_U2H1_HRESETN 42 +#define R9A07G043_USB_U2P_EXL_SYSRST 43 +#define R9A07G043_USB_PRESETN 44 +#define R9A07G043_ETH0_RST_HW_N 45 +#define R9A07G043_ETH1_RST_HW_N 46 +#define R9A07G043_I2C0_MRST 47 +#define R9A07G043_I2C1_MRST 48 +#define R9A07G043_I2C2_MRST 49 +#define R9A07G043_I2C3_MRST 50 +#define R9A07G043_SCIF0_RST_SYSTEM_N 51 +#define R9A07G043_SCIF1_RST_SYSTEM_N 52 +#define R9A07G043_SCIF2_RST_SYSTEM_N 53 +#define R9A07G043_SCIF3_RST_SYSTEM_N 54 +#define R9A07G043_SCIF4_RST_SYSTEM_N 55 +#define R9A07G043_SCI0_RST 56 +#define R9A07G043_SCI1_RST 57 +#define R9A07G043_IRDA_RST 58 +#define R9A07G043_RSPI0_RST 59 +#define R9A07G043_RSPI1_RST 60 +#define R9A07G043_RSPI2_RST 61 +#define R9A07G043_CANFD_RSTP_N 62 +#define R9A07G043_CANFD_RSTC_N 63 +#define R9A07G043_GPIO_RSTN 64 +#define R9A07G043_GPIO_PORT_RESETN 65 +#define R9A07G043_GPIO_SPARE_RESETN 66 +#define R9A07G043_ADC_PRESETN 67 +#define R9A07G043_ADC_ADRST_N 68 +#define R9A07G043_TSU_PRESETN 69 +#define R9A07G043_NCEPLDM_DTM_PWR_RST_N 70 /* RZ/Five Only */ +#define R9A07G043_NCEPLDM_ARESETN 71 /* RZ/Five Only */ +#define R9A07G043_NCEPLMT_POR_RSTN 72 /* RZ/Five Only */ +#define R9A07G043_NCEPLMT_ARESETN 73 /* RZ/Five Only */ +#define R9A07G043_NCEPLIC_ARESETN 74 /* RZ/Five Only */ +#define R9A07G043_AX45MP_ARESETNM 75 /* RZ/Five Only */ +#define R9A07G043_AX45MP_ARESETNS 76 /* RZ/Five Only */ +#define R9A07G043_AX45MP_L2_RESETN 77 /* RZ/Five Only */ +#define R9A07G043_AX45MP_CORE0_RESETN 78 /* RZ/Five Only */ +#define R9A07G043_IAX45_RESETN 79 /* RZ/Five Only */ + + +#endif /* __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__ */ diff --git a/include/dt-bindings/clock/r9a07g044-cpg.h b/include/dt-bindings/clock/r9a07g044-cpg.h new file mode 100644 index 000000000000..0bb17ff1a01a --- /dev/null +++ b/include/dt-bindings/clock/r9a07g044-cpg.h @@ -0,0 +1,220 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__ +#define __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__ + +#include <dt-bindings/clock/renesas-cpg-mssr.h> + +/* R9A07G044 CPG Core Clocks */ +#define R9A07G044_CLK_I 0 +#define R9A07G044_CLK_I2 1 +#define R9A07G044_CLK_G 2 +#define R9A07G044_CLK_S0 3 +#define R9A07G044_CLK_S1 4 +#define R9A07G044_CLK_SPI0 5 +#define R9A07G044_CLK_SPI1 6 +#define R9A07G044_CLK_SD0 7 +#define R9A07G044_CLK_SD1 8 +#define R9A07G044_CLK_M0 9 +#define R9A07G044_CLK_M1 10 +#define R9A07G044_CLK_M2 11 +#define R9A07G044_CLK_M3 12 +#define R9A07G044_CLK_M4 13 +#define R9A07G044_CLK_HP 14 +#define R9A07G044_CLK_TSU 15 +#define R9A07G044_CLK_ZT 16 +#define R9A07G044_CLK_P0 17 +#define R9A07G044_CLK_P1 18 +#define R9A07G044_CLK_P2 19 +#define R9A07G044_CLK_AT 20 +#define R9A07G044_OSCCLK 21 +#define R9A07G044_CLK_P0_DIV2 22 + +/* R9A07G044 Module Clocks */ +#define R9A07G044_CA55_SCLK 0 +#define R9A07G044_CA55_PCLK 1 +#define R9A07G044_CA55_ATCLK 2 +#define R9A07G044_CA55_GICCLK 3 +#define R9A07G044_CA55_PERICLK 4 +#define R9A07G044_CA55_ACLK 5 +#define R9A07G044_CA55_TSCLK 6 +#define R9A07G044_GIC600_GICCLK 7 +#define R9A07G044_IA55_CLK 8 +#define R9A07G044_IA55_PCLK 9 +#define R9A07G044_MHU_PCLK 10 +#define R9A07G044_SYC_CNT_CLK 11 +#define R9A07G044_DMAC_ACLK 12 +#define R9A07G044_DMAC_PCLK 13 +#define R9A07G044_OSTM0_PCLK 14 +#define R9A07G044_OSTM1_PCLK 15 +#define R9A07G044_OSTM2_PCLK 16 +#define R9A07G044_MTU_X_MCK_MTU3 17 +#define R9A07G044_POE3_CLKM_POE 18 +#define R9A07G044_GPT_PCLK 19 +#define R9A07G044_POEG_A_CLKP 20 +#define R9A07G044_POEG_B_CLKP 21 +#define R9A07G044_POEG_C_CLKP 22 +#define R9A07G044_POEG_D_CLKP 23 +#define R9A07G044_WDT0_PCLK 24 +#define R9A07G044_WDT0_CLK 25 +#define R9A07G044_WDT1_PCLK 26 +#define R9A07G044_WDT1_CLK 27 +#define R9A07G044_WDT2_PCLK 28 +#define R9A07G044_WDT2_CLK 29 +#define R9A07G044_SPI_CLK2 30 +#define R9A07G044_SPI_CLK 31 +#define R9A07G044_SDHI0_IMCLK 32 +#define R9A07G044_SDHI0_IMCLK2 33 +#define R9A07G044_SDHI0_CLK_HS 34 +#define R9A07G044_SDHI0_ACLK 35 +#define R9A07G044_SDHI1_IMCLK 36 +#define R9A07G044_SDHI1_IMCLK2 37 +#define R9A07G044_SDHI1_CLK_HS 38 +#define R9A07G044_SDHI1_ACLK 39 +#define R9A07G044_GPU_CLK 40 +#define R9A07G044_GPU_AXI_CLK 41 +#define R9A07G044_GPU_ACE_CLK 42 +#define R9A07G044_ISU_ACLK 43 +#define R9A07G044_ISU_PCLK 44 +#define R9A07G044_H264_CLK_A 45 +#define R9A07G044_H264_CLK_P 46 +#define R9A07G044_CRU_SYSCLK 47 +#define R9A07G044_CRU_VCLK 48 +#define R9A07G044_CRU_PCLK 49 +#define R9A07G044_CRU_ACLK 50 +#define R9A07G044_MIPI_DSI_PLLCLK 51 +#define R9A07G044_MIPI_DSI_SYSCLK 52 +#define R9A07G044_MIPI_DSI_ACLK 53 +#define R9A07G044_MIPI_DSI_PCLK 54 +#define R9A07G044_MIPI_DSI_VCLK 55 +#define R9A07G044_MIPI_DSI_LPCLK 56 +#define R9A07G044_LCDC_CLK_A 57 +#define R9A07G044_LCDC_CLK_P 58 +#define R9A07G044_LCDC_CLK_D 59 +#define R9A07G044_SSI0_PCLK2 60 +#define R9A07G044_SSI0_PCLK_SFR 61 +#define R9A07G044_SSI1_PCLK2 62 +#define R9A07G044_SSI1_PCLK_SFR 63 +#define R9A07G044_SSI2_PCLK2 64 +#define R9A07G044_SSI2_PCLK_SFR 65 +#define R9A07G044_SSI3_PCLK2 66 +#define R9A07G044_SSI3_PCLK_SFR 67 +#define R9A07G044_SRC_CLKP 68 +#define R9A07G044_USB_U2H0_HCLK 69 +#define R9A07G044_USB_U2H1_HCLK 70 +#define R9A07G044_USB_U2P_EXR_CPUCLK 71 +#define R9A07G044_USB_PCLK 72 +#define R9A07G044_ETH0_CLK_AXI 73 +#define R9A07G044_ETH0_CLK_CHI 74 +#define R9A07G044_ETH1_CLK_AXI 75 +#define R9A07G044_ETH1_CLK_CHI 76 +#define R9A07G044_I2C0_PCLK 77 +#define R9A07G044_I2C1_PCLK 78 +#define R9A07G044_I2C2_PCLK 79 +#define R9A07G044_I2C3_PCLK 80 +#define R9A07G044_SCIF0_CLK_PCK 81 +#define R9A07G044_SCIF1_CLK_PCK 82 +#define R9A07G044_SCIF2_CLK_PCK 83 +#define R9A07G044_SCIF3_CLK_PCK 84 +#define R9A07G044_SCIF4_CLK_PCK 85 +#define R9A07G044_SCI0_CLKP 86 +#define R9A07G044_SCI1_CLKP 87 +#define R9A07G044_IRDA_CLKP 88 +#define R9A07G044_RSPI0_CLKB 89 +#define R9A07G044_RSPI1_CLKB 90 +#define R9A07G044_RSPI2_CLKB 91 +#define R9A07G044_CANFD_PCLK 92 +#define R9A07G044_GPIO_HCLK 93 +#define R9A07G044_ADC_ADCLK 94 +#define R9A07G044_ADC_PCLK 95 +#define R9A07G044_TSU_PCLK 96 + +/* R9A07G044 Resets */ +#define R9A07G044_CA55_RST_1_0 0 +#define R9A07G044_CA55_RST_1_1 1 +#define R9A07G044_CA55_RST_3_0 2 +#define R9A07G044_CA55_RST_3_1 3 +#define R9A07G044_CA55_RST_4 4 +#define R9A07G044_CA55_RST_5 5 +#define R9A07G044_CA55_RST_6 6 +#define R9A07G044_CA55_RST_7 7 +#define R9A07G044_CA55_RST_8 8 +#define R9A07G044_CA55_RST_9 9 +#define R9A07G044_CA55_RST_10 10 +#define R9A07G044_CA55_RST_11 11 +#define R9A07G044_CA55_RST_12 12 +#define R9A07G044_GIC600_GICRESET_N 13 +#define R9A07G044_GIC600_DBG_GICRESET_N 14 +#define R9A07G044_IA55_RESETN 15 +#define R9A07G044_MHU_RESETN 16 +#define R9A07G044_DMAC_ARESETN 17 +#define R9A07G044_DMAC_RST_ASYNC 18 +#define R9A07G044_SYC_RESETN 19 +#define R9A07G044_OSTM0_PRESETZ 20 +#define R9A07G044_OSTM1_PRESETZ 21 +#define R9A07G044_OSTM2_PRESETZ 22 +#define R9A07G044_MTU_X_PRESET_MTU3 23 +#define R9A07G044_POE3_RST_M_REG 24 +#define R9A07G044_GPT_RST_C 25 +#define R9A07G044_POEG_A_RST 26 +#define R9A07G044_POEG_B_RST 27 +#define R9A07G044_POEG_C_RST 28 +#define R9A07G044_POEG_D_RST 29 +#define R9A07G044_WDT0_PRESETN 30 +#define R9A07G044_WDT1_PRESETN 31 +#define R9A07G044_WDT2_PRESETN 32 +#define R9A07G044_SPI_RST 33 +#define R9A07G044_SDHI0_IXRST 34 +#define R9A07G044_SDHI1_IXRST 35 +#define R9A07G044_GPU_RESETN 36 +#define R9A07G044_GPU_AXI_RESETN 37 +#define R9A07G044_GPU_ACE_RESETN 38 +#define R9A07G044_ISU_ARESETN 39 +#define R9A07G044_ISU_PRESETN 40 +#define R9A07G044_H264_X_RESET_VCP 41 +#define R9A07G044_H264_CP_PRESET_P 42 +#define R9A07G044_CRU_CMN_RSTB 43 +#define R9A07G044_CRU_PRESETN 44 +#define R9A07G044_CRU_ARESETN 45 +#define R9A07G044_MIPI_DSI_CMN_RSTB 46 +#define R9A07G044_MIPI_DSI_ARESET_N 47 +#define R9A07G044_MIPI_DSI_PRESET_N 48 +#define R9A07G044_LCDC_RESET_N 49 +#define R9A07G044_SSI0_RST_M2_REG 50 +#define R9A07G044_SSI1_RST_M2_REG 51 +#define R9A07G044_SSI2_RST_M2_REG 52 +#define R9A07G044_SSI3_RST_M2_REG 53 +#define R9A07G044_SRC_RST 54 +#define R9A07G044_USB_U2H0_HRESETN 55 +#define R9A07G044_USB_U2H1_HRESETN 56 +#define R9A07G044_USB_U2P_EXL_SYSRST 57 +#define R9A07G044_USB_PRESETN 58 +#define R9A07G044_ETH0_RST_HW_N 59 +#define R9A07G044_ETH1_RST_HW_N 60 +#define R9A07G044_I2C0_MRST 61 +#define R9A07G044_I2C1_MRST 62 +#define R9A07G044_I2C2_MRST 63 +#define R9A07G044_I2C3_MRST 64 +#define R9A07G044_SCIF0_RST_SYSTEM_N 65 +#define R9A07G044_SCIF1_RST_SYSTEM_N 66 +#define R9A07G044_SCIF2_RST_SYSTEM_N 67 +#define R9A07G044_SCIF3_RST_SYSTEM_N 68 +#define R9A07G044_SCIF4_RST_SYSTEM_N 69 +#define R9A07G044_SCI0_RST 70 +#define R9A07G044_SCI1_RST 71 +#define R9A07G044_IRDA_RST 72 +#define R9A07G044_RSPI0_RST 73 +#define R9A07G044_RSPI1_RST 74 +#define R9A07G044_RSPI2_RST 75 +#define R9A07G044_CANFD_RSTP_N 76 +#define R9A07G044_CANFD_RSTC_N 77 +#define R9A07G044_GPIO_RSTN 78 +#define R9A07G044_GPIO_PORT_RESETN 79 +#define R9A07G044_GPIO_SPARE_RESETN 80 +#define R9A07G044_ADC_PRESETN 81 +#define R9A07G044_ADC_ADRST_N 82 +#define R9A07G044_TSU_PRESETN 83 + +#endif /* __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__ */ diff --git a/include/dt-bindings/clock/r9a07g054-cpg.h b/include/dt-bindings/clock/r9a07g054-cpg.h new file mode 100644 index 000000000000..43f4dbda872c --- /dev/null +++ b/include/dt-bindings/clock/r9a07g054-cpg.h @@ -0,0 +1,229 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R9A07G054_CPG_H__ +#define __DT_BINDINGS_CLOCK_R9A07G054_CPG_H__ + +#include <dt-bindings/clock/renesas-cpg-mssr.h> + +/* R9A07G054 CPG Core Clocks */ +#define R9A07G054_CLK_I 0 +#define R9A07G054_CLK_I2 1 +#define R9A07G054_CLK_G 2 +#define R9A07G054_CLK_S0 3 +#define R9A07G054_CLK_S1 4 +#define R9A07G054_CLK_SPI0 5 +#define R9A07G054_CLK_SPI1 6 +#define R9A07G054_CLK_SD0 7 +#define R9A07G054_CLK_SD1 8 +#define R9A07G054_CLK_M0 9 +#define R9A07G054_CLK_M1 10 +#define R9A07G054_CLK_M2 11 +#define R9A07G054_CLK_M3 12 +#define R9A07G054_CLK_M4 13 +#define R9A07G054_CLK_HP 14 +#define R9A07G054_CLK_TSU 15 +#define R9A07G054_CLK_ZT 16 +#define R9A07G054_CLK_P0 17 +#define R9A07G054_CLK_P1 18 +#define R9A07G054_CLK_P2 19 +#define R9A07G054_CLK_AT 20 +#define R9A07G054_OSCCLK 21 +#define R9A07G054_CLK_P0_DIV2 22 +#define R9A07G054_CLK_DRP_M 23 +#define R9A07G054_CLK_DRP_D 24 +#define R9A07G054_CLK_DRP_A 25 + +/* R9A07G054 Module Clocks */ +#define R9A07G054_CA55_SCLK 0 +#define R9A07G054_CA55_PCLK 1 +#define R9A07G054_CA55_ATCLK 2 +#define R9A07G054_CA55_GICCLK 3 +#define R9A07G054_CA55_PERICLK 4 +#define R9A07G054_CA55_ACLK 5 +#define R9A07G054_CA55_TSCLK 6 +#define R9A07G054_GIC600_GICCLK 7 +#define R9A07G054_IA55_CLK 8 +#define R9A07G054_IA55_PCLK 9 +#define R9A07G054_MHU_PCLK 10 +#define R9A07G054_SYC_CNT_CLK 11 +#define R9A07G054_DMAC_ACLK 12 +#define R9A07G054_DMAC_PCLK 13 +#define R9A07G054_OSTM0_PCLK 14 +#define R9A07G054_OSTM1_PCLK 15 +#define R9A07G054_OSTM2_PCLK 16 +#define R9A07G054_MTU_X_MCK_MTU3 17 +#define R9A07G054_POE3_CLKM_POE 18 +#define R9A07G054_GPT_PCLK 19 +#define R9A07G054_POEG_A_CLKP 20 +#define R9A07G054_POEG_B_CLKP 21 +#define R9A07G054_POEG_C_CLKP 22 +#define R9A07G054_POEG_D_CLKP 23 +#define R9A07G054_WDT0_PCLK 24 +#define R9A07G054_WDT0_CLK 25 +#define R9A07G054_WDT1_PCLK 26 +#define R9A07G054_WDT1_CLK 27 +#define R9A07G054_WDT2_PCLK 28 +#define R9A07G054_WDT2_CLK 29 +#define R9A07G054_SPI_CLK2 30 +#define R9A07G054_SPI_CLK 31 +#define R9A07G054_SDHI0_IMCLK 32 +#define R9A07G054_SDHI0_IMCLK2 33 +#define R9A07G054_SDHI0_CLK_HS 34 +#define R9A07G054_SDHI0_ACLK 35 +#define R9A07G054_SDHI1_IMCLK 36 +#define R9A07G054_SDHI1_IMCLK2 37 +#define R9A07G054_SDHI1_CLK_HS 38 +#define R9A07G054_SDHI1_ACLK 39 +#define R9A07G054_GPU_CLK 40 +#define R9A07G054_GPU_AXI_CLK 41 +#define R9A07G054_GPU_ACE_CLK 42 +#define R9A07G054_ISU_ACLK 43 +#define R9A07G054_ISU_PCLK 44 +#define R9A07G054_H264_CLK_A 45 +#define R9A07G054_H264_CLK_P 46 +#define R9A07G054_CRU_SYSCLK 47 +#define R9A07G054_CRU_VCLK 48 +#define R9A07G054_CRU_PCLK 49 +#define R9A07G054_CRU_ACLK 50 +#define R9A07G054_MIPI_DSI_PLLCLK 51 +#define R9A07G054_MIPI_DSI_SYSCLK 52 +#define R9A07G054_MIPI_DSI_ACLK 53 +#define R9A07G054_MIPI_DSI_PCLK 54 +#define R9A07G054_MIPI_DSI_VCLK 55 +#define R9A07G054_MIPI_DSI_LPCLK 56 +#define R9A07G054_LCDC_CLK_A 57 +#define R9A07G054_LCDC_CLK_P 58 +#define R9A07G054_LCDC_CLK_D 59 +#define R9A07G054_SSI0_PCLK2 60 +#define R9A07G054_SSI0_PCLK_SFR 61 +#define R9A07G054_SSI1_PCLK2 62 +#define R9A07G054_SSI1_PCLK_SFR 63 +#define R9A07G054_SSI2_PCLK2 64 +#define R9A07G054_SSI2_PCLK_SFR 65 +#define R9A07G054_SSI3_PCLK2 66 +#define R9A07G054_SSI3_PCLK_SFR 67 +#define R9A07G054_SRC_CLKP 68 +#define R9A07G054_USB_U2H0_HCLK 69 +#define R9A07G054_USB_U2H1_HCLK 70 +#define R9A07G054_USB_U2P_EXR_CPUCLK 71 +#define R9A07G054_USB_PCLK 72 +#define R9A07G054_ETH0_CLK_AXI 73 +#define R9A07G054_ETH0_CLK_CHI 74 +#define R9A07G054_ETH1_CLK_AXI 75 +#define R9A07G054_ETH1_CLK_CHI 76 +#define R9A07G054_I2C0_PCLK 77 +#define R9A07G054_I2C1_PCLK 78 +#define R9A07G054_I2C2_PCLK 79 +#define R9A07G054_I2C3_PCLK 80 +#define R9A07G054_SCIF0_CLK_PCK 81 +#define R9A07G054_SCIF1_CLK_PCK 82 +#define R9A07G054_SCIF2_CLK_PCK 83 +#define R9A07G054_SCIF3_CLK_PCK 84 +#define R9A07G054_SCIF4_CLK_PCK 85 +#define R9A07G054_SCI0_CLKP 86 +#define R9A07G054_SCI1_CLKP 87 +#define R9A07G054_IRDA_CLKP 88 +#define R9A07G054_RSPI0_CLKB 89 +#define R9A07G054_RSPI1_CLKB 90 +#define R9A07G054_RSPI2_CLKB 91 +#define R9A07G054_CANFD_PCLK 92 +#define R9A07G054_GPIO_HCLK 93 +#define R9A07G054_ADC_ADCLK 94 +#define R9A07G054_ADC_PCLK 95 +#define R9A07G054_TSU_PCLK 96 +#define R9A07G054_STPAI_INITCLK 97 +#define R9A07G054_STPAI_ACLK 98 +#define R9A07G054_STPAI_MCLK 99 +#define R9A07G054_STPAI_DCLKIN 100 +#define R9A07G054_STPAI_ACLK_DRP 101 + +/* R9A07G054 Resets */ +#define R9A07G054_CA55_RST_1_0 0 +#define R9A07G054_CA55_RST_1_1 1 +#define R9A07G054_CA55_RST_3_0 2 +#define R9A07G054_CA55_RST_3_1 3 +#define R9A07G054_CA55_RST_4 4 +#define R9A07G054_CA55_RST_5 5 +#define R9A07G054_CA55_RST_6 6 +#define R9A07G054_CA55_RST_7 7 +#define R9A07G054_CA55_RST_8 8 +#define R9A07G054_CA55_RST_9 9 +#define R9A07G054_CA55_RST_10 10 +#define R9A07G054_CA55_RST_11 11 +#define R9A07G054_CA55_RST_12 12 +#define R9A07G054_GIC600_GICRESET_N 13 +#define R9A07G054_GIC600_DBG_GICRESET_N 14 +#define R9A07G054_IA55_RESETN 15 +#define R9A07G054_MHU_RESETN 16 +#define R9A07G054_DMAC_ARESETN 17 +#define R9A07G054_DMAC_RST_ASYNC 18 +#define R9A07G054_SYC_RESETN 19 +#define R9A07G054_OSTM0_PRESETZ 20 +#define R9A07G054_OSTM1_PRESETZ 21 +#define R9A07G054_OSTM2_PRESETZ 22 +#define R9A07G054_MTU_X_PRESET_MTU3 23 +#define R9A07G054_POE3_RST_M_REG 24 +#define R9A07G054_GPT_RST_C 25 +#define R9A07G054_POEG_A_RST 26 +#define R9A07G054_POEG_B_RST 27 +#define R9A07G054_POEG_C_RST 28 +#define R9A07G054_POEG_D_RST 29 +#define R9A07G054_WDT0_PRESETN 30 +#define R9A07G054_WDT1_PRESETN 31 +#define R9A07G054_WDT2_PRESETN 32 +#define R9A07G054_SPI_RST 33 +#define R9A07G054_SDHI0_IXRST 34 +#define R9A07G054_SDHI1_IXRST 35 +#define R9A07G054_GPU_RESETN 36 +#define R9A07G054_GPU_AXI_RESETN 37 +#define R9A07G054_GPU_ACE_RESETN 38 +#define R9A07G054_ISU_ARESETN 39 +#define R9A07G054_ISU_PRESETN 40 +#define R9A07G054_H264_X_RESET_VCP 41 +#define R9A07G054_H264_CP_PRESET_P 42 +#define R9A07G054_CRU_CMN_RSTB 43 +#define R9A07G054_CRU_PRESETN 44 +#define R9A07G054_CRU_ARESETN 45 +#define R9A07G054_MIPI_DSI_CMN_RSTB 46 +#define R9A07G054_MIPI_DSI_ARESET_N 47 +#define R9A07G054_MIPI_DSI_PRESET_N 48 +#define R9A07G054_LCDC_RESET_N 49 +#define R9A07G054_SSI0_RST_M2_REG 50 +#define R9A07G054_SSI1_RST_M2_REG 51 +#define R9A07G054_SSI2_RST_M2_REG 52 +#define R9A07G054_SSI3_RST_M2_REG 53 +#define R9A07G054_SRC_RST 54 +#define R9A07G054_USB_U2H0_HRESETN 55 +#define R9A07G054_USB_U2H1_HRESETN 56 +#define R9A07G054_USB_U2P_EXL_SYSRST 57 +#define R9A07G054_USB_PRESETN 58 +#define R9A07G054_ETH0_RST_HW_N 59 +#define R9A07G054_ETH1_RST_HW_N 60 +#define R9A07G054_I2C0_MRST 61 +#define R9A07G054_I2C1_MRST 62 +#define R9A07G054_I2C2_MRST 63 +#define R9A07G054_I2C3_MRST 64 +#define R9A07G054_SCIF0_RST_SYSTEM_N 65 +#define R9A07G054_SCIF1_RST_SYSTEM_N 66 +#define R9A07G054_SCIF2_RST_SYSTEM_N 67 +#define R9A07G054_SCIF3_RST_SYSTEM_N 68 +#define R9A07G054_SCIF4_RST_SYSTEM_N 69 +#define R9A07G054_SCI0_RST 70 +#define R9A07G054_SCI1_RST 71 +#define R9A07G054_IRDA_RST 72 +#define R9A07G054_RSPI0_RST 73 +#define R9A07G054_RSPI1_RST 74 +#define R9A07G054_RSPI2_RST 75 +#define R9A07G054_CANFD_RSTP_N 76 +#define R9A07G054_CANFD_RSTC_N 77 +#define R9A07G054_GPIO_RSTN 78 +#define R9A07G054_GPIO_PORT_RESETN 79 +#define R9A07G054_GPIO_SPARE_RESETN 80 +#define R9A07G054_ADC_PRESETN 81 +#define R9A07G054_ADC_ADRST_N 82 +#define R9A07G054_TSU_PRESETN 83 +#define R9A07G054_STPAI_ARESETN 84 + +#endif /* __DT_BINDINGS_CLOCK_R9A07G054_CPG_H__ */ diff --git a/include/dt-bindings/clock/r9a09g011-cpg.h b/include/dt-bindings/clock/r9a09g011-cpg.h new file mode 100644 index 000000000000..41dd585d7115 --- /dev/null +++ b/include/dt-bindings/clock/r9a09g011-cpg.h @@ -0,0 +1,352 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R9A09G011_CPG_H__ +#define __DT_BINDINGS_CLOCK_R9A09G011_CPG_H__ + +#include <dt-bindings/clock/renesas-cpg-mssr.h> + +/* Module Clocks */ +#define R9A09G011_SYS_CLK 0 +#define R9A09G011_PFC_PCLK 1 +#define R9A09G011_PMC_CORE_CLOCK 2 +#define R9A09G011_GIC_CLK 3 +#define R9A09G011_RAMA_ACLK 4 +#define R9A09G011_ROMA_ACLK 5 +#define R9A09G011_SEC_ACLK 6 +#define R9A09G011_SEC_PCLK 7 +#define R9A09G011_SEC_TCLK 8 +#define R9A09G011_DMAA_ACLK 9 +#define R9A09G011_TSU0_PCLK 10 +#define R9A09G011_TSU1_PCLK 11 + +#define R9A09G011_CST_TRACECLK 12 +#define R9A09G011_CST_SB_CLK 13 +#define R9A09G011_CST_AHB_CLK 14 +#define R9A09G011_CST_ATB_SB_CLK 15 +#define R9A09G011_CST_TS_SB_CLK 16 + +#define R9A09G011_SDI0_ACLK 17 +#define R9A09G011_SDI0_IMCLK 18 +#define R9A09G011_SDI0_IMCLK2 19 +#define R9A09G011_SDI0_CLK_HS 20 +#define R9A09G011_SDI1_ACLK 21 +#define R9A09G011_SDI1_IMCLK 22 +#define R9A09G011_SDI1_IMCLK2 23 +#define R9A09G011_SDI1_CLK_HS 24 +#define R9A09G011_EMM_ACLK 25 +#define R9A09G011_EMM_IMCLK 26 +#define R9A09G011_EMM_IMCLK2 27 +#define R9A09G011_EMM_CLK_HS 28 +#define R9A09G011_NFI_ACLK 29 +#define R9A09G011_NFI_NF_CLK 30 + +#define R9A09G011_PCI_ACLK 31 +#define R9A09G011_PCI_CLK_PMU 32 +#define R9A09G011_PCI_APB_CLK 33 +#define R9A09G011_USB_ACLK_H 34 +#define R9A09G011_USB_ACLK_P 35 +#define R9A09G011_USB_PCLK 36 +#define R9A09G011_ETH0_CLK_AXI 37 +#define R9A09G011_ETH0_CLK_CHI 38 +#define R9A09G011_ETH0_GPTP_EXT 39 + +#define R9A09G011_SDT_CLK 40 +#define R9A09G011_SDT_CLKAPB 41 +#define R9A09G011_SDT_CLK48 42 +#define R9A09G011_GRP_CLK 43 +#define R9A09G011_CIF_P0_CLK 44 +#define R9A09G011_CIF_P1_CLK 45 +#define R9A09G011_CIF_APB_CLK 46 +#define R9A09G011_DCI_CLKAXI 47 +#define R9A09G011_DCI_CLKAPB 48 +#define R9A09G011_DCI_CLKDCI2 49 + +#define R9A09G011_HMI_PCLK 50 +#define R9A09G011_LCI_PCLK 51 +#define R9A09G011_LCI_ACLK 52 +#define R9A09G011_LCI_VCLK 53 +#define R9A09G011_LCI_LPCLK 54 + +#define R9A09G011_AUI_CLK 55 +#define R9A09G011_AUI_CLKAXI 56 +#define R9A09G011_AUI_CLKAPB 57 +#define R9A09G011_AUMCLK 58 +#define R9A09G011_GMCLK0 59 +#define R9A09G011_GMCLK1 60 +#define R9A09G011_MTR_CLK0 61 +#define R9A09G011_MTR_CLK1 62 +#define R9A09G011_MTR_CLKAPB 63 +#define R9A09G011_GFT_CLK 64 +#define R9A09G011_GFT_CLKAPB 65 +#define R9A09G011_GFT_MCLK 66 + +#define R9A09G011_ATGA_CLK 67 +#define R9A09G011_ATGA_CLKAPB 68 +#define R9A09G011_ATGB_CLK 69 +#define R9A09G011_ATGB_CLKAPB 70 +#define R9A09G011_SYC_CNT_CLK 71 + +#define R9A09G011_CPERI_GRPA_PCLK 72 +#define R9A09G011_TIM0_CLK 73 +#define R9A09G011_TIM1_CLK 74 +#define R9A09G011_TIM2_CLK 75 +#define R9A09G011_TIM3_CLK 76 +#define R9A09G011_TIM4_CLK 77 +#define R9A09G011_TIM5_CLK 78 +#define R9A09G011_TIM6_CLK 79 +#define R9A09G011_TIM7_CLK 80 +#define R9A09G011_IIC_PCLK0 81 + +#define R9A09G011_CPERI_GRPB_PCLK 82 +#define R9A09G011_TIM8_CLK 83 +#define R9A09G011_TIM9_CLK 84 +#define R9A09G011_TIM10_CLK 85 +#define R9A09G011_TIM11_CLK 86 +#define R9A09G011_TIM12_CLK 87 +#define R9A09G011_TIM13_CLK 88 +#define R9A09G011_TIM14_CLK 89 +#define R9A09G011_TIM15_CLK 90 +#define R9A09G011_IIC_PCLK1 91 + +#define R9A09G011_CPERI_GRPC_PCLK 92 +#define R9A09G011_TIM16_CLK 93 +#define R9A09G011_TIM17_CLK 94 +#define R9A09G011_TIM18_CLK 95 +#define R9A09G011_TIM19_CLK 96 +#define R9A09G011_TIM20_CLK 97 +#define R9A09G011_TIM21_CLK 98 +#define R9A09G011_TIM22_CLK 99 +#define R9A09G011_TIM23_CLK 100 +#define R9A09G011_WDT0_PCLK 101 +#define R9A09G011_WDT0_CLK 102 +#define R9A09G011_WDT1_PCLK 103 +#define R9A09G011_WDT1_CLK 104 + +#define R9A09G011_CPERI_GRPD_PCLK 105 +#define R9A09G011_TIM24_CLK 106 +#define R9A09G011_TIM25_CLK 107 +#define R9A09G011_TIM26_CLK 108 +#define R9A09G011_TIM27_CLK 109 +#define R9A09G011_TIM28_CLK 110 +#define R9A09G011_TIM29_CLK 111 +#define R9A09G011_TIM30_CLK 112 +#define R9A09G011_TIM31_CLK 113 + +#define R9A09G011_CPERI_GRPE_PCLK 114 +#define R9A09G011_PWM0_CLK 115 +#define R9A09G011_PWM1_CLK 116 +#define R9A09G011_PWM2_CLK 117 +#define R9A09G011_PWM3_CLK 118 +#define R9A09G011_PWM4_CLK 119 +#define R9A09G011_PWM5_CLK 120 +#define R9A09G011_PWM6_CLK 121 +#define R9A09G011_PWM7_CLK 122 + +#define R9A09G011_CPERI_GRPF_PCLK 123 +#define R9A09G011_PWM8_CLK 124 +#define R9A09G011_PWM9_CLK 125 +#define R9A09G011_PWM10_CLK 126 +#define R9A09G011_PWM11_CLK 127 +#define R9A09G011_PWM12_CLK 128 +#define R9A09G011_PWM13_CLK 129 +#define R9A09G011_PWM14_CLK 130 +#define R9A09G011_PWM15_CLK 131 + +#define R9A09G011_CPERI_GRPG_PCLK 132 +#define R9A09G011_CPERI_GRPH_PCLK 133 +#define R9A09G011_URT_PCLK 134 +#define R9A09G011_URT0_CLK 135 +#define R9A09G011_URT1_CLK 136 +#define R9A09G011_CSI0_CLK 137 +#define R9A09G011_CSI1_CLK 138 +#define R9A09G011_CSI2_CLK 139 +#define R9A09G011_CSI3_CLK 140 +#define R9A09G011_CSI4_CLK 141 +#define R9A09G011_CSI5_CLK 142 + +#define R9A09G011_ICB_ACLK1 143 +#define R9A09G011_ICB_GIC_CLK 144 +#define R9A09G011_ICB_MPCLK1 145 +#define R9A09G011_ICB_SPCLK1 146 +#define R9A09G011_ICB_CLK48 147 +#define R9A09G011_ICB_CLK48_2 148 +#define R9A09G011_ICB_CLK48_3 149 +#define R9A09G011_ICB_CLK48_4L 150 +#define R9A09G011_ICB_CLK48_4R 151 +#define R9A09G011_ICB_CLK48_5 152 +#define R9A09G011_ICB_CST_ATB_SB_CLK 153 +#define R9A09G011_ICB_CST_CS_CLK 154 +#define R9A09G011_ICB_CLK100_1 155 +#define R9A09G011_ICB_ETH0_CLK_AXI 156 +#define R9A09G011_ICB_DCI_CLKAXI 157 +#define R9A09G011_ICB_SYC_CNT_CLK 158 + +#define R9A09G011_ICB_DRPA_ACLK 159 +#define R9A09G011_ICB_RFX_ACLK 160 +#define R9A09G011_ICB_RFX_PCLK5 161 +#define R9A09G011_ICB_MMC_ACLK 162 + +#define R9A09G011_ICB_MPCLK3 163 +#define R9A09G011_ICB_CIMA_CLK 164 +#define R9A09G011_ICB_CIMB_CLK 165 +#define R9A09G011_ICB_BIMA_CLK 166 +#define R9A09G011_ICB_FCD_CLKAXI 167 +#define R9A09G011_ICB_VD_ACLK4 168 +#define R9A09G011_ICB_MPCLK4 169 +#define R9A09G011_ICB_VCD_PCLK4 170 + +#define R9A09G011_CA53_CLK 171 +#define R9A09G011_CA53_ACLK 172 +#define R9A09G011_CA53_APCLK_DBG 173 +#define R9A09G011_CST_APB_CA53_CLK 174 +#define R9A09G011_CA53_ATCLK 175 +#define R9A09G011_CST_CS_CLK 176 +#define R9A09G011_CA53_TSCLK 177 +#define R9A09G011_CST_TS_CLK 178 +#define R9A09G011_CA53_APCLK_REG 179 + +#define R9A09G011_DRPA_ACLK 180 +#define R9A09G011_DRPA_DCLK 181 +#define R9A09G011_DRPA_INITCLK 182 + +#define R9A09G011_RAMB0_ACLK 183 +#define R9A09G011_RAMB1_ACLK 184 +#define R9A09G011_RAMB2_ACLK 185 +#define R9A09G011_RAMB3_ACLK 186 + +#define R9A09G011_CIMA_CLKAPB 187 +#define R9A09G011_CIMA_CLK 188 +#define R9A09G011_CIMB_CLK 189 +#define R9A09G011_FAFA_CLK 190 +#define R9A09G011_STG_CLKAXI 191 +#define R9A09G011_STG_CLK0 192 + +#define R9A09G011_BIMA_CLKAPB 193 +#define R9A09G011_BIMA_CLK 194 +#define R9A09G011_FAFB_CLK 195 +#define R9A09G011_FCD_CLK 196 +#define R9A09G011_FCD_CLKAXI 197 + +#define R9A09G011_RIM_CLK 198 +#define R9A09G011_VCD_ACLK 199 +#define R9A09G011_VCD_PCLK 200 +#define R9A09G011_JPG0_CLK 201 +#define R9A09G011_JPG0_ACLK 202 + +#define R9A09G011_MMC_CORE_DDRC_CLK 203 +#define R9A09G011_MMC_ACLK 204 +#define R9A09G011_MMC_PCLK 205 +#define R9A09G011_DDI_APBCLK 206 + +/* Resets */ +#define R9A09G011_SYS_RST_N 0 +#define R9A09G011_PFC_PRESETN 1 +#define R9A09G011_RAMA_ARESETN 2 +#define R9A09G011_ROM_ARESETN 3 +#define R9A09G011_DMAA_ARESETN 4 +#define R9A09G011_SEC_ARESETN 5 +#define R9A09G011_SEC_PRESETN 6 +#define R9A09G011_SEC_RSTB 7 +#define R9A09G011_TSU0_RESETN 8 +#define R9A09G011_TSU1_RESETN 9 +#define R9A09G011_PMC_RESET_N 10 + +#define R9A09G011_CST_NTRST 11 +#define R9A09G011_CST_NPOTRST 12 +#define R9A09G011_CST_NTRST2 13 +#define R9A09G011_CST_CS_RESETN 14 +#define R9A09G011_CST_TS_RESETN 15 +#define R9A09G011_CST_TRESETN 16 +#define R9A09G011_CST_SB_RESETN 17 +#define R9A09G011_CST_AHB_RESETN 18 +#define R9A09G011_CST_TS_SB_RESETN 19 +#define R9A09G011_CST_APB_CA53_RESETN 20 +#define R9A09G011_CST_ATB_SB_RESETN 21 + +#define R9A09G011_SDI0_IXRST 22 +#define R9A09G011_SDI1_IXRST 23 +#define R9A09G011_EMM_IXRST 24 +#define R9A09G011_NFI_MARESETN 25 +#define R9A09G011_NFI_REG_RST_N 26 +#define R9A09G011_USB_PRESET_N 27 +#define R9A09G011_USB_DRD_RESET 28 +#define R9A09G011_USB_ARESETN_P 29 +#define R9A09G011_USB_ARESETN_H 30 +#define R9A09G011_ETH0_RST_HW_N 31 +#define R9A09G011_PCI_ARESETN 32 + +#define R9A09G011_SDT_RSTSYSAX 33 +#define R9A09G011_GRP_RESETN 34 +#define R9A09G011_CIF_RST_N 35 +#define R9A09G011_DCU_RSTSYSAX 36 +#define R9A09G011_HMI_RST_N 37 +#define R9A09G011_HMI_PRESETN 38 +#define R9A09G011_LCI_PRESETN 39 +#define R9A09G011_LCI_ARESETN 40 + +#define R9A09G011_AUI_RSTSYSAX 41 +#define R9A09G011_MTR_RSTSYSAX 42 +#define R9A09G011_GFT_RSTSYSAX 43 +#define R9A09G011_ATGA_RSTSYSAX 44 +#define R9A09G011_ATGB_RSTSYSAX 45 +#define R9A09G011_SYC_RST_N 46 + +#define R9A09G011_TIM_GPA_PRESETN 47 +#define R9A09G011_TIM_GPB_PRESETN 48 +#define R9A09G011_TIM_GPC_PRESETN 49 +#define R9A09G011_TIM_GPD_PRESETN 50 +#define R9A09G011_PWM_GPE_PRESETN 51 +#define R9A09G011_PWM_GPF_PRESETN 52 +#define R9A09G011_CSI_GPG_PRESETN 53 +#define R9A09G011_CSI_GPH_PRESETN 54 +#define R9A09G011_IIC_GPA_PRESETN 55 +#define R9A09G011_IIC_GPB_PRESETN 56 +#define R9A09G011_URT_PRESETN 57 +#define R9A09G011_WDT0_PRESETN 58 +#define R9A09G011_WDT1_PRESETN 59 + +#define R9A09G011_ICB_PD_AWO_RST_N 60 +#define R9A09G011_ICB_PD_MMC_RST_N 61 +#define R9A09G011_ICB_PD_VD0_RST_N 62 +#define R9A09G011_ICB_PD_VD1_RST_N 63 +#define R9A09G011_ICB_PD_RFX_RST_N 64 + +#define R9A09G011_CA53_NCPUPORESET0 65 +#define R9A09G011_CA53_NCPUPORESET1 66 +#define R9A09G011_CA53_NCORERESET0 67 +#define R9A09G011_CA53_NCORERESET1 68 +#define R9A09G011_CA53_NPRESETDBG 69 +#define R9A09G011_CA53_L2RESET 70 +#define R9A09G011_CA53_NMISCRESET_HM 71 +#define R9A09G011_CA53_NMISCRESET_SM 72 +#define R9A09G011_CA53_NARESET 73 + +#define R9A09G011_DRPA_ARESETN 74 + +#define R9A09G011_RAMB0_ARESETN 75 +#define R9A09G011_RAMB1_ARESETN 76 +#define R9A09G011_RAMB2_ARESETN 77 +#define R9A09G011_RAMB3_ARESETN 78 + +#define R9A09G011_CIMA_RSTSYSAX 79 +#define R9A09G011_CIMB_RSTSYSAX 80 +#define R9A09G011_FAFA_RSTSYSAX 81 +#define R9A09G011_STG_RSTSYSAX 82 + +#define R9A09G011_BIMA_RSTSYSAX 83 +#define R9A09G011_FAFB_RSTSYSAX 84 +#define R9A09G011_FCD_RSTSYSAX 85 +#define R9A09G011_RIM_RSTSYSAX 86 +#define R9A09G011_VCD_RESETN 87 +#define R9A09G011_JPG_XRESET 88 + +#define R9A09G011_MMC_CORE_DDRC_RSTN 89 +#define R9A09G011_MMC_ARESETN_N 90 +#define R9A09G011_MMC_PRESETN 91 +#define R9A09G011_DDI_PWROK 92 +#define R9A09G011_DDI_RESET 93 +#define R9A09G011_DDI_RESETN_APB 94 + +#endif /* __DT_BINDINGS_CLOCK_R9A09G011_CPG_H__ */ diff --git a/include/dt-bindings/clock/rk3036-cru.h b/include/dt-bindings/clock/rk3036-cru.h index 35a5a01f9697..a96a9870ad59 100644 --- a/include/dt-bindings/clock/rk3036-cru.h +++ b/include/dt-bindings/clock/rk3036-cru.h @@ -81,6 +81,7 @@ #define HCLK_OTG0 449 #define HCLK_OTG1 450 #define HCLK_NANDC 453 +#define HCLK_SFC 454 #define HCLK_SDMMC 456 #define HCLK_SDIO 457 #define HCLK_EMMC 459 diff --git a/include/dt-bindings/clock/rk3368-cru.h b/include/dt-bindings/clock/rk3368-cru.h index 0a06c5f514d7..83c72a163fd3 100644 --- a/include/dt-bindings/clock/rk3368-cru.h +++ b/include/dt-bindings/clock/rk3368-cru.h @@ -78,6 +78,7 @@ #define SCLK_TIMER13 136 #define SCLK_TIMER14 137 #define SCLK_TIMER15 138 +#define SCLK_VIP_OUT 139 #define DCLK_VOP 190 #define MCLK_CRYPTO 191 @@ -148,6 +149,8 @@ #define PCLK_VIP 367 #define PCLK_WDT 368 #define PCLK_EFUSE256 369 +#define PCLK_DPHYRX 370 +#define PCLK_DPHYTX0 371 /* hclk gates */ #define HCLK_SFC 448 diff --git a/include/dt-bindings/clock/rk3568-cru.h b/include/dt-bindings/clock/rk3568-cru.h new file mode 100644 index 000000000000..d29890865150 --- /dev/null +++ b/include/dt-bindings/clock/rk3568-cru.h @@ -0,0 +1,926 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2021 Rockchip Electronics Co. Ltd. + * Author: Elaine Zhang <zhangqing@rock-chips.com> + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H + +/* pmucru-clocks indices */ + +/* pmucru plls */ +#define PLL_PPLL 1 +#define PLL_HPLL 2 + +/* pmucru clocks */ +#define XIN_OSC0_DIV 4 +#define CLK_RTC_32K 5 +#define CLK_PMU 6 +#define CLK_I2C0 7 +#define CLK_RTC32K_FRAC 8 +#define CLK_UART0_DIV 9 +#define CLK_UART0_FRAC 10 +#define SCLK_UART0 11 +#define DBCLK_GPIO0 12 +#define CLK_PWM0 13 +#define CLK_CAPTURE_PWM0_NDFT 14 +#define CLK_PMUPVTM 15 +#define CLK_CORE_PMUPVTM 16 +#define CLK_REF24M 17 +#define XIN_OSC0_USBPHY0_G 18 +#define CLK_USBPHY0_REF 19 +#define XIN_OSC0_USBPHY1_G 20 +#define CLK_USBPHY1_REF 21 +#define XIN_OSC0_MIPIDSIPHY0_G 22 +#define CLK_MIPIDSIPHY0_REF 23 +#define XIN_OSC0_MIPIDSIPHY1_G 24 +#define CLK_MIPIDSIPHY1_REF 25 +#define CLK_WIFI_DIV 26 +#define CLK_WIFI_OSC0 27 +#define CLK_WIFI 28 +#define CLK_PCIEPHY0_DIV 29 +#define CLK_PCIEPHY0_OSC0 30 +#define CLK_PCIEPHY0_REF 31 +#define CLK_PCIEPHY1_DIV 32 +#define CLK_PCIEPHY1_OSC0 33 +#define CLK_PCIEPHY1_REF 34 +#define CLK_PCIEPHY2_DIV 35 +#define CLK_PCIEPHY2_OSC0 36 +#define CLK_PCIEPHY2_REF 37 +#define CLK_PCIE30PHY_REF_M 38 +#define CLK_PCIE30PHY_REF_N 39 +#define CLK_HDMI_REF 40 +#define XIN_OSC0_EDPPHY_G 41 +#define PCLK_PDPMU 42 +#define PCLK_PMU 43 +#define PCLK_UART0 44 +#define PCLK_I2C0 45 +#define PCLK_GPIO0 46 +#define PCLK_PMUPVTM 47 +#define PCLK_PWM0 48 +#define CLK_PDPMU 49 +#define SCLK_32K_IOE 50 + +#define CLKPMU_NR_CLKS (SCLK_32K_IOE + 1) + +/* cru-clocks indices */ + +/* cru plls */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_CPLL 3 +#define PLL_GPLL 4 +#define PLL_VPLL 5 +#define PLL_NPLL 6 + +/* cru clocks */ +#define CPLL_333M 9 +#define ARMCLK 10 +#define USB480M 11 +#define ACLK_CORE_NIU2BUS 18 +#define CLK_CORE_PVTM 19 +#define CLK_CORE_PVTM_CORE 20 +#define CLK_CORE_PVTPLL 21 +#define CLK_GPU_SRC 22 +#define CLK_GPU_PRE_NDFT 23 +#define CLK_GPU_PRE_MUX 24 +#define ACLK_GPU_PRE 25 +#define PCLK_GPU_PRE 26 +#define CLK_GPU 27 +#define CLK_GPU_NP5 28 +#define PCLK_GPU_PVTM 29 +#define CLK_GPU_PVTM 30 +#define CLK_GPU_PVTM_CORE 31 +#define CLK_GPU_PVTPLL 32 +#define CLK_NPU_SRC 33 +#define CLK_NPU_PRE_NDFT 34 +#define CLK_NPU 35 +#define CLK_NPU_NP5 36 +#define HCLK_NPU_PRE 37 +#define PCLK_NPU_PRE 38 +#define ACLK_NPU_PRE 39 +#define ACLK_NPU 40 +#define HCLK_NPU 41 +#define PCLK_NPU_PVTM 42 +#define CLK_NPU_PVTM 43 +#define CLK_NPU_PVTM_CORE 44 +#define CLK_NPU_PVTPLL 45 +#define CLK_DDRPHY1X_SRC 46 +#define CLK_DDRPHY1X_HWFFC_SRC 47 +#define CLK_DDR1X 48 +#define CLK_MSCH 49 +#define CLK24_DDRMON 50 +#define ACLK_GIC_AUDIO 51 +#define HCLK_GIC_AUDIO 52 +#define HCLK_SDMMC_BUFFER 53 +#define DCLK_SDMMC_BUFFER 54 +#define ACLK_GIC600 55 +#define ACLK_SPINLOCK 56 +#define HCLK_I2S0_8CH 57 +#define HCLK_I2S1_8CH 58 +#define HCLK_I2S2_2CH 59 +#define HCLK_I2S3_2CH 60 +#define CLK_I2S0_8CH_TX_SRC 61 +#define CLK_I2S0_8CH_TX_FRAC 62 +#define MCLK_I2S0_8CH_TX 63 +#define I2S0_MCLKOUT_TX 64 +#define CLK_I2S0_8CH_RX_SRC 65 +#define CLK_I2S0_8CH_RX_FRAC 66 +#define MCLK_I2S0_8CH_RX 67 +#define I2S0_MCLKOUT_RX 68 +#define CLK_I2S1_8CH_TX_SRC 69 +#define CLK_I2S1_8CH_TX_FRAC 70 +#define MCLK_I2S1_8CH_TX 71 +#define I2S1_MCLKOUT_TX 72 +#define CLK_I2S1_8CH_RX_SRC 73 +#define CLK_I2S1_8CH_RX_FRAC 74 +#define MCLK_I2S1_8CH_RX 75 +#define I2S1_MCLKOUT_RX 76 +#define CLK_I2S2_2CH_SRC 77 +#define CLK_I2S2_2CH_FRAC 78 +#define MCLK_I2S2_2CH 79 +#define I2S2_MCLKOUT 80 +#define CLK_I2S3_2CH_TX_SRC 81 +#define CLK_I2S3_2CH_TX_FRAC 82 +#define MCLK_I2S3_2CH_TX 83 +#define I2S3_MCLKOUT_TX 84 +#define CLK_I2S3_2CH_RX_SRC 85 +#define CLK_I2S3_2CH_RX_FRAC 86 +#define MCLK_I2S3_2CH_RX 87 +#define I2S3_MCLKOUT_RX 88 +#define HCLK_PDM 89 +#define MCLK_PDM 90 +#define HCLK_VAD 91 +#define HCLK_SPDIF_8CH 92 +#define MCLK_SPDIF_8CH_SRC 93 +#define MCLK_SPDIF_8CH_FRAC 94 +#define MCLK_SPDIF_8CH 95 +#define HCLK_AUDPWM 96 +#define SCLK_AUDPWM_SRC 97 +#define SCLK_AUDPWM_FRAC 98 +#define SCLK_AUDPWM 99 +#define HCLK_ACDCDIG 100 +#define CLK_ACDCDIG_I2C 101 +#define CLK_ACDCDIG_DAC 102 +#define CLK_ACDCDIG_ADC 103 +#define ACLK_SECURE_FLASH 104 +#define HCLK_SECURE_FLASH 105 +#define ACLK_CRYPTO_NS 106 +#define HCLK_CRYPTO_NS 107 +#define CLK_CRYPTO_NS_CORE 108 +#define CLK_CRYPTO_NS_PKA 109 +#define CLK_CRYPTO_NS_RNG 110 +#define HCLK_TRNG_NS 111 +#define CLK_TRNG_NS 112 +#define PCLK_OTPC_NS 113 +#define CLK_OTPC_NS_SBPI 114 +#define CLK_OTPC_NS_USR 115 +#define HCLK_NANDC 116 +#define NCLK_NANDC 117 +#define HCLK_SFC 118 +#define HCLK_SFC_XIP 119 +#define SCLK_SFC 120 +#define ACLK_EMMC 121 +#define HCLK_EMMC 122 +#define BCLK_EMMC 123 +#define CCLK_EMMC 124 +#define TCLK_EMMC 125 +#define ACLK_PIPE 126 +#define PCLK_PIPE 127 +#define PCLK_PIPE_GRF 128 +#define ACLK_PCIE20_MST 129 +#define ACLK_PCIE20_SLV 130 +#define ACLK_PCIE20_DBI 131 +#define PCLK_PCIE20 132 +#define CLK_PCIE20_AUX_NDFT 133 +#define CLK_PCIE20_AUX_DFT 134 +#define CLK_PCIE20_PIPE_DFT 135 +#define ACLK_PCIE30X1_MST 136 +#define ACLK_PCIE30X1_SLV 137 +#define ACLK_PCIE30X1_DBI 138 +#define PCLK_PCIE30X1 139 +#define CLK_PCIE30X1_AUX_NDFT 140 +#define CLK_PCIE30X1_AUX_DFT 141 +#define CLK_PCIE30X1_PIPE_DFT 142 +#define ACLK_PCIE30X2_MST 143 +#define ACLK_PCIE30X2_SLV 144 +#define ACLK_PCIE30X2_DBI 145 +#define PCLK_PCIE30X2 146 +#define CLK_PCIE30X2_AUX_NDFT 147 +#define CLK_PCIE30X2_AUX_DFT 148 +#define CLK_PCIE30X2_PIPE_DFT 149 +#define ACLK_SATA0 150 +#define CLK_SATA0_PMALIVE 151 +#define CLK_SATA0_RXOOB 152 +#define CLK_SATA0_PIPE_NDFT 153 +#define CLK_SATA0_PIPE_DFT 154 +#define ACLK_SATA1 155 +#define CLK_SATA1_PMALIVE 156 +#define CLK_SATA1_RXOOB 157 +#define CLK_SATA1_PIPE_NDFT 158 +#define CLK_SATA1_PIPE_DFT 159 +#define ACLK_SATA2 160 +#define CLK_SATA2_PMALIVE 161 +#define CLK_SATA2_RXOOB 162 +#define CLK_SATA2_PIPE_NDFT 163 +#define CLK_SATA2_PIPE_DFT 164 +#define ACLK_USB3OTG0 165 +#define CLK_USB3OTG0_REF 166 +#define CLK_USB3OTG0_SUSPEND 167 +#define ACLK_USB3OTG1 168 +#define CLK_USB3OTG1_REF 169 +#define CLK_USB3OTG1_SUSPEND 170 +#define CLK_XPCS_EEE 171 +#define PCLK_XPCS 172 +#define ACLK_PHP 173 +#define HCLK_PHP 174 +#define PCLK_PHP 175 +#define HCLK_SDMMC0 176 +#define CLK_SDMMC0 177 +#define HCLK_SDMMC1 178 +#define CLK_SDMMC1 179 +#define ACLK_GMAC0 180 +#define PCLK_GMAC0 181 +#define CLK_MAC0_2TOP 182 +#define CLK_MAC0_OUT 183 +#define CLK_MAC0_REFOUT 184 +#define CLK_GMAC0_PTP_REF 185 +#define ACLK_USB 186 +#define HCLK_USB 187 +#define PCLK_USB 188 +#define HCLK_USB2HOST0 189 +#define HCLK_USB2HOST0_ARB 190 +#define HCLK_USB2HOST1 191 +#define HCLK_USB2HOST1_ARB 192 +#define HCLK_SDMMC2 193 +#define CLK_SDMMC2 194 +#define ACLK_GMAC1 195 +#define PCLK_GMAC1 196 +#define CLK_MAC1_2TOP 197 +#define CLK_MAC1_OUT 198 +#define CLK_MAC1_REFOUT 199 +#define CLK_GMAC1_PTP_REF 200 +#define ACLK_PERIMID 201 +#define HCLK_PERIMID 202 +#define ACLK_VI 203 +#define HCLK_VI 204 +#define PCLK_VI 205 +#define ACLK_VICAP 206 +#define HCLK_VICAP 207 +#define DCLK_VICAP 208 +#define ICLK_VICAP_G 209 +#define ACLK_ISP 210 +#define HCLK_ISP 211 +#define CLK_ISP 212 +#define PCLK_CSI2HOST1 213 +#define CLK_CIF_OUT 214 +#define CLK_CAM0_OUT 215 +#define CLK_CAM1_OUT 216 +#define ACLK_VO 217 +#define HCLK_VO 218 +#define PCLK_VO 219 +#define ACLK_VOP_PRE 220 +#define ACLK_VOP 221 +#define HCLK_VOP 222 +#define DCLK_VOP0 223 +#define DCLK_VOP1 224 +#define DCLK_VOP2 225 +#define CLK_VOP_PWM 226 +#define ACLK_HDCP 227 +#define HCLK_HDCP 228 +#define PCLK_HDCP 229 +#define PCLK_HDMI_HOST 230 +#define CLK_HDMI_SFR 231 +#define PCLK_DSITX_0 232 +#define PCLK_DSITX_1 233 +#define PCLK_EDP_CTRL 234 +#define CLK_EDP_200M 235 +#define ACLK_VPU_PRE 236 +#define HCLK_VPU_PRE 237 +#define ACLK_VPU 238 +#define HCLK_VPU 239 +#define ACLK_RGA_PRE 240 +#define HCLK_RGA_PRE 241 +#define PCLK_RGA_PRE 242 +#define ACLK_RGA 243 +#define HCLK_RGA 244 +#define CLK_RGA_CORE 245 +#define ACLK_IEP 246 +#define HCLK_IEP 247 +#define CLK_IEP_CORE 248 +#define HCLK_EBC 249 +#define DCLK_EBC 250 +#define ACLK_JDEC 251 +#define HCLK_JDEC 252 +#define ACLK_JENC 253 +#define HCLK_JENC 254 +#define PCLK_EINK 255 +#define HCLK_EINK 256 +#define ACLK_RKVENC_PRE 257 +#define HCLK_RKVENC_PRE 258 +#define ACLK_RKVENC 259 +#define HCLK_RKVENC 260 +#define CLK_RKVENC_CORE 261 +#define ACLK_RKVDEC_PRE 262 +#define HCLK_RKVDEC_PRE 263 +#define ACLK_RKVDEC 264 +#define HCLK_RKVDEC 265 +#define CLK_RKVDEC_CA 266 +#define CLK_RKVDEC_CORE 267 +#define CLK_RKVDEC_HEVC_CA 268 +#define ACLK_BUS 269 +#define PCLK_BUS 270 +#define PCLK_TSADC 271 +#define CLK_TSADC_TSEN 272 +#define CLK_TSADC 273 +#define PCLK_SARADC 274 +#define CLK_SARADC 275 +#define PCLK_SCR 276 +#define PCLK_WDT_NS 277 +#define TCLK_WDT_NS 278 +#define ACLK_DMAC0 279 +#define ACLK_DMAC1 280 +#define ACLK_MCU 281 +#define PCLK_INTMUX 282 +#define PCLK_MAILBOX 283 +#define PCLK_UART1 284 +#define CLK_UART1_SRC 285 +#define CLK_UART1_FRAC 286 +#define SCLK_UART1 287 +#define PCLK_UART2 288 +#define CLK_UART2_SRC 289 +#define CLK_UART2_FRAC 290 +#define SCLK_UART2 291 +#define PCLK_UART3 292 +#define CLK_UART3_SRC 293 +#define CLK_UART3_FRAC 294 +#define SCLK_UART3 295 +#define PCLK_UART4 296 +#define CLK_UART4_SRC 297 +#define CLK_UART4_FRAC 298 +#define SCLK_UART4 299 +#define PCLK_UART5 300 +#define CLK_UART5_SRC 301 +#define CLK_UART5_FRAC 302 +#define SCLK_UART5 303 +#define PCLK_UART6 304 +#define CLK_UART6_SRC 305 +#define CLK_UART6_FRAC 306 +#define SCLK_UART6 307 +#define PCLK_UART7 308 +#define CLK_UART7_SRC 309 +#define CLK_UART7_FRAC 310 +#define SCLK_UART7 311 +#define PCLK_UART8 312 +#define CLK_UART8_SRC 313 +#define CLK_UART8_FRAC 314 +#define SCLK_UART8 315 +#define PCLK_UART9 316 +#define CLK_UART9_SRC 317 +#define CLK_UART9_FRAC 318 +#define SCLK_UART9 319 +#define PCLK_CAN0 320 +#define CLK_CAN0 321 +#define PCLK_CAN1 322 +#define CLK_CAN1 323 +#define PCLK_CAN2 324 +#define CLK_CAN2 325 +#define CLK_I2C 326 +#define PCLK_I2C1 327 +#define CLK_I2C1 328 +#define PCLK_I2C2 329 +#define CLK_I2C2 330 +#define PCLK_I2C3 331 +#define CLK_I2C3 332 +#define PCLK_I2C4 333 +#define CLK_I2C4 334 +#define PCLK_I2C5 335 +#define CLK_I2C5 336 +#define PCLK_SPI0 337 +#define CLK_SPI0 338 +#define PCLK_SPI1 339 +#define CLK_SPI1 340 +#define PCLK_SPI2 341 +#define CLK_SPI2 342 +#define PCLK_SPI3 343 +#define CLK_SPI3 344 +#define PCLK_PWM1 345 +#define CLK_PWM1 346 +#define CLK_PWM1_CAPTURE 347 +#define PCLK_PWM2 348 +#define CLK_PWM2 349 +#define CLK_PWM2_CAPTURE 350 +#define PCLK_PWM3 351 +#define CLK_PWM3 352 +#define CLK_PWM3_CAPTURE 353 +#define DBCLK_GPIO 354 +#define PCLK_GPIO1 355 +#define DBCLK_GPIO1 356 +#define PCLK_GPIO2 357 +#define DBCLK_GPIO2 358 +#define PCLK_GPIO3 359 +#define DBCLK_GPIO3 360 +#define PCLK_GPIO4 361 +#define DBCLK_GPIO4 362 +#define OCC_SCAN_CLK_GPIO 363 +#define PCLK_TIMER 364 +#define CLK_TIMER0 365 +#define CLK_TIMER1 366 +#define CLK_TIMER2 367 +#define CLK_TIMER3 368 +#define CLK_TIMER4 369 +#define CLK_TIMER5 370 +#define ACLK_TOP_HIGH 371 +#define ACLK_TOP_LOW 372 +#define HCLK_TOP 373 +#define PCLK_TOP 374 +#define PCLK_PCIE30PHY 375 +#define CLK_OPTC_ARB 376 +#define PCLK_MIPICSIPHY 377 +#define PCLK_MIPIDSIPHY0 378 +#define PCLK_MIPIDSIPHY1 379 +#define PCLK_PIPEPHY0 380 +#define PCLK_PIPEPHY1 381 +#define PCLK_PIPEPHY2 382 +#define PCLK_CPU_BOOST 383 +#define CLK_CPU_BOOST 384 +#define PCLK_OTPPHY 385 +#define SCLK_GMAC0 386 +#define SCLK_GMAC0_RGMII_SPEED 387 +#define SCLK_GMAC0_RMII_SPEED 388 +#define SCLK_GMAC0_RX_TX 389 +#define SCLK_GMAC1 390 +#define SCLK_GMAC1_RGMII_SPEED 391 +#define SCLK_GMAC1_RMII_SPEED 392 +#define SCLK_GMAC1_RX_TX 393 +#define SCLK_SDMMC0_DRV 394 +#define SCLK_SDMMC0_SAMPLE 395 +#define SCLK_SDMMC1_DRV 396 +#define SCLK_SDMMC1_SAMPLE 397 +#define SCLK_SDMMC2_DRV 398 +#define SCLK_SDMMC2_SAMPLE 399 +#define SCLK_EMMC_DRV 400 +#define SCLK_EMMC_SAMPLE 401 +#define PCLK_EDPPHY_GRF 402 +#define CLK_HDMI_CEC 403 +#define CLK_I2S0_8CH_TX 404 +#define CLK_I2S0_8CH_RX 405 +#define CLK_I2S1_8CH_TX 406 +#define CLK_I2S1_8CH_RX 407 +#define CLK_I2S2_2CH 408 +#define CLK_I2S3_2CH_TX 409 +#define CLK_I2S3_2CH_RX 410 +#define CPLL_500M 411 +#define CPLL_250M 412 +#define CPLL_125M 413 +#define CPLL_62P5M 414 +#define CPLL_50M 415 +#define CPLL_25M 416 +#define CPLL_100M 417 +#define SCLK_DDRCLK 418 + +#define PCLK_CORE_PVTM 450 + +#define CLK_NR_CLKS (PCLK_CORE_PVTM + 1) + +/* pmu soft-reset indices */ +/* pmucru_softrst_con0 */ +#define SRST_P_PDPMU_NIU 0 +#define SRST_P_PMUCRU 1 +#define SRST_P_PMUGRF 2 +#define SRST_P_I2C0 3 +#define SRST_I2C0 4 +#define SRST_P_UART0 5 +#define SRST_S_UART0 6 +#define SRST_P_PWM0 7 +#define SRST_PWM0 8 +#define SRST_P_GPIO0 9 +#define SRST_GPIO0 10 +#define SRST_P_PMUPVTM 11 +#define SRST_PMUPVTM 12 + +/* soft-reset indices */ + +/* cru_softrst_con0 */ +#define SRST_NCORERESET0 0 +#define SRST_NCORERESET1 1 +#define SRST_NCORERESET2 2 +#define SRST_NCORERESET3 3 +#define SRST_NCPUPORESET0 4 +#define SRST_NCPUPORESET1 5 +#define SRST_NCPUPORESET2 6 +#define SRST_NCPUPORESET3 7 +#define SRST_NSRESET 8 +#define SRST_NSPORESET 9 +#define SRST_NATRESET 10 +#define SRST_NGICRESET 11 +#define SRST_NPRESET 12 +#define SRST_NPERIPHRESET 13 + +/* cru_softrst_con1 */ +#define SRST_A_CORE_NIU2DDR 16 +#define SRST_A_CORE_NIU2BUS 17 +#define SRST_P_DBG_NIU 18 +#define SRST_P_DBG 19 +#define SRST_P_DBG_DAPLITE 20 +#define SRST_DAP 21 +#define SRST_A_ADB400_CORE2GIC 22 +#define SRST_A_ADB400_GIC2CORE 23 +#define SRST_P_CORE_GRF 24 +#define SRST_P_CORE_PVTM 25 +#define SRST_CORE_PVTM 26 +#define SRST_CORE_PVTPLL 27 + +/* cru_softrst_con2 */ +#define SRST_GPU 32 +#define SRST_A_GPU_NIU 33 +#define SRST_P_GPU_NIU 34 +#define SRST_P_GPU_PVTM 35 +#define SRST_GPU_PVTM 36 +#define SRST_GPU_PVTPLL 37 +#define SRST_A_NPU_NIU 40 +#define SRST_H_NPU_NIU 41 +#define SRST_P_NPU_NIU 42 +#define SRST_A_NPU 43 +#define SRST_H_NPU 44 +#define SRST_P_NPU_PVTM 45 +#define SRST_NPU_PVTM 46 +#define SRST_NPU_PVTPLL 47 + +/* cru_softrst_con3 */ +#define SRST_A_MSCH 51 +#define SRST_HWFFC_CTRL 52 +#define SRST_DDR_ALWAYSON 53 +#define SRST_A_DDRSPLIT 54 +#define SRST_DDRDFI_CTL 55 +#define SRST_A_DMA2DDR 57 + +/* cru_softrst_con4 */ +#define SRST_A_PERIMID_NIU 64 +#define SRST_H_PERIMID_NIU 65 +#define SRST_A_GIC_AUDIO_NIU 66 +#define SRST_H_GIC_AUDIO_NIU 67 +#define SRST_A_GIC600 68 +#define SRST_A_GIC600_DEBUG 69 +#define SRST_A_GICADB_CORE2GIC 70 +#define SRST_A_GICADB_GIC2CORE 71 +#define SRST_A_SPINLOCK 72 +#define SRST_H_SDMMC_BUFFER 73 +#define SRST_D_SDMMC_BUFFER 74 +#define SRST_H_I2S0_8CH 75 +#define SRST_H_I2S1_8CH 76 +#define SRST_H_I2S2_2CH 77 +#define SRST_H_I2S3_2CH 78 + +/* cru_softrst_con5 */ +#define SRST_M_I2S0_8CH_TX 80 +#define SRST_M_I2S0_8CH_RX 81 +#define SRST_M_I2S1_8CH_TX 82 +#define SRST_M_I2S1_8CH_RX 83 +#define SRST_M_I2S2_2CH 84 +#define SRST_M_I2S3_2CH_TX 85 +#define SRST_M_I2S3_2CH_RX 86 +#define SRST_H_PDM 87 +#define SRST_M_PDM 88 +#define SRST_H_VAD 89 +#define SRST_H_SPDIF_8CH 90 +#define SRST_M_SPDIF_8CH 91 +#define SRST_H_AUDPWM 92 +#define SRST_S_AUDPWM 93 +#define SRST_H_ACDCDIG 94 +#define SRST_ACDCDIG 95 + +/* cru_softrst_con6 */ +#define SRST_A_SECURE_FLASH_NIU 96 +#define SRST_H_SECURE_FLASH_NIU 97 +#define SRST_A_CRYPTO_NS 103 +#define SRST_H_CRYPTO_NS 104 +#define SRST_CRYPTO_NS_CORE 105 +#define SRST_CRYPTO_NS_PKA 106 +#define SRST_CRYPTO_NS_RNG 107 +#define SRST_H_TRNG_NS 108 +#define SRST_TRNG_NS 109 + +/* cru_softrst_con7 */ +#define SRST_H_NANDC 112 +#define SRST_N_NANDC 113 +#define SRST_H_SFC 114 +#define SRST_H_SFC_XIP 115 +#define SRST_S_SFC 116 +#define SRST_A_EMMC 117 +#define SRST_H_EMMC 118 +#define SRST_B_EMMC 119 +#define SRST_C_EMMC 120 +#define SRST_T_EMMC 121 + +/* cru_softrst_con8 */ +#define SRST_A_PIPE_NIU 128 +#define SRST_P_PIPE_NIU 130 +#define SRST_P_PIPE_GRF 133 +#define SRST_A_SATA0 134 +#define SRST_SATA0_PIPE 135 +#define SRST_SATA0_PMALIVE 136 +#define SRST_SATA0_RXOOB 137 +#define SRST_A_SATA1 138 +#define SRST_SATA1_PIPE 139 +#define SRST_SATA1_PMALIVE 140 +#define SRST_SATA1_RXOOB 141 + +/* cru_softrst_con9 */ +#define SRST_A_SATA2 144 +#define SRST_SATA2_PIPE 145 +#define SRST_SATA2_PMALIVE 146 +#define SRST_SATA2_RXOOB 147 +#define SRST_USB3OTG0 148 +#define SRST_USB3OTG1 149 +#define SRST_XPCS 150 +#define SRST_XPCS_TX_DIV10 151 +#define SRST_XPCS_RX_DIV10 152 +#define SRST_XPCS_XGXS_RX 153 + +/* cru_softrst_con10 */ +#define SRST_P_PCIE20 160 +#define SRST_PCIE20_POWERUP 161 +#define SRST_MSTR_ARESET_PCIE20 162 +#define SRST_SLV_ARESET_PCIE20 163 +#define SRST_DBI_ARESET_PCIE20 164 +#define SRST_BRESET_PCIE20 165 +#define SRST_PERST_PCIE20 166 +#define SRST_CORE_RST_PCIE20 167 +#define SRST_NSTICKY_RST_PCIE20 168 +#define SRST_STICKY_RST_PCIE20 169 +#define SRST_PWR_RST_PCIE20 170 + +/* cru_softrst_con11 */ +#define SRST_P_PCIE30X1 176 +#define SRST_PCIE30X1_POWERUP 177 +#define SRST_M_ARESET_PCIE30X1 178 +#define SRST_S_ARESET_PCIE30X1 179 +#define SRST_D_ARESET_PCIE30X1 180 +#define SRST_BRESET_PCIE30X1 181 +#define SRST_PERST_PCIE30X1 182 +#define SRST_CORE_RST_PCIE30X1 183 +#define SRST_NSTC_RST_PCIE30X1 184 +#define SRST_STC_RST_PCIE30X1 185 +#define SRST_PWR_RST_PCIE30X1 186 + +/* cru_softrst_con12 */ +#define SRST_P_PCIE30X2 192 +#define SRST_PCIE30X2_POWERUP 193 +#define SRST_M_ARESET_PCIE30X2 194 +#define SRST_S_ARESET_PCIE30X2 195 +#define SRST_D_ARESET_PCIE30X2 196 +#define SRST_BRESET_PCIE30X2 197 +#define SRST_PERST_PCIE30X2 198 +#define SRST_CORE_RST_PCIE30X2 199 +#define SRST_NSTC_RST_PCIE30X2 200 +#define SRST_STC_RST_PCIE30X2 201 +#define SRST_PWR_RST_PCIE30X2 202 + +/* cru_softrst_con13 */ +#define SRST_A_PHP_NIU 208 +#define SRST_H_PHP_NIU 209 +#define SRST_P_PHP_NIU 210 +#define SRST_H_SDMMC0 211 +#define SRST_SDMMC0 212 +#define SRST_H_SDMMC1 213 +#define SRST_SDMMC1 214 +#define SRST_A_GMAC0 215 +#define SRST_GMAC0_TIMESTAMP 216 + +/* cru_softrst_con14 */ +#define SRST_A_USB_NIU 224 +#define SRST_H_USB_NIU 225 +#define SRST_P_USB_NIU 226 +#define SRST_P_USB_GRF 227 +#define SRST_H_USB2HOST0 228 +#define SRST_H_USB2HOST0_ARB 229 +#define SRST_USB2HOST0_UTMI 230 +#define SRST_H_USB2HOST1 231 +#define SRST_H_USB2HOST1_ARB 232 +#define SRST_USB2HOST1_UTMI 233 +#define SRST_H_SDMMC2 234 +#define SRST_SDMMC2 235 +#define SRST_A_GMAC1 236 +#define SRST_GMAC1_TIMESTAMP 237 + +/* cru_softrst_con15 */ +#define SRST_A_VI_NIU 240 +#define SRST_H_VI_NIU 241 +#define SRST_P_VI_NIU 242 +#define SRST_A_VICAP 247 +#define SRST_H_VICAP 248 +#define SRST_D_VICAP 249 +#define SRST_I_VICAP 250 +#define SRST_P_VICAP 251 +#define SRST_H_ISP 252 +#define SRST_ISP 253 +#define SRST_P_CSI2HOST1 255 + +/* cru_softrst_con16 */ +#define SRST_A_VO_NIU 256 +#define SRST_H_VO_NIU 257 +#define SRST_P_VO_NIU 258 +#define SRST_A_VOP_NIU 259 +#define SRST_A_VOP 260 +#define SRST_H_VOP 261 +#define SRST_VOP0 262 +#define SRST_VOP1 263 +#define SRST_VOP2 264 +#define SRST_VOP_PWM 265 +#define SRST_A_HDCP 266 +#define SRST_H_HDCP 267 +#define SRST_P_HDCP 268 +#define SRST_P_HDMI_HOST 270 +#define SRST_HDMI_HOST 271 + +/* cru_softrst_con17 */ +#define SRST_P_DSITX_0 272 +#define SRST_P_DSITX_1 273 +#define SRST_P_EDP_CTRL 274 +#define SRST_EDP_24M 275 +#define SRST_A_VPU_NIU 280 +#define SRST_H_VPU_NIU 281 +#define SRST_A_VPU 282 +#define SRST_H_VPU 283 +#define SRST_H_EINK 286 +#define SRST_P_EINK 287 + +/* cru_softrst_con18 */ +#define SRST_A_RGA_NIU 288 +#define SRST_H_RGA_NIU 289 +#define SRST_P_RGA_NIU 290 +#define SRST_A_RGA 292 +#define SRST_H_RGA 293 +#define SRST_RGA_CORE 294 +#define SRST_A_IEP 295 +#define SRST_H_IEP 296 +#define SRST_IEP_CORE 297 +#define SRST_H_EBC 298 +#define SRST_D_EBC 299 +#define SRST_A_JDEC 300 +#define SRST_H_JDEC 301 +#define SRST_A_JENC 302 +#define SRST_H_JENC 303 + +/* cru_softrst_con19 */ +#define SRST_A_VENC_NIU 304 +#define SRST_H_VENC_NIU 305 +#define SRST_A_RKVENC 307 +#define SRST_H_RKVENC 308 +#define SRST_RKVENC_CORE 309 + +/* cru_softrst_con20 */ +#define SRST_A_RKVDEC_NIU 320 +#define SRST_H_RKVDEC_NIU 321 +#define SRST_A_RKVDEC 322 +#define SRST_H_RKVDEC 323 +#define SRST_RKVDEC_CA 324 +#define SRST_RKVDEC_CORE 325 +#define SRST_RKVDEC_HEVC_CA 326 + +/* cru_softrst_con21 */ +#define SRST_A_BUS_NIU 336 +#define SRST_P_BUS_NIU 338 +#define SRST_P_CAN0 340 +#define SRST_CAN0 341 +#define SRST_P_CAN1 342 +#define SRST_CAN1 343 +#define SRST_P_CAN2 344 +#define SRST_CAN2 345 +#define SRST_P_GPIO1 346 +#define SRST_GPIO1 347 +#define SRST_P_GPIO2 348 +#define SRST_GPIO2 349 +#define SRST_P_GPIO3 350 +#define SRST_GPIO3 351 + +/* cru_softrst_con22 */ +#define SRST_P_GPIO4 352 +#define SRST_GPIO4 353 +#define SRST_P_I2C1 354 +#define SRST_I2C1 355 +#define SRST_P_I2C2 356 +#define SRST_I2C2 357 +#define SRST_P_I2C3 358 +#define SRST_I2C3 359 +#define SRST_P_I2C4 360 +#define SRST_I2C4 361 +#define SRST_P_I2C5 362 +#define SRST_I2C5 363 +#define SRST_P_OTPC_NS 364 +#define SRST_OTPC_NS_SBPI 365 +#define SRST_OTPC_NS_USR 366 + +/* cru_softrst_con23 */ +#define SRST_P_PWM1 368 +#define SRST_PWM1 369 +#define SRST_P_PWM2 370 +#define SRST_PWM2 371 +#define SRST_P_PWM3 372 +#define SRST_PWM3 373 +#define SRST_P_SPI0 374 +#define SRST_SPI0 375 +#define SRST_P_SPI1 376 +#define SRST_SPI1 377 +#define SRST_P_SPI2 378 +#define SRST_SPI2 379 +#define SRST_P_SPI3 380 +#define SRST_SPI3 381 + +/* cru_softrst_con24 */ +#define SRST_P_SARADC 384 +#define SRST_P_TSADC 385 +#define SRST_TSADC 386 +#define SRST_P_TIMER 387 +#define SRST_TIMER0 388 +#define SRST_TIMER1 389 +#define SRST_TIMER2 390 +#define SRST_TIMER3 391 +#define SRST_TIMER4 392 +#define SRST_TIMER5 393 +#define SRST_P_UART1 394 +#define SRST_S_UART1 395 + +/* cru_softrst_con25 */ +#define SRST_P_UART2 400 +#define SRST_S_UART2 401 +#define SRST_P_UART3 402 +#define SRST_S_UART3 403 +#define SRST_P_UART4 404 +#define SRST_S_UART4 405 +#define SRST_P_UART5 406 +#define SRST_S_UART5 407 +#define SRST_P_UART6 408 +#define SRST_S_UART6 409 +#define SRST_P_UART7 410 +#define SRST_S_UART7 411 +#define SRST_P_UART8 412 +#define SRST_S_UART8 413 +#define SRST_P_UART9 414 +#define SRST_S_UART9 415 + +/* cru_softrst_con26 */ +#define SRST_P_GRF 416 +#define SRST_P_GRF_VCCIO12 417 +#define SRST_P_GRF_VCCIO34 418 +#define SRST_P_GRF_VCCIO567 419 +#define SRST_P_SCR 420 +#define SRST_P_WDT_NS 421 +#define SRST_T_WDT_NS 422 +#define SRST_P_DFT2APB 423 +#define SRST_A_MCU 426 +#define SRST_P_INTMUX 427 +#define SRST_P_MAILBOX 428 + +/* cru_softrst_con27 */ +#define SRST_A_TOP_HIGH_NIU 432 +#define SRST_A_TOP_LOW_NIU 433 +#define SRST_H_TOP_NIU 434 +#define SRST_P_TOP_NIU 435 +#define SRST_P_TOP_CRU 438 +#define SRST_P_DDRPHY 439 +#define SRST_DDRPHY 440 +#define SRST_P_MIPICSIPHY 442 +#define SRST_P_MIPIDSIPHY0 443 +#define SRST_P_MIPIDSIPHY1 444 +#define SRST_P_PCIE30PHY 445 +#define SRST_PCIE30PHY 446 +#define SRST_P_PCIE30PHY_GRF 447 + +/* cru_softrst_con28 */ +#define SRST_P_APB2ASB_LEFT 448 +#define SRST_P_APB2ASB_BOTTOM 449 +#define SRST_P_ASB2APB_LEFT 450 +#define SRST_P_ASB2APB_BOTTOM 451 +#define SRST_P_PIPEPHY0 452 +#define SRST_PIPEPHY0 453 +#define SRST_P_PIPEPHY1 454 +#define SRST_PIPEPHY1 455 +#define SRST_P_PIPEPHY2 456 +#define SRST_PIPEPHY2 457 +#define SRST_P_USB2PHY0_GRF 458 +#define SRST_P_USB2PHY1_GRF 459 +#define SRST_P_CPU_BOOST 460 +#define SRST_CPU_BOOST 461 +#define SRST_P_OTPPHY 462 +#define SRST_OTPPHY 463 + +/* cru_softrst_con29 */ +#define SRST_USB2PHY0_POR 464 +#define SRST_USB2PHY0_USB3OTG0 465 +#define SRST_USB2PHY0_USB3OTG1 466 +#define SRST_USB2PHY1_POR 467 +#define SRST_USB2PHY1_USB2HOST0 468 +#define SRST_USB2PHY1_USB2HOST1 469 +#define SRST_P_EDPPHY_GRF 470 +#define SRST_TSADCPHY 471 +#define SRST_GMAC0_DELAYLINE 472 +#define SRST_GMAC1_DELAYLINE 473 +#define SRST_OTPC_ARB 474 +#define SRST_P_PIPEPHY0_GRF 475 +#define SRST_P_PIPEPHY1_GRF 476 +#define SRST_P_PIPEPHY2_GRF 477 + +#endif diff --git a/include/dt-bindings/clock/rockchip,rv1126-cru.h b/include/dt-bindings/clock/rockchip,rv1126-cru.h new file mode 100644 index 000000000000..e89a3a5a4a34 --- /dev/null +++ b/include/dt-bindings/clock/rockchip,rv1126-cru.h @@ -0,0 +1,632 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Rockchip Electronics Co. Ltd. + * Author: Finley Xiao <finley.xiao@rock-chips.com> + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1126_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RV1126_H + +/* pmucru-clocks indices */ + +/* pll clocks */ +#define PLL_GPLL 1 + +/* sclk (special clocks) */ +#define CLK_OSC0_DIV32K 2 +#define CLK_RTC32K 3 +#define CLK_WIFI_DIV 4 +#define CLK_WIFI_OSC0 5 +#define CLK_WIFI 6 +#define CLK_PMU 7 +#define SCLK_UART1_DIV 8 +#define SCLK_UART1_FRACDIV 9 +#define SCLK_UART1_MUX 10 +#define SCLK_UART1 11 +#define CLK_I2C0 12 +#define CLK_I2C2 13 +#define CLK_CAPTURE_PWM0 14 +#define CLK_PWM0 15 +#define CLK_CAPTURE_PWM1 16 +#define CLK_PWM1 17 +#define CLK_SPI0 18 +#define DBCLK_GPIO0 19 +#define CLK_PMUPVTM 20 +#define CLK_CORE_PMUPVTM 21 +#define CLK_REF12M 22 +#define CLK_USBPHY_OTG_REF 23 +#define CLK_USBPHY_HOST_REF 24 +#define CLK_REF24M 25 +#define CLK_MIPIDSIPHY_REF 26 + +/* pclk */ +#define PCLK_PDPMU 30 +#define PCLK_PMU 31 +#define PCLK_UART1 32 +#define PCLK_I2C0 33 +#define PCLK_I2C2 34 +#define PCLK_PWM0 35 +#define PCLK_PWM1 36 +#define PCLK_SPI0 37 +#define PCLK_GPIO0 38 +#define PCLK_PMUSGRF 39 +#define PCLK_PMUGRF 40 +#define PCLK_PMUCRU 41 +#define PCLK_CHIPVEROTP 42 +#define PCLK_PDPMU_NIU 43 +#define PCLK_PMUPVTM 44 +#define PCLK_SCRKEYGEN 45 + +#define CLKPMU_NR_CLKS (PCLK_SCRKEYGEN + 1) + +/* cru-clocks indices */ + +/* pll clocks */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_CPLL 3 +#define PLL_HPLL 4 + +/* sclk (special clocks) */ +#define ARMCLK 5 +#define USB480M 6 +#define CLK_CORE_CPUPVTM 7 +#define CLK_CPUPVTM 8 +#define CLK_SCR1 9 +#define CLK_SCR1_CORE 10 +#define CLK_SCR1_RTC 11 +#define CLK_SCR1_JTAG 12 +#define SCLK_UART0_DIV 13 +#define SCLK_UART0_FRAC 14 +#define SCLK_UART0_MUX 15 +#define SCLK_UART0 16 +#define SCLK_UART2_DIV 17 +#define SCLK_UART2_FRAC 18 +#define SCLK_UART2_MUX 19 +#define SCLK_UART2 20 +#define SCLK_UART3_DIV 21 +#define SCLK_UART3_FRAC 22 +#define SCLK_UART3_MUX 23 +#define SCLK_UART3 24 +#define SCLK_UART4_DIV 25 +#define SCLK_UART4_FRAC 26 +#define SCLK_UART4_MUX 27 +#define SCLK_UART4 28 +#define SCLK_UART5_DIV 29 +#define SCLK_UART5_FRAC 30 +#define SCLK_UART5_MUX 31 +#define SCLK_UART5 32 +#define CLK_I2C1 33 +#define CLK_I2C3 34 +#define CLK_I2C4 35 +#define CLK_I2C5 36 +#define CLK_SPI1 37 +#define CLK_CAPTURE_PWM2 38 +#define CLK_PWM2 39 +#define DBCLK_GPIO1 40 +#define DBCLK_GPIO2 41 +#define DBCLK_GPIO3 42 +#define DBCLK_GPIO4 43 +#define CLK_SARADC 44 +#define CLK_TIMER0 45 +#define CLK_TIMER1 46 +#define CLK_TIMER2 47 +#define CLK_TIMER3 48 +#define CLK_TIMER4 49 +#define CLK_TIMER5 50 +#define CLK_CAN 51 +#define CLK_NPU_TSADC 52 +#define CLK_NPU_TSADCPHY 53 +#define CLK_CPU_TSADC 54 +#define CLK_CPU_TSADCPHY 55 +#define CLK_CRYPTO_CORE 56 +#define CLK_CRYPTO_PKA 57 +#define MCLK_I2S0_TX_DIV 58 +#define MCLK_I2S0_TX_FRACDIV 59 +#define MCLK_I2S0_TX_MUX 60 +#define MCLK_I2S0_TX 61 +#define MCLK_I2S0_RX_DIV 62 +#define MCLK_I2S0_RX_FRACDIV 63 +#define MCLK_I2S0_RX_MUX 64 +#define MCLK_I2S0_RX 65 +#define MCLK_I2S0_TX_OUT2IO 66 +#define MCLK_I2S0_RX_OUT2IO 67 +#define MCLK_I2S1_DIV 68 +#define MCLK_I2S1_FRACDIV 69 +#define MCLK_I2S1_MUX 70 +#define MCLK_I2S1 71 +#define MCLK_I2S1_OUT2IO 72 +#define MCLK_I2S2_DIV 73 +#define MCLK_I2S2_FRACDIV 74 +#define MCLK_I2S2_MUX 75 +#define MCLK_I2S2 76 +#define MCLK_I2S2_OUT2IO 77 +#define MCLK_PDM 78 +#define SCLK_ADUPWM_DIV 79 +#define SCLK_AUDPWM_FRACDIV 80 +#define SCLK_AUDPWM_MUX 81 +#define SCLK_AUDPWM 82 +#define CLK_ACDCDIG_ADC 83 +#define CLK_ACDCDIG_DAC 84 +#define CLK_ACDCDIG_I2C 85 +#define CLK_VENC_CORE 86 +#define CLK_VDEC_CORE 87 +#define CLK_VDEC_CA 88 +#define CLK_VDEC_HEVC_CA 89 +#define CLK_RGA_CORE 90 +#define CLK_IEP_CORE 91 +#define CLK_ISP_DIV 92 +#define CLK_ISP_NP5 93 +#define CLK_ISP_NUX 94 +#define CLK_ISP 95 +#define CLK_CIF_OUT_DIV 96 +#define CLK_CIF_OUT_FRACDIV 97 +#define CLK_CIF_OUT_MUX 98 +#define CLK_CIF_OUT 99 +#define CLK_MIPICSI_OUT_DIV 100 +#define CLK_MIPICSI_OUT_FRACDIV 101 +#define CLK_MIPICSI_OUT_MUX 102 +#define CLK_MIPICSI_OUT 103 +#define CLK_ISPP_DIV 104 +#define CLK_ISPP_NP5 105 +#define CLK_ISPP_NUX 106 +#define CLK_ISPP 107 +#define CLK_SDMMC 108 +#define SCLK_SDMMC_DRV 109 +#define SCLK_SDMMC_SAMPLE 110 +#define CLK_SDIO 111 +#define SCLK_SDIO_DRV 112 +#define SCLK_SDIO_SAMPLE 113 +#define CLK_EMMC 114 +#define SCLK_EMMC_DRV 115 +#define SCLK_EMMC_SAMPLE 116 +#define CLK_NANDC 117 +#define SCLK_SFC 118 +#define CLK_USBHOST_UTMI_OHCI 119 +#define CLK_USBOTG_REF 120 +#define CLK_GMAC_DIV 121 +#define CLK_GMAC_RGMII_M0 122 +#define CLK_GMAC_SRC_M0 123 +#define CLK_GMAC_RGMII_M1 124 +#define CLK_GMAC_SRC_M1 125 +#define CLK_GMAC_SRC 126 +#define CLK_GMAC_REF 127 +#define CLK_GMAC_TX_SRC 128 +#define CLK_GMAC_TX_DIV5 129 +#define CLK_GMAC_TX_DIV50 130 +#define RGMII_MODE_CLK 131 +#define CLK_GMAC_RX_SRC 132 +#define CLK_GMAC_RX_DIV2 133 +#define CLK_GMAC_RX_DIV20 134 +#define RMII_MODE_CLK 135 +#define CLK_GMAC_TX_RX 136 +#define CLK_GMAC_PTPREF 137 +#define CLK_GMAC_ETHERNET_OUT 138 +#define CLK_DDRPHY 139 +#define CLK_DDR_MON 140 +#define TMCLK_DDR_MON 141 +#define CLK_NPU_DIV 142 +#define CLK_NPU_NP5 143 +#define CLK_CORE_NPU 144 +#define CLK_CORE_NPUPVTM 145 +#define CLK_NPUPVTM 146 +#define SCLK_DDRCLK 147 +#define CLK_OTP 148 + +/* dclk */ +#define DCLK_DECOM 150 +#define DCLK_VOP_DIV 151 +#define DCLK_VOP_FRACDIV 152 +#define DCLK_VOP_MUX 153 +#define DCLK_VOP 154 +#define DCLK_CIF 155 +#define DCLK_CIFLITE 156 + +/* aclk */ +#define ACLK_PDBUS 160 +#define ACLK_DMAC 161 +#define ACLK_DCF 162 +#define ACLK_SPINLOCK 163 +#define ACLK_DECOM 164 +#define ACLK_PDCRYPTO 165 +#define ACLK_CRYPTO 166 +#define ACLK_PDVEPU 167 +#define ACLK_VENC 168 +#define ACLK_PDVDEC 169 +#define ACLK_PDJPEG 170 +#define ACLK_VDEC 171 +#define ACLK_JPEG 172 +#define ACLK_PDVO 173 +#define ACLK_RGA 174 +#define ACLK_VOP 175 +#define ACLK_IEP 176 +#define ACLK_PDVI_DIV 177 +#define ACLK_PDVI_NP5 178 +#define ACLK_PDVI 179 +#define ACLK_ISP 180 +#define ACLK_CIF 181 +#define ACLK_CIFLITE 182 +#define ACLK_PDISPP_DIV 183 +#define ACLK_PDISPP_NP5 184 +#define ACLK_PDISPP 185 +#define ACLK_ISPP 186 +#define ACLK_PDPHP 187 +#define ACLK_PDUSB 188 +#define ACLK_USBOTG 189 +#define ACLK_PDGMAC 190 +#define ACLK_GMAC 191 +#define ACLK_PDNPU_DIV 192 +#define ACLK_PDNPU_NP5 193 +#define ACLK_PDNPU 194 +#define ACLK_NPU 195 + +/* hclk */ +#define HCLK_PDCORE_NIU 200 +#define HCLK_PDUSB 201 +#define HCLK_PDCRYPTO 202 +#define HCLK_CRYPTO 203 +#define HCLK_PDAUDIO 204 +#define HCLK_I2S0 205 +#define HCLK_I2S1 206 +#define HCLK_I2S2 207 +#define HCLK_PDM 208 +#define HCLK_AUDPWM 209 +#define HCLK_PDVEPU 210 +#define HCLK_VENC 211 +#define HCLK_PDVDEC 212 +#define HCLK_PDJPEG 213 +#define HCLK_VDEC 214 +#define HCLK_JPEG 215 +#define HCLK_PDVO 216 +#define HCLK_RGA 217 +#define HCLK_VOP 218 +#define HCLK_IEP 219 +#define HCLK_PDVI 220 +#define HCLK_ISP 221 +#define HCLK_CIF 222 +#define HCLK_CIFLITE 223 +#define HCLK_PDISPP 224 +#define HCLK_ISPP 225 +#define HCLK_PDPHP 226 +#define HCLK_PDSDMMC 227 +#define HCLK_SDMMC 228 +#define HCLK_PDSDIO 229 +#define HCLK_SDIO 230 +#define HCLK_PDNVM 231 +#define HCLK_EMMC 232 +#define HCLK_NANDC 233 +#define HCLK_SFC 234 +#define HCLK_SFCXIP 235 +#define HCLK_PDBUS 236 +#define HCLK_USBHOST 237 +#define HCLK_USBHOST_ARB 238 +#define HCLK_PDNPU 239 +#define HCLK_NPU 240 + +/* pclk */ +#define PCLK_CPUPVTM 245 +#define PCLK_PDBUS 246 +#define PCLK_DCF 247 +#define PCLK_WDT 248 +#define PCLK_MAILBOX 249 +#define PCLK_UART0 250 +#define PCLK_UART2 251 +#define PCLK_UART3 252 +#define PCLK_UART4 253 +#define PCLK_UART5 254 +#define PCLK_I2C1 255 +#define PCLK_I2C3 256 +#define PCLK_I2C4 257 +#define PCLK_I2C5 258 +#define PCLK_SPI1 259 +#define PCLK_PWM2 261 +#define PCLK_GPIO1 262 +#define PCLK_GPIO2 263 +#define PCLK_GPIO3 264 +#define PCLK_GPIO4 265 +#define PCLK_SARADC 266 +#define PCLK_TIMER 267 +#define PCLK_DECOM 268 +#define PCLK_CAN 269 +#define PCLK_NPU_TSADC 270 +#define PCLK_CPU_TSADC 271 +#define PCLK_ACDCDIG 272 +#define PCLK_PDVO 273 +#define PCLK_DSIHOST 274 +#define PCLK_PDVI 275 +#define PCLK_CSIHOST 276 +#define PCLK_PDGMAC 277 +#define PCLK_GMAC 278 +#define PCLK_PDDDR 279 +#define PCLK_DDR_MON 280 +#define PCLK_PDNPU 281 +#define PCLK_NPUPVTM 282 +#define PCLK_PDTOP 283 +#define PCLK_TOPCRU 284 +#define PCLK_TOPGRF 285 +#define PCLK_CPUEMADET 286 +#define PCLK_DDRPHY 287 +#define PCLK_DSIPHY 289 +#define PCLK_CSIPHY0 290 +#define PCLK_CSIPHY1 291 +#define PCLK_USBPHY_HOST 292 +#define PCLK_USBPHY_OTG 293 +#define PCLK_OTP 294 + +#define CLK_NR_CLKS (PCLK_OTP + 1) + +/* pmu soft-reset indices */ + +/* pmu_cru_softrst_con0 */ +#define SRST_PDPMU_NIU_P 0 +#define SRST_PMU_SGRF_P 1 +#define SRST_PMU_SGRF_REMAP_P 2 +#define SRST_I2C0_P 3 +#define SRST_I2C0 4 +#define SRST_I2C2_P 7 +#define SRST_I2C2 8 +#define SRST_UART1_P 9 +#define SRST_UART1 10 +#define SRST_PWM0_P 11 +#define SRST_PWM0 12 +#define SRST_PWM1_P 13 +#define SRST_PWM1 14 +#define SRST_DDR_FAIL_SAFE 15 + +/* pmu_cru_softrst_con1 */ +#define SRST_GPIO0_P 17 +#define SRST_GPIO0_DB 18 +#define SRST_SPI0_P 19 +#define SRST_SPI0 20 +#define SRST_PMUGRF_P 21 +#define SRST_CHIPVEROTP_P 22 +#define SRST_PMUPVTM 24 +#define SRST_PMUPVTM_P 25 +#define SRST_PMUCRU_P 30 + +/* soft-reset indices */ + +/* cru_softrst_con0 */ +#define SRST_CORE0_PO 0 +#define SRST_CORE1_PO 1 +#define SRST_CORE2_PO 2 +#define SRST_CORE3_PO 3 +#define SRST_CORE0 4 +#define SRST_CORE1 5 +#define SRST_CORE2 6 +#define SRST_CORE3 7 +#define SRST_CORE0_DBG 8 +#define SRST_CORE1_DBG 9 +#define SRST_CORE2_DBG 10 +#define SRST_CORE3_DBG 11 +#define SRST_NL2 12 +#define SRST_CORE_NIU_A 13 +#define SRST_DBG_DAPLITE_P 14 +#define SRST_DAPLITE_P 15 + +/* cru_softrst_con1 */ +#define SRST_PDBUS_NIU1_A 16 +#define SRST_PDBUS_NIU1_H 17 +#define SRST_PDBUS_NIU1_P 18 +#define SRST_PDBUS_NIU2_A 19 +#define SRST_PDBUS_NIU2_H 20 +#define SRST_PDBUS_NIU3_A 21 +#define SRST_PDBUS_NIU3_H 22 +#define SRST_PDBUS_HOLD_NIU1_A 23 +#define SRST_DBG_NIU_P 24 +#define SRST_PDCORE_NIIU_H 25 +#define SRST_MUC_NIU 26 +#define SRST_DCF_A 29 +#define SRST_DCF_P 30 +#define SRST_SYSTEM_SRAM_A 31 + +/* cru_softrst_con2 */ +#define SRST_I2C1_P 32 +#define SRST_I2C1 33 +#define SRST_I2C3_P 34 +#define SRST_I2C3 35 +#define SRST_I2C4_P 36 +#define SRST_I2C4 37 +#define SRST_I2C5_P 38 +#define SRST_I2C5 39 +#define SRST_SPI1_P 40 +#define SRST_SPI1 41 +#define SRST_MCU_CORE 42 +#define SRST_PWM2_P 44 +#define SRST_PWM2 45 +#define SRST_SPINLOCK_A 46 + +/* cru_softrst_con3 */ +#define SRST_UART0_P 48 +#define SRST_UART0 49 +#define SRST_UART2_P 50 +#define SRST_UART2 51 +#define SRST_UART3_P 52 +#define SRST_UART3 53 +#define SRST_UART4_P 54 +#define SRST_UART4 55 +#define SRST_UART5_P 56 +#define SRST_UART5 57 +#define SRST_WDT_P 58 +#define SRST_SARADC_P 59 +#define SRST_GRF_P 61 +#define SRST_TIMER_P 62 +#define SRST_MAILBOX_P 63 + +/* cru_softrst_con4 */ +#define SRST_TIMER0 64 +#define SRST_TIMER1 65 +#define SRST_TIMER2 66 +#define SRST_TIMER3 67 +#define SRST_TIMER4 68 +#define SRST_TIMER5 69 +#define SRST_INTMUX_P 70 +#define SRST_GPIO1_P 72 +#define SRST_GPIO1_DB 73 +#define SRST_GPIO2_P 74 +#define SRST_GPIO2_DB 75 +#define SRST_GPIO3_P 76 +#define SRST_GPIO3_DB 77 +#define SRST_GPIO4_P 78 +#define SRST_GPIO4_DB 79 + +/* cru_softrst_con5 */ +#define SRST_CAN_P 80 +#define SRST_CAN 81 +#define SRST_DECOM_A 85 +#define SRST_DECOM_P 86 +#define SRST_DECOM_D 87 +#define SRST_PDCRYPTO_NIU_A 88 +#define SRST_PDCRYPTO_NIU_H 89 +#define SRST_CRYPTO_A 90 +#define SRST_CRYPTO_H 91 +#define SRST_CRYPTO_CORE 92 +#define SRST_CRYPTO_PKA 93 +#define SRST_SGRF_P 95 + +/* cru_softrst_con6 */ +#define SRST_PDAUDIO_NIU_H 96 +#define SRST_PDAUDIO_NIU_P 97 +#define SRST_I2S0_H 98 +#define SRST_I2S0_TX_M 99 +#define SRST_I2S0_RX_M 100 +#define SRST_I2S1_H 101 +#define SRST_I2S1_M 102 +#define SRST_I2S2_H 103 +#define SRST_I2S2_M 104 +#define SRST_PDM_H 105 +#define SRST_PDM_M 106 +#define SRST_AUDPWM_H 107 +#define SRST_AUDPWM 108 +#define SRST_ACDCDIG_P 109 +#define SRST_ACDCDIG 110 + +/* cru_softrst_con7 */ +#define SRST_PDVEPU_NIU_A 112 +#define SRST_PDVEPU_NIU_H 113 +#define SRST_VENC_A 114 +#define SRST_VENC_H 115 +#define SRST_VENC_CORE 116 +#define SRST_PDVDEC_NIU_A 117 +#define SRST_PDVDEC_NIU_H 118 +#define SRST_VDEC_A 119 +#define SRST_VDEC_H 120 +#define SRST_VDEC_CORE 121 +#define SRST_VDEC_CA 122 +#define SRST_VDEC_HEVC_CA 123 +#define SRST_PDJPEG_NIU_A 124 +#define SRST_PDJPEG_NIU_H 125 +#define SRST_JPEG_A 126 +#define SRST_JPEG_H 127 + +/* cru_softrst_con8 */ +#define SRST_PDVO_NIU_A 128 +#define SRST_PDVO_NIU_H 129 +#define SRST_PDVO_NIU_P 130 +#define SRST_RGA_A 131 +#define SRST_RGA_H 132 +#define SRST_RGA_CORE 133 +#define SRST_VOP_A 134 +#define SRST_VOP_H 135 +#define SRST_VOP_D 136 +#define SRST_TXBYTEHS_DSIHOST 137 +#define SRST_DSIHOST_P 138 +#define SRST_IEP_A 139 +#define SRST_IEP_H 140 +#define SRST_IEP_CORE 141 +#define SRST_ISP_RX_P 142 + +/* cru_softrst_con9 */ +#define SRST_PDVI_NIU_A 144 +#define SRST_PDVI_NIU_H 145 +#define SRST_PDVI_NIU_P 146 +#define SRST_ISP 147 +#define SRST_CIF_A 148 +#define SRST_CIF_H 149 +#define SRST_CIF_D 150 +#define SRST_CIF_P 151 +#define SRST_CIF_I 152 +#define SRST_CIF_RX_P 153 +#define SRST_PDISPP_NIU_A 154 +#define SRST_PDISPP_NIU_H 155 +#define SRST_ISPP_A 156 +#define SRST_ISPP_H 157 +#define SRST_ISPP 158 +#define SRST_CSIHOST_P 159 + +/* cru_softrst_con10 */ +#define SRST_PDPHPMID_NIU_A 160 +#define SRST_PDPHPMID_NIU_H 161 +#define SRST_PDNVM_NIU_H 163 +#define SRST_SDMMC_H 164 +#define SRST_SDIO_H 165 +#define SRST_EMMC_H 166 +#define SRST_SFC_H 167 +#define SRST_SFCXIP_H 168 +#define SRST_SFC 169 +#define SRST_NANDC_H 170 +#define SRST_NANDC 171 +#define SRST_PDSDMMC_H 173 +#define SRST_PDSDIO_H 174 + +/* cru_softrst_con11 */ +#define SRST_PDUSB_NIU_A 176 +#define SRST_PDUSB_NIU_H 177 +#define SRST_USBHOST_H 178 +#define SRST_USBHOST_ARB_H 179 +#define SRST_USBHOST_UTMI 180 +#define SRST_USBOTG_A 181 +#define SRST_USBPHY_OTG_P 182 +#define SRST_USBPHY_HOST_P 183 +#define SRST_USBPHYPOR_OTG 184 +#define SRST_USBPHYPOR_HOST 185 +#define SRST_PDGMAC_NIU_A 188 +#define SRST_PDGMAC_NIU_P 189 +#define SRST_GMAC_A 190 + +/* cru_softrst_con12 */ +#define SRST_DDR_DFICTL_P 193 +#define SRST_DDR_MON_P 194 +#define SRST_DDR_STANDBY_P 195 +#define SRST_DDR_GRF_P 196 +#define SRST_DDR_MSCH_P 197 +#define SRST_DDR_SPLIT_A 198 +#define SRST_DDR_MSCH 199 +#define SRST_DDR_DFICTL 202 +#define SRST_DDR_STANDBY 203 +#define SRST_NPUMCU_NIU 205 +#define SRST_DDRPHY_P 206 +#define SRST_DDRPHY 207 + +/* cru_softrst_con13 */ +#define SRST_PDNPU_NIU_A 208 +#define SRST_PDNPU_NIU_H 209 +#define SRST_PDNPU_NIU_P 210 +#define SRST_NPU_A 211 +#define SRST_NPU_H 212 +#define SRST_NPU 213 +#define SRST_NPUPVTM_P 214 +#define SRST_NPUPVTM 215 +#define SRST_NPU_TSADC_P 216 +#define SRST_NPU_TSADC 217 +#define SRST_NPU_TSADCPHY 218 +#define SRST_CIFLITE_A 220 +#define SRST_CIFLITE_H 221 +#define SRST_CIFLITE_D 222 +#define SRST_CIFLITE_RX_P 223 + +/* cru_softrst_con14 */ +#define SRST_TOPNIU_P 224 +#define SRST_TOPCRU_P 225 +#define SRST_TOPGRF_P 226 +#define SRST_CPUEMADET_P 227 +#define SRST_CSIPHY0_P 228 +#define SRST_CSIPHY1_P 229 +#define SRST_DSIPHY_P 230 +#define SRST_CPU_TSADC_P 232 +#define SRST_CPU_TSADC 233 +#define SRST_CPU_TSADCPHY 234 +#define SRST_CPUPVTM_P 235 +#define SRST_CPUPVTM 236 + +#endif diff --git a/include/dt-bindings/clock/samsung,exynosautov9.h b/include/dt-bindings/clock/samsung,exynosautov9.h new file mode 100644 index 000000000000..42133af6d6b9 --- /dev/null +++ b/include/dt-bindings/clock/samsung,exynosautov9.h @@ -0,0 +1,367 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022 Samsung Electronics Co., Ltd. + * Author: Chanho Park <chanho61.park@samsung.com> + * + * Device Tree binding constants for Exynos Auto V9 clock controller. + */ + +#ifndef _DT_BINDINGS_CLOCK_EXYNOSAUTOV9_H +#define _DT_BINDINGS_CLOCK_EXYNOSAUTOV9_H + +/* CMU_TOP */ +#define FOUT_SHARED0_PLL 1 +#define FOUT_SHARED1_PLL 2 +#define FOUT_SHARED2_PLL 3 +#define FOUT_SHARED3_PLL 4 +#define FOUT_SHARED4_PLL 5 + +/* MUX in CMU_TOP */ +#define MOUT_SHARED0_PLL 6 +#define MOUT_SHARED1_PLL 7 +#define MOUT_SHARED2_PLL 8 +#define MOUT_SHARED3_PLL 9 +#define MOUT_SHARED4_PLL 10 +#define MOUT_CLKCMU_CMU_BOOST 11 +#define MOUT_CLKCMU_CMU_CMUREF 12 +#define MOUT_CLKCMU_ACC_BUS 13 +#define MOUT_CLKCMU_APM_BUS 14 +#define MOUT_CLKCMU_AUD_CPU 15 +#define MOUT_CLKCMU_AUD_BUS 16 +#define MOUT_CLKCMU_BUSC_BUS 17 +#define MOUT_CLKCMU_BUSMC_BUS 19 +#define MOUT_CLKCMU_CORE_BUS 20 +#define MOUT_CLKCMU_CPUCL0_SWITCH 21 +#define MOUT_CLKCMU_CPUCL0_CLUSTER 22 +#define MOUT_CLKCMU_CPUCL1_SWITCH 24 +#define MOUT_CLKCMU_CPUCL1_CLUSTER 25 +#define MOUT_CLKCMU_DPTX_BUS 26 +#define MOUT_CLKCMU_DPTX_DPGTC 27 +#define MOUT_CLKCMU_DPUM_BUS 28 +#define MOUT_CLKCMU_DPUS0_BUS 29 +#define MOUT_CLKCMU_DPUS1_BUS 30 +#define MOUT_CLKCMU_FSYS0_BUS 31 +#define MOUT_CLKCMU_FSYS0_PCIE 32 +#define MOUT_CLKCMU_FSYS1_BUS 33 +#define MOUT_CLKCMU_FSYS1_USBDRD 34 +#define MOUT_CLKCMU_FSYS1_MMC_CARD 35 +#define MOUT_CLKCMU_FSYS2_BUS 36 +#define MOUT_CLKCMU_FSYS2_UFS_EMBD 37 +#define MOUT_CLKCMU_FSYS2_ETHERNET 38 +#define MOUT_CLKCMU_G2D_G2D 39 +#define MOUT_CLKCMU_G2D_MSCL 40 +#define MOUT_CLKCMU_G3D00_SWITCH 41 +#define MOUT_CLKCMU_G3D01_SWITCH 42 +#define MOUT_CLKCMU_G3D1_SWITCH 43 +#define MOUT_CLKCMU_ISPB_BUS 44 +#define MOUT_CLKCMU_MFC_MFC 45 +#define MOUT_CLKCMU_MFC_WFD 46 +#define MOUT_CLKCMU_MIF_SWITCH 47 +#define MOUT_CLKCMU_MIF_BUSP 48 +#define MOUT_CLKCMU_NPU_BUS 49 +#define MOUT_CLKCMU_PERIC0_BUS 50 +#define MOUT_CLKCMU_PERIC0_IP 51 +#define MOUT_CLKCMU_PERIC1_BUS 52 +#define MOUT_CLKCMU_PERIC1_IP 53 +#define MOUT_CLKCMU_PERIS_BUS 54 + +/* DIV in CMU_TOP */ +#define DOUT_SHARED0_DIV3 101 +#define DOUT_SHARED0_DIV2 102 +#define DOUT_SHARED1_DIV3 103 +#define DOUT_SHARED1_DIV2 104 +#define DOUT_SHARED1_DIV4 105 +#define DOUT_SHARED2_DIV3 106 +#define DOUT_SHARED2_DIV2 107 +#define DOUT_SHARED2_DIV4 108 +#define DOUT_SHARED4_DIV2 109 +#define DOUT_SHARED4_DIV4 110 +#define DOUT_CLKCMU_CMU_BOOST 111 +#define DOUT_CLKCMU_ACC_BUS 112 +#define DOUT_CLKCMU_APM_BUS 113 +#define DOUT_CLKCMU_AUD_CPU 114 +#define DOUT_CLKCMU_AUD_BUS 115 +#define DOUT_CLKCMU_BUSC_BUS 116 +#define DOUT_CLKCMU_BUSMC_BUS 118 +#define DOUT_CLKCMU_CORE_BUS 119 +#define DOUT_CLKCMU_CPUCL0_SWITCH 120 +#define DOUT_CLKCMU_CPUCL0_CLUSTER 121 +#define DOUT_CLKCMU_CPUCL1_SWITCH 123 +#define DOUT_CLKCMU_CPUCL1_CLUSTER 124 +#define DOUT_CLKCMU_DPTX_BUS 125 +#define DOUT_CLKCMU_DPTX_DPGTC 126 +#define DOUT_CLKCMU_DPUM_BUS 127 +#define DOUT_CLKCMU_DPUS0_BUS 128 +#define DOUT_CLKCMU_DPUS1_BUS 129 +#define DOUT_CLKCMU_FSYS0_BUS 130 +#define DOUT_CLKCMU_FSYS0_PCIE 131 +#define DOUT_CLKCMU_FSYS1_BUS 132 +#define DOUT_CLKCMU_FSYS1_USBDRD 133 +#define DOUT_CLKCMU_FSYS2_BUS 134 +#define DOUT_CLKCMU_FSYS2_UFS_EMBD 135 +#define DOUT_CLKCMU_FSYS2_ETHERNET 136 +#define DOUT_CLKCMU_G2D_G2D 137 +#define DOUT_CLKCMU_G2D_MSCL 138 +#define DOUT_CLKCMU_G3D00_SWITCH 139 +#define DOUT_CLKCMU_G3D01_SWITCH 140 +#define DOUT_CLKCMU_G3D1_SWITCH 141 +#define DOUT_CLKCMU_ISPB_BUS 142 +#define DOUT_CLKCMU_MFC_MFC 143 +#define DOUT_CLKCMU_MFC_WFD 144 +#define DOUT_CLKCMU_MIF_SWITCH 145 +#define DOUT_CLKCMU_MIF_BUSP 146 +#define DOUT_CLKCMU_NPU_BUS 147 +#define DOUT_CLKCMU_PERIC0_BUS 148 +#define DOUT_CLKCMU_PERIC0_IP 149 +#define DOUT_CLKCMU_PERIC1_BUS 150 +#define DOUT_CLKCMU_PERIC1_IP 151 +#define DOUT_CLKCMU_PERIS_BUS 152 + +/* GAT in CMU_TOP */ +#define GOUT_CLKCMU_CMU_BOOST 201 +#define GOUT_CLKCMU_CPUCL0_BOOST 202 +#define GOUT_CLKCMU_CPUCL1_BOOST 203 +#define GOUT_CLKCMU_CORE_BOOST 204 +#define GOUT_CLKCMU_BUSC_BOOST 205 +#define GOUT_CLKCMU_BUSMC_BOOST 206 +#define GOUT_CLKCMU_MIF_BOOST 207 +#define GOUT_CLKCMU_ACC_BUS 208 +#define GOUT_CLKCMU_APM_BUS 209 +#define GOUT_CLKCMU_AUD_CPU 210 +#define GOUT_CLKCMU_AUD_BUS 211 +#define GOUT_CLKCMU_BUSC_BUS 212 +#define GOUT_CLKCMU_BUSMC_BUS 214 +#define GOUT_CLKCMU_CORE_BUS 215 +#define GOUT_CLKCMU_CPUCL0_SWITCH 216 +#define GOUT_CLKCMU_CPUCL0_CLUSTER 217 +#define GOUT_CLKCMU_CPUCL1_SWITCH 219 +#define GOUT_CLKCMU_CPUCL1_CLUSTER 220 +#define GOUT_CLKCMU_DPTX_BUS 221 +#define GOUT_CLKCMU_DPTX_DPGTC 222 +#define GOUT_CLKCMU_DPUM_BUS 223 +#define GOUT_CLKCMU_DPUS0_BUS 224 +#define GOUT_CLKCMU_DPUS1_BUS 225 +#define GOUT_CLKCMU_FSYS0_BUS 226 +#define GOUT_CLKCMU_FSYS0_PCIE 227 +#define GOUT_CLKCMU_FSYS1_BUS 228 +#define GOUT_CLKCMU_FSYS1_USBDRD 229 +#define GOUT_CLKCMU_FSYS1_MMC_CARD 230 +#define GOUT_CLKCMU_FSYS2_BUS 231 +#define GOUT_CLKCMU_FSYS2_UFS_EMBD 232 +#define GOUT_CLKCMU_FSYS2_ETHERNET 233 +#define GOUT_CLKCMU_G2D_G2D 234 +#define GOUT_CLKCMU_G2D_MSCL 235 +#define GOUT_CLKCMU_G3D00_SWITCH 236 +#define GOUT_CLKCMU_G3D01_SWITCH 237 +#define GOUT_CLKCMU_G3D1_SWITCH 238 +#define GOUT_CLKCMU_ISPB_BUS 239 +#define GOUT_CLKCMU_MFC_MFC 240 +#define GOUT_CLKCMU_MFC_WFD 241 +#define GOUT_CLKCMU_MIF_SWITCH 242 +#define GOUT_CLKCMU_MIF_BUSP 243 +#define GOUT_CLKCMU_NPU_BUS 244 +#define GOUT_CLKCMU_PERIC0_BUS 245 +#define GOUT_CLKCMU_PERIC0_IP 246 +#define GOUT_CLKCMU_PERIC1_BUS 247 +#define GOUT_CLKCMU_PERIC1_IP 248 +#define GOUT_CLKCMU_PERIS_BUS 249 + +#define TOP_NR_CLK 250 + +/* CMU_BUSMC */ +#define CLK_MOUT_BUSMC_BUS_USER 1 +#define CLK_DOUT_BUSMC_BUSP 2 +#define CLK_GOUT_BUSMC_PDMA0_PCLK 3 +#define CLK_GOUT_BUSMC_SPDMA_PCLK 4 + +#define BUSMC_NR_CLK 5 + +/* CMU_CORE */ +#define CLK_MOUT_CORE_BUS_USER 1 +#define CLK_DOUT_CORE_BUSP 2 +#define CLK_GOUT_CORE_CCI_CLK 3 +#define CLK_GOUT_CORE_CCI_PCLK 4 +#define CLK_GOUT_CORE_CMU_CORE_PCLK 5 + +#define CORE_NR_CLK 6 + +/* CMU_FSYS0 */ +#define CLK_MOUT_FSYS0_BUS_USER 1 +#define CLK_MOUT_FSYS0_PCIE_USER 2 +#define CLK_GOUT_FSYS0_BUS_PCLK 3 + +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_REFCLK 4 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_REFCLK 5 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_DBI_ACLK 6 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_MSTR_ACLK 7 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_SLV_ACLK 8 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_DBI_ACLK 9 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_MSTR_ACLK 10 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_SLV_ACLK 11 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_PIPE_CLK 12 +#define CLK_GOUT_FSYS0_PCIE_GEN3A_2L0_CLK 13 +#define CLK_GOUT_FSYS0_PCIE_GEN3B_2L0_CLK 14 + +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_REFCLK 15 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_REFCLK 16 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_DBI_ACLK 17 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_MSTR_ACLK 18 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_SLV_ACLK 19 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_DBI_ACLK 20 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_MSTR_ACLK 21 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_SLV_ACLK 22 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_PIPE_CLK 23 +#define CLK_GOUT_FSYS0_PCIE_GEN3A_2L1_CLK 24 +#define CLK_GOUT_FSYS0_PCIE_GEN3B_2L1_CLK 25 + +#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_REFCLK 26 +#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_REFCLK 27 +#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_DBI_ACLK 28 +#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_MSTR_ACLK 29 +#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_SLV_ACLK 30 +#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_DBI_ACLK 31 +#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_MSTR_ACLK 32 +#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_SLV_ACLK 33 +#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_PIPE_CLK 34 +#define CLK_GOUT_FSYS0_PCIE_GEN3A_4L_CLK 35 +#define CLK_GOUT_FSYS0_PCIE_GEN3B_4L_CLK 36 + +#define FSYS0_NR_CLK 37 + +/* CMU_FSYS1 */ +#define FOUT_MMC_PLL 1 + +#define CLK_MOUT_FSYS1_BUS_USER 2 +#define CLK_MOUT_FSYS1_MMC_PLL 3 +#define CLK_MOUT_FSYS1_MMC_CARD_USER 4 +#define CLK_MOUT_FSYS1_USBDRD_USER 5 +#define CLK_MOUT_FSYS1_MMC_CARD 6 + +#define CLK_DOUT_FSYS1_MMC_CARD 7 + +#define CLK_GOUT_FSYS1_PCLK 8 +#define CLK_GOUT_FSYS1_MMC_CARD_SDCLKIN 9 +#define CLK_GOUT_FSYS1_MMC_CARD_ACLK 10 +#define CLK_GOUT_FSYS1_USB20DRD_0_REFCLK 11 +#define CLK_GOUT_FSYS1_USB20DRD_1_REFCLK 12 +#define CLK_GOUT_FSYS1_USB30DRD_0_REFCLK 13 +#define CLK_GOUT_FSYS1_USB30DRD_1_REFCLK 14 +#define CLK_GOUT_FSYS1_USB20_0_ACLK 15 +#define CLK_GOUT_FSYS1_USB20_1_ACLK 16 +#define CLK_GOUT_FSYS1_USB30_0_ACLK 17 +#define CLK_GOUT_FSYS1_USB30_1_ACLK 18 + +#define FSYS1_NR_CLK 19 + +/* CMU_FSYS2 */ +#define CLK_MOUT_FSYS2_BUS_USER 1 +#define CLK_MOUT_FSYS2_UFS_EMBD_USER 2 +#define CLK_MOUT_FSYS2_ETHERNET_USER 3 +#define CLK_GOUT_FSYS2_UFS_EMBD0_ACLK 4 +#define CLK_GOUT_FSYS2_UFS_EMBD0_UNIPRO 5 +#define CLK_GOUT_FSYS2_UFS_EMBD1_ACLK 6 +#define CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO 7 + +#define FSYS2_NR_CLK 8 + +/* CMU_PERIC0 */ +#define CLK_MOUT_PERIC0_BUS_USER 1 +#define CLK_MOUT_PERIC0_IP_USER 2 +#define CLK_MOUT_PERIC0_USI00_USI 3 +#define CLK_MOUT_PERIC0_USI01_USI 4 +#define CLK_MOUT_PERIC0_USI02_USI 5 +#define CLK_MOUT_PERIC0_USI03_USI 6 +#define CLK_MOUT_PERIC0_USI04_USI 7 +#define CLK_MOUT_PERIC0_USI05_USI 8 +#define CLK_MOUT_PERIC0_USI_I2C 9 + +#define CLK_DOUT_PERIC0_USI00_USI 10 +#define CLK_DOUT_PERIC0_USI01_USI 11 +#define CLK_DOUT_PERIC0_USI02_USI 12 +#define CLK_DOUT_PERIC0_USI03_USI 13 +#define CLK_DOUT_PERIC0_USI04_USI 14 +#define CLK_DOUT_PERIC0_USI05_USI 15 +#define CLK_DOUT_PERIC0_USI_I2C 16 + +#define CLK_GOUT_PERIC0_IPCLK_0 20 +#define CLK_GOUT_PERIC0_IPCLK_1 21 +#define CLK_GOUT_PERIC0_IPCLK_2 22 +#define CLK_GOUT_PERIC0_IPCLK_3 23 +#define CLK_GOUT_PERIC0_IPCLK_4 24 +#define CLK_GOUT_PERIC0_IPCLK_5 25 +#define CLK_GOUT_PERIC0_IPCLK_6 26 +#define CLK_GOUT_PERIC0_IPCLK_7 27 +#define CLK_GOUT_PERIC0_IPCLK_8 28 +#define CLK_GOUT_PERIC0_IPCLK_9 29 +#define CLK_GOUT_PERIC0_IPCLK_10 30 +#define CLK_GOUT_PERIC0_IPCLK_11 31 +#define CLK_GOUT_PERIC0_PCLK_0 32 +#define CLK_GOUT_PERIC0_PCLK_1 33 +#define CLK_GOUT_PERIC0_PCLK_2 34 +#define CLK_GOUT_PERIC0_PCLK_3 35 +#define CLK_GOUT_PERIC0_PCLK_4 36 +#define CLK_GOUT_PERIC0_PCLK_5 37 +#define CLK_GOUT_PERIC0_PCLK_6 38 +#define CLK_GOUT_PERIC0_PCLK_7 39 +#define CLK_GOUT_PERIC0_PCLK_8 40 +#define CLK_GOUT_PERIC0_PCLK_9 41 +#define CLK_GOUT_PERIC0_PCLK_10 42 +#define CLK_GOUT_PERIC0_PCLK_11 43 + +#define PERIC0_NR_CLK 44 + +/* CMU_PERIC1 */ +#define CLK_MOUT_PERIC1_BUS_USER 1 +#define CLK_MOUT_PERIC1_IP_USER 2 +#define CLK_MOUT_PERIC1_USI06_USI 3 +#define CLK_MOUT_PERIC1_USI07_USI 4 +#define CLK_MOUT_PERIC1_USI08_USI 5 +#define CLK_MOUT_PERIC1_USI09_USI 6 +#define CLK_MOUT_PERIC1_USI10_USI 7 +#define CLK_MOUT_PERIC1_USI11_USI 8 +#define CLK_MOUT_PERIC1_USI_I2C 9 + +#define CLK_DOUT_PERIC1_USI06_USI 10 +#define CLK_DOUT_PERIC1_USI07_USI 11 +#define CLK_DOUT_PERIC1_USI08_USI 12 +#define CLK_DOUT_PERIC1_USI09_USI 13 +#define CLK_DOUT_PERIC1_USI10_USI 14 +#define CLK_DOUT_PERIC1_USI11_USI 15 +#define CLK_DOUT_PERIC1_USI_I2C 16 + +#define CLK_GOUT_PERIC1_IPCLK_0 20 +#define CLK_GOUT_PERIC1_IPCLK_1 21 +#define CLK_GOUT_PERIC1_IPCLK_2 22 +#define CLK_GOUT_PERIC1_IPCLK_3 23 +#define CLK_GOUT_PERIC1_IPCLK_4 24 +#define CLK_GOUT_PERIC1_IPCLK_5 25 +#define CLK_GOUT_PERIC1_IPCLK_6 26 +#define CLK_GOUT_PERIC1_IPCLK_7 27 +#define CLK_GOUT_PERIC1_IPCLK_8 28 +#define CLK_GOUT_PERIC1_IPCLK_9 29 +#define CLK_GOUT_PERIC1_IPCLK_10 30 +#define CLK_GOUT_PERIC1_IPCLK_11 31 +#define CLK_GOUT_PERIC1_PCLK_0 32 +#define CLK_GOUT_PERIC1_PCLK_1 33 +#define CLK_GOUT_PERIC1_PCLK_2 34 +#define CLK_GOUT_PERIC1_PCLK_3 35 +#define CLK_GOUT_PERIC1_PCLK_4 36 +#define CLK_GOUT_PERIC1_PCLK_5 37 +#define CLK_GOUT_PERIC1_PCLK_6 38 +#define CLK_GOUT_PERIC1_PCLK_7 39 +#define CLK_GOUT_PERIC1_PCLK_8 40 +#define CLK_GOUT_PERIC1_PCLK_9 41 +#define CLK_GOUT_PERIC1_PCLK_10 42 +#define CLK_GOUT_PERIC1_PCLK_11 43 + +#define PERIC1_NR_CLK 44 + +/* CMU_PERIS */ +#define CLK_MOUT_PERIS_BUS_USER 1 +#define CLK_GOUT_SYSREG_PERIS_PCLK 2 +#define CLK_GOUT_WDT_CLUSTER0 3 +#define CLK_GOUT_WDT_CLUSTER1 4 + +#define PERIS_NR_CLK 5 + +#endif /* _DT_BINDINGS_CLOCK_EXYNOSAUTOV9_H */ diff --git a/include/dt-bindings/clock/sifive-fu540-prci.h b/include/dt-bindings/clock/sifive-fu540-prci.h index 3b21d0522c91..5af372e8385f 100644 --- a/include/dt-bindings/clock/sifive-fu540-prci.h +++ b/include/dt-bindings/clock/sifive-fu540-prci.h @@ -10,9 +10,9 @@ /* Clock indexes for use by Device Tree data and the PRCI driver */ -#define PRCI_CLK_COREPLL 0 -#define PRCI_CLK_DDRPLL 1 -#define PRCI_CLK_GEMGXLPLL 2 -#define PRCI_CLK_TLCLK 3 +#define FU540_PRCI_CLK_COREPLL 0 +#define FU540_PRCI_CLK_DDRPLL 1 +#define FU540_PRCI_CLK_GEMGXLPLL 2 +#define FU540_PRCI_CLK_TLCLK 3 #endif diff --git a/include/dt-bindings/clock/sifive-fu740-prci.h b/include/dt-bindings/clock/sifive-fu740-prci.h new file mode 100644 index 000000000000..672bdadbf6c0 --- /dev/null +++ b/include/dt-bindings/clock/sifive-fu740-prci.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (C) 2019 SiFive, Inc. + * Wesley Terpstra + * Paul Walmsley + * Zong Li + */ + +#ifndef __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H +#define __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H + +/* Clock indexes for use by Device Tree data and the PRCI driver */ + +#define FU740_PRCI_CLK_COREPLL 0 +#define FU740_PRCI_CLK_DDRPLL 1 +#define FU740_PRCI_CLK_GEMGXLPLL 2 +#define FU740_PRCI_CLK_DVFSCOREPLL 3 +#define FU740_PRCI_CLK_HFPCLKPLL 4 +#define FU740_PRCI_CLK_CLTXPLL 5 +#define FU740_PRCI_CLK_TLCLK 6 +#define FU740_PRCI_CLK_PCLK 7 +#define FU740_PRCI_CLK_PCIE_AUX 8 + +#endif /* __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H */ diff --git a/include/dt-bindings/clock/sprd,sc9863a-clk.h b/include/dt-bindings/clock/sprd,sc9863a-clk.h new file mode 100644 index 000000000000..4e030421641f --- /dev/null +++ b/include/dt-bindings/clock/sprd,sc9863a-clk.h @@ -0,0 +1,339 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Unisoc SC9863A platform clocks + * + * Copyright (C) 2019, Unisoc Communications Inc. + */ + +#ifndef _DT_BINDINGS_CLK_SC9863A_H_ +#define _DT_BINDINGS_CLK_SC9863A_H_ + +#define CLK_MPLL0_GATE 0 +#define CLK_DPLL0_GATE 1 +#define CLK_LPLL_GATE 2 +#define CLK_GPLL_GATE 3 +#define CLK_DPLL1_GATE 4 +#define CLK_MPLL1_GATE 5 +#define CLK_MPLL2_GATE 6 +#define CLK_ISPPLL_GATE 7 +#define CLK_PMU_APB_NUM (CLK_ISPPLL_GATE + 1) + +#define CLK_AUDIO_GATE 0 +#define CLK_RPLL 1 +#define CLK_RPLL_390M 2 +#define CLK_RPLL_260M 3 +#define CLK_RPLL_195M 4 +#define CLK_RPLL_26M 5 +#define CLK_ANLG_PHY_G5_NUM (CLK_RPLL_26M + 1) + +#define CLK_TWPLL 0 +#define CLK_TWPLL_768M 1 +#define CLK_TWPLL_384M 2 +#define CLK_TWPLL_192M 3 +#define CLK_TWPLL_96M 4 +#define CLK_TWPLL_48M 5 +#define CLK_TWPLL_24M 6 +#define CLK_TWPLL_12M 7 +#define CLK_TWPLL_512M 8 +#define CLK_TWPLL_256M 9 +#define CLK_TWPLL_128M 10 +#define CLK_TWPLL_64M 11 +#define CLK_TWPLL_307M2 12 +#define CLK_TWPLL_219M4 13 +#define CLK_TWPLL_170M6 14 +#define CLK_TWPLL_153M6 15 +#define CLK_TWPLL_76M8 16 +#define CLK_TWPLL_51M2 17 +#define CLK_TWPLL_38M4 18 +#define CLK_TWPLL_19M2 19 +#define CLK_LPLL 20 +#define CLK_LPLL_409M6 21 +#define CLK_LPLL_245M76 22 +#define CLK_GPLL 23 +#define CLK_ISPPLL 24 +#define CLK_ISPPLL_468M 25 +#define CLK_ANLG_PHY_G1_NUM (CLK_ISPPLL_468M + 1) + +#define CLK_DPLL0 0 +#define CLK_DPLL1 1 +#define CLK_DPLL0_933M 2 +#define CLK_DPLL0_622M3 3 +#define CLK_DPLL0_400M 4 +#define CLK_DPLL0_266M7 5 +#define CLK_DPLL0_123M1 6 +#define CLK_DPLL0_50M 7 +#define CLK_ANLG_PHY_G7_NUM (CLK_DPLL0_50M + 1) + +#define CLK_MPLL0 0 +#define CLK_MPLL1 1 +#define CLK_MPLL2 2 +#define CLK_MPLL2_675M 3 +#define CLK_ANLG_PHY_G4_NUM (CLK_MPLL2_675M + 1) + +#define CLK_AP_APB 0 +#define CLK_AP_CE 1 +#define CLK_NANDC_ECC 2 +#define CLK_NANDC_26M 3 +#define CLK_EMMC_32K 4 +#define CLK_SDIO0_32K 5 +#define CLK_SDIO1_32K 6 +#define CLK_SDIO2_32K 7 +#define CLK_OTG_UTMI 8 +#define CLK_AP_UART0 9 +#define CLK_AP_UART1 10 +#define CLK_AP_UART2 11 +#define CLK_AP_UART3 12 +#define CLK_AP_UART4 13 +#define CLK_AP_I2C0 14 +#define CLK_AP_I2C1 15 +#define CLK_AP_I2C2 16 +#define CLK_AP_I2C3 17 +#define CLK_AP_I2C4 18 +#define CLK_AP_I2C5 19 +#define CLK_AP_I2C6 20 +#define CLK_AP_SPI0 21 +#define CLK_AP_SPI1 22 +#define CLK_AP_SPI2 23 +#define CLK_AP_SPI3 24 +#define CLK_AP_IIS0 25 +#define CLK_AP_IIS1 26 +#define CLK_AP_IIS2 27 +#define CLK_SIM0 28 +#define CLK_SIM0_32K 29 +#define CLK_AP_CLK_NUM (CLK_SIM0_32K + 1) + +#define CLK_13M 0 +#define CLK_6M5 1 +#define CLK_4M3 2 +#define CLK_2M 3 +#define CLK_250K 4 +#define CLK_RCO_25M 5 +#define CLK_RCO_4M 6 +#define CLK_RCO_2M 7 +#define CLK_EMC 8 +#define CLK_AON_APB 9 +#define CLK_ADI 10 +#define CLK_AUX0 11 +#define CLK_AUX1 12 +#define CLK_AUX2 13 +#define CLK_PROBE 14 +#define CLK_PWM0 15 +#define CLK_PWM1 16 +#define CLK_PWM2 17 +#define CLK_AON_THM 18 +#define CLK_AUDIF 19 +#define CLK_CPU_DAP 20 +#define CLK_CPU_TS 21 +#define CLK_DJTAG_TCK 22 +#define CLK_EMC_REF 23 +#define CLK_CSSYS 24 +#define CLK_AON_PMU 25 +#define CLK_PMU_26M 26 +#define CLK_AON_TMR 27 +#define CLK_POWER_CPU 28 +#define CLK_AP_AXI 29 +#define CLK_SDIO0_2X 30 +#define CLK_SDIO1_2X 31 +#define CLK_SDIO2_2X 32 +#define CLK_EMMC_2X 33 +#define CLK_DPU 34 +#define CLK_DPU_DPI 35 +#define CLK_OTG_REF 36 +#define CLK_SDPHY_APB 37 +#define CLK_ALG_IO_APB 38 +#define CLK_GPU_CORE 39 +#define CLK_GPU_SOC 40 +#define CLK_MM_EMC 41 +#define CLK_MM_AHB 42 +#define CLK_BPC 43 +#define CLK_DCAM_IF 44 +#define CLK_ISP 45 +#define CLK_JPG 46 +#define CLK_CPP 47 +#define CLK_SENSOR0 48 +#define CLK_SENSOR1 49 +#define CLK_SENSOR2 50 +#define CLK_MM_VEMC 51 +#define CLK_MM_VAHB 52 +#define CLK_VSP 53 +#define CLK_CORE0 54 +#define CLK_CORE1 55 +#define CLK_CORE2 56 +#define CLK_CORE3 57 +#define CLK_CORE4 58 +#define CLK_CORE5 59 +#define CLK_CORE6 60 +#define CLK_CORE7 61 +#define CLK_SCU 62 +#define CLK_ACE 63 +#define CLK_AXI_PERIPH 64 +#define CLK_AXI_ACP 65 +#define CLK_ATB 66 +#define CLK_DEBUG_APB 67 +#define CLK_GIC 68 +#define CLK_PERIPH 69 +#define CLK_AON_CLK_NUM (CLK_VSP + 1) + +#define CLK_OTG_EB 0 +#define CLK_DMA_EB 1 +#define CLK_CE_EB 2 +#define CLK_NANDC_EB 3 +#define CLK_SDIO0_EB 4 +#define CLK_SDIO1_EB 5 +#define CLK_SDIO2_EB 6 +#define CLK_EMMC_EB 7 +#define CLK_EMMC_32K_EB 8 +#define CLK_SDIO0_32K_EB 9 +#define CLK_SDIO1_32K_EB 10 +#define CLK_SDIO2_32K_EB 11 +#define CLK_NANDC_26M_EB 12 +#define CLK_DMA_EB2 13 +#define CLK_CE_EB2 14 +#define CLK_AP_AHB_GATE_NUM (CLK_CE_EB2 + 1) + +#define CLK_GPIO_EB 0 +#define CLK_PWM0_EB 1 +#define CLK_PWM1_EB 2 +#define CLK_PWM2_EB 3 +#define CLK_PWM3_EB 4 +#define CLK_KPD_EB 5 +#define CLK_AON_SYST_EB 6 +#define CLK_AP_SYST_EB 7 +#define CLK_AON_TMR_EB 8 +#define CLK_EFUSE_EB 9 +#define CLK_EIC_EB 10 +#define CLK_INTC_EB 11 +#define CLK_ADI_EB 12 +#define CLK_AUDIF_EB 13 +#define CLK_AUD_EB 14 +#define CLK_VBC_EB 15 +#define CLK_PIN_EB 16 +#define CLK_AP_WDG_EB 17 +#define CLK_MM_EB 18 +#define CLK_AON_APB_CKG_EB 19 +#define CLK_CA53_TS0_EB 20 +#define CLK_CA53_TS1_EB 21 +#define CLK_CS53_DAP_EB 22 +#define CLK_PMU_EB 23 +#define CLK_THM_EB 24 +#define CLK_AUX0_EB 25 +#define CLK_AUX1_EB 26 +#define CLK_AUX2_EB 27 +#define CLK_PROBE_EB 28 +#define CLK_EMC_REF_EB 29 +#define CLK_CA53_WDG_EB 30 +#define CLK_AP_TMR1_EB 31 +#define CLK_AP_TMR2_EB 32 +#define CLK_DISP_EMC_EB 33 +#define CLK_ZIP_EMC_EB 34 +#define CLK_GSP_EMC_EB 35 +#define CLK_MM_VSP_EB 36 +#define CLK_MDAR_EB 37 +#define CLK_RTC4M0_CAL_EB 38 +#define CLK_RTC4M1_CAL_EB 39 +#define CLK_DJTAG_EB 40 +#define CLK_MBOX_EB 41 +#define CLK_AON_DMA_EB 42 +#define CLK_AON_APB_DEF_EB 43 +#define CLK_CA5_TS0_EB 44 +#define CLK_DBG_EB 45 +#define CLK_DBG_EMC_EB 46 +#define CLK_CROSS_TRIG_EB 47 +#define CLK_SERDES_DPHY_EB 48 +#define CLK_ARCH_RTC_EB 49 +#define CLK_KPD_RTC_EB 50 +#define CLK_AON_SYST_RTC_EB 51 +#define CLK_AP_SYST_RTC_EB 52 +#define CLK_AON_TMR_RTC_EB 53 +#define CLK_AP_TMR0_RTC_EB 54 +#define CLK_EIC_RTC_EB 55 +#define CLK_EIC_RTCDV5_EB 56 +#define CLK_AP_WDG_RTC_EB 57 +#define CLK_CA53_WDG_RTC_EB 58 +#define CLK_THM_RTC_EB 59 +#define CLK_ATHMA_RTC_EB 60 +#define CLK_GTHMA_RTC_EB 61 +#define CLK_ATHMA_RTC_A_EB 62 +#define CLK_GTHMA_RTC_A_EB 63 +#define CLK_AP_TMR1_RTC_EB 64 +#define CLK_AP_TMR2_RTC_EB 65 +#define CLK_DXCO_LC_RTC_EB 66 +#define CLK_BB_CAL_RTC_EB 67 +#define CLK_GNU_EB 68 +#define CLK_DISP_EB 69 +#define CLK_MM_EMC_EB 70 +#define CLK_POWER_CPU_EB 71 +#define CLK_HW_I2C_EB 72 +#define CLK_MM_VSP_EMC_EB 73 +#define CLK_VSP_EB 74 +#define CLK_CSSYS_EB 75 +#define CLK_DMC_EB 76 +#define CLK_ROSC_EB 77 +#define CLK_S_D_CFG_EB 78 +#define CLK_S_D_REF_EB 79 +#define CLK_B_DMA_EB 80 +#define CLK_ANLG_EB 81 +#define CLK_ANLG_APB_EB 82 +#define CLK_BSMTMR_EB 83 +#define CLK_AP_AXI_EB 84 +#define CLK_AP_INTC0_EB 85 +#define CLK_AP_INTC1_EB 86 +#define CLK_AP_INTC2_EB 87 +#define CLK_AP_INTC3_EB 88 +#define CLK_AP_INTC4_EB 89 +#define CLK_AP_INTC5_EB 90 +#define CLK_SCC_EB 91 +#define CLK_DPHY_CFG_EB 92 +#define CLK_DPHY_REF_EB 93 +#define CLK_CPHY_CFG_EB 94 +#define CLK_OTG_REF_EB 95 +#define CLK_SERDES_EB 96 +#define CLK_AON_AP_EMC_EB 97 +#define CLK_AON_APB_GATE_NUM (CLK_AON_AP_EMC_EB + 1) + +#define CLK_MAHB_CKG_EB 0 +#define CLK_MDCAM_EB 1 +#define CLK_MISP_EB 2 +#define CLK_MAHBCSI_EB 3 +#define CLK_MCSI_S_EB 4 +#define CLK_MCSI_T_EB 5 +#define CLK_DCAM_AXI_EB 6 +#define CLK_ISP_AXI_EB 7 +#define CLK_MCSI_EB 8 +#define CLK_MCSI_S_CKG_EB 9 +#define CLK_MCSI_T_CKG_EB 10 +#define CLK_SENSOR0_EB 11 +#define CLK_SENSOR1_EB 12 +#define CLK_SENSOR2_EB 13 +#define CLK_MCPHY_CFG_EB 14 +#define CLK_MM_GATE_NUM (CLK_MCPHY_CFG_EB + 1) + +#define CLK_MIPI_CSI 0 +#define CLK_MIPI_CSI_S 1 +#define CLK_MIPI_CSI_M 2 +#define CLK_MM_CLK_NUM (CLK_MIPI_CSI_M + 1) + +#define CLK_SIM0_EB 0 +#define CLK_IIS0_EB 1 +#define CLK_IIS1_EB 2 +#define CLK_IIS2_EB 3 +#define CLK_SPI0_EB 4 +#define CLK_SPI1_EB 5 +#define CLK_SPI2_EB 6 +#define CLK_I2C0_EB 7 +#define CLK_I2C1_EB 8 +#define CLK_I2C2_EB 9 +#define CLK_I2C3_EB 10 +#define CLK_I2C4_EB 11 +#define CLK_UART0_EB 12 +#define CLK_UART1_EB 13 +#define CLK_UART2_EB 14 +#define CLK_UART3_EB 15 +#define CLK_UART4_EB 16 +#define CLK_SIM0_32K_EB 17 +#define CLK_SPI3_EB 18 +#define CLK_I2C5_EB 19 +#define CLK_I2C6_EB 20 +#define CLK_AP_APB_GATE_NUM (CLK_I2C6_EB + 1) + +#endif /* _DT_BINDINGS_CLK_SC9863A_H_ */ diff --git a/include/dt-bindings/clock/sprd,ums512-clk.h b/include/dt-bindings/clock/sprd,ums512-clk.h new file mode 100644 index 000000000000..4f1d90849944 --- /dev/null +++ b/include/dt-bindings/clock/sprd,ums512-clk.h @@ -0,0 +1,397 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Unisoc UMS512 SoC DTS file + * + * Copyright (C) 2022, Unisoc Inc. + */ + +#ifndef _DT_BINDINGS_CLK_UMS512_H_ +#define _DT_BINDINGS_CLK_UMS512_H_ + +#define CLK_26M_AUD 0 +#define CLK_13M 1 +#define CLK_6M5 2 +#define CLK_4M3 3 +#define CLK_2M 4 +#define CLK_1M 5 +#define CLK_250K 6 +#define CLK_RCO_25M 7 +#define CLK_RCO_4M 8 +#define CLK_RCO_2M 9 +#define CLK_ISPPLL_GATE 10 +#define CLK_DPLL0_GATE 11 +#define CLK_DPLL1_GATE 12 +#define CLK_LPLL_GATE 13 +#define CLK_TWPLL_GATE 14 +#define CLK_GPLL_GATE 15 +#define CLK_RPLL_GATE 16 +#define CLK_CPPLL_GATE 17 +#define CLK_MPLL0_GATE 18 +#define CLK_MPLL1_GATE 19 +#define CLK_MPLL2_GATE 20 +#define CLK_PMU_GATE_NUM (CLK_MPLL2_GATE + 1) + +#define CLK_DPLL0 0 +#define CLK_DPLL0_58M31 1 +#define CLK_ANLG_PHY_G0_NUM (CLK_DPLL0_58M31 + 1) + +#define CLK_MPLL1 0 +#define CLK_MPLL1_63M38 1 +#define CLK_ANLG_PHY_G2_NUM (CLK_MPLL1_63M38 + 1) + +#define CLK_RPLL 0 +#define CLK_AUDIO_GATE 1 +#define CLK_MPLL0 2 +#define CLK_MPLL0_56M88 3 +#define CLK_MPLL2 4 +#define CLK_MPLL2_47M13 5 +#define CLK_ANLG_PHY_G3_NUM (CLK_MPLL2_47M13 + 1) + +#define CLK_TWPLL 0 +#define CLK_TWPLL_768M 1 +#define CLK_TWPLL_384M 2 +#define CLK_TWPLL_192M 3 +#define CLK_TWPLL_96M 4 +#define CLK_TWPLL_48M 5 +#define CLK_TWPLL_24M 6 +#define CLK_TWPLL_12M 7 +#define CLK_TWPLL_512M 8 +#define CLK_TWPLL_256M 9 +#define CLK_TWPLL_128M 10 +#define CLK_TWPLL_64M 11 +#define CLK_TWPLL_307M2 12 +#define CLK_TWPLL_219M4 13 +#define CLK_TWPLL_170M6 14 +#define CLK_TWPLL_153M6 15 +#define CLK_TWPLL_76M8 16 +#define CLK_TWPLL_51M2 17 +#define CLK_TWPLL_38M4 18 +#define CLK_TWPLL_19M2 19 +#define CLK_TWPLL_12M29 20 +#define CLK_LPLL 21 +#define CLK_LPLL_614M4 22 +#define CLK_LPLL_409M6 23 +#define CLK_LPLL_245M76 24 +#define CLK_LPLL_30M72 25 +#define CLK_ISPPLL 26 +#define CLK_ISPPLL_468M 27 +#define CLK_ISPPLL_78M 28 +#define CLK_GPLL 29 +#define CLK_GPLL_40M 30 +#define CLK_CPPLL 31 +#define CLK_CPPLL_39M32 32 +#define CLK_ANLG_PHY_GC_NUM (CLK_CPPLL_39M32 + 1) + +#define CLK_AP_APB 0 +#define CLK_IPI 1 +#define CLK_AP_UART0 2 +#define CLK_AP_UART1 3 +#define CLK_AP_UART2 4 +#define CLK_AP_I2C0 5 +#define CLK_AP_I2C1 6 +#define CLK_AP_I2C2 7 +#define CLK_AP_I2C3 8 +#define CLK_AP_I2C4 9 +#define CLK_AP_SPI0 10 +#define CLK_AP_SPI1 11 +#define CLK_AP_SPI2 12 +#define CLK_AP_SPI3 13 +#define CLK_AP_IIS0 14 +#define CLK_AP_IIS1 15 +#define CLK_AP_IIS2 16 +#define CLK_AP_SIM 17 +#define CLK_AP_CE 18 +#define CLK_SDIO0_2X 19 +#define CLK_SDIO1_2X 20 +#define CLK_EMMC_2X 21 +#define CLK_VSP 22 +#define CLK_DISPC0 23 +#define CLK_DISPC0_DPI 24 +#define CLK_DSI_APB 25 +#define CLK_DSI_RXESC 26 +#define CLK_DSI_LANEBYTE 27 +#define CLK_VDSP 28 +#define CLK_VDSP_M 29 +#define CLK_AP_CLK_NUM (CLK_VDSP_M + 1) + +#define CLK_DSI_EB 0 +#define CLK_DISPC_EB 1 +#define CLK_VSP_EB 2 +#define CLK_VDMA_EB 3 +#define CLK_DMA_PUB_EB 4 +#define CLK_DMA_SEC_EB 5 +#define CLK_IPI_EB 6 +#define CLK_AHB_CKG_EB 7 +#define CLK_BM_CLK_EB 8 +#define CLK_AP_AHB_GATE_NUM (CLK_BM_CLK_EB + 1) + +#define CLK_AON_APB 0 +#define CLK_ADI 1 +#define CLK_AUX0 2 +#define CLK_AUX1 3 +#define CLK_AUX2 4 +#define CLK_PROBE 5 +#define CLK_PWM0 6 +#define CLK_PWM1 7 +#define CLK_PWM2 8 +#define CLK_PWM3 9 +#define CLK_EFUSE 10 +#define CLK_UART0 11 +#define CLK_UART1 12 +#define CLK_THM0 13 +#define CLK_THM1 14 +#define CLK_THM2 15 +#define CLK_THM3 16 +#define CLK_AON_I2C 17 +#define CLK_AON_IIS 18 +#define CLK_SCC 19 +#define CLK_APCPU_DAP 20 +#define CLK_APCPU_DAP_MTCK 21 +#define CLK_APCPU_TS 22 +#define CLK_DEBUG_TS 23 +#define CLK_DSI_TEST_S 24 +#define CLK_DJTAG_TCK 25 +#define CLK_DJTAG_TCK_HW 26 +#define CLK_AON_TMR 27 +#define CLK_AON_PMU 28 +#define CLK_DEBOUNCE 29 +#define CLK_APCPU_PMU 30 +#define CLK_TOP_DVFS 31 +#define CLK_OTG_UTMI 32 +#define CLK_OTG_REF 33 +#define CLK_CSSYS 34 +#define CLK_CSSYS_PUB 35 +#define CLK_CSSYS_APB 36 +#define CLK_AP_AXI 37 +#define CLK_AP_MM 38 +#define CLK_SDIO2_2X 39 +#define CLK_ANALOG_IO_APB 40 +#define CLK_DMC_REF_CLK 41 +#define CLK_EMC 42 +#define CLK_USB 43 +#define CLK_26M_PMU 44 +#define CLK_AON_APB_NUM (CLK_26M_PMU + 1) + +#define CLK_MM_AHB 0 +#define CLK_MM_MTX 1 +#define CLK_SENSOR0 2 +#define CLK_SENSOR1 3 +#define CLK_SENSOR2 4 +#define CLK_CPP 5 +#define CLK_JPG 6 +#define CLK_FD 7 +#define CLK_DCAM_IF 8 +#define CLK_DCAM_AXI 9 +#define CLK_ISP 10 +#define CLK_MIPI_CSI0 11 +#define CLK_MIPI_CSI1 12 +#define CLK_MIPI_CSI2 13 +#define CLK_MM_CLK_NUM (CLK_MIPI_CSI2 + 1) + +#define CLK_RC100M_CAL_EB 0 +#define CLK_DJTAG_TCK_EB 1 +#define CLK_DJTAG_EB 2 +#define CLK_AUX0_EB 3 +#define CLK_AUX1_EB 4 +#define CLK_AUX2_EB 5 +#define CLK_PROBE_EB 6 +#define CLK_MM_EB 7 +#define CLK_GPU_EB 8 +#define CLK_MSPI_EB 9 +#define CLK_APCPU_DAP_EB 10 +#define CLK_AON_CSSYS_EB 11 +#define CLK_CSSYS_APB_EB 12 +#define CLK_CSSYS_PUB_EB 13 +#define CLK_SDPHY_CFG_EB 14 +#define CLK_SDPHY_REF_EB 15 +#define CLK_EFUSE_EB 16 +#define CLK_GPIO_EB 17 +#define CLK_MBOX_EB 18 +#define CLK_KPD_EB 19 +#define CLK_AON_SYST_EB 20 +#define CLK_AP_SYST_EB 21 +#define CLK_AON_TMR_EB 22 +#define CLK_OTG_UTMI_EB 23 +#define CLK_OTG_PHY_EB 24 +#define CLK_SPLK_EB 25 +#define CLK_PIN_EB 26 +#define CLK_ANA_EB 27 +#define CLK_APCPU_TS0_EB 28 +#define CLK_APB_BUSMON_EB 29 +#define CLK_AON_IIS_EB 30 +#define CLK_SCC_EB 31 +#define CLK_THM0_EB 32 +#define CLK_THM1_EB 33 +#define CLK_THM2_EB 34 +#define CLK_ASIM_TOP_EB 35 +#define CLK_I2C_EB 36 +#define CLK_PMU_EB 37 +#define CLK_ADI_EB 38 +#define CLK_EIC_EB 39 +#define CLK_AP_INTC0_EB 40 +#define CLK_AP_INTC1_EB 41 +#define CLK_AP_INTC2_EB 42 +#define CLK_AP_INTC3_EB 43 +#define CLK_AP_INTC4_EB 44 +#define CLK_AP_INTC5_EB 45 +#define CLK_AUDCP_INTC_EB 46 +#define CLK_AP_TMR0_EB 47 +#define CLK_AP_TMR1_EB 48 +#define CLK_AP_TMR2_EB 49 +#define CLK_PWM0_EB 50 +#define CLK_PWM1_EB 51 +#define CLK_PWM2_EB 52 +#define CLK_PWM3_EB 53 +#define CLK_AP_WDG_EB 54 +#define CLK_APCPU_WDG_EB 55 +#define CLK_SERDES_EB 56 +#define CLK_ARCH_RTC_EB 57 +#define CLK_KPD_RTC_EB 58 +#define CLK_AON_SYST_RTC_EB 59 +#define CLK_AP_SYST_RTC_EB 60 +#define CLK_AON_TMR_RTC_EB 61 +#define CLK_EIC_RTC_EB 62 +#define CLK_EIC_RTCDV5_EB 63 +#define CLK_AP_WDG_RTC_EB 64 +#define CLK_AC_WDG_RTC_EB 65 +#define CLK_AP_TMR0_RTC_EB 66 +#define CLK_AP_TMR1_RTC_EB 67 +#define CLK_AP_TMR2_RTC_EB 68 +#define CLK_DCXO_LC_RTC_EB 69 +#define CLK_BB_CAL_RTC_EB 70 +#define CLK_AP_EMMC_RTC_EB 71 +#define CLK_AP_SDIO0_RTC_EB 72 +#define CLK_AP_SDIO1_RTC_EB 73 +#define CLK_AP_SDIO2_RTC_EB 74 +#define CLK_DSI_CSI_TEST_EB 75 +#define CLK_DJTAG_TCK_EN 76 +#define CLK_DPHY_REF_EB 77 +#define CLK_DMC_REF_EB 78 +#define CLK_OTG_REF_EB 79 +#define CLK_TSEN_EB 80 +#define CLK_TMR_EB 81 +#define CLK_RC100M_REF_EB 82 +#define CLK_RC100M_FDK_EB 83 +#define CLK_DEBOUNCE_EB 84 +#define CLK_DET_32K_EB 85 +#define CLK_TOP_CSSYS_EB 86 +#define CLK_AP_AXI_EN 87 +#define CLK_SDIO0_2X_EN 88 +#define CLK_SDIO0_1X_EN 89 +#define CLK_SDIO1_2X_EN 90 +#define CLK_SDIO1_1X_EN 91 +#define CLK_SDIO2_2X_EN 92 +#define CLK_SDIO2_1X_EN 93 +#define CLK_EMMC_2X_EN 94 +#define CLK_EMMC_1X_EN 95 +#define CLK_PLL_TEST_EN 96 +#define CLK_CPHY_CFG_EN 97 +#define CLK_DEBUG_TS_EN 98 +#define CLK_ACCESS_AUD_EN 99 +#define CLK_AON_APB_GATE_NUM (CLK_ACCESS_AUD_EN + 1) + +#define CLK_MM_CPP_EB 0 +#define CLK_MM_JPG_EB 1 +#define CLK_MM_DCAM_EB 2 +#define CLK_MM_ISP_EB 3 +#define CLK_MM_CSI2_EB 4 +#define CLK_MM_CSI1_EB 5 +#define CLK_MM_CSI0_EB 6 +#define CLK_MM_CKG_EB 7 +#define CLK_ISP_AHB_EB 8 +#define CLK_MM_DVFS_EB 9 +#define CLK_MM_FD_EB 10 +#define CLK_MM_SENSOR2_EB 11 +#define CLK_MM_SENSOR1_EB 12 +#define CLK_MM_SENSOR0_EB 13 +#define CLK_MM_MIPI_CSI2_EB 14 +#define CLK_MM_MIPI_CSI1_EB 15 +#define CLK_MM_MIPI_CSI0_EB 16 +#define CLK_DCAM_AXI_EB 17 +#define CLK_ISP_AXI_EB 18 +#define CLK_MM_CPHY_EB 19 +#define CLK_MM_GATE_CLK_NUM (CLK_MM_CPHY_EB + 1) + +#define CLK_SIM0_EB 0 +#define CLK_IIS0_EB 1 +#define CLK_IIS1_EB 2 +#define CLK_IIS2_EB 3 +#define CLK_APB_REG_EB 4 +#define CLK_SPI0_EB 5 +#define CLK_SPI1_EB 6 +#define CLK_SPI2_EB 7 +#define CLK_SPI3_EB 8 +#define CLK_I2C0_EB 9 +#define CLK_I2C1_EB 10 +#define CLK_I2C2_EB 11 +#define CLK_I2C3_EB 12 +#define CLK_I2C4_EB 13 +#define CLK_UART0_EB 14 +#define CLK_UART1_EB 15 +#define CLK_UART2_EB 16 +#define CLK_SIM0_32K_EB 17 +#define CLK_SPI0_LFIN_EB 18 +#define CLK_SPI1_LFIN_EB 19 +#define CLK_SPI2_LFIN_EB 20 +#define CLK_SPI3_LFIN_EB 21 +#define CLK_SDIO0_EB 22 +#define CLK_SDIO1_EB 23 +#define CLK_SDIO2_EB 24 +#define CLK_EMMC_EB 25 +#define CLK_SDIO0_32K_EB 26 +#define CLK_SDIO1_32K_EB 27 +#define CLK_SDIO2_32K_EB 28 +#define CLK_EMMC_32K_EB 29 +#define CLK_AP_APB_GATE_NUM (CLK_EMMC_32K_EB + 1) + +#define CLK_GPU_CORE_EB 0 +#define CLK_GPU_CORE 1 +#define CLK_GPU_MEM_EB 2 +#define CLK_GPU_MEM 3 +#define CLK_GPU_SYS_EB 4 +#define CLK_GPU_SYS 5 +#define CLK_GPU_CLK_NUM (CLK_GPU_SYS + 1) + +#define CLK_AUDCP_IIS0_EB 0 +#define CLK_AUDCP_IIS1_EB 1 +#define CLK_AUDCP_IIS2_EB 2 +#define CLK_AUDCP_UART_EB 3 +#define CLK_AUDCP_DMA_CP_EB 4 +#define CLK_AUDCP_DMA_AP_EB 5 +#define CLK_AUDCP_SRC48K_EB 6 +#define CLK_AUDCP_MCDT_EB 7 +#define CLK_AUDCP_VBCIFD_EB 8 +#define CLK_AUDCP_VBC_EB 9 +#define CLK_AUDCP_SPLK_EB 10 +#define CLK_AUDCP_ICU_EB 11 +#define CLK_AUDCP_DMA_AP_ASHB_EB 12 +#define CLK_AUDCP_DMA_CP_ASHB_EB 13 +#define CLK_AUDCP_AUD_EB 14 +#define CLK_AUDCP_VBC_24M_EB 15 +#define CLK_AUDCP_TMR_26M_EB 16 +#define CLK_AUDCP_DVFS_ASHB_EB 17 +#define CLK_AUDCP_AHB_GATE_NUM (CLK_AUDCP_DVFS_ASHB_EB + 1) + +#define CLK_AUDCP_WDG_EB 0 +#define CLK_AUDCP_RTC_WDG_EB 1 +#define CLK_AUDCP_TMR0_EB 2 +#define CLK_AUDCP_TMR1_EB 3 +#define CLK_AUDCP_APB_GATE_NUM (CLK_AUDCP_TMR1_EB + 1) + +#define CLK_ACORE0 0 +#define CLK_ACORE1 1 +#define CLK_ACORE2 2 +#define CLK_ACORE3 3 +#define CLK_ACORE4 4 +#define CLK_ACORE5 5 +#define CLK_PCORE0 6 +#define CLK_PCORE1 7 +#define CLK_SCU 8 +#define CLK_ACE 9 +#define CLK_PERIPH 10 +#define CLK_GIC 11 +#define CLK_ATB 12 +#define CLK_DEBUG_APB 13 +#define CLK_APCPU_SEC_NUM (CLK_DEBUG_APB + 1) + +#endif /* _DT_BINDINGS_CLK_UMS512_H_ */ diff --git a/include/dt-bindings/clock/starfive-jh7100-audio.h b/include/dt-bindings/clock/starfive-jh7100-audio.h new file mode 100644 index 000000000000..fbb4eae6572b --- /dev/null +++ b/include/dt-bindings/clock/starfive-jh7100-audio.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk> + */ + +#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7100_AUDIO_H__ +#define __DT_BINDINGS_CLOCK_STARFIVE_JH7100_AUDIO_H__ + +#define JH7100_AUDCLK_ADC_MCLK 0 +#define JH7100_AUDCLK_I2S1_MCLK 1 +#define JH7100_AUDCLK_I2SADC_APB 2 +#define JH7100_AUDCLK_I2SADC_BCLK 3 +#define JH7100_AUDCLK_I2SADC_BCLK_N 4 +#define JH7100_AUDCLK_I2SADC_LRCLK 5 +#define JH7100_AUDCLK_PDM_APB 6 +#define JH7100_AUDCLK_PDM_MCLK 7 +#define JH7100_AUDCLK_I2SVAD_APB 8 +#define JH7100_AUDCLK_SPDIF 9 +#define JH7100_AUDCLK_SPDIF_APB 10 +#define JH7100_AUDCLK_PWMDAC_APB 11 +#define JH7100_AUDCLK_DAC_MCLK 12 +#define JH7100_AUDCLK_I2SDAC_APB 13 +#define JH7100_AUDCLK_I2SDAC_BCLK 14 +#define JH7100_AUDCLK_I2SDAC_BCLK_N 15 +#define JH7100_AUDCLK_I2SDAC_LRCLK 16 +#define JH7100_AUDCLK_I2S1_APB 17 +#define JH7100_AUDCLK_I2S1_BCLK 18 +#define JH7100_AUDCLK_I2S1_BCLK_N 19 +#define JH7100_AUDCLK_I2S1_LRCLK 20 +#define JH7100_AUDCLK_I2SDAC16K_APB 21 +#define JH7100_AUDCLK_APB0_BUS 22 +#define JH7100_AUDCLK_DMA1P_AHB 23 +#define JH7100_AUDCLK_USB_APB 24 +#define JH7100_AUDCLK_USB_LPM 25 +#define JH7100_AUDCLK_USB_STB 26 +#define JH7100_AUDCLK_APB_EN 27 +#define JH7100_AUDCLK_VAD_MEM 28 + +#define JH7100_AUDCLK_END 29 + +#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7100_AUDIO_H__ */ diff --git a/include/dt-bindings/clock/starfive-jh7100.h b/include/dt-bindings/clock/starfive-jh7100.h new file mode 100644 index 000000000000..aa0863b9728d --- /dev/null +++ b/include/dt-bindings/clock/starfive-jh7100.h @@ -0,0 +1,202 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Copyright (C) 2021 Ahmad Fatoum, Pengutronix + */ + +#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7100_H__ +#define __DT_BINDINGS_CLOCK_STARFIVE_JH7100_H__ + +#define JH7100_CLK_CPUNDBUS_ROOT 0 +#define JH7100_CLK_DLA_ROOT 1 +#define JH7100_CLK_DSP_ROOT 2 +#define JH7100_CLK_GMACUSB_ROOT 3 +#define JH7100_CLK_PERH0_ROOT 4 +#define JH7100_CLK_PERH1_ROOT 5 +#define JH7100_CLK_VIN_ROOT 6 +#define JH7100_CLK_VOUT_ROOT 7 +#define JH7100_CLK_AUDIO_ROOT 8 +#define JH7100_CLK_CDECHIFI4_ROOT 9 +#define JH7100_CLK_CDEC_ROOT 10 +#define JH7100_CLK_VOUTBUS_ROOT 11 +#define JH7100_CLK_CPUNBUS_ROOT_DIV 12 +#define JH7100_CLK_DSP_ROOT_DIV 13 +#define JH7100_CLK_PERH0_SRC 14 +#define JH7100_CLK_PERH1_SRC 15 +#define JH7100_CLK_PLL0_TESTOUT 16 +#define JH7100_CLK_PLL1_TESTOUT 17 +#define JH7100_CLK_PLL2_TESTOUT 18 +#define JH7100_CLK_PLL2_REF 19 +#define JH7100_CLK_CPU_CORE 20 +#define JH7100_CLK_CPU_AXI 21 +#define JH7100_CLK_AHB_BUS 22 +#define JH7100_CLK_APB1_BUS 23 +#define JH7100_CLK_APB2_BUS 24 +#define JH7100_CLK_DOM3AHB_BUS 25 +#define JH7100_CLK_DOM7AHB_BUS 26 +#define JH7100_CLK_U74_CORE0 27 +#define JH7100_CLK_U74_CORE1 28 +#define JH7100_CLK_U74_AXI 29 +#define JH7100_CLK_U74RTC_TOGGLE 30 +#define JH7100_CLK_SGDMA2P_AXI 31 +#define JH7100_CLK_DMA2PNOC_AXI 32 +#define JH7100_CLK_SGDMA2P_AHB 33 +#define JH7100_CLK_DLA_BUS 34 +#define JH7100_CLK_DLA_AXI 35 +#define JH7100_CLK_DLANOC_AXI 36 +#define JH7100_CLK_DLA_APB 37 +#define JH7100_CLK_VP6_CORE 38 +#define JH7100_CLK_VP6BUS_SRC 39 +#define JH7100_CLK_VP6_AXI 40 +#define JH7100_CLK_VCDECBUS_SRC 41 +#define JH7100_CLK_VDEC_BUS 42 +#define JH7100_CLK_VDEC_AXI 43 +#define JH7100_CLK_VDECBRG_MAIN 44 +#define JH7100_CLK_VDEC_BCLK 45 +#define JH7100_CLK_VDEC_CCLK 46 +#define JH7100_CLK_VDEC_APB 47 +#define JH7100_CLK_JPEG_AXI 48 +#define JH7100_CLK_JPEG_CCLK 49 +#define JH7100_CLK_JPEG_APB 50 +#define JH7100_CLK_GC300_2X 51 +#define JH7100_CLK_GC300_AHB 52 +#define JH7100_CLK_JPCGC300_AXIBUS 53 +#define JH7100_CLK_GC300_AXI 54 +#define JH7100_CLK_JPCGC300_MAIN 55 +#define JH7100_CLK_VENC_BUS 56 +#define JH7100_CLK_VENC_AXI 57 +#define JH7100_CLK_VENCBRG_MAIN 58 +#define JH7100_CLK_VENC_BCLK 59 +#define JH7100_CLK_VENC_CCLK 60 +#define JH7100_CLK_VENC_APB 61 +#define JH7100_CLK_DDRPLL_DIV2 62 +#define JH7100_CLK_DDRPLL_DIV4 63 +#define JH7100_CLK_DDRPLL_DIV8 64 +#define JH7100_CLK_DDROSC_DIV2 65 +#define JH7100_CLK_DDRC0 66 +#define JH7100_CLK_DDRC1 67 +#define JH7100_CLK_DDRPHY_APB 68 +#define JH7100_CLK_NOC_ROB 69 +#define JH7100_CLK_NOC_COG 70 +#define JH7100_CLK_NNE_AHB 71 +#define JH7100_CLK_NNEBUS_SRC1 72 +#define JH7100_CLK_NNE_BUS 73 +#define JH7100_CLK_NNE_AXI 74 +#define JH7100_CLK_NNENOC_AXI 75 +#define JH7100_CLK_DLASLV_AXI 76 +#define JH7100_CLK_DSPX2C_AXI 77 +#define JH7100_CLK_HIFI4_SRC 78 +#define JH7100_CLK_HIFI4_COREFREE 79 +#define JH7100_CLK_HIFI4_CORE 80 +#define JH7100_CLK_HIFI4_BUS 81 +#define JH7100_CLK_HIFI4_AXI 82 +#define JH7100_CLK_HIFI4NOC_AXI 83 +#define JH7100_CLK_SGDMA1P_BUS 84 +#define JH7100_CLK_SGDMA1P_AXI 85 +#define JH7100_CLK_DMA1P_AXI 86 +#define JH7100_CLK_X2C_AXI 87 +#define JH7100_CLK_USB_BUS 88 +#define JH7100_CLK_USB_AXI 89 +#define JH7100_CLK_USBNOC_AXI 90 +#define JH7100_CLK_USBPHY_ROOTDIV 91 +#define JH7100_CLK_USBPHY_125M 92 +#define JH7100_CLK_USBPHY_PLLDIV25M 93 +#define JH7100_CLK_USBPHY_25M 94 +#define JH7100_CLK_AUDIO_DIV 95 +#define JH7100_CLK_AUDIO_SRC 96 +#define JH7100_CLK_AUDIO_12288 97 +#define JH7100_CLK_VIN_SRC 98 +#define JH7100_CLK_ISP0_BUS 99 +#define JH7100_CLK_ISP0_AXI 100 +#define JH7100_CLK_ISP0NOC_AXI 101 +#define JH7100_CLK_ISPSLV_AXI 102 +#define JH7100_CLK_ISP1_BUS 103 +#define JH7100_CLK_ISP1_AXI 104 +#define JH7100_CLK_ISP1NOC_AXI 105 +#define JH7100_CLK_VIN_BUS 106 +#define JH7100_CLK_VIN_AXI 107 +#define JH7100_CLK_VINNOC_AXI 108 +#define JH7100_CLK_VOUT_SRC 109 +#define JH7100_CLK_DISPBUS_SRC 110 +#define JH7100_CLK_DISP_BUS 111 +#define JH7100_CLK_DISP_AXI 112 +#define JH7100_CLK_DISPNOC_AXI 113 +#define JH7100_CLK_SDIO0_AHB 114 +#define JH7100_CLK_SDIO0_CCLKINT 115 +#define JH7100_CLK_SDIO0_CCLKINT_INV 116 +#define JH7100_CLK_SDIO1_AHB 117 +#define JH7100_CLK_SDIO1_CCLKINT 118 +#define JH7100_CLK_SDIO1_CCLKINT_INV 119 +#define JH7100_CLK_GMAC_AHB 120 +#define JH7100_CLK_GMAC_ROOT_DIV 121 +#define JH7100_CLK_GMAC_PTP_REF 122 +#define JH7100_CLK_GMAC_GTX 123 +#define JH7100_CLK_GMAC_RMII_TX 124 +#define JH7100_CLK_GMAC_RMII_RX 125 +#define JH7100_CLK_GMAC_TX 126 +#define JH7100_CLK_GMAC_TX_INV 127 +#define JH7100_CLK_GMAC_RX_PRE 128 +#define JH7100_CLK_GMAC_RX_INV 129 +#define JH7100_CLK_GMAC_RMII 130 +#define JH7100_CLK_GMAC_TOPHYREF 131 +#define JH7100_CLK_SPI2AHB_AHB 132 +#define JH7100_CLK_SPI2AHB_CORE 133 +#define JH7100_CLK_EZMASTER_AHB 134 +#define JH7100_CLK_E24_AHB 135 +#define JH7100_CLK_E24RTC_TOGGLE 136 +#define JH7100_CLK_QSPI_AHB 137 +#define JH7100_CLK_QSPI_APB 138 +#define JH7100_CLK_QSPI_REF 139 +#define JH7100_CLK_SEC_AHB 140 +#define JH7100_CLK_AES 141 +#define JH7100_CLK_SHA 142 +#define JH7100_CLK_PKA 143 +#define JH7100_CLK_TRNG_APB 144 +#define JH7100_CLK_OTP_APB 145 +#define JH7100_CLK_UART0_APB 146 +#define JH7100_CLK_UART0_CORE 147 +#define JH7100_CLK_UART1_APB 148 +#define JH7100_CLK_UART1_CORE 149 +#define JH7100_CLK_SPI0_APB 150 +#define JH7100_CLK_SPI0_CORE 151 +#define JH7100_CLK_SPI1_APB 152 +#define JH7100_CLK_SPI1_CORE 153 +#define JH7100_CLK_I2C0_APB 154 +#define JH7100_CLK_I2C0_CORE 155 +#define JH7100_CLK_I2C1_APB 156 +#define JH7100_CLK_I2C1_CORE 157 +#define JH7100_CLK_GPIO_APB 158 +#define JH7100_CLK_UART2_APB 159 +#define JH7100_CLK_UART2_CORE 160 +#define JH7100_CLK_UART3_APB 161 +#define JH7100_CLK_UART3_CORE 162 +#define JH7100_CLK_SPI2_APB 163 +#define JH7100_CLK_SPI2_CORE 164 +#define JH7100_CLK_SPI3_APB 165 +#define JH7100_CLK_SPI3_CORE 166 +#define JH7100_CLK_I2C2_APB 167 +#define JH7100_CLK_I2C2_CORE 168 +#define JH7100_CLK_I2C3_APB 169 +#define JH7100_CLK_I2C3_CORE 170 +#define JH7100_CLK_WDTIMER_APB 171 +#define JH7100_CLK_WDT_CORE 172 +#define JH7100_CLK_TIMER0_CORE 173 +#define JH7100_CLK_TIMER1_CORE 174 +#define JH7100_CLK_TIMER2_CORE 175 +#define JH7100_CLK_TIMER3_CORE 176 +#define JH7100_CLK_TIMER4_CORE 177 +#define JH7100_CLK_TIMER5_CORE 178 +#define JH7100_CLK_TIMER6_CORE 179 +#define JH7100_CLK_VP6INTC_APB 180 +#define JH7100_CLK_PWM_APB 181 +#define JH7100_CLK_MSI_APB 182 +#define JH7100_CLK_TEMP_APB 183 +#define JH7100_CLK_TEMP_SENSE 184 +#define JH7100_CLK_SYSERR_APB 185 + +#define JH7100_CLK_PLL0_OUT 186 +#define JH7100_CLK_PLL1_OUT 187 +#define JH7100_CLK_PLL2_OUT 188 + +#define JH7100_CLK_END 189 + +#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7100_H__ */ diff --git a/include/dt-bindings/clock/ste-db8500-clkout.h b/include/dt-bindings/clock/ste-db8500-clkout.h new file mode 100644 index 000000000000..ca07cb2bd1bc --- /dev/null +++ b/include/dt-bindings/clock/ste-db8500-clkout.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __STE_CLK_DB8500_CLKOUT_H__ +#define __STE_CLK_DB8500_CLKOUT_H__ + +#define DB8500_CLKOUT_1 0 +#define DB8500_CLKOUT_2 1 + +#define DB8500_CLKOUT_SRC_CLK38M 0 +#define DB8500_CLKOUT_SRC_ACLK 1 +#define DB8500_CLKOUT_SRC_SYSCLK 2 +#define DB8500_CLKOUT_SRC_LCDCLK 3 +#define DB8500_CLKOUT_SRC_SDMMCCLK 4 +#define DB8500_CLKOUT_SRC_TVCLK 5 +#define DB8500_CLKOUT_SRC_TIMCLK 6 +#define DB8500_CLKOUT_SRC_CLK009 7 + +#endif diff --git a/include/dt-bindings/clock/stm32fx-clock.h b/include/dt-bindings/clock/stm32fx-clock.h index 1cc89c548578..e5dad050d518 100644 --- a/include/dt-bindings/clock/stm32fx-clock.h +++ b/include/dt-bindings/clock/stm32fx-clock.h @@ -7,10 +7,10 @@ */ /* - * List of clocks wich are not derived from system clock (SYSCLOCK) + * List of clocks which are not derived from system clock (SYSCLOCK) * * The index of these clocks is the secondary index of DT bindings - * (see Documentatoin/devicetree/bindings/clock/st,stm32-rcc.txt) + * (see Documentation/devicetree/bindings/clock/st,stm32-rcc.txt) * * e.g: <assigned-clocks = <&rcc 1 CLK_LSE>; diff --git a/include/dt-bindings/clock/stm32mp1-clks.h b/include/dt-bindings/clock/stm32mp1-clks.h index 4cdaf135829c..25e8cfd43459 100644 --- a/include/dt-bindings/clock/stm32mp1-clks.h +++ b/include/dt-bindings/clock/stm32mp1-clks.h @@ -248,4 +248,27 @@ #define STM32MP1_LAST_CLK 232 +/* SCMI clock identifiers */ +#define CK_SCMI_HSE 0 +#define CK_SCMI_HSI 1 +#define CK_SCMI_CSI 2 +#define CK_SCMI_LSE 3 +#define CK_SCMI_LSI 4 +#define CK_SCMI_PLL2_Q 5 +#define CK_SCMI_PLL2_R 6 +#define CK_SCMI_MPU 7 +#define CK_SCMI_AXI 8 +#define CK_SCMI_BSEC 9 +#define CK_SCMI_CRYP1 10 +#define CK_SCMI_GPIOZ 11 +#define CK_SCMI_HASH1 12 +#define CK_SCMI_I2C4 13 +#define CK_SCMI_I2C6 14 +#define CK_SCMI_IWDG1 15 +#define CK_SCMI_RNG1 16 +#define CK_SCMI_RTC 17 +#define CK_SCMI_RTCAPB 18 +#define CK_SCMI_SPI6 19 +#define CK_SCMI_USART1 20 + #endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */ diff --git a/include/dt-bindings/clock/stm32mp13-clks.h b/include/dt-bindings/clock/stm32mp13-clks.h new file mode 100644 index 000000000000..02befd25edce --- /dev/null +++ b/include/dt-bindings/clock/stm32mp13-clks.h @@ -0,0 +1,229 @@ +/* SPDX-License-Identifier: GPL-2.0+ or BSD-3-Clause */ +/* + * Copyright (C) STMicroelectronics 2020 - All Rights Reserved + * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics. + */ + +#ifndef _DT_BINDINGS_STM32MP13_CLKS_H_ +#define _DT_BINDINGS_STM32MP13_CLKS_H_ + +/* OSCILLATOR clocks */ +#define CK_HSE 0 +#define CK_CSI 1 +#define CK_LSI 2 +#define CK_LSE 3 +#define CK_HSI 4 +#define CK_HSE_DIV2 5 + +/* PLL */ +#define PLL1 6 +#define PLL2 7 +#define PLL3 8 +#define PLL4 9 + +/* ODF */ +#define PLL1_P 10 +#define PLL1_Q 11 +#define PLL1_R 12 +#define PLL2_P 13 +#define PLL2_Q 14 +#define PLL2_R 15 +#define PLL3_P 16 +#define PLL3_Q 17 +#define PLL3_R 18 +#define PLL4_P 19 +#define PLL4_Q 20 +#define PLL4_R 21 + +#define PCLK1 22 +#define PCLK2 23 +#define PCLK3 24 +#define PCLK4 25 +#define PCLK5 26 +#define PCLK6 27 + +/* SYSTEM CLOCK */ +#define CK_PER 28 +#define CK_MPU 29 +#define CK_AXI 30 +#define CK_MLAHB 31 + +/* BASE TIMER */ +#define CK_TIMG1 32 +#define CK_TIMG2 33 +#define CK_TIMG3 34 + +/* AUX */ +#define RTC 35 + +/* TRACE & DEBUG clocks */ +#define CK_DBG 36 +#define CK_TRACE 37 + +/* MCO clocks */ +#define CK_MCO1 38 +#define CK_MCO2 39 + +/* IP clocks */ +#define SYSCFG 40 +#define VREF 41 +#define DTS 42 +#define PMBCTRL 43 +#define HDP 44 +#define IWDG2 45 +#define STGENRO 46 +#define USART1 47 +#define RTCAPB 48 +#define TZC 49 +#define TZPC 50 +#define IWDG1 51 +#define BSEC 52 +#define DMA1 53 +#define DMA2 54 +#define DMAMUX1 55 +#define DMAMUX2 56 +#define GPIOA 57 +#define GPIOB 58 +#define GPIOC 59 +#define GPIOD 60 +#define GPIOE 61 +#define GPIOF 62 +#define GPIOG 63 +#define GPIOH 64 +#define GPIOI 65 +#define CRYP1 66 +#define HASH1 67 +#define BKPSRAM 68 +#define MDMA 69 +#define CRC1 70 +#define USBH 71 +#define DMA3 72 +#define TSC 73 +#define PKA 74 +#define AXIMC 75 +#define MCE 76 +#define ETH1TX 77 +#define ETH2TX 78 +#define ETH1RX 79 +#define ETH2RX 80 +#define ETH1MAC 81 +#define ETH2MAC 82 +#define ETH1STP 83 +#define ETH2STP 84 + +/* IP clocks with parents */ +#define SDMMC1_K 85 +#define SDMMC2_K 86 +#define ADC1_K 87 +#define ADC2_K 88 +#define FMC_K 89 +#define QSPI_K 90 +#define RNG1_K 91 +#define USBPHY_K 92 +#define STGEN_K 93 +#define SPDIF_K 94 +#define SPI1_K 95 +#define SPI2_K 96 +#define SPI3_K 97 +#define SPI4_K 98 +#define SPI5_K 99 +#define I2C1_K 100 +#define I2C2_K 101 +#define I2C3_K 102 +#define I2C4_K 103 +#define I2C5_K 104 +#define TIM2_K 105 +#define TIM3_K 106 +#define TIM4_K 107 +#define TIM5_K 108 +#define TIM6_K 109 +#define TIM7_K 110 +#define TIM12_K 111 +#define TIM13_K 112 +#define TIM14_K 113 +#define TIM1_K 114 +#define TIM8_K 115 +#define TIM15_K 116 +#define TIM16_K 117 +#define TIM17_K 118 +#define LPTIM1_K 119 +#define LPTIM2_K 120 +#define LPTIM3_K 121 +#define LPTIM4_K 122 +#define LPTIM5_K 123 +#define USART1_K 124 +#define USART2_K 125 +#define USART3_K 126 +#define UART4_K 127 +#define UART5_K 128 +#define USART6_K 129 +#define UART7_K 130 +#define UART8_K 131 +#define DFSDM_K 132 +#define FDCAN_K 133 +#define SAI1_K 134 +#define SAI2_K 135 +#define ADFSDM_K 136 +#define USBO_K 137 +#define LTDC_PX 138 +#define ETH1CK_K 139 +#define ETH1PTP_K 140 +#define ETH2CK_K 141 +#define ETH2PTP_K 142 +#define DCMIPP_K 143 +#define SAES_K 144 +#define DTS_K 145 + +/* DDR */ +#define DDRC1 146 +#define DDRC1LP 147 +#define DDRC2 148 +#define DDRC2LP 149 +#define DDRPHYC 150 +#define DDRPHYCLP 151 +#define DDRCAPB 152 +#define DDRCAPBLP 153 +#define AXIDCG 154 +#define DDRPHYCAPB 155 +#define DDRPHYCAPBLP 156 +#define DDRPERFM 157 + +#define ADC1 158 +#define ADC2 159 +#define SAI1 160 +#define SAI2 161 + +#define STM32MP1_LAST_CLK 162 + +/* SCMI clock identifiers */ +#define CK_SCMI_HSE 0 +#define CK_SCMI_HSI 1 +#define CK_SCMI_CSI 2 +#define CK_SCMI_LSE 3 +#define CK_SCMI_LSI 4 +#define CK_SCMI_HSE_DIV2 5 +#define CK_SCMI_PLL2_Q 6 +#define CK_SCMI_PLL2_R 7 +#define CK_SCMI_PLL3_P 8 +#define CK_SCMI_PLL3_Q 9 +#define CK_SCMI_PLL3_R 10 +#define CK_SCMI_PLL4_P 11 +#define CK_SCMI_PLL4_Q 12 +#define CK_SCMI_PLL4_R 13 +#define CK_SCMI_MPU 14 +#define CK_SCMI_AXI 15 +#define CK_SCMI_MLAHB 16 +#define CK_SCMI_CKPER 17 +#define CK_SCMI_PCLK1 18 +#define CK_SCMI_PCLK2 19 +#define CK_SCMI_PCLK3 20 +#define CK_SCMI_PCLK4 21 +#define CK_SCMI_PCLK5 22 +#define CK_SCMI_PCLK6 23 +#define CK_SCMI_CKTIMG1 24 +#define CK_SCMI_CKTIMG2 25 +#define CK_SCMI_CKTIMG3 26 +#define CK_SCMI_RTC 27 +#define CK_SCMI_RTCAPB 28 + +#endif /* _DT_BINDINGS_STM32MP13_CLKS_H_ */ diff --git a/include/dt-bindings/clock/stratix10-clock.h b/include/dt-bindings/clock/stratix10-clock.h index 08b98e20b7cc..636498f9e08e 100644 --- a/include/dt-bindings/clock/stratix10-clock.h +++ b/include/dt-bindings/clock/stratix10-clock.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2017, Intel Corporation */ diff --git a/include/dt-bindings/clock/sun20i-d1-ccu.h b/include/dt-bindings/clock/sun20i-d1-ccu.h new file mode 100644 index 000000000000..e3ac53315e1a --- /dev/null +++ b/include/dt-bindings/clock/sun20i-d1-ccu.h @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* + * Copyright (C) 2020 huangzhenwei@allwinnertech.com + * Copyright (C) 2021 Samuel Holland <samuel@sholland.org> + */ + +#ifndef _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_ +#define _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_ + +#define CLK_PLL_CPUX 0 +#define CLK_PLL_DDR0 1 +#define CLK_PLL_PERIPH0_4X 2 +#define CLK_PLL_PERIPH0_2X 3 +#define CLK_PLL_PERIPH0_800M 4 +#define CLK_PLL_PERIPH0 5 +#define CLK_PLL_PERIPH0_DIV3 6 +#define CLK_PLL_VIDEO0_4X 7 +#define CLK_PLL_VIDEO0_2X 8 +#define CLK_PLL_VIDEO0 9 +#define CLK_PLL_VIDEO1_4X 10 +#define CLK_PLL_VIDEO1_2X 11 +#define CLK_PLL_VIDEO1 12 +#define CLK_PLL_VE 13 +#define CLK_PLL_AUDIO0_4X 14 +#define CLK_PLL_AUDIO0_2X 15 +#define CLK_PLL_AUDIO0 16 +#define CLK_PLL_AUDIO1 17 +#define CLK_PLL_AUDIO1_DIV2 18 +#define CLK_PLL_AUDIO1_DIV5 19 +#define CLK_CPUX 20 +#define CLK_CPUX_AXI 21 +#define CLK_CPUX_APB 22 +#define CLK_PSI_AHB 23 +#define CLK_APB0 24 +#define CLK_APB1 25 +#define CLK_MBUS 26 +#define CLK_DE 27 +#define CLK_BUS_DE 28 +#define CLK_DI 29 +#define CLK_BUS_DI 30 +#define CLK_G2D 31 +#define CLK_BUS_G2D 32 +#define CLK_CE 33 +#define CLK_BUS_CE 34 +#define CLK_VE 35 +#define CLK_BUS_VE 36 +#define CLK_BUS_DMA 37 +#define CLK_BUS_MSGBOX0 38 +#define CLK_BUS_MSGBOX1 39 +#define CLK_BUS_MSGBOX2 40 +#define CLK_BUS_SPINLOCK 41 +#define CLK_BUS_HSTIMER 42 +#define CLK_AVS 43 +#define CLK_BUS_DBG 44 +#define CLK_BUS_PWM 45 +#define CLK_BUS_IOMMU 46 +#define CLK_DRAM 47 +#define CLK_MBUS_DMA 48 +#define CLK_MBUS_VE 49 +#define CLK_MBUS_CE 50 +#define CLK_MBUS_TVIN 51 +#define CLK_MBUS_CSI 52 +#define CLK_MBUS_G2D 53 +#define CLK_MBUS_RISCV 54 +#define CLK_BUS_DRAM 55 +#define CLK_MMC0 56 +#define CLK_MMC1 57 +#define CLK_MMC2 58 +#define CLK_BUS_MMC0 59 +#define CLK_BUS_MMC1 60 +#define CLK_BUS_MMC2 61 +#define CLK_BUS_UART0 62 +#define CLK_BUS_UART1 63 +#define CLK_BUS_UART2 64 +#define CLK_BUS_UART3 65 +#define CLK_BUS_UART4 66 +#define CLK_BUS_UART5 67 +#define CLK_BUS_I2C0 68 +#define CLK_BUS_I2C1 69 +#define CLK_BUS_I2C2 70 +#define CLK_BUS_I2C3 71 +#define CLK_SPI0 72 +#define CLK_SPI1 73 +#define CLK_BUS_SPI0 74 +#define CLK_BUS_SPI1 75 +#define CLK_EMAC_25M 76 +#define CLK_BUS_EMAC 77 +#define CLK_IR_TX 78 +#define CLK_BUS_IR_TX 79 +#define CLK_BUS_GPADC 80 +#define CLK_BUS_THS 81 +#define CLK_I2S0 82 +#define CLK_I2S1 83 +#define CLK_I2S2 84 +#define CLK_I2S2_ASRC 85 +#define CLK_BUS_I2S0 86 +#define CLK_BUS_I2S1 87 +#define CLK_BUS_I2S2 88 +#define CLK_SPDIF_TX 89 +#define CLK_SPDIF_RX 90 +#define CLK_BUS_SPDIF 91 +#define CLK_DMIC 92 +#define CLK_BUS_DMIC 93 +#define CLK_AUDIO_DAC 94 +#define CLK_AUDIO_ADC 95 +#define CLK_BUS_AUDIO 96 +#define CLK_USB_OHCI0 97 +#define CLK_USB_OHCI1 98 +#define CLK_BUS_OHCI0 99 +#define CLK_BUS_OHCI1 100 +#define CLK_BUS_EHCI0 101 +#define CLK_BUS_EHCI1 102 +#define CLK_BUS_OTG 103 +#define CLK_BUS_LRADC 104 +#define CLK_BUS_DPSS_TOP 105 +#define CLK_HDMI_24M 106 +#define CLK_HDMI_CEC_32K 107 +#define CLK_HDMI_CEC 108 +#define CLK_BUS_HDMI 109 +#define CLK_MIPI_DSI 110 +#define CLK_BUS_MIPI_DSI 111 +#define CLK_TCON_LCD0 112 +#define CLK_BUS_TCON_LCD0 113 +#define CLK_TCON_TV 114 +#define CLK_BUS_TCON_TV 115 +#define CLK_TVE 116 +#define CLK_BUS_TVE_TOP 117 +#define CLK_BUS_TVE 118 +#define CLK_TVD 119 +#define CLK_BUS_TVD_TOP 120 +#define CLK_BUS_TVD 121 +#define CLK_LEDC 122 +#define CLK_BUS_LEDC 123 +#define CLK_CSI_TOP 124 +#define CLK_CSI_MCLK 125 +#define CLK_BUS_CSI 126 +#define CLK_TPADC 127 +#define CLK_BUS_TPADC 128 +#define CLK_BUS_TZMA 129 +#define CLK_DSP 130 +#define CLK_BUS_DSP_CFG 131 +#define CLK_RISCV 132 +#define CLK_RISCV_AXI 133 +#define CLK_BUS_RISCV_CFG 134 +#define CLK_FANOUT_24M 135 +#define CLK_FANOUT_12M 136 +#define CLK_FANOUT_16M 137 +#define CLK_FANOUT_25M 138 +#define CLK_FANOUT_32K 139 +#define CLK_FANOUT_27M 140 +#define CLK_FANOUT_PCLK 141 +#define CLK_FANOUT0 142 +#define CLK_FANOUT1 143 +#define CLK_FANOUT2 144 + +#endif /* _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_ */ diff --git a/include/dt-bindings/clock/sun20i-d1-r-ccu.h b/include/dt-bindings/clock/sun20i-d1-r-ccu.h new file mode 100644 index 000000000000..4c2697fd32b0 --- /dev/null +++ b/include/dt-bindings/clock/sun20i-d1-r-ccu.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* + * Copyright (C) 2021 Samuel Holland <samuel@sholland.org> + */ + +#ifndef _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_ +#define _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_ + +#define CLK_R_AHB 0 + +#define CLK_BUS_R_TIMER 2 +#define CLK_BUS_R_TWD 3 +#define CLK_BUS_R_PPU 4 +#define CLK_R_IR_RX 5 +#define CLK_BUS_R_IR_RX 6 +#define CLK_BUS_R_RTC 7 +#define CLK_BUS_R_CPUCFG 8 + +#endif /* _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_ */ diff --git a/include/dt-bindings/clock/sun50i-a100-ccu.h b/include/dt-bindings/clock/sun50i-a100-ccu.h new file mode 100644 index 000000000000..28dc36e1a232 --- /dev/null +++ b/include/dt-bindings/clock/sun50i-a100-ccu.h @@ -0,0 +1,116 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* + * Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com> + */ + +#ifndef _DT_BINDINGS_CLK_SUN50I_A100_H_ +#define _DT_BINDINGS_CLK_SUN50I_A100_H_ + +#define CLK_PLL_PERIPH0 3 + +#define CLK_CPUX 24 + +#define CLK_APB1 29 + +#define CLK_MBUS 31 +#define CLK_DE 32 +#define CLK_BUS_DE 33 +#define CLK_G2D 34 +#define CLK_BUS_G2D 35 +#define CLK_GPU 36 +#define CLK_BUS_GPU 37 +#define CLK_CE 38 +#define CLK_BUS_CE 39 +#define CLK_VE 40 +#define CLK_BUS_VE 41 +#define CLK_BUS_DMA 42 +#define CLK_BUS_MSGBOX 43 +#define CLK_BUS_SPINLOCK 44 +#define CLK_BUS_HSTIMER 45 +#define CLK_AVS 46 +#define CLK_BUS_DBG 47 +#define CLK_BUS_PSI 48 +#define CLK_BUS_PWM 49 +#define CLK_BUS_IOMMU 50 +#define CLK_MBUS_DMA 51 +#define CLK_MBUS_VE 52 +#define CLK_MBUS_CE 53 +#define CLK_MBUS_NAND 54 +#define CLK_MBUS_CSI 55 +#define CLK_MBUS_ISP 56 +#define CLK_MBUS_G2D 57 + +#define CLK_NAND0 59 +#define CLK_NAND1 60 +#define CLK_BUS_NAND 61 +#define CLK_MMC0 62 +#define CLK_MMC1 63 +#define CLK_MMC2 64 +#define CLK_MMC3 65 +#define CLK_BUS_MMC0 66 +#define CLK_BUS_MMC1 67 +#define CLK_BUS_MMC2 68 +#define CLK_BUS_UART0 69 +#define CLK_BUS_UART1 70 +#define CLK_BUS_UART2 71 +#define CLK_BUS_UART3 72 +#define CLK_BUS_UART4 73 +#define CLK_BUS_I2C0 74 +#define CLK_BUS_I2C1 75 +#define CLK_BUS_I2C2 76 +#define CLK_BUS_I2C3 77 +#define CLK_SPI0 78 +#define CLK_SPI1 79 +#define CLK_SPI2 80 +#define CLK_BUS_SPI0 81 +#define CLK_BUS_SPI1 82 +#define CLK_BUS_SPI2 83 +#define CLK_EMAC_25M 84 +#define CLK_BUS_EMAC 85 +#define CLK_IR_RX 86 +#define CLK_BUS_IR_RX 87 +#define CLK_IR_TX 88 +#define CLK_BUS_IR_TX 89 +#define CLK_BUS_GPADC 90 +#define CLK_BUS_THS 91 +#define CLK_I2S0 92 +#define CLK_I2S1 93 +#define CLK_I2S2 94 +#define CLK_I2S3 95 +#define CLK_BUS_I2S0 96 +#define CLK_BUS_I2S1 97 +#define CLK_BUS_I2S2 98 +#define CLK_BUS_I2S3 99 +#define CLK_SPDIF 100 +#define CLK_BUS_SPDIF 101 +#define CLK_DMIC 102 +#define CLK_BUS_DMIC 103 +#define CLK_AUDIO_DAC 104 +#define CLK_AUDIO_ADC 105 +#define CLK_AUDIO_4X 106 +#define CLK_BUS_AUDIO_CODEC 107 +#define CLK_USB_OHCI0 108 +#define CLK_USB_PHY0 109 +#define CLK_USB_OHCI1 110 +#define CLK_USB_PHY1 111 +#define CLK_BUS_OHCI0 112 +#define CLK_BUS_OHCI1 113 +#define CLK_BUS_EHCI0 114 +#define CLK_BUS_EHCI1 115 +#define CLK_BUS_OTG 116 +#define CLK_BUS_LRADC 117 +#define CLK_BUS_DPSS_TOP0 118 +#define CLK_BUS_DPSS_TOP1 119 +#define CLK_MIPI_DSI 120 +#define CLK_BUS_MIPI_DSI 121 +#define CLK_TCON_LCD 122 +#define CLK_BUS_TCON_LCD 123 +#define CLK_LEDC 124 +#define CLK_BUS_LEDC 125 +#define CLK_CSI_TOP 126 +#define CLK_CSI0_MCLK 127 +#define CLK_CSI1_MCLK 128 +#define CLK_BUS_CSI 129 +#define CLK_CSI_ISP 130 + +#endif /* _DT_BINDINGS_CLK_SUN50I_A100_H_ */ diff --git a/include/dt-bindings/clock/sun50i-a100-r-ccu.h b/include/dt-bindings/clock/sun50i-a100-r-ccu.h new file mode 100644 index 000000000000..07312e7264fb --- /dev/null +++ b/include/dt-bindings/clock/sun50i-a100-r-ccu.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com> + */ + +#ifndef _DT_BINDINGS_CLK_SUN50I_A100_R_CCU_H_ +#define _DT_BINDINGS_CLK_SUN50I_A100_R_CCU_H_ + +#define CLK_R_APB1 2 + +#define CLK_R_APB1_TIMER 4 +#define CLK_R_APB1_TWD 5 +#define CLK_R_APB1_PWM 6 +#define CLK_R_APB1_BUS_PWM 7 +#define CLK_R_APB1_PPU 8 +#define CLK_R_APB2_UART 9 +#define CLK_R_APB2_I2C0 10 +#define CLK_R_APB2_I2C1 11 +#define CLK_R_APB1_IR 12 +#define CLK_R_APB1_BUS_IR 13 +#define CLK_R_AHB_BUS_RTC 14 + +#endif /* _DT_BINDINGS_CLK_SUN50I_A100_R_CCU_H_ */ diff --git a/include/dt-bindings/clock/sun50i-a64-ccu.h b/include/dt-bindings/clock/sun50i-a64-ccu.h index e512a1c9b0fc..175892189e9d 100644 --- a/include/dt-bindings/clock/sun50i-a64-ccu.h +++ b/include/dt-bindings/clock/sun50i-a64-ccu.h @@ -113,7 +113,7 @@ #define CLK_USB_OHCI0 91 #define CLK_USB_OHCI1 93 - +#define CLK_DRAM 94 #define CLK_DRAM_VE 95 #define CLK_DRAM_CSI 96 #define CLK_DRAM_DEINTERLACE 97 @@ -131,7 +131,7 @@ #define CLK_AVS 109 #define CLK_HDMI 110 #define CLK_HDMI_DDC 111 - +#define CLK_MBUS 112 #define CLK_DSI_DPHY 113 #define CLK_GPU 114 diff --git a/include/dt-bindings/clock/sun50i-h6-r-ccu.h b/include/dt-bindings/clock/sun50i-h6-r-ccu.h index 76136132a13e..a96087abc86f 100644 --- a/include/dt-bindings/clock/sun50i-h6-r-ccu.h +++ b/include/dt-bindings/clock/sun50i-h6-r-ccu.h @@ -21,4 +21,7 @@ #define CLK_IR 11 #define CLK_W1 12 +#define CLK_R_APB2_RSB 13 +#define CLK_R_APB1_RTC 14 + #endif /* _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ */ diff --git a/include/dt-bindings/clock/sun50i-h616-ccu.h b/include/dt-bindings/clock/sun50i-h616-ccu.h new file mode 100644 index 000000000000..1191aca53ac6 --- /dev/null +++ b/include/dt-bindings/clock/sun50i-h616-ccu.h @@ -0,0 +1,116 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* + * Copyright (C) 2020 Arm Ltd. + */ + +#ifndef _DT_BINDINGS_CLK_SUN50I_H616_H_ +#define _DT_BINDINGS_CLK_SUN50I_H616_H_ + +#define CLK_PLL_PERIPH0 4 + +#define CLK_CPUX 21 + +#define CLK_APB1 26 + +#define CLK_DE 29 +#define CLK_BUS_DE 30 +#define CLK_DEINTERLACE 31 +#define CLK_BUS_DEINTERLACE 32 +#define CLK_G2D 33 +#define CLK_BUS_G2D 34 +#define CLK_GPU0 35 +#define CLK_BUS_GPU 36 +#define CLK_GPU1 37 +#define CLK_CE 38 +#define CLK_BUS_CE 39 +#define CLK_VE 40 +#define CLK_BUS_VE 41 +#define CLK_BUS_DMA 42 +#define CLK_BUS_HSTIMER 43 +#define CLK_AVS 44 +#define CLK_BUS_DBG 45 +#define CLK_BUS_PSI 46 +#define CLK_BUS_PWM 47 +#define CLK_BUS_IOMMU 48 + +#define CLK_MBUS_DMA 50 +#define CLK_MBUS_VE 51 +#define CLK_MBUS_CE 52 +#define CLK_MBUS_TS 53 +#define CLK_MBUS_NAND 54 +#define CLK_MBUS_G2D 55 + +#define CLK_NAND0 57 +#define CLK_NAND1 58 +#define CLK_BUS_NAND 59 +#define CLK_MMC0 60 +#define CLK_MMC1 61 +#define CLK_MMC2 62 +#define CLK_BUS_MMC0 63 +#define CLK_BUS_MMC1 64 +#define CLK_BUS_MMC2 65 +#define CLK_BUS_UART0 66 +#define CLK_BUS_UART1 67 +#define CLK_BUS_UART2 68 +#define CLK_BUS_UART3 69 +#define CLK_BUS_UART4 70 +#define CLK_BUS_UART5 71 +#define CLK_BUS_I2C0 72 +#define CLK_BUS_I2C1 73 +#define CLK_BUS_I2C2 74 +#define CLK_BUS_I2C3 75 +#define CLK_BUS_I2C4 76 +#define CLK_SPI0 77 +#define CLK_SPI1 78 +#define CLK_BUS_SPI0 79 +#define CLK_BUS_SPI1 80 +#define CLK_EMAC_25M 81 +#define CLK_BUS_EMAC0 82 +#define CLK_BUS_EMAC1 83 +#define CLK_TS 84 +#define CLK_BUS_TS 85 +#define CLK_BUS_THS 86 +#define CLK_SPDIF 87 +#define CLK_BUS_SPDIF 88 +#define CLK_DMIC 89 +#define CLK_BUS_DMIC 90 +#define CLK_AUDIO_CODEC_1X 91 +#define CLK_AUDIO_CODEC_4X 92 +#define CLK_BUS_AUDIO_CODEC 93 +#define CLK_AUDIO_HUB 94 +#define CLK_BUS_AUDIO_HUB 95 +#define CLK_USB_OHCI0 96 +#define CLK_USB_PHY0 97 +#define CLK_USB_OHCI1 98 +#define CLK_USB_PHY1 99 +#define CLK_USB_OHCI2 100 +#define CLK_USB_PHY2 101 +#define CLK_USB_OHCI3 102 +#define CLK_USB_PHY3 103 +#define CLK_BUS_OHCI0 104 +#define CLK_BUS_OHCI1 105 +#define CLK_BUS_OHCI2 106 +#define CLK_BUS_OHCI3 107 +#define CLK_BUS_EHCI0 108 +#define CLK_BUS_EHCI1 109 +#define CLK_BUS_EHCI2 110 +#define CLK_BUS_EHCI3 111 +#define CLK_BUS_OTG 112 +#define CLK_BUS_KEYADC 113 +#define CLK_HDMI 114 +#define CLK_HDMI_SLOW 115 +#define CLK_HDMI_CEC 116 +#define CLK_BUS_HDMI 117 +#define CLK_BUS_TCON_TOP 118 +#define CLK_TCON_TV0 119 +#define CLK_TCON_TV1 120 +#define CLK_BUS_TCON_TV0 121 +#define CLK_BUS_TCON_TV1 122 +#define CLK_TVE0 123 +#define CLK_BUS_TVE_TOP 124 +#define CLK_BUS_TVE0 125 +#define CLK_HDCP 126 +#define CLK_BUS_HDCP 127 +#define CLK_PLL_SYSTEM_32K 128 + +#endif /* _DT_BINDINGS_CLK_SUN50I_H616_H_ */ diff --git a/include/dt-bindings/clock/sun6i-rtc.h b/include/dt-bindings/clock/sun6i-rtc.h new file mode 100644 index 000000000000..c845493e4d37 --- /dev/null +++ b/include/dt-bindings/clock/sun6i-rtc.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ + +#ifndef _DT_BINDINGS_CLK_SUN6I_RTC_H_ +#define _DT_BINDINGS_CLK_SUN6I_RTC_H_ + +#define CLK_OSC32K 0 +#define CLK_OSC32K_FANOUT 1 +#define CLK_IOSC 2 + +#endif /* _DT_BINDINGS_CLK_SUN6I_RTC_H_ */ diff --git a/include/dt-bindings/clock/sun8i-h3-ccu.h b/include/dt-bindings/clock/sun8i-h3-ccu.h index 30d2d15373a2..5d4ada2c22e6 100644 --- a/include/dt-bindings/clock/sun8i-h3-ccu.h +++ b/include/dt-bindings/clock/sun8i-h3-ccu.h @@ -126,7 +126,7 @@ #define CLK_USB_OHCI1 93 #define CLK_USB_OHCI2 94 #define CLK_USB_OHCI3 95 - +#define CLK_DRAM 96 #define CLK_DRAM_VE 97 #define CLK_DRAM_CSI 98 #define CLK_DRAM_DEINTERLACE 99 diff --git a/include/dt-bindings/clock/sunplus,sp7021-clkc.h b/include/dt-bindings/clock/sunplus,sp7021-clkc.h new file mode 100644 index 000000000000..cd84321eb2b5 --- /dev/null +++ b/include/dt-bindings/clock/sunplus,sp7021-clkc.h @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) Sunplus Technology Co., Ltd. + * All rights reserved. + */ +#ifndef _DT_BINDINGS_CLOCK_SUNPLUS_SP7021_H +#define _DT_BINDINGS_CLOCK_SUNPLUS_SP7021_H + +/* gates */ +#define CLK_RTC 0 +#define CLK_OTPRX 1 +#define CLK_NOC 2 +#define CLK_BR 3 +#define CLK_SPIFL 4 +#define CLK_PERI0 5 +#define CLK_PERI1 6 +#define CLK_STC0 7 +#define CLK_STC_AV0 8 +#define CLK_STC_AV1 9 +#define CLK_STC_AV2 10 +#define CLK_UA0 11 +#define CLK_UA1 12 +#define CLK_UA2 13 +#define CLK_UA3 14 +#define CLK_UA4 15 +#define CLK_HWUA 16 +#define CLK_DDC0 17 +#define CLK_UADMA 18 +#define CLK_CBDMA0 19 +#define CLK_CBDMA1 20 +#define CLK_SPI_COMBO_0 21 +#define CLK_SPI_COMBO_1 22 +#define CLK_SPI_COMBO_2 23 +#define CLK_SPI_COMBO_3 24 +#define CLK_AUD 25 +#define CLK_USBC0 26 +#define CLK_USBC1 27 +#define CLK_UPHY0 28 +#define CLK_UPHY1 29 +#define CLK_I2CM0 30 +#define CLK_I2CM1 31 +#define CLK_I2CM2 32 +#define CLK_I2CM3 33 +#define CLK_PMC 34 +#define CLK_CARD_CTL0 35 +#define CLK_CARD_CTL1 36 +#define CLK_CARD_CTL4 37 +#define CLK_BCH 38 +#define CLK_DDFCH 39 +#define CLK_CSIIW0 40 +#define CLK_CSIIW1 41 +#define CLK_MIPICSI0 42 +#define CLK_MIPICSI1 43 +#define CLK_HDMI_TX 44 +#define CLK_VPOST 45 +#define CLK_TGEN 46 +#define CLK_DMIX 47 +#define CLK_TCON 48 +#define CLK_GPIO 49 +#define CLK_MAILBOX 50 +#define CLK_SPIND 51 +#define CLK_I2C2CBUS 52 +#define CLK_SEC 53 +#define CLK_DVE 54 +#define CLK_GPOST0 55 +#define CLK_OSD0 56 +#define CLK_DISP_PWM 57 +#define CLK_UADBG 58 +#define CLK_FIO_CTL 59 +#define CLK_FPGA 60 +#define CLK_L2SW 61 +#define CLK_ICM 62 +#define CLK_AXI_GLOBAL 63 + +/* plls */ +#define PLL_A 64 +#define PLL_E 65 +#define PLL_E_2P5 66 +#define PLL_E_25 67 +#define PLL_E_112P5 68 +#define PLL_F 69 +#define PLL_TV 70 +#define PLL_TV_A 71 +#define PLL_SYS 72 + +#define CLK_MAX 73 + +#endif diff --git a/include/dt-bindings/clock/tegra114-car.h b/include/dt-bindings/clock/tegra114-car.h index bb5c2c999c05..a93426f008ac 100644 --- a/include/dt-bindings/clock/tegra114-car.h +++ b/include/dt-bindings/clock/tegra114-car.h @@ -228,6 +228,8 @@ #define TEGRA114_CLK_CLK_M 201 #define TEGRA114_CLK_CLK_M_DIV2 202 #define TEGRA114_CLK_CLK_M_DIV4 203 +#define TEGRA114_CLK_OSC_DIV2 202 +#define TEGRA114_CLK_OSC_DIV4 203 #define TEGRA114_CLK_PLL_REF 204 #define TEGRA114_CLK_PLL_C 205 #define TEGRA114_CLK_PLL_C_OUT1 206 @@ -270,11 +272,11 @@ #define TEGRA114_CLK_AUDIO3 242 #define TEGRA114_CLK_AUDIO4 243 #define TEGRA114_CLK_SPDIF 244 -#define TEGRA114_CLK_CLK_OUT_1 245 -#define TEGRA114_CLK_CLK_OUT_2 246 -#define TEGRA114_CLK_CLK_OUT_3 247 -#define TEGRA114_CLK_BLINK 248 -/* 249 */ +/* 245 */ +/* 246 */ +/* 247 */ +/* 248 */ +#define TEGRA114_CLK_OSC 249 /* 250 */ /* 251 */ #define TEGRA114_CLK_XUSB_HOST_SRC 252 @@ -333,9 +335,9 @@ #define TEGRA114_CLK_AUDIO3_MUX 303 #define TEGRA114_CLK_AUDIO4_MUX 304 #define TEGRA114_CLK_SPDIF_MUX 305 -#define TEGRA114_CLK_CLK_OUT_1_MUX 306 -#define TEGRA114_CLK_CLK_OUT_2_MUX 307 -#define TEGRA114_CLK_CLK_OUT_3_MUX 308 +/* 306 */ +/* 307 */ +/* 308 */ #define TEGRA114_CLK_DSIA_MUX 309 #define TEGRA114_CLK_DSIB_MUX 310 #define TEGRA114_CLK_XUSB_SS_DIV2 311 diff --git a/include/dt-bindings/clock/tegra124-car-common.h b/include/dt-bindings/clock/tegra124-car-common.h index 0c4f5be0a742..c59f9de01b4d 100644 --- a/include/dt-bindings/clock/tegra124-car-common.h +++ b/include/dt-bindings/clock/tegra124-car-common.h @@ -227,6 +227,8 @@ #define TEGRA124_CLK_CLK_M 201 #define TEGRA124_CLK_CLK_M_DIV2 202 #define TEGRA124_CLK_CLK_M_DIV4 203 +#define TEGRA124_CLK_OSC_DIV2 202 +#define TEGRA124_CLK_OSC_DIV4 203 #define TEGRA124_CLK_PLL_REF 204 #define TEGRA124_CLK_PLL_C 205 #define TEGRA124_CLK_PLL_C_OUT1 206 @@ -269,11 +271,11 @@ #define TEGRA124_CLK_AUDIO3 242 #define TEGRA124_CLK_AUDIO4 243 #define TEGRA124_CLK_SPDIF 244 -#define TEGRA124_CLK_CLK_OUT_1 245 -#define TEGRA124_CLK_CLK_OUT_2 246 -#define TEGRA124_CLK_CLK_OUT_3 247 -#define TEGRA124_CLK_BLINK 248 -/* 249 */ +/* 245 */ +/* 246 */ +/* 247 */ +/* 248 */ +#define TEGRA124_CLK_OSC 249 /* 250 */ /* 251 */ #define TEGRA124_CLK_XUSB_HOST_SRC 252 @@ -332,9 +334,9 @@ #define TEGRA124_CLK_AUDIO3_MUX 303 #define TEGRA124_CLK_AUDIO4_MUX 304 #define TEGRA124_CLK_SPDIF_MUX 305 -#define TEGRA124_CLK_CLK_OUT_1_MUX 306 -#define TEGRA124_CLK_CLK_OUT_2_MUX 307 -#define TEGRA124_CLK_CLK_OUT_3_MUX 308 +/* 306 */ +/* 307 */ +/* 308 */ /* 309 */ /* 310 */ #define TEGRA124_CLK_SOR0_LVDS 311 /* deprecated */ diff --git a/include/dt-bindings/clock/tegra20-car.h b/include/dt-bindings/clock/tegra20-car.h index b21a0eb32921..fe541f627965 100644 --- a/include/dt-bindings/clock/tegra20-car.h +++ b/include/dt-bindings/clock/tegra20-car.h @@ -131,7 +131,7 @@ #define TEGRA20_CLK_CCLK 108 #define TEGRA20_CLK_HCLK 109 #define TEGRA20_CLK_PCLK 110 -#define TEGRA20_CLK_BLINK 111 +/* 111 */ #define TEGRA20_CLK_PLL_A 112 #define TEGRA20_CLK_PLL_A_OUT0 113 #define TEGRA20_CLK_PLL_C 114 diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h index 44f60623f99b..9cfcc3baa52c 100644 --- a/include/dt-bindings/clock/tegra210-car.h +++ b/include/dt-bindings/clock/tegra210-car.h @@ -262,6 +262,8 @@ #define TEGRA210_CLK_CLK_M 233 #define TEGRA210_CLK_CLK_M_DIV2 234 #define TEGRA210_CLK_CLK_M_DIV4 235 +#define TEGRA210_CLK_OSC_DIV2 234 +#define TEGRA210_CLK_OSC_DIV4 235 #define TEGRA210_CLK_PLL_REF 236 #define TEGRA210_CLK_PLL_C 237 #define TEGRA210_CLK_PLL_C_OUT1 238 @@ -304,10 +306,10 @@ #define TEGRA210_CLK_AUDIO3 274 #define TEGRA210_CLK_AUDIO4 275 #define TEGRA210_CLK_SPDIF 276 -#define TEGRA210_CLK_CLK_OUT_1 277 -#define TEGRA210_CLK_CLK_OUT_2 278 -#define TEGRA210_CLK_CLK_OUT_3 279 -#define TEGRA210_CLK_BLINK 280 +/* 277 */ +#define TEGRA210_CLK_QSPI_PM 278 +/* 279 */ +/* 280 */ #define TEGRA210_CLK_SOR0_LVDS 281 /* deprecated */ #define TEGRA210_CLK_SOR0_OUT 281 #define TEGRA210_CLK_SOR1_OUT 282 @@ -349,14 +351,14 @@ #define TEGRA210_CLK_PLL_P_OUT_XUSB 317 #define TEGRA210_CLK_XUSB_SSP_SRC 318 #define TEGRA210_CLK_PLL_RE_OUT1 319 -/* 320 */ -/* 321 */ +#define TEGRA210_CLK_PLL_MB_UD 320 +#define TEGRA210_CLK_PLL_P_UD 321 #define TEGRA210_CLK_ISP 322 #define TEGRA210_CLK_PLL_A_OUT_ADSP 323 #define TEGRA210_CLK_PLL_A_OUT0_OUT_ADSP 324 /* 325 */ -/* 326 */ -/* 327 */ +#define TEGRA210_CLK_OSC 326 +#define TEGRA210_CLK_CSI_TPG 327 /* 328 */ /* 329 */ /* 330 */ @@ -386,9 +388,9 @@ #define TEGRA210_CLK_AUDIO3_MUX 353 #define TEGRA210_CLK_AUDIO4_MUX 354 #define TEGRA210_CLK_SPDIF_MUX 355 -#define TEGRA210_CLK_CLK_OUT_1_MUX 356 -#define TEGRA210_CLK_CLK_OUT_2_MUX 357 -#define TEGRA210_CLK_CLK_OUT_3_MUX 358 +/* 356 */ +/* 357 */ +/* 358 */ #define TEGRA210_CLK_DSIA_MUX 359 #define TEGRA210_CLK_DSIB_MUX 360 /* 361 */ diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h new file mode 100644 index 000000000000..173364a93381 --- /dev/null +++ b/include/dt-bindings/clock/tegra234-clock.h @@ -0,0 +1,278 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */ + +#ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H +#define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H + +/** + * @file + * @defgroup bpmp_clock_ids Clock ID's + * @{ + */ +/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AHUB */ +#define TEGRA234_CLK_AHUB 4U +/** @brief output of gate CLK_ENB_APB2APE */ +#define TEGRA234_CLK_APB2APE 5U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_APE */ +#define TEGRA234_CLK_APE 6U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK */ +#define TEGRA234_CLK_AUD_MCLK 7U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1 */ +#define TEGRA234_CLK_DMIC1 15U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2 */ +#define TEGRA234_CLK_DMIC2 16U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3 */ +#define TEGRA234_CLK_DMIC3 17U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4 */ +#define TEGRA234_CLK_DMIC4 18U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1 */ +#define TEGRA234_CLK_DSPK1 29U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2 */ +#define TEGRA234_CLK_DSPK2 30U +/** + * @brief controls the EMC clock frequency. + * @details Doing a clk_set_rate on this clock will select the + * appropriate clock source, program the source rate and execute a + * specific sequence to switch to the new clock source for both memory + * controllers. This can be used to control the balance between memory + * throughput and memory controller power. + */ +#define TEGRA234_CLK_EMC 31U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X */ +#define TEGRA234_CLK_HOST1X 46U +/** @brief output of gate CLK_ENB_FUSE */ +#define TEGRA234_CLK_FUSE 40U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 */ +#define TEGRA234_CLK_I2C1 48U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */ +#define TEGRA234_CLK_I2C2 49U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */ +#define TEGRA234_CLK_I2C3 50U +/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */ +#define TEGRA234_CLK_I2C4 51U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */ +#define TEGRA234_CLK_I2C6 52U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */ +#define TEGRA234_CLK_I2C7 53U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */ +#define TEGRA234_CLK_I2C8 54U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */ +#define TEGRA234_CLK_I2C9 55U +/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S1 */ +#define TEGRA234_CLK_I2S1 56U +/** @brief clock recovered from I2S1 input */ +#define TEGRA234_CLK_I2S1_SYNC_INPUT 57U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 */ +#define TEGRA234_CLK_I2S2 58U +/** @brief clock recovered from I2S2 input */ +#define TEGRA234_CLK_I2S2_SYNC_INPUT 59U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S3 */ +#define TEGRA234_CLK_I2S3 60U +/** @brief clock recovered from I2S3 input */ +#define TEGRA234_CLK_I2S3_SYNC_INPUT 61U +/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S4 */ +#define TEGRA234_CLK_I2S4 62U +/** @brief clock recovered from I2S4 input */ +#define TEGRA234_CLK_I2S4_SYNC_INPUT 63U +/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S5 */ +#define TEGRA234_CLK_I2S5 64U +/** @brief clock recovered from I2S5 input */ +#define TEGRA234_CLK_I2S5_SYNC_INPUT 65U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S6 */ +#define TEGRA234_CLK_I2S6 66U +/** @brief clock recovered from I2S6 input */ +#define TEGRA234_CLK_I2S6_SYNC_INPUT 67U +/** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */ +#define TEGRA234_CLK_PLLA 93U +/** @brief PLLP clk output */ +#define TEGRA234_CLK_PLLP_OUT0 102U +/** @brief output of the divider CLK_RST_CONTROLLER_PLLA_OUT */ +#define TEGRA234_CLK_PLLA_OUT0 104U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */ +#define TEGRA234_CLK_PWM1 105U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */ +#define TEGRA234_CLK_PWM2 106U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM3 */ +#define TEGRA234_CLK_PWM3 107U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM4 */ +#define TEGRA234_CLK_PWM4 108U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM5 */ +#define TEGRA234_CLK_PWM5 109U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM6 */ +#define TEGRA234_CLK_PWM6 110U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM7 */ +#define TEGRA234_CLK_PWM7 111U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */ +#define TEGRA234_CLK_PWM8 112U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */ +#define TEGRA234_CLK_SDMMC4 123U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1 */ +#define TEGRA234_CLK_SYNC_DMIC1 139U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2 */ +#define TEGRA234_CLK_SYNC_DMIC2 140U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3 */ +#define TEGRA234_CLK_SYNC_DMIC3 141U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4 */ +#define TEGRA234_CLK_SYNC_DMIC4 142U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1 */ +#define TEGRA234_CLK_SYNC_DSPK1 143U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2 */ +#define TEGRA234_CLK_SYNC_DSPK2 144U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1 */ +#define TEGRA234_CLK_SYNC_I2S1 145U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2 */ +#define TEGRA234_CLK_SYNC_I2S2 146U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3 */ +#define TEGRA234_CLK_SYNC_I2S3 147U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4 */ +#define TEGRA234_CLK_SYNC_I2S4 148U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5 */ +#define TEGRA234_CLK_SYNC_I2S5 149U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6 */ +#define TEGRA234_CLK_SYNC_I2S6 150U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */ +#define TEGRA234_CLK_UARTA 155U +/** @brief output of gate CLK_ENB_PEX1_CORE_6 */ +#define TEGRA234_CLK_PEX1_C6_CORE 161U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VIC */ +#define TEGRA234_CLK_VIC 167U +/** @brief output of gate CLK_ENB_PEX2_CORE_7 */ +#define TEGRA234_CLK_PEX2_C7_CORE 171U +/** @brief output of gate CLK_ENB_PEX2_CORE_8 */ +#define TEGRA234_CLK_PEX2_C8_CORE 172U +/** @brief output of gate CLK_ENB_PEX2_CORE_9 */ +#define TEGRA234_CLK_PEX2_C9_CORE 173U +/** @brief output of gate CLK_ENB_PEX2_CORE_10 */ +#define TEGRA234_CLK_PEX2_C10_CORE 187U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0 switch divider output */ +#define TEGRA234_CLK_QSPI0_2X_PM 192U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1 switch divider output */ +#define TEGRA234_CLK_QSPI1_2X_PM 193U +/** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0 */ +#define TEGRA234_CLK_QSPI0_PM 194U +/** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1 */ +#define TEGRA234_CLK_QSPI1_PM 195U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM switch divider output */ +#define TEGRA234_CLK_SDMMC_LEGACY_TM 219U +/** @brief output of gate CLK_ENB_PEX0_CORE_0 */ +#define TEGRA234_CLK_PEX0_C0_CORE 220U +/** @brief output of gate CLK_ENB_PEX0_CORE_1 */ +#define TEGRA234_CLK_PEX0_C1_CORE 221U +/** @brief output of gate CLK_ENB_PEX0_CORE_2 */ +#define TEGRA234_CLK_PEX0_C2_CORE 222U +/** @brief output of gate CLK_ENB_PEX0_CORE_3 */ +#define TEGRA234_CLK_PEX0_C3_CORE 223U +/** @brief output of gate CLK_ENB_PEX0_CORE_4 */ +#define TEGRA234_CLK_PEX0_C4_CORE 224U +/** @brief output of gate CLK_ENB_PEX1_CORE_5 */ +#define TEGRA234_CLK_PEX1_C5_CORE 225U +/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */ +#define TEGRA234_CLK_PLLC4 237U +/** @brief RX clock recovered from MGBE0 lane input */ +#define TEGRA234_CLK_MGBE0_RX_INPUT 248U +/** @brief RX clock recovered from MGBE1 lane input */ +#define TEGRA234_CLK_MGBE1_RX_INPUT 249U +/** @brief RX clock recovered from MGBE2 lane input */ +#define TEGRA234_CLK_MGBE2_RX_INPUT 250U +/** @brief RX clock recovered from MGBE3 lane input */ +#define TEGRA234_CLK_MGBE3_RX_INPUT 251U +/** @brief 32K input clock provided by PMIC */ +#define TEGRA234_CLK_CLK_32K 289U +/** @brief Monitored branch of MBGE0 RX input clock */ +#define TEGRA234_CLK_MGBE0_RX_INPUT_M 357U +/** @brief Monitored branch of MBGE1 RX input clock */ +#define TEGRA234_CLK_MGBE1_RX_INPUT_M 358U +/** @brief Monitored branch of MBGE2 RX input clock */ +#define TEGRA234_CLK_MGBE2_RX_INPUT_M 359U +/** @brief Monitored branch of MBGE3 RX input clock */ +#define TEGRA234_CLK_MGBE3_RX_INPUT_M 360U +/** @brief Monitored branch of MGBE0 RX PCS mux output */ +#define TEGRA234_CLK_MGBE0_RX_PCS_M 361U +/** @brief Monitored branch of MGBE1 RX PCS mux output */ +#define TEGRA234_CLK_MGBE1_RX_PCS_M 362U +/** @brief Monitored branch of MGBE2 RX PCS mux output */ +#define TEGRA234_CLK_MGBE2_RX_PCS_M 363U +/** @brief Monitored branch of MGBE3 RX PCS mux output */ +#define TEGRA234_CLK_MGBE3_RX_PCS_M 364U +/** @brief RX PCS clock recovered from MGBE0 lane input */ +#define TEGRA234_CLK_MGBE0_RX_PCS_INPUT 369U +/** @brief RX PCS clock recovered from MGBE1 lane input */ +#define TEGRA234_CLK_MGBE1_RX_PCS_INPUT 370U +/** @brief RX PCS clock recovered from MGBE2 lane input */ +#define TEGRA234_CLK_MGBE2_RX_PCS_INPUT 371U +/** @brief RX PCS clock recovered from MGBE3 lane input */ +#define TEGRA234_CLK_MGBE3_RX_PCS_INPUT 372U +/** @brief output of mux controlled by GBE_UPHY_MGBE0_RX_PCS_CLK_SRC_SEL */ +#define TEGRA234_CLK_MGBE0_RX_PCS 373U +/** @brief GBE_UPHY_MGBE0_TX_CLK divider gated output */ +#define TEGRA234_CLK_MGBE0_TX 374U +/** @brief GBE_UPHY_MGBE0_TX_PCS_CLK divider gated output */ +#define TEGRA234_CLK_MGBE0_TX_PCS 375U +/** @brief GBE_UPHY_MGBE0_MAC_CLK divider output */ +#define TEGRA234_CLK_MGBE0_MAC_DIVIDER 376U +/** @brief GBE_UPHY_MGBE0_MAC_CLK gate output */ +#define TEGRA234_CLK_MGBE0_MAC 377U +/** @brief GBE_UPHY_MGBE0_MACSEC_CLK gate output */ +#define TEGRA234_CLK_MGBE0_MACSEC 378U +/** @brief GBE_UPHY_MGBE0_EEE_PCS_CLK gate output */ +#define TEGRA234_CLK_MGBE0_EEE_PCS 379U +/** @brief GBE_UPHY_MGBE0_APP_CLK gate output */ +#define TEGRA234_CLK_MGBE0_APP 380U +/** @brief GBE_UPHY_MGBE0_PTP_REF_CLK divider gated output */ +#define TEGRA234_CLK_MGBE0_PTP_REF 381U +/** @brief output of mux controlled by GBE_UPHY_MGBE1_RX_PCS_CLK_SRC_SEL */ +#define TEGRA234_CLK_MGBE1_RX_PCS 382U +/** @brief GBE_UPHY_MGBE1_TX_CLK divider gated output */ +#define TEGRA234_CLK_MGBE1_TX 383U +/** @brief GBE_UPHY_MGBE1_TX_PCS_CLK divider gated output */ +#define TEGRA234_CLK_MGBE1_TX_PCS 384U +/** @brief GBE_UPHY_MGBE1_MAC_CLK divider output */ +#define TEGRA234_CLK_MGBE1_MAC_DIVIDER 385U +/** @brief GBE_UPHY_MGBE1_MAC_CLK gate output */ +#define TEGRA234_CLK_MGBE1_MAC 386U +/** @brief GBE_UPHY_MGBE1_EEE_PCS_CLK gate output */ +#define TEGRA234_CLK_MGBE1_EEE_PCS 388U +/** @brief GBE_UPHY_MGBE1_APP_CLK gate output */ +#define TEGRA234_CLK_MGBE1_APP 389U +/** @brief GBE_UPHY_MGBE1_PTP_REF_CLK divider gated output */ +#define TEGRA234_CLK_MGBE1_PTP_REF 390U +/** @brief output of mux controlled by GBE_UPHY_MGBE2_RX_PCS_CLK_SRC_SEL */ +#define TEGRA234_CLK_MGBE2_RX_PCS 391U +/** @brief GBE_UPHY_MGBE2_TX_CLK divider gated output */ +#define TEGRA234_CLK_MGBE2_TX 392U +/** @brief GBE_UPHY_MGBE2_TX_PCS_CLK divider gated output */ +#define TEGRA234_CLK_MGBE2_TX_PCS 393U +/** @brief GBE_UPHY_MGBE2_MAC_CLK divider output */ +#define TEGRA234_CLK_MGBE2_MAC_DIVIDER 394U +/** @brief GBE_UPHY_MGBE2_MAC_CLK gate output */ +#define TEGRA234_CLK_MGBE2_MAC 395U +/** @brief GBE_UPHY_MGBE2_EEE_PCS_CLK gate output */ +#define TEGRA234_CLK_MGBE2_EEE_PCS 397U +/** @brief GBE_UPHY_MGBE2_APP_CLK gate output */ +#define TEGRA234_CLK_MGBE2_APP 398U +/** @brief GBE_UPHY_MGBE2_PTP_REF_CLK divider gated output */ +#define TEGRA234_CLK_MGBE2_PTP_REF 399U +/** @brief output of mux controlled by GBE_UPHY_MGBE3_RX_PCS_CLK_SRC_SEL */ +#define TEGRA234_CLK_MGBE3_RX_PCS 400U +/** @brief GBE_UPHY_MGBE3_TX_CLK divider gated output */ +#define TEGRA234_CLK_MGBE3_TX 401U +/** @brief GBE_UPHY_MGBE3_TX_PCS_CLK divider gated output */ +#define TEGRA234_CLK_MGBE3_TX_PCS 402U +/** @brief GBE_UPHY_MGBE3_MAC_CLK divider output */ +#define TEGRA234_CLK_MGBE3_MAC_DIVIDER 403U +/** @brief GBE_UPHY_MGBE3_MAC_CLK gate output */ +#define TEGRA234_CLK_MGBE3_MAC 404U +/** @brief GBE_UPHY_MGBE3_MACSEC_CLK gate output */ +#define TEGRA234_CLK_MGBE3_MACSEC 405U +/** @brief GBE_UPHY_MGBE3_EEE_PCS_CLK gate output */ +#define TEGRA234_CLK_MGBE3_EEE_PCS 406U +/** @brief GBE_UPHY_MGBE3_APP_CLK gate output */ +#define TEGRA234_CLK_MGBE3_APP 407U +/** @brief GBE_UPHY_MGBE3_PTP_REF_CLK divider gated output */ +#define TEGRA234_CLK_MGBE3_PTP_REF 408U +/** @brief CLK_RST_CONTROLLER_AZA2XBITCLK_OUT_SWITCH_DIVIDER switch divider output (aza_2xbitclk) */ +#define TEGRA234_CLK_AZA_2XBIT 457U +/** @brief aza_2xbitclk / 2 (aza_bitclk) */ +#define TEGRA234_CLK_AZA_BIT 458U + +#endif diff --git a/include/dt-bindings/clock/tegra30-car.h b/include/dt-bindings/clock/tegra30-car.h index 3c90f1535551..f193663e6f28 100644 --- a/include/dt-bindings/clock/tegra30-car.h +++ b/include/dt-bindings/clock/tegra30-car.h @@ -196,6 +196,8 @@ #define TEGRA30_CLK_CLK_M 171 #define TEGRA30_CLK_CLK_M_DIV2 172 #define TEGRA30_CLK_CLK_M_DIV4 173 +#define TEGRA30_CLK_OSC_DIV2 172 +#define TEGRA30_CLK_OSC_DIV4 173 #define TEGRA30_CLK_PLL_REF 174 #define TEGRA30_CLK_PLL_C 175 #define TEGRA30_CLK_PLL_C_OUT1 176 @@ -230,11 +232,11 @@ #define TEGRA30_CLK_AUDIO3 204 #define TEGRA30_CLK_AUDIO4 205 #define TEGRA30_CLK_SPDIF 206 -#define TEGRA30_CLK_CLK_OUT_1 207 /* (extern1) */ -#define TEGRA30_CLK_CLK_OUT_2 208 /* (extern2) */ -#define TEGRA30_CLK_CLK_OUT_3 209 /* (extern3) */ +/* 207 */ +/* 208 */ +/* 209 */ #define TEGRA30_CLK_SCLK 210 -#define TEGRA30_CLK_BLINK 211 +/* 211 */ #define TEGRA30_CLK_CCLK_G 212 #define TEGRA30_CLK_CCLK_LP 213 #define TEGRA30_CLK_TWD 214 @@ -243,7 +245,7 @@ #define TEGRA30_CLK_HCLK 217 #define TEGRA30_CLK_PCLK 218 /* 219 */ -/* 220 */ +#define TEGRA30_CLK_OSC 220 /* 221 */ /* 222 */ /* 223 */ @@ -260,9 +262,9 @@ /* 297 */ /* 298 */ /* 299 */ -#define TEGRA30_CLK_CLK_OUT_1_MUX 300 -#define TEGRA30_CLK_CLK_OUT_2_MUX 301 -#define TEGRA30_CLK_CLK_OUT_3_MUX 302 +/* 300 */ +/* 301 */ +/* 302 */ #define TEGRA30_CLK_AUDIO0_MUX 303 #define TEGRA30_CLK_AUDIO1_MUX 304 #define TEGRA30_CLK_AUDIO2_MUX 305 diff --git a/include/dt-bindings/clock/ti-dra7-atl.h b/include/dt-bindings/clock/ti-dra7-atl.h index 42dd4164f6f4..b0e71e3cce95 100644 --- a/include/dt-bindings/clock/ti-dra7-atl.h +++ b/include/dt-bindings/clock/ti-dra7-atl.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * This header provides constants for DRA7 ATL (Audio Tracking Logic) * @@ -6,15 +7,6 @@ * Copyright (C) 2013 Texas Instruments, Inc. * * Peter Ujfalusi <peter.ujfalusi@ti.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #ifndef _DT_BINDINGS_CLK_DRA7_ATL_H diff --git a/include/dt-bindings/clock/toshiba,tmpv770x.h b/include/dt-bindings/clock/toshiba,tmpv770x.h new file mode 100644 index 000000000000..5fce713001fd --- /dev/null +++ b/include/dt-bindings/clock/toshiba,tmpv770x.h @@ -0,0 +1,181 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLOCK_TOSHIBA_TMPV770X_H_ +#define _DT_BINDINGS_CLOCK_TOSHIBA_TMPV770X_H_ + +/* PLL */ +#define TMPV770X_PLL_PIPLL0 0 +#define TMPV770X_PLL_PIPLL1 1 +#define TMPV770X_PLL_PIDNNPLL 2 +#define TMPV770X_PLL_PIETHERPLL 3 +#define TMPV770X_PLL_PIDDRCPLL 4 +#define TMPV770X_PLL_PIVOIFPLL 5 +#define TMPV770X_PLL_PIIMGERPLL 6 +#define TMPV770X_NR_PLL 7 + +/* Clocks */ +#define TMPV770X_CLK_PIPLL1_DIV1 0 +#define TMPV770X_CLK_PIPLL1_DIV2 1 +#define TMPV770X_CLK_PIPLL1_DIV4 2 +#define TMPV770X_CLK_PIDNNPLL_DIV1 3 +#define TMPV770X_CLK_DDRC_PHY_PLL0 4 +#define TMPV770X_CLK_DDRC_PHY_PLL1 5 +#define TMPV770X_CLK_D_PHYPLL 6 +#define TMPV770X_CLK_PHY_PCIEPLL 7 +#define TMPV770X_CLK_CA53CL0 8 +#define TMPV770X_CLK_CA53CL1 9 +#define TMPV770X_CLK_PISDMAC 10 +#define TMPV770X_CLK_PIPDMAC0 11 +#define TMPV770X_CLK_PIPDMAC1 12 +#define TMPV770X_CLK_PIWRAM 13 +#define TMPV770X_CLK_DDRC0 14 +#define TMPV770X_CLK_DDRC0_SCLK 15 +#define TMPV770X_CLK_DDRC0_NCLK 16 +#define TMPV770X_CLK_DDRC0_MCLK 17 +#define TMPV770X_CLK_DDRC0_APBCLK 18 +#define TMPV770X_CLK_DDRC1 19 +#define TMPV770X_CLK_DDRC1_SCLK 20 +#define TMPV770X_CLK_DDRC1_NCLK 21 +#define TMPV770X_CLK_DDRC1_MCLK 22 +#define TMPV770X_CLK_DDRC1_APBCLK 23 +#define TMPV770X_CLK_HOX 24 +#define TMPV770X_CLK_PCIE_MSTR 25 +#define TMPV770X_CLK_PCIE_AUX 26 +#define TMPV770X_CLK_PIINTC 27 +#define TMPV770X_CLK_PIETHER_BUS 28 +#define TMPV770X_CLK_PISPI0 29 +#define TMPV770X_CLK_PISPI1 30 +#define TMPV770X_CLK_PISPI2 31 +#define TMPV770X_CLK_PISPI3 32 +#define TMPV770X_CLK_PISPI4 33 +#define TMPV770X_CLK_PISPI5 34 +#define TMPV770X_CLK_PISPI6 35 +#define TMPV770X_CLK_PIUART0 36 +#define TMPV770X_CLK_PIUART1 37 +#define TMPV770X_CLK_PIUART2 38 +#define TMPV770X_CLK_PIUART3 39 +#define TMPV770X_CLK_PII2C0 40 +#define TMPV770X_CLK_PII2C1 41 +#define TMPV770X_CLK_PII2C2 42 +#define TMPV770X_CLK_PII2C3 43 +#define TMPV770X_CLK_PII2C4 44 +#define TMPV770X_CLK_PII2C5 45 +#define TMPV770X_CLK_PII2C6 46 +#define TMPV770X_CLK_PII2C7 47 +#define TMPV770X_CLK_PII2C8 48 +#define TMPV770X_CLK_PIGPIO 49 +#define TMPV770X_CLK_PIPGM 50 +#define TMPV770X_CLK_PIPCMIF 51 +#define TMPV770X_CLK_PIPCMIF_AUDIO_O 52 +#define TMPV770X_CLK_PIPCMIF_AUDIO_I 53 +#define TMPV770X_CLK_PICMPT0 54 +#define TMPV770X_CLK_PICMPT1 55 +#define TMPV770X_CLK_PITSC 56 +#define TMPV770X_CLK_PIUWDT 57 +#define TMPV770X_CLK_PISWDT 58 +#define TMPV770X_CLK_WDTCLK 59 +#define TMPV770X_CLK_PISUBUS_150M 60 +#define TMPV770X_CLK_PISUBUS_300M 61 +#define TMPV770X_CLK_PIPMU 62 +#define TMPV770X_CLK_PIGPMU 63 +#define TMPV770X_CLK_PITMU 64 +#define TMPV770X_CLK_WRCK 65 +#define TMPV770X_CLK_PIEMM 66 +#define TMPV770X_CLK_PIMISC 67 +#define TMPV770X_CLK_PIGCOMM 68 +#define TMPV770X_CLK_PIDCOMM 69 +#define TMPV770X_CLK_PICKMON 70 +#define TMPV770X_CLK_PIMBUS 71 +#define TMPV770X_CLK_SBUSCLK 72 +#define TMPV770X_CLK_DDR0_APBCLKCLK 73 +#define TMPV770X_CLK_DDR1_APBCLKCLK 74 +#define TMPV770X_CLK_DSP0_PBCLK 75 +#define TMPV770X_CLK_DSP1_PBCLK 76 +#define TMPV770X_CLK_DSP2_PBCLK 77 +#define TMPV770X_CLK_DSP3_PBCLK 78 +#define TMPV770X_CLK_DSVIIF0_APBCLK 79 +#define TMPV770X_CLK_VIIF0_APBCLK 80 +#define TMPV770X_CLK_VIIF0_CFGCLK 81 +#define TMPV770X_CLK_VIIF1_APBCLK 82 +#define TMPV770X_CLK_VIIF1_CFGCLK 83 +#define TMPV770X_CLK_VIIF2_APBCLK 84 +#define TMPV770X_CLK_VIIF2_CFGCLK 85 +#define TMPV770X_CLK_VIIF3_APBCLK 86 +#define TMPV770X_CLK_VIIF3_CFGCLK 87 +#define TMPV770X_CLK_VIIF4_APBCLK 88 +#define TMPV770X_CLK_VIIF4_CFGCLK 89 +#define TMPV770X_CLK_VIIF5_APBCLK 90 +#define TMPV770X_CLK_VIIF5_CFGCLK 91 +#define TMPV770X_CLK_VOIF_SBUSCLK 92 +#define TMPV770X_CLK_VOIF_PROCCLK 93 +#define TMPV770X_CLK_VOIF_DPHYCFGCLK 94 +#define TMPV770X_CLK_DNN0 95 +#define TMPV770X_CLK_STMAT 96 +#define TMPV770X_CLK_HWA0 97 +#define TMPV770X_CLK_AFFINE0 98 +#define TMPV770X_CLK_HAMAT 99 +#define TMPV770X_CLK_SMLDB 100 +#define TMPV770X_CLK_HWA0_ASYNC 101 +#define TMPV770X_CLK_HWA2 102 +#define TMPV770X_CLK_FLMAT 103 +#define TMPV770X_CLK_PYRAMID 104 +#define TMPV770X_CLK_HWA2_ASYNC 105 +#define TMPV770X_CLK_DSP0 106 +#define TMPV770X_CLK_VIIFBS0 107 +#define TMPV770X_CLK_VIIFBS0_L2ISP 108 +#define TMPV770X_CLK_VIIFBS0_L1ISP 109 +#define TMPV770X_CLK_VIIFBS0_PROC 110 +#define TMPV770X_CLK_VIIFBS1 111 +#define TMPV770X_CLK_VIIFBS2 112 +#define TMPV770X_CLK_VIIFOP_MBUS 113 +#define TMPV770X_CLK_VIIFOP0_PROC 114 +#define TMPV770X_CLK_PIETHER_2P5M 115 +#define TMPV770X_CLK_PIETHER_25M 116 +#define TMPV770X_CLK_PIETHER_50M 117 +#define TMPV770X_CLK_PIETHER_125M 118 +#define TMPV770X_CLK_VOIF0_DPHYCFG 119 +#define TMPV770X_CLK_VOIF0_PROC 120 +#define TMPV770X_CLK_VOIF0_SBUS 121 +#define TMPV770X_CLK_VOIF0_DSIREF 122 +#define TMPV770X_CLK_VOIF0_PIXEL 123 +#define TMPV770X_CLK_PIREFCLK 124 +#define TMPV770X_CLK_SBUS 125 +#define TMPV770X_CLK_BUSLCK 126 +#define TMPV770X_NR_CLK 127 + +/* Reset */ +#define TMPV770X_RESET_PIETHER_2P5M 0 +#define TMPV770X_RESET_PIETHER_25M 1 +#define TMPV770X_RESET_PIETHER_50M 2 +#define TMPV770X_RESET_PIETHER_125M 3 +#define TMPV770X_RESET_HOX 4 +#define TMPV770X_RESET_PCIE_MSTR 5 +#define TMPV770X_RESET_PCIE_AUX 6 +#define TMPV770X_RESET_PIINTC 7 +#define TMPV770X_RESET_PIETHER_BUS 8 +#define TMPV770X_RESET_PISPI0 9 +#define TMPV770X_RESET_PISPI1 10 +#define TMPV770X_RESET_PISPI2 11 +#define TMPV770X_RESET_PISPI3 12 +#define TMPV770X_RESET_PISPI4 13 +#define TMPV770X_RESET_PISPI5 14 +#define TMPV770X_RESET_PISPI6 15 +#define TMPV770X_RESET_PIUART0 16 +#define TMPV770X_RESET_PIUART1 17 +#define TMPV770X_RESET_PIUART2 18 +#define TMPV770X_RESET_PIUART3 19 +#define TMPV770X_RESET_PII2C0 20 +#define TMPV770X_RESET_PII2C1 21 +#define TMPV770X_RESET_PII2C2 22 +#define TMPV770X_RESET_PII2C3 23 +#define TMPV770X_RESET_PII2C4 24 +#define TMPV770X_RESET_PII2C5 25 +#define TMPV770X_RESET_PII2C6 26 +#define TMPV770X_RESET_PII2C7 27 +#define TMPV770X_RESET_PII2C8 28 +#define TMPV770X_RESET_PIPCMIF 29 +#define TMPV770X_RESET_PICKMON 30 +#define TMPV770X_RESET_SBUSCLK 31 +#define TMPV770X_NR_RESET 32 + +#endif /*_DT_BINDINGS_CLOCK_TOSHIBA_TMPV770X_H_ */ diff --git a/include/dt-bindings/clock/versaclock.h b/include/dt-bindings/clock/versaclock.h new file mode 100644 index 000000000000..c6a6a0946564 --- /dev/null +++ b/include/dt-bindings/clock/versaclock.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +/* This file defines field values used by the versaclock 6 family + * for defining output type + */ + +#define VC5_LVPECL 0 +#define VC5_CMOS 1 +#define VC5_HCSL33 2 +#define VC5_LVDS 3 +#define VC5_CMOS2 4 +#define VC5_CMOSD 5 +#define VC5_HCSL25 6 diff --git a/include/dt-bindings/clock/vf610-clock.h b/include/dt-bindings/clock/vf610-clock.h index 95394f35a74a..373644e46747 100644 --- a/include/dt-bindings/clock/vf610-clock.h +++ b/include/dt-bindings/clock/vf610-clock.h @@ -195,6 +195,8 @@ #define VF610_CLK_WKPU 186 #define VF610_CLK_TCON0 187 #define VF610_CLK_TCON1 188 -#define VF610_CLK_END 189 +#define VF610_CLK_CAAM 189 +#define VF610_CLK_CRC 190 +#define VF610_CLK_END 191 #endif /* __DT_BINDINGS_CLOCK_VF610_H */ diff --git a/include/dt-bindings/clock/x1000-cgu.h b/include/dt-bindings/clock/x1000-cgu.h deleted file mode 100644 index bbaebaf7adb9..000000000000 --- a/include/dt-bindings/clock/x1000-cgu.h +++ /dev/null @@ -1,44 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides clock numbers for the ingenic,x1000-cgu DT binding. - * - * They are roughly ordered as: - * - external clocks - * - PLLs - * - muxes/dividers in the order they appear in the x1000 programmers manual - * - gates in order of their bit in the CLKGR* registers - */ - -#ifndef __DT_BINDINGS_CLOCK_X1000_CGU_H__ -#define __DT_BINDINGS_CLOCK_X1000_CGU_H__ - -#define X1000_CLK_EXCLK 0 -#define X1000_CLK_RTCLK 1 -#define X1000_CLK_APLL 2 -#define X1000_CLK_MPLL 3 -#define X1000_CLK_SCLKA 4 -#define X1000_CLK_CPUMUX 5 -#define X1000_CLK_CPU 6 -#define X1000_CLK_L2CACHE 7 -#define X1000_CLK_AHB0 8 -#define X1000_CLK_AHB2PMUX 9 -#define X1000_CLK_AHB2 10 -#define X1000_CLK_PCLK 11 -#define X1000_CLK_DDR 12 -#define X1000_CLK_MAC 13 -#define X1000_CLK_MSCMUX 14 -#define X1000_CLK_MSC0 15 -#define X1000_CLK_MSC1 16 -#define X1000_CLK_SSIPLL 17 -#define X1000_CLK_SSIMUX 18 -#define X1000_CLK_SFC 19 -#define X1000_CLK_I2C0 20 -#define X1000_CLK_I2C1 21 -#define X1000_CLK_I2C2 22 -#define X1000_CLK_UART0 23 -#define X1000_CLK_UART1 24 -#define X1000_CLK_UART2 25 -#define X1000_CLK_SSI 26 -#define X1000_CLK_PDMA 27 - -#endif /* __DT_BINDINGS_CLOCK_X1000_CGU_H__ */ diff --git a/include/dt-bindings/clock/xlnx-vcu.h b/include/dt-bindings/clock/xlnx-vcu.h new file mode 100644 index 000000000000..1ed76b9563b6 --- /dev/null +++ b/include/dt-bindings/clock/xlnx-vcu.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 Pengutronix, Michael Tretter <kernel@pengutronix.de> + */ + +#ifndef _DT_BINDINGS_CLOCK_XLNX_VCU_H +#define _DT_BINDINGS_CLOCK_XLNX_VCU_H + +#define CLK_XVCU_ENC_CORE 0 +#define CLK_XVCU_ENC_MCU 1 +#define CLK_XVCU_DEC_CORE 2 +#define CLK_XVCU_DEC_MCU 3 +#define CLK_XVCU_NUM_CLOCKS 4 + +#endif /* _DT_BINDINGS_CLOCK_XLNX_VCU_H */ diff --git a/include/dt-bindings/clock/zx296702-clock.h b/include/dt-bindings/clock/zx296702-clock.h deleted file mode 100644 index e04126111aae..000000000000 --- a/include/dt-bindings/clock/zx296702-clock.h +++ /dev/null @@ -1,180 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2014 Linaro Ltd. - * Copyright (C) 2014 ZTE Corporation. - */ - -#ifndef __DT_BINDINGS_CLOCK_ZX296702_H -#define __DT_BINDINGS_CLOCK_ZX296702_H - -#define ZX296702_OSC 0 -#define ZX296702_PLL_A9 1 -#define ZX296702_PLL_A9_350M 2 -#define ZX296702_PLL_MAC_1000M 3 -#define ZX296702_PLL_MAC_333M 4 -#define ZX296702_PLL_MM0_1188M 5 -#define ZX296702_PLL_MM0_396M 6 -#define ZX296702_PLL_MM0_198M 7 -#define ZX296702_PLL_MM1_108M 8 -#define ZX296702_PLL_MM1_72M 9 -#define ZX296702_PLL_MM1_54M 10 -#define ZX296702_PLL_LSP_104M 11 -#define ZX296702_PLL_LSP_26M 12 -#define ZX296702_PLL_AUDIO_294M912 13 -#define ZX296702_PLL_DDR_266M 14 -#define ZX296702_CLK_148M5 15 -#define ZX296702_MATRIX_ACLK 16 -#define ZX296702_MAIN_HCLK 17 -#define ZX296702_MAIN_PCLK 18 -#define ZX296702_CLK_500 19 -#define ZX296702_CLK_250 20 -#define ZX296702_CLK_125 21 -#define ZX296702_CLK_74M25 22 -#define ZX296702_A9_WCLK 23 -#define ZX296702_A9_AS1_ACLK_MUX 24 -#define ZX296702_A9_TRACE_CLKIN_MUX 25 -#define ZX296702_A9_AS1_ACLK_DIV 26 -#define ZX296702_CLK_2 27 -#define ZX296702_CLK_27 28 -#define ZX296702_DECPPU_ACLK_MUX 29 -#define ZX296702_PPU_ACLK_MUX 30 -#define ZX296702_MALI400_ACLK_MUX 31 -#define ZX296702_VOU_ACLK_MUX 32 -#define ZX296702_VOU_MAIN_WCLK_MUX 33 -#define ZX296702_VOU_AUX_WCLK_MUX 34 -#define ZX296702_VOU_SCALER_WCLK_MUX 35 -#define ZX296702_R2D_ACLK_MUX 36 -#define ZX296702_R2D_WCLK_MUX 37 -#define ZX296702_CLK_50 38 -#define ZX296702_CLK_25 39 -#define ZX296702_CLK_12 40 -#define ZX296702_CLK_16M384 41 -#define ZX296702_CLK_32K768 42 -#define ZX296702_SEC_WCLK_DIV 43 -#define ZX296702_DDR_WCLK_MUX 44 -#define ZX296702_NAND_WCLK_MUX 45 -#define ZX296702_LSP_26_WCLK_MUX 46 -#define ZX296702_A9_AS0_ACLK 47 -#define ZX296702_A9_AS1_ACLK 48 -#define ZX296702_A9_TRACE_CLKIN 49 -#define ZX296702_DECPPU_AXI_M_ACLK 50 -#define ZX296702_DECPPU_AHB_S_HCLK 51 -#define ZX296702_PPU_AXI_M_ACLK 52 -#define ZX296702_PPU_AHB_S_HCLK 53 -#define ZX296702_VOU_AXI_M_ACLK 54 -#define ZX296702_VOU_APB_PCLK 55 -#define ZX296702_VOU_MAIN_CHANNEL_WCLK 56 -#define ZX296702_VOU_AUX_CHANNEL_WCLK 57 -#define ZX296702_VOU_HDMI_OSCLK_CEC 58 -#define ZX296702_VOU_SCALER_WCLK 59 -#define ZX296702_MALI400_AXI_M_ACLK 60 -#define ZX296702_MALI400_APB_PCLK 61 -#define ZX296702_R2D_WCLK 62 -#define ZX296702_R2D_AXI_M_ACLK 63 -#define ZX296702_R2D_AHB_HCLK 64 -#define ZX296702_DDR3_AXI_S0_ACLK 65 -#define ZX296702_DDR3_APB_PCLK 66 -#define ZX296702_DDR3_WCLK 67 -#define ZX296702_USB20_0_AHB_HCLK 68 -#define ZX296702_USB20_0_EXTREFCLK 69 -#define ZX296702_USB20_1_AHB_HCLK 70 -#define ZX296702_USB20_1_EXTREFCLK 71 -#define ZX296702_USB20_2_AHB_HCLK 72 -#define ZX296702_USB20_2_EXTREFCLK 73 -#define ZX296702_GMAC_AXI_M_ACLK 74 -#define ZX296702_GMAC_APB_PCLK 75 -#define ZX296702_GMAC_125_CLKIN 76 -#define ZX296702_GMAC_RMII_CLKIN 77 -#define ZX296702_GMAC_25M_CLK 78 -#define ZX296702_NANDFLASH_AHB_HCLK 79 -#define ZX296702_NANDFLASH_WCLK 80 -#define ZX296702_LSP0_APB_PCLK 81 -#define ZX296702_LSP0_AHB_HCLK 82 -#define ZX296702_LSP0_26M_WCLK 83 -#define ZX296702_LSP0_104M_WCLK 84 -#define ZX296702_LSP0_16M384_WCLK 85 -#define ZX296702_LSP1_APB_PCLK 86 -#define ZX296702_LSP1_26M_WCLK 87 -#define ZX296702_LSP1_104M_WCLK 88 -#define ZX296702_LSP1_32K_CLK 89 -#define ZX296702_AON_HCLK 90 -#define ZX296702_SYS_CTRL_PCLK 91 -#define ZX296702_DMA_PCLK 92 -#define ZX296702_DMA_ACLK 93 -#define ZX296702_SEC_HCLK 94 -#define ZX296702_AES_WCLK 95 -#define ZX296702_DES_WCLK 96 -#define ZX296702_IRAM_ACLK 97 -#define ZX296702_IROM_ACLK 98 -#define ZX296702_BOOT_CTRL_HCLK 99 -#define ZX296702_EFUSE_CLK_30 100 -#define ZX296702_VOU_MAIN_CHANNEL_DIV 101 -#define ZX296702_VOU_AUX_CHANNEL_DIV 102 -#define ZX296702_VOU_TV_ENC_HD_DIV 103 -#define ZX296702_VOU_TV_ENC_SD_DIV 104 -#define ZX296702_VL0_MUX 105 -#define ZX296702_VL1_MUX 106 -#define ZX296702_VL2_MUX 107 -#define ZX296702_GL0_MUX 108 -#define ZX296702_GL1_MUX 109 -#define ZX296702_GL2_MUX 110 -#define ZX296702_WB_MUX 111 -#define ZX296702_HDMI_MUX 112 -#define ZX296702_VOU_TV_ENC_HD_MUX 113 -#define ZX296702_VOU_TV_ENC_SD_MUX 114 -#define ZX296702_VL0_CLK 115 -#define ZX296702_VL1_CLK 116 -#define ZX296702_VL2_CLK 117 -#define ZX296702_GL0_CLK 118 -#define ZX296702_GL1_CLK 119 -#define ZX296702_GL2_CLK 120 -#define ZX296702_WB_CLK 121 -#define ZX296702_CL_CLK 122 -#define ZX296702_MAIN_MIX_CLK 123 -#define ZX296702_AUX_MIX_CLK 124 -#define ZX296702_HDMI_CLK 125 -#define ZX296702_VOU_TV_ENC_HD_DAC_CLK 126 -#define ZX296702_VOU_TV_ENC_SD_DAC_CLK 127 -#define ZX296702_A9_PERIPHCLK 128 -#define ZX296702_TOPCLK_END 129 - -#define ZX296702_SDMMC1_WCLK_MUX 0 -#define ZX296702_SDMMC1_WCLK_DIV 1 -#define ZX296702_SDMMC1_WCLK 2 -#define ZX296702_SDMMC1_PCLK 3 -#define ZX296702_SPDIF0_WCLK_MUX 4 -#define ZX296702_SPDIF0_WCLK 5 -#define ZX296702_SPDIF0_PCLK 6 -#define ZX296702_SPDIF0_DIV 7 -#define ZX296702_I2S0_WCLK_MUX 8 -#define ZX296702_I2S0_WCLK 9 -#define ZX296702_I2S0_PCLK 10 -#define ZX296702_I2S0_DIV 11 -#define ZX296702_I2S1_WCLK_MUX 12 -#define ZX296702_I2S1_WCLK 13 -#define ZX296702_I2S1_PCLK 14 -#define ZX296702_I2S1_DIV 15 -#define ZX296702_I2S2_WCLK_MUX 16 -#define ZX296702_I2S2_WCLK 17 -#define ZX296702_I2S2_PCLK 18 -#define ZX296702_I2S2_DIV 19 -#define ZX296702_GPIO_CLK 20 -#define ZX296702_LSP0CLK_END 21 - -#define ZX296702_UART0_WCLK_MUX 0 -#define ZX296702_UART0_WCLK 1 -#define ZX296702_UART0_PCLK 2 -#define ZX296702_UART1_WCLK_MUX 3 -#define ZX296702_UART1_WCLK 4 -#define ZX296702_UART1_PCLK 5 -#define ZX296702_SDMMC0_WCLK_MUX 6 -#define ZX296702_SDMMC0_WCLK_DIV 7 -#define ZX296702_SDMMC0_WCLK 8 -#define ZX296702_SDMMC0_PCLK 9 -#define ZX296702_SPDIF1_WCLK_MUX 10 -#define ZX296702_SPDIF1_WCLK 11 -#define ZX296702_SPDIF1_PCLK 12 -#define ZX296702_SPDIF1_DIV 13 -#define ZX296702_LSP1CLK_END 14 - -#endif /* __DT_BINDINGS_CLOCK_ZX296702_H */ diff --git a/include/dt-bindings/clock/zx296718-clock.h b/include/dt-bindings/clock/zx296718-clock.h deleted file mode 100644 index bf2ff6d2ee23..000000000000 --- a/include/dt-bindings/clock/zx296718-clock.h +++ /dev/null @@ -1,164 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2015 - 2016 ZTE Corporation. - */ -#ifndef __DT_BINDINGS_CLOCK_ZX296718_H -#define __DT_BINDINGS_CLOCK_ZX296718_H - -/* PLL */ -#define ZX296718_PLL_CPU 1 -#define ZX296718_PLL_MAC 2 -#define ZX296718_PLL_MM0 3 -#define ZX296718_PLL_MM1 4 -#define ZX296718_PLL_VGA 5 -#define ZX296718_PLL_DDR 6 -#define ZX296718_PLL_AUDIO 7 -#define ZX296718_PLL_HSIC 8 -#define CPU_DBG_GATE 9 -#define A72_GATE 10 -#define CPU_PERI_GATE 11 -#define A53_GATE 12 -#define DDR1_GATE 13 -#define DDR0_GATE 14 -#define SD1_WCLK 15 -#define SD1_AHB 16 -#define SD0_WCLK 17 -#define SD0_AHB 18 -#define EMMC_WCLK 19 -#define EMMC_NAND_AXI 20 -#define NAND_WCLK 21 -#define EMMC_NAND_AHB 22 -#define LSP1_148M5 23 -#define LSP1_99M 24 -#define LSP1_24M 25 -#define LSP0_74M25 26 -#define LSP0_32K 27 -#define LSP0_148M5 28 -#define LSP0_99M 29 -#define LSP0_24M 30 -#define DEMUX_AXI 31 -#define DEMUX_APB 32 -#define DEMUX_148M5 33 -#define DEMUX_108M 34 -#define AUDIO_APB 35 -#define AUDIO_99M 36 -#define AUDIO_24M 37 -#define AUDIO_16M384 38 -#define AUDIO_32K 39 -#define WDT_WCLK 40 -#define TIMER_WCLK 41 -#define VDE_ACLK 42 -#define VCE_ACLK 43 -#define HDE_ACLK 44 -#define GPU_ACLK 45 -#define SAPPU_ACLK 46 -#define SAPPU_WCLK 47 -#define VOU_ACLK 48 -#define VOU_MAIN_WCLK 49 -#define VOU_AUX_WCLK 50 -#define VOU_PPU_WCLK 51 -#define MIPI_CFG_CLK 52 -#define VGA_I2C_WCLK 53 -#define MIPI_REF_CLK 54 -#define HDMI_OSC_CEC 55 -#define HDMI_OSC_CLK 56 -#define HDMI_XCLK 57 -#define VIU_M0_ACLK 58 -#define VIU_M1_ACLK 59 -#define VIU_WCLK 60 -#define VIU_JPEG_WCLK 61 -#define VIU_CFG_CLK 62 -#define TS_SYS_WCLK 63 -#define TS_SYS_108M 64 -#define USB20_HCLK 65 -#define USB20_PHY_CLK 66 -#define USB21_HCLK 67 -#define USB21_PHY_CLK 68 -#define GMAC_RMIICLK 69 -#define GMAC_PCLK 70 -#define GMAC_ACLK 71 -#define GMAC_RFCLK 72 -#define TEMPSENSOR_GATE 73 - -#define TOP_NR_CLKS 74 - - -#define LSP0_TIMER3_PCLK 1 -#define LSP0_TIMER3_WCLK 2 -#define LSP0_TIMER4_PCLK 3 -#define LSP0_TIMER4_WCLK 4 -#define LSP0_TIMER5_PCLK 5 -#define LSP0_TIMER5_WCLK 6 -#define LSP0_UART3_PCLK 7 -#define LSP0_UART3_WCLK 8 -#define LSP0_UART1_PCLK 9 -#define LSP0_UART1_WCLK 10 -#define LSP0_UART2_PCLK 11 -#define LSP0_UART2_WCLK 12 -#define LSP0_SPIFC0_PCLK 13 -#define LSP0_SPIFC0_WCLK 14 -#define LSP0_I2C4_PCLK 15 -#define LSP0_I2C4_WCLK 16 -#define LSP0_I2C5_PCLK 17 -#define LSP0_I2C5_WCLK 18 -#define LSP0_SSP0_PCLK 19 -#define LSP0_SSP0_WCLK 20 -#define LSP0_SSP1_PCLK 21 -#define LSP0_SSP1_WCLK 22 -#define LSP0_USIM_PCLK 23 -#define LSP0_USIM_WCLK 24 -#define LSP0_GPIO_PCLK 25 -#define LSP0_GPIO_WCLK 26 -#define LSP0_I2C3_PCLK 27 -#define LSP0_I2C3_WCLK 28 - -#define LSP0_NR_CLKS 29 - - -#define LSP1_UART4_PCLK 1 -#define LSP1_UART4_WCLK 2 -#define LSP1_UART5_PCLK 3 -#define LSP1_UART5_WCLK 4 -#define LSP1_PWM_PCLK 5 -#define LSP1_PWM_WCLK 6 -#define LSP1_I2C2_PCLK 7 -#define LSP1_I2C2_WCLK 8 -#define LSP1_SSP2_PCLK 9 -#define LSP1_SSP2_WCLK 10 -#define LSP1_SSP3_PCLK 11 -#define LSP1_SSP3_WCLK 12 -#define LSP1_SSP4_PCLK 13 -#define LSP1_SSP4_WCLK 14 -#define LSP1_USIM1_PCLK 15 -#define LSP1_USIM1_WCLK 16 - -#define LSP1_NR_CLKS 17 - - -#define AUDIO_I2S0_WCLK 1 -#define AUDIO_I2S0_PCLK 2 -#define AUDIO_I2S1_WCLK 3 -#define AUDIO_I2S1_PCLK 4 -#define AUDIO_I2S2_WCLK 5 -#define AUDIO_I2S2_PCLK 6 -#define AUDIO_I2S3_WCLK 7 -#define AUDIO_I2S3_PCLK 8 -#define AUDIO_I2C0_WCLK 9 -#define AUDIO_I2C0_PCLK 10 -#define AUDIO_SPDIF0_WCLK 11 -#define AUDIO_SPDIF0_PCLK 12 -#define AUDIO_SPDIF1_WCLK 13 -#define AUDIO_SPDIF1_PCLK 14 -#define AUDIO_TIMER_WCLK 15 -#define AUDIO_TIMER_PCLK 16 -#define AUDIO_TDM_WCLK 17 -#define AUDIO_TDM_PCLK 18 -#define AUDIO_TS_PCLK 19 -#define I2S0_WCLK_MUX 20 -#define I2S1_WCLK_MUX 21 -#define I2S2_WCLK_MUX 22 -#define I2S3_WCLK_MUX 23 - -#define AUDIO_NR_CLKS 24 - -#endif diff --git a/include/dt-bindings/display/sdtv-standards.h b/include/dt-bindings/display/sdtv-standards.h new file mode 100644 index 000000000000..fbc1a3db2ea7 --- /dev/null +++ b/include/dt-bindings/display/sdtv-standards.h @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0-only or X11 */ +/* + * Copyright 2019 Pengutronix, Marco Felsch <kernel@pengutronix.de> + */ + +#ifndef _DT_BINDINGS_DISPLAY_SDTV_STDS_H +#define _DT_BINDINGS_DISPLAY_SDTV_STDS_H + +/* + * Attention: Keep the SDTV_STD_* bit definitions in sync with + * include/uapi/linux/videodev2.h V4L2_STD_* bit definitions. + */ +/* One bit for each standard */ +#define SDTV_STD_PAL_B 0x00000001 +#define SDTV_STD_PAL_B1 0x00000002 +#define SDTV_STD_PAL_G 0x00000004 +#define SDTV_STD_PAL_H 0x00000008 +#define SDTV_STD_PAL_I 0x00000010 +#define SDTV_STD_PAL_D 0x00000020 +#define SDTV_STD_PAL_D1 0x00000040 +#define SDTV_STD_PAL_K 0x00000080 + +#define SDTV_STD_PAL (SDTV_STD_PAL_B | \ + SDTV_STD_PAL_B1 | \ + SDTV_STD_PAL_G | \ + SDTV_STD_PAL_H | \ + SDTV_STD_PAL_I | \ + SDTV_STD_PAL_D | \ + SDTV_STD_PAL_D1 | \ + SDTV_STD_PAL_K) + +#define SDTV_STD_PAL_M 0x00000100 +#define SDTV_STD_PAL_N 0x00000200 +#define SDTV_STD_PAL_Nc 0x00000400 +#define SDTV_STD_PAL_60 0x00000800 + +#define SDTV_STD_NTSC_M 0x00001000 /* BTSC */ +#define SDTV_STD_NTSC_M_JP 0x00002000 /* EIA-J */ +#define SDTV_STD_NTSC_443 0x00004000 +#define SDTV_STD_NTSC_M_KR 0x00008000 /* FM A2 */ + +#define SDTV_STD_NTSC (SDTV_STD_NTSC_M | \ + SDTV_STD_NTSC_M_JP | \ + SDTV_STD_NTSC_M_KR) + +#define SDTV_STD_SECAM_B 0x00010000 +#define SDTV_STD_SECAM_D 0x00020000 +#define SDTV_STD_SECAM_G 0x00040000 +#define SDTV_STD_SECAM_H 0x00080000 +#define SDTV_STD_SECAM_K 0x00100000 +#define SDTV_STD_SECAM_K1 0x00200000 +#define SDTV_STD_SECAM_L 0x00400000 +#define SDTV_STD_SECAM_LC 0x00800000 + +#define SDTV_STD_SECAM (SDTV_STD_SECAM_B | \ + SDTV_STD_SECAM_D | \ + SDTV_STD_SECAM_G | \ + SDTV_STD_SECAM_H | \ + SDTV_STD_SECAM_K | \ + SDTV_STD_SECAM_K1 | \ + SDTV_STD_SECAM_L | \ + SDTV_STD_SECAM_LC) + +/* Standards for Countries with 60Hz Line frequency */ +#define SDTV_STD_525_60 (SDTV_STD_PAL_M | \ + SDTV_STD_PAL_60 | \ + SDTV_STD_NTSC | \ + SDTV_STD_NTSC_443) + +/* Standards for Countries with 50Hz Line frequency */ +#define SDTV_STD_625_50 (SDTV_STD_PAL | \ + SDTV_STD_PAL_N | \ + SDTV_STD_PAL_Nc | \ + SDTV_STD_SECAM) + +#endif /* _DT_BINDINGS_DISPLAY_SDTV_STDS_H */ diff --git a/include/dt-bindings/dma/jz4775-dma.h b/include/dt-bindings/dma/jz4775-dma.h new file mode 100644 index 000000000000..8d27e2c69dca --- /dev/null +++ b/include/dt-bindings/dma/jz4775-dma.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * This header provides macros for JZ4775 DMA bindings. + * + * Copyright (c) 2020 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> + */ + +#ifndef __DT_BINDINGS_DMA_JZ4775_DMA_H__ +#define __DT_BINDINGS_DMA_JZ4775_DMA_H__ + +/* + * Request type numbers for the JZ4775 DMA controller (written to the DRTn + * register for the channel). + */ +#define JZ4775_DMA_I2S0_TX 0x6 +#define JZ4775_DMA_I2S0_RX 0x7 +#define JZ4775_DMA_AUTO 0x8 +#define JZ4775_DMA_SADC_RX 0x9 +#define JZ4775_DMA_UART3_TX 0x0e +#define JZ4775_DMA_UART3_RX 0x0f +#define JZ4775_DMA_UART2_TX 0x10 +#define JZ4775_DMA_UART2_RX 0x11 +#define JZ4775_DMA_UART1_TX 0x12 +#define JZ4775_DMA_UART1_RX 0x13 +#define JZ4775_DMA_UART0_TX 0x14 +#define JZ4775_DMA_UART0_RX 0x15 +#define JZ4775_DMA_SSI0_TX 0x16 +#define JZ4775_DMA_SSI0_RX 0x17 +#define JZ4775_DMA_MSC0_TX 0x1a +#define JZ4775_DMA_MSC0_RX 0x1b +#define JZ4775_DMA_MSC1_TX 0x1c +#define JZ4775_DMA_MSC1_RX 0x1d +#define JZ4775_DMA_MSC2_TX 0x1e +#define JZ4775_DMA_MSC2_RX 0x1f +#define JZ4775_DMA_PCM0_TX 0x20 +#define JZ4775_DMA_PCM0_RX 0x21 +#define JZ4775_DMA_SMB0_TX 0x24 +#define JZ4775_DMA_SMB0_RX 0x25 +#define JZ4775_DMA_SMB1_TX 0x26 +#define JZ4775_DMA_SMB1_RX 0x27 +#define JZ4775_DMA_SMB2_TX 0x28 +#define JZ4775_DMA_SMB2_RX 0x29 + +#endif /* __DT_BINDINGS_DMA_JZ4775_DMA_H__ */ diff --git a/include/dt-bindings/dma/qcom-gpi.h b/include/dt-bindings/dma/qcom-gpi.h new file mode 100644 index 000000000000..ebda2a37f52a --- /dev/null +++ b/include/dt-bindings/dma/qcom-gpi.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ +/* Copyright (c) 2020, Linaro Ltd. */ + +#ifndef __DT_BINDINGS_DMA_QCOM_GPI_H__ +#define __DT_BINDINGS_DMA_QCOM_GPI_H__ + +#define QCOM_GPI_SPI 1 +#define QCOM_GPI_UART 2 +#define QCOM_GPI_I2C 3 + +#endif /* __DT_BINDINGS_DMA_QCOM_GPI_H__ */ diff --git a/include/dt-bindings/dma/x2000-dma.h b/include/dt-bindings/dma/x2000-dma.h new file mode 100644 index 000000000000..db2cd4830b00 --- /dev/null +++ b/include/dt-bindings/dma/x2000-dma.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * This header provides macros for X2000 DMA bindings. + * + * Copyright (c) 2020 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> + */ + +#ifndef __DT_BINDINGS_DMA_X2000_DMA_H__ +#define __DT_BINDINGS_DMA_X2000_DMA_H__ + +/* + * Request type numbers for the X2000 DMA controller (written to the DRTn + * register for the channel). + */ +#define X2000_DMA_AUTO 0x8 +#define X2000_DMA_UART5_TX 0xa +#define X2000_DMA_UART5_RX 0xb +#define X2000_DMA_UART4_TX 0xc +#define X2000_DMA_UART4_RX 0xd +#define X2000_DMA_UART3_TX 0xe +#define X2000_DMA_UART3_RX 0xf +#define X2000_DMA_UART2_TX 0x10 +#define X2000_DMA_UART2_RX 0x11 +#define X2000_DMA_UART1_TX 0x12 +#define X2000_DMA_UART1_RX 0x13 +#define X2000_DMA_UART0_TX 0x14 +#define X2000_DMA_UART0_RX 0x15 +#define X2000_DMA_SSI0_TX 0x16 +#define X2000_DMA_SSI0_RX 0x17 +#define X2000_DMA_SSI1_TX 0x18 +#define X2000_DMA_SSI1_RX 0x19 +#define X2000_DMA_I2C0_TX 0x24 +#define X2000_DMA_I2C0_RX 0x25 +#define X2000_DMA_I2C1_TX 0x26 +#define X2000_DMA_I2C1_RX 0x27 +#define X2000_DMA_I2C2_TX 0x28 +#define X2000_DMA_I2C2_RX 0x29 +#define X2000_DMA_I2C3_TX 0x2a +#define X2000_DMA_I2C3_RX 0x2b +#define X2000_DMA_I2C4_TX 0x2c +#define X2000_DMA_I2C4_RX 0x2d +#define X2000_DMA_I2C5_TX 0x2e +#define X2000_DMA_I2C5_RX 0x2f +#define X2000_DMA_UART6_TX 0x30 +#define X2000_DMA_UART6_RX 0x31 +#define X2000_DMA_UART7_TX 0x32 +#define X2000_DMA_UART7_RX 0x33 +#define X2000_DMA_UART8_TX 0x34 +#define X2000_DMA_UART8_RX 0x35 +#define X2000_DMA_UART9_TX 0x36 +#define X2000_DMA_UART9_RX 0x37 +#define X2000_DMA_SADC_RX 0x38 + +#endif /* __DT_BINDINGS_DMA_X2000_DMA_H__ */ diff --git a/include/dt-bindings/dma/xlnx-zynqmp-dpdma.h b/include/dt-bindings/dma/xlnx-zynqmp-dpdma.h new file mode 100644 index 000000000000..3719cda5679d --- /dev/null +++ b/include/dt-bindings/dma/xlnx-zynqmp-dpdma.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright 2019 Laurent Pinchart <laurent.pinchart@ideasonboard.com> + */ + +#ifndef __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ +#define __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ + +#define ZYNQMP_DPDMA_VIDEO0 0 +#define ZYNQMP_DPDMA_VIDEO1 1 +#define ZYNQMP_DPDMA_VIDEO2 2 +#define ZYNQMP_DPDMA_GRAPHICS 3 +#define ZYNQMP_DPDMA_AUDIO0 4 +#define ZYNQMP_DPDMA_AUDIO1 5 + +#endif /* __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ */ diff --git a/include/dt-bindings/firmware/imx/rsrc.h b/include/dt-bindings/firmware/imx/rsrc.h index 4e61f6485097..1675de05ad33 100644 --- a/include/dt-bindings/firmware/imx/rsrc.h +++ b/include/dt-bindings/firmware/imx/rsrc.h @@ -37,10 +37,14 @@ #define IMX_SC_R_DC_0_BLIT2 21 #define IMX_SC_R_DC_0_BLIT_OUT 22 #define IMX_SC_R_PERF 23 +#define IMX_SC_R_USB_1_PHY 24 #define IMX_SC_R_DC_0_WARP 25 +#define IMX_SC_R_V2X_MU_0 26 +#define IMX_SC_R_V2X_MU_1 27 #define IMX_SC_R_DC_0_VIDEO0 28 #define IMX_SC_R_DC_0_VIDEO1 29 #define IMX_SC_R_DC_0_FRAC0 30 +#define IMX_SC_R_V2X_MU_2 31 #define IMX_SC_R_DC_0 32 #define IMX_SC_R_GPU_2_PID0 33 #define IMX_SC_R_DC_0_PLL_0 34 @@ -49,7 +53,10 @@ #define IMX_SC_R_DC_1_BLIT1 37 #define IMX_SC_R_DC_1_BLIT2 38 #define IMX_SC_R_DC_1_BLIT_OUT 39 +#define IMX_SC_R_V2X_MU_3 40 +#define IMX_SC_R_V2X_MU_4 41 #define IMX_SC_R_DC_1_WARP 42 +#define IMX_SC_R_SECVIO 44 #define IMX_SC_R_DC_1_VIDEO0 45 #define IMX_SC_R_DC_1_VIDEO1 46 #define IMX_SC_R_DC_1_FRAC0 47 @@ -111,6 +118,7 @@ #define IMX_SC_R_CAN_0 105 #define IMX_SC_R_CAN_1 106 #define IMX_SC_R_CAN_2 107 +#define IMX_SC_R_CAN(x) (IMX_SC_R_CAN_0 + (x)) #define IMX_SC_R_DMA_1_CH0 108 #define IMX_SC_R_DMA_1_CH1 109 #define IMX_SC_R_DMA_1_CH2 110 @@ -547,4 +555,88 @@ #define IMX_SC_R_ATTESTATION 545 #define IMX_SC_R_LAST 546 +/* + * Defines for SC PM CLK + */ +#define IMX_SC_PM_CLK_SLV_BUS 0 /* Slave bus clock */ +#define IMX_SC_PM_CLK_MST_BUS 1 /* Master bus clock */ +#define IMX_SC_PM_CLK_PER 2 /* Peripheral clock */ +#define IMX_SC_PM_CLK_PHY 3 /* Phy clock */ +#define IMX_SC_PM_CLK_MISC 4 /* Misc clock */ +#define IMX_SC_PM_CLK_MISC0 0 /* Misc 0 clock */ +#define IMX_SC_PM_CLK_MISC1 1 /* Misc 1 clock */ +#define IMX_SC_PM_CLK_MISC2 2 /* Misc 2 clock */ +#define IMX_SC_PM_CLK_MISC3 3 /* Misc 3 clock */ +#define IMX_SC_PM_CLK_MISC4 4 /* Misc 4 clock */ +#define IMX_SC_PM_CLK_CPU 2 /* CPU clock */ +#define IMX_SC_PM_CLK_PLL 4 /* PLL */ +#define IMX_SC_PM_CLK_BYPASS 4 /* Bypass clock */ + +/* + * Defines for SC CONTROL + */ +#define IMX_SC_C_TEMP 0 +#define IMX_SC_C_TEMP_HI 1 +#define IMX_SC_C_TEMP_LOW 2 +#define IMX_SC_C_PXL_LINK_MST1_ADDR 3 +#define IMX_SC_C_PXL_LINK_MST2_ADDR 4 +#define IMX_SC_C_PXL_LINK_MST_ENB 5 +#define IMX_SC_C_PXL_LINK_MST1_ENB 6 +#define IMX_SC_C_PXL_LINK_MST2_ENB 7 +#define IMX_SC_C_PXL_LINK_SLV1_ADDR 8 +#define IMX_SC_C_PXL_LINK_SLV2_ADDR 9 +#define IMX_SC_C_PXL_LINK_MST_VLD 10 +#define IMX_SC_C_PXL_LINK_MST1_VLD 11 +#define IMX_SC_C_PXL_LINK_MST2_VLD 12 +#define IMX_SC_C_SINGLE_MODE 13 +#define IMX_SC_C_ID 14 +#define IMX_SC_C_PXL_CLK_POLARITY 15 +#define IMX_SC_C_LINESTATE 16 +#define IMX_SC_C_PCIE_G_RST 17 +#define IMX_SC_C_PCIE_BUTTON_RST 18 +#define IMX_SC_C_PCIE_PERST 19 +#define IMX_SC_C_PHY_RESET 20 +#define IMX_SC_C_PXL_LINK_RATE_CORRECTION 21 +#define IMX_SC_C_PANIC 22 +#define IMX_SC_C_PRIORITY_GROUP 23 +#define IMX_SC_C_TXCLK 24 +#define IMX_SC_C_CLKDIV 25 +#define IMX_SC_C_DISABLE_50 26 +#define IMX_SC_C_DISABLE_125 27 +#define IMX_SC_C_SEL_125 28 +#define IMX_SC_C_MODE 29 +#define IMX_SC_C_SYNC_CTRL0 30 +#define IMX_SC_C_KACHUNK_CNT 31 +#define IMX_SC_C_KACHUNK_SEL 32 +#define IMX_SC_C_SYNC_CTRL1 33 +#define IMX_SC_C_DPI_RESET 34 +#define IMX_SC_C_MIPI_RESET 35 +#define IMX_SC_C_DUAL_MODE 36 +#define IMX_SC_C_VOLTAGE 37 +#define IMX_SC_C_PXL_LINK_SEL 38 +#define IMX_SC_C_OFS_SEL 39 +#define IMX_SC_C_OFS_AUDIO 40 +#define IMX_SC_C_OFS_PERIPH 41 +#define IMX_SC_C_OFS_IRQ 42 +#define IMX_SC_C_RST0 43 +#define IMX_SC_C_RST1 44 +#define IMX_SC_C_SEL0 45 +#define IMX_SC_C_CALIB0 46 +#define IMX_SC_C_CALIB1 47 +#define IMX_SC_C_CALIB2 48 +#define IMX_SC_C_IPG_DEBUG 49 +#define IMX_SC_C_IPG_DOZE 50 +#define IMX_SC_C_IPG_WAIT 51 +#define IMX_SC_C_IPG_STOP 52 +#define IMX_SC_C_IPG_STOP_MODE 53 +#define IMX_SC_C_IPG_STOP_ACK 54 +#define IMX_SC_C_SYNC_CTRL 55 +#define IMX_SC_C_OFS_AUDIO_ALT 56 +#define IMX_SC_C_DSP_BYP 57 +#define IMX_SC_C_CLK_GEN_EN 58 +#define IMX_SC_C_INTF_SEL 59 +#define IMX_SC_C_RXC_DLY 60 +#define IMX_SC_C_TIMER_SEL 61 +#define IMX_SC_C_LAST 62 + #endif /* __DT_BINDINGS_RSCRC_IMX_H */ diff --git a/include/dt-bindings/gce/mt6779-gce.h b/include/dt-bindings/gce/mt6779-gce.h new file mode 100644 index 000000000000..06101316ace4 --- /dev/null +++ b/include/dt-bindings/gce/mt6779-gce.h @@ -0,0 +1,222 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2019 MediaTek Inc. + * Author: Dennis-YC Hsieh <dennis-yc.hsieh@mediatek.com> + */ + +#ifndef _DT_BINDINGS_GCE_MT6779_H +#define _DT_BINDINGS_GCE_MT6779_H + +#define CMDQ_NO_TIMEOUT 0xffffffff + +/* GCE HW thread priority */ +#define CMDQ_THR_PRIO_LOWEST 0 +#define CMDQ_THR_PRIO_1 1 +#define CMDQ_THR_PRIO_2 2 +#define CMDQ_THR_PRIO_3 3 +#define CMDQ_THR_PRIO_4 4 +#define CMDQ_THR_PRIO_5 5 +#define CMDQ_THR_PRIO_6 6 +#define CMDQ_THR_PRIO_HIGHEST 7 + +/* GCE subsys table */ +#define SUBSYS_1300XXXX 0 +#define SUBSYS_1400XXXX 1 +#define SUBSYS_1401XXXX 2 +#define SUBSYS_1402XXXX 3 +#define SUBSYS_1502XXXX 4 +#define SUBSYS_1880XXXX 5 +#define SUBSYS_1881XXXX 6 +#define SUBSYS_1882XXXX 7 +#define SUBSYS_1883XXXX 8 +#define SUBSYS_1884XXXX 9 +#define SUBSYS_1000XXXX 10 +#define SUBSYS_1001XXXX 11 +#define SUBSYS_1002XXXX 12 +#define SUBSYS_1003XXXX 13 +#define SUBSYS_1004XXXX 14 +#define SUBSYS_1005XXXX 15 +#define SUBSYS_1020XXXX 16 +#define SUBSYS_1028XXXX 17 +#define SUBSYS_1700XXXX 18 +#define SUBSYS_1701XXXX 19 +#define SUBSYS_1702XXXX 20 +#define SUBSYS_1703XXXX 21 +#define SUBSYS_1800XXXX 22 +#define SUBSYS_1801XXXX 23 +#define SUBSYS_1802XXXX 24 +#define SUBSYS_1804XXXX 25 +#define SUBSYS_1805XXXX 26 +#define SUBSYS_1808XXXX 27 +#define SUBSYS_180aXXXX 28 +#define SUBSYS_180bXXXX 29 +#define CMDQ_SUBSYS_OFF 32 + +/* GCE hardware events */ +#define CMDQ_EVENT_DISP_RDMA0_SOF 0 +#define CMDQ_EVENT_DISP_RDMA1_SOF 1 +#define CMDQ_EVENT_MDP_RDMA0_SOF 2 +#define CMDQ_EVENT_MDP_RDMA1_SOF 3 +#define CMDQ_EVENT_MDP_RSZ0_SOF 4 +#define CMDQ_EVENT_MDP_RSZ1_SOF 5 +#define CMDQ_EVENT_MDP_TDSHP_SOF 6 +#define CMDQ_EVENT_MDP_WROT0_SOF 7 +#define CMDQ_EVENT_MDP_WROT1_SOF 8 +#define CMDQ_EVENT_DISP_OVL0_SOF 9 +#define CMDQ_EVENT_DISP_2L_OVL0_SOF 10 +#define CMDQ_EVENT_DISP_2L_OVL1_SOF 11 +#define CMDQ_EVENT_DISP_WDMA0_SOF 12 +#define CMDQ_EVENT_DISP_COLOR0_SOF 13 +#define CMDQ_EVENT_DISP_CCORR0_SOF 14 +#define CMDQ_EVENT_DISP_AAL0_SOF 15 +#define CMDQ_EVENT_DISP_GAMMA0_SOF 16 +#define CMDQ_EVENT_DISP_DITHER0_SOF 17 +#define CMDQ_EVENT_DISP_PWM0_SOF 18 +#define CMDQ_EVENT_DISP_DSI0_SOF 19 +#define CMDQ_EVENT_DISP_DPI0_SOF 20 +#define CMDQ_EVENT_DISP_POSTMASK0_SOF 21 +#define CMDQ_EVENT_DISP_RSZ0_SOF 22 +#define CMDQ_EVENT_MDP_AAL_SOF 23 +#define CMDQ_EVENT_MDP_CCORR_SOF 24 +#define CMDQ_EVENT_DISP_DBI0_SOF 25 +#define CMDQ_EVENT_ISP_RELAY_SOF 26 +#define CMDQ_EVENT_IPU_RELAY_SOF 27 +#define CMDQ_EVENT_DISP_RDMA0_EOF 28 +#define CMDQ_EVENT_DISP_RDMA1_EOF 29 +#define CMDQ_EVENT_MDP_RDMA0_EOF 30 +#define CMDQ_EVENT_MDP_RDMA1_EOF 31 +#define CMDQ_EVENT_MDP_RSZ0_EOF 32 +#define CMDQ_EVENT_MDP_RSZ1_EOF 33 +#define CMDQ_EVENT_MDP_TDSHP_EOF 34 +#define CMDQ_EVENT_MDP_WROT0_W_EOF 35 +#define CMDQ_EVENT_MDP_WROT1_W_EOF 36 +#define CMDQ_EVENT_DISP_OVL0_EOF 37 +#define CMDQ_EVENT_DISP_2L_OVL0_EOF 38 +#define CMDQ_EVENT_DISP_2L_OVL1_EOF 39 +#define CMDQ_EVENT_DISP_WDMA0_EOF 40 +#define CMDQ_EVENT_DISP_COLOR0_EOF 41 +#define CMDQ_EVENT_DISP_CCORR0_EOF 42 +#define CMDQ_EVENT_DISP_AAL0_EOF 43 +#define CMDQ_EVENT_DISP_GAMMA0_EOF 44 +#define CMDQ_EVENT_DISP_DITHER0_EOF 45 +#define CMDQ_EVENT_DISP_DSI0_EOF 46 +#define CMDQ_EVENT_DISP_DPI0_EOF 47 +#define CMDQ_EVENT_DISP_RSZ0_EOF 49 +#define CMDQ_EVENT_MDP_AAL_FRAME_DONE 50 +#define CMDQ_EVENT_MDP_CCORR_FRAME_DONE 51 +#define CMDQ_EVENT_DISP_POSTMASK0_FRAME_DONE 52 +#define CMDQ_EVENT_MUTEX0_STREAM_EOF 130 +#define CMDQ_EVENT_MUTEX1_STREAM_EOF 131 +#define CMDQ_EVENT_MUTEX2_STREAM_EOF 132 +#define CMDQ_EVENT_MUTEX3_STREAM_EOF 133 +#define CMDQ_EVENT_MUTEX4_STREAM_EOF 134 +#define CMDQ_EVENT_MUTEX5_STREAM_EOF 135 +#define CMDQ_EVENT_MUTEX6_STREAM_EOF 136 +#define CMDQ_EVENT_MUTEX7_STREAM_EOF 137 +#define CMDQ_EVENT_MUTEX8_STREAM_EOF 138 +#define CMDQ_EVENT_MUTEX9_STREAM_EOF 139 +#define CMDQ_EVENT_MUTEX10_STREAM_EOF 140 +#define CMDQ_EVENT_MUTEX11_STREAM_EOF 141 +#define CMDQ_EVENT_DISP_RDMA0_UNDERRUN 142 +#define CMDQ_EVENT_DISP_RDMA1_UNDERRUN 143 +#define CMDQ_EVENT_DISP_RDMA2_UNDERRUN 144 +#define CMDQ_EVENT_DISP_RDMA3_UNDERRUN 145 +#define CMDQ_EVENT_DSI0_TE 146 +#define CMDQ_EVENT_DSI0_IRQ_EVENT 147 +#define CMDQ_EVENT_DSI0_DONE_EVENT 148 +#define CMDQ_EVENT_DISP_POSTMASK0_RST_DONE 150 +#define CMDQ_EVENT_DISP_WDMA0_RST_DONE 151 +#define CMDQ_EVENT_MDP_WROT0_RST_DONE 153 +#define CMDQ_EVENT_MDP_RDMA0_RST_DONE 154 +#define CMDQ_EVENT_DISP_OVL0_RST_DONE 155 +#define CMDQ_EVENT_DISP_OVL0_2L_RST_DONE 156 +#define CMDQ_EVENT_DISP_OVL1_2L_RST_DONE 157 +#define CMDQ_EVENT_DIP_CQ_THREAD0_EOF 257 +#define CMDQ_EVENT_DIP_CQ_THREAD1_EOF 258 +#define CMDQ_EVENT_DIP_CQ_THREAD2_EOF 259 +#define CMDQ_EVENT_DIP_CQ_THREAD3_EOF 260 +#define CMDQ_EVENT_DIP_CQ_THREAD4_EOF 261 +#define CMDQ_EVENT_DIP_CQ_THREAD5_EOF 262 +#define CMDQ_EVENT_DIP_CQ_THREAD6_EOF 263 +#define CMDQ_EVENT_DIP_CQ_THREAD7_EOF 264 +#define CMDQ_EVENT_DIP_CQ_THREAD8_EOF 265 +#define CMDQ_EVENT_DIP_CQ_THREAD9_EOF 266 +#define CMDQ_EVENT_DIP_CQ_THREAD10_EOF 267 +#define CMDQ_EVENT_DIP_CQ_THREAD11_EOF 268 +#define CMDQ_EVENT_DIP_CQ_THREAD12_EOF 269 +#define CMDQ_EVENT_DIP_CQ_THREAD13_EOF 270 +#define CMDQ_EVENT_DIP_CQ_THREAD14_EOF 271 +#define CMDQ_EVENT_DIP_CQ_THREAD15_EOF 272 +#define CMDQ_EVENT_DIP_CQ_THREAD16_EOF 273 +#define CMDQ_EVENT_DIP_CQ_THREAD17_EOF 274 +#define CMDQ_EVENT_DIP_CQ_THREAD18_EOF 275 +#define CMDQ_EVENT_DIP_DMA_ERR_EVENT 276 +#define CMDQ_EVENT_AMD_FRAME_DONE 277 +#define CMDQ_EVENT_MFB_DONE 278 +#define CMDQ_EVENT_WPE_A_EOF 279 +#define CMDQ_EVENT_VENC_EOF 289 +#define CMDQ_EVENT_VENC_CMDQ_PAUSE_DONE 290 +#define CMDQ_EVENT_JPEG_ENC_EOF 291 +#define CMDQ_EVENT_VENC_MB_DONE 292 +#define CMDQ_EVENT_VENC_128BYTE_CNT_DONE 293 +#define CMDQ_EVENT_ISP_FRAME_DONE_A 321 +#define CMDQ_EVENT_ISP_FRAME_DONE_B 322 +#define CMDQ_EVENT_ISP_FRAME_DONE_C 323 +#define CMDQ_EVENT_ISP_CAMSV_0_PASS1_DONE 324 +#define CMDQ_EVENT_ISP_CAMSV_0_2_PASS1_DONE 325 +#define CMDQ_EVENT_ISP_CAMSV_1_PASS1_DONE 326 +#define CMDQ_EVENT_ISP_CAMSV_2_PASS1_DONE 327 +#define CMDQ_EVENT_ISP_CAMSV_3_PASS1_DONE 328 +#define CMDQ_EVENT_ISP_TSF_DONE 329 +#define CMDQ_EVENT_SENINF_0_FIFO_FULL 330 +#define CMDQ_EVENT_SENINF_1_FIFO_FULL 331 +#define CMDQ_EVENT_SENINF_2_FIFO_FULL 332 +#define CMDQ_EVENT_SENINF_3_FIFO_FULL 333 +#define CMDQ_EVENT_SENINF_4_FIFO_FULL 334 +#define CMDQ_EVENT_SENINF_5_FIFO_FULL 335 +#define CMDQ_EVENT_SENINF_6_FIFO_FULL 336 +#define CMDQ_EVENT_SENINF_7_FIFO_FULL 337 +#define CMDQ_EVENT_TG_OVRUN_A_INT_DLY 338 +#define CMDQ_EVENT_TG_OVRUN_B_INT_DLY 339 +#define CMDQ_EVENT_TG_OVRUN_C_INT 340 +#define CMDQ_EVENT_TG_GRABERR_A_INT_DLY 341 +#define CMDQ_EVENT_TG_GRABERR_B_INT_DLY 342 +#define CMDQ_EVENT_TG_GRABERR_C_INT 343 +#define CMDQ_EVENT_CQ_VR_SNAP_A_INT_DLY 344 +#define CMDQ_EVENT_CQ_VR_SNAP_B_INT_DLY 345 +#define CMDQ_EVENT_CQ_VR_SNAP_C_INT 346 +#define CMDQ_EVENT_DMA_R1_ERROR_A_INT_DLY 347 +#define CMDQ_EVENT_DMA_R1_ERROR_B_INT_DLY 348 +#define CMDQ_EVENT_DMA_R1_ERROR_C_INT 349 +#define CMDQ_EVENT_APU_GCE_CORE0_EVENT_0 353 +#define CMDQ_EVENT_APU_GCE_CORE0_EVENT_1 354 +#define CMDQ_EVENT_APU_GCE_CORE0_EVENT_2 355 +#define CMDQ_EVENT_APU_GCE_CORE0_EVENT_3 356 +#define CMDQ_EVENT_APU_GCE_CORE1_EVENT_0 385 +#define CMDQ_EVENT_APU_GCE_CORE1_EVENT_1 386 +#define CMDQ_EVENT_APU_GCE_CORE1_EVENT_2 387 +#define CMDQ_EVENT_APU_GCE_CORE1_EVENT_3 388 +#define CMDQ_EVENT_VDEC_EVENT_0 416 +#define CMDQ_EVENT_VDEC_EVENT_1 417 +#define CMDQ_EVENT_VDEC_EVENT_2 418 +#define CMDQ_EVENT_VDEC_EVENT_3 419 +#define CMDQ_EVENT_VDEC_EVENT_4 420 +#define CMDQ_EVENT_VDEC_EVENT_5 421 +#define CMDQ_EVENT_VDEC_EVENT_6 422 +#define CMDQ_EVENT_VDEC_EVENT_7 423 +#define CMDQ_EVENT_VDEC_EVENT_8 424 +#define CMDQ_EVENT_VDEC_EVENT_9 425 +#define CMDQ_EVENT_VDEC_EVENT_10 426 +#define CMDQ_EVENT_VDEC_EVENT_11 427 +#define CMDQ_EVENT_VDEC_EVENT_12 428 +#define CMDQ_EVENT_VDEC_EVENT_13 429 +#define CMDQ_EVENT_VDEC_EVENT_14 430 +#define CMDQ_EVENT_VDEC_EVENT_15 431 +#define CMDQ_EVENT_FDVT_DONE 449 +#define CMDQ_EVENT_FE_DONE 450 +#define CMDQ_EVENT_RSC_EOF 451 +#define CMDQ_EVENT_DVS_DONE_ASYNC_SHOT 452 +#define CMDQ_EVENT_DVP_DONE_ASYNC_SHOT 453 +#define CMDQ_EVENT_DSI0_TE_INFRA 898 + +#endif diff --git a/include/dt-bindings/gce/mt8186-gce.h b/include/dt-bindings/gce/mt8186-gce.h new file mode 100644 index 000000000000..f12e3cb586ce --- /dev/null +++ b/include/dt-bindings/gce/mt8186-gce.h @@ -0,0 +1,421 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2022 MediaTek Inc. + * Author: Yongqiang Niu <yongqiang.niu@mediatek.com> + */ + +#ifndef _DT_BINDINGS_GCE_MT8186_H +#define _DT_BINDINGS_GCE_MT8186_H + +/* assign timeout 0 also means default */ +#define CMDQ_NO_TIMEOUT 0xffffffff +#define CMDQ_TIMEOUT_DEFAULT 1000 + +/* GCE thread priority */ +#define CMDQ_THR_PRIO_LOWEST 0 +#define CMDQ_THR_PRIO_1 1 +#define CMDQ_THR_PRIO_2 2 +#define CMDQ_THR_PRIO_3 3 +#define CMDQ_THR_PRIO_4 4 +#define CMDQ_THR_PRIO_5 5 +#define CMDQ_THR_PRIO_6 6 +#define CMDQ_THR_PRIO_HIGHEST 7 + +/* CPR count in 32bit register */ +#define GCE_CPR_COUNT 1312 + +/* GCE subsys table */ +#define SUBSYS_1300XXXX 0 +#define SUBSYS_1400XXXX 1 +#define SUBSYS_1401XXXX 2 +#define SUBSYS_1402XXXX 3 +#define SUBSYS_1502XXXX 4 +#define SUBSYS_1582XXXX 5 +#define SUBSYS_1B00XXXX 6 +#define SUBSYS_1C00XXXX 7 +#define SUBSYS_1C10XXXX 8 +#define SUBSYS_1000XXXX 9 +#define SUBSYS_1001XXXX 10 +#define SUBSYS_1020XXXX 11 +#define SUBSYS_1021XXXX 12 +#define SUBSYS_1022XXXX 13 +#define SUBSYS_1023XXXX 14 +#define SUBSYS_1060XXXX 15 +#define SUBSYS_1602XXXX 16 +#define SUBSYS_1608XXXX 17 +#define SUBSYS_1700XXXX 18 +#define SUBSYS_1701XXXX 19 +#define SUBSYS_1702XXXX 20 +#define SUBSYS_1703XXXX 21 +#define SUBSYS_1706XXXX 22 +#define SUBSYS_1A00XXXX 23 +#define SUBSYS_1A01XXXX 24 +#define SUBSYS_1A02XXXX 25 +#define SUBSYS_1A03XXXX 26 +#define SUBSYS_1A04XXXX 27 +#define SUBSYS_1A05XXXX 28 +#define SUBSYS_1A06XXXX 29 +#define SUBSYS_NO_SUPPORT 99 + +/* GCE General Purpose Register (GPR) support + * Leave note for scenario usage here + */ +/* GCE: write mask */ +#define GCE_GPR_R00 0x00 +#define GCE_GPR_R01 0x01 +/* MDP: P1: JPEG dest */ +#define GCE_GPR_R02 0x02 +#define GCE_GPR_R03 0x03 +/* MDP: PQ color */ +#define GCE_GPR_R04 0x04 +/* MDP: 2D sharpness */ +#define GCE_GPR_R05 0x05 +/* DISP: poll esd */ +#define GCE_GPR_R06 0x06 +#define GCE_GPR_R07 0x07 +/* MDP: P4: 2D sharpness dst */ +#define GCE_GPR_R08 0x08 +#define GCE_GPR_R09 0x09 +/* VCU: poll with timeout for GPR timer */ +#define GCE_GPR_R10 0x0A +#define GCE_GPR_R11 0x0B +/* CMDQ: debug */ +#define GCE_GPR_R12 0x0C +#define GCE_GPR_R13 0x0D +/* CMDQ: P7: debug */ +#define GCE_GPR_R14 0x0E +#define GCE_GPR_R15 0x0F + +/* GCE hardware events */ +/* VDEC */ +#define CMDQ_EVENT_LINE_COUNT_THRESHOLD_INTERRUPT 0 +#define CMDQ_EVENT_VDEC_INT 1 +#define CMDQ_EVENT_VDEC_PAUSE 2 +#define CMDQ_EVENT_VDEC_DEC_ERROR 3 +#define CMDQ_EVENT_MDEC_TIMEOUT 4 +#define CMDQ_EVENT_DRAM_ACCESS_DONE 5 +#define CMDQ_EVENT_INI_FETCH_RDY 6 +#define CMDQ_EVENT_PROCESS_FLAG 7 +#define CMDQ_EVENT_SEARCH_START_CODE_DONE 8 +#define CMDQ_EVENT_REF_REORDER_DONE 9 +#define CMDQ_EVENT_WP_TBLE_DONE 10 +#define CMDQ_EVENT_COUNT_SRAM_CLR_DONE 11 +#define CMDQ_EVENT_GCE_CNT_OP_THRESHOLD 15 +#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_0 16 +#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_1 17 +#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_2 18 +#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_3 19 +#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_4 20 +#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_5 21 +#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_6 22 +#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_7 23 +#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_8 24 +#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_9 25 +#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_10 26 +#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_11 27 +#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_12 28 +#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_13 29 +#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_14 30 +#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_15 31 +#define CMDQ_EVENT_WPE_GCE_FRAME_DONE 32 + +/* CAM */ +#define CMDQ_EVENT_ISP_FRAME_DONE_A 65 +#define CMDQ_EVENT_ISP_FRAME_DONE_B 66 +#define CMDQ_EVENT_CAMSV1_PASS1_DONE 70 +#define CMDQ_EVENT_CAMSV2_PASS1_DONE 71 +#define CMDQ_EVENT_CAMSV3_PASS1_DONE 72 +#define CMDQ_EVENT_MRAW_0_PASS1_DONE 73 +#define CMDQ_EVENT_SENINF_CAM0_FIFO_FULL 75 +#define CMDQ_EVENT_SENINF_CAM1_FIFO_FULL 76 +#define CMDQ_EVENT_SENINF_CAM2_FIFO_FULL 77 +#define CMDQ_EVENT_SENINF_CAM3_FIFO_FULL 78 +#define CMDQ_EVENT_SENINF_CAM4_FIFO_FULL 79 +#define CMDQ_EVENT_SENINF_CAM5_FIFO_FULL 80 +#define CMDQ_EVENT_SENINF_CAM6_FIFO_FULL 81 +#define CMDQ_EVENT_SENINF_CAM7_FIFO_FULL 82 +#define CMDQ_EVENT_SENINF_CAM8_FIFO_FULL 83 +#define CMDQ_EVENT_SENINF_CAM9_FIFO_FULL 84 +#define CMDQ_EVENT_SENINF_CAM10_FIFO_FULL 85 +#define CMDQ_EVENT_SENINF_CAM11_FIFO_FULL 86 +#define CMDQ_EVENT_SENINF_CAM12_FIFO_FULL 87 +#define CMDQ_EVENT_TG_OVRUN_A_INT 88 +#define CMDQ_EVENT_DMA_R1_ERROR_A_INT 89 +#define CMDQ_EVENT_TG_OVRUN_B_INT 90 +#define CMDQ_EVENT_DMA_R1_ERROR_B_INT 91 +#define CMDQ_EVENT_TG_OVRUN_M0_INT 94 +#define CMDQ_EVENT_R1_ERROR_M0_INT 95 +#define CMDQ_EVENT_TG_GRABERR_M0_INT 96 +#define CMDQ_EVENT_TG_GRABERR_A_INT 98 +#define CMDQ_EVENT_CQ_VR_SNAP_A_INT 99 +#define CMDQ_EVENT_TG_GRABERR_B_INT 100 +#define CMDQ_EVENT_CQ_VR_SNAP_B_INT 101 +/* VENC */ +#define CMDQ_EVENT_VENC_CMDQ_FRAME_DONE 129 +#define CMDQ_EVENT_VENC_CMDQ_PAUSE_DONE 130 +#define CMDQ_EVENT_JPGENC_CMDQ_DONE 131 +#define CMDQ_EVENT_VENC_CMDQ_MB_DONE 132 +#define CMDQ_EVENT_VENC_CMDQ_128BYTE_CNT_DONE 133 +#define CMDQ_EVENT_VENC_CMDQ_PPS_DONE 136 +#define CMDQ_EVENT_VENC_CMDQ_SPS_DONE 137 +#define CMDQ_EVENT_VENC_CMDQ_VPS_DONE 138 +/* IPE */ +#define CMDQ_EVENT_FDVT_DONE 161 +#define CMDQ_EVENT_FE_DONE 162 +#define CMDQ_EVENT_RSC_DONE 163 +#define CMDQ_EVENT_DVS_DONE_ASYNC_SHOT 164 +#define CMDQ_EVENT_DVP_DONE_ASYNC_SHOT 165 +/* IMG2 */ +#define CMDQ_EVENT_GCE_IMG2_EVENT0 193 +#define CMDQ_EVENT_GCE_IMG2_EVENT1 194 +#define CMDQ_EVENT_GCE_IMG2_EVENT2 195 +#define CMDQ_EVENT_GCE_IMG2_EVENT3 196 +#define CMDQ_EVENT_GCE_IMG2_EVENT4 197 +#define CMDQ_EVENT_GCE_IMG2_EVENT5 198 +#define CMDQ_EVENT_GCE_IMG2_EVENT6 199 +#define CMDQ_EVENT_GCE_IMG2_EVENT7 200 +#define CMDQ_EVENT_GCE_IMG2_EVENT8 201 +#define CMDQ_EVENT_GCE_IMG2_EVENT9 202 +#define CMDQ_EVENT_GCE_IMG2_EVENT10 203 +#define CMDQ_EVENT_GCE_IMG2_EVENT11 204 +#define CMDQ_EVENT_GCE_IMG2_EVENT12 205 +#define CMDQ_EVENT_GCE_IMG2_EVENT13 206 +#define CMDQ_EVENT_GCE_IMG2_EVENT14 207 +#define CMDQ_EVENT_GCE_IMG2_EVENT15 208 +#define CMDQ_EVENT_GCE_IMG2_EVENT16 209 +#define CMDQ_EVENT_GCE_IMG2_EVENT17 210 +#define CMDQ_EVENT_GCE_IMG2_EVENT18 211 +#define CMDQ_EVENT_GCE_IMG2_EVENT19 212 +#define CMDQ_EVENT_GCE_IMG2_EVENT20 213 +#define CMDQ_EVENT_GCE_IMG2_EVENT21 214 +#define CMDQ_EVENT_GCE_IMG2_EVENT22 215 +#define CMDQ_EVENT_GCE_IMG2_EVENT23 216 +/* IMG1 */ +#define CMDQ_EVENT_GCE_IMG1_EVENT0 225 +#define CMDQ_EVENT_GCE_IMG1_EVENT1 226 +#define CMDQ_EVENT_GCE_IMG1_EVENT2 227 +#define CMDQ_EVENT_GCE_IMG1_EVENT3 228 +#define CMDQ_EVENT_GCE_IMG1_EVENT4 229 +#define CMDQ_EVENT_GCE_IMG1_EVENT5 230 +#define CMDQ_EVENT_GCE_IMG1_EVENT6 231 +#define CMDQ_EVENT_GCE_IMG1_EVENT7 232 +#define CMDQ_EVENT_GCE_IMG1_EVENT8 233 +#define CMDQ_EVENT_GCE_IMG1_EVENT9 234 +#define CMDQ_EVENT_GCE_IMG1_EVENT10 235 +#define CMDQ_EVENT_GCE_IMG1_EVENT11 236 +#define CMDQ_EVENT_GCE_IMG1_EVENT12 237 +#define CMDQ_EVENT_GCE_IMG1_EVENT13 238 +#define CMDQ_EVENT_GCE_IMG1_EVENT14 239 +#define CMDQ_EVENT_GCE_IMG1_EVENT15 240 +#define CMDQ_EVENT_GCE_IMG1_EVENT16 241 +#define CMDQ_EVENT_GCE_IMG1_EVENT17 242 +#define CMDQ_EVENT_GCE_IMG1_EVENT18 243 +#define CMDQ_EVENT_GCE_IMG1_EVENT19 244 +#define CMDQ_EVENT_GCE_IMG1_EVENT20 245 +#define CMDQ_EVENT_GCE_IMG1_EVENT21 246 +#define CMDQ_EVENT_GCE_IMG1_EVENT22 247 +#define CMDQ_EVENT_GCE_IMG1_EVENT23 248 +/* MDP */ +#define CMDQ_EVENT_MDP_RDMA0_SOF 256 +#define CMDQ_EVENT_MDP_RDMA1_SOF 257 +#define CMDQ_EVENT_MDP_AAL0_SOF 258 +#define CMDQ_EVENT_MDP_AAL1_SOF 259 +#define CMDQ_EVENT_MDP_HDR0_SOF 260 +#define CMDQ_EVENT_MDP_RSZ0_SOF 261 +#define CMDQ_EVENT_MDP_RSZ1_SOF 262 +#define CMDQ_EVENT_MDP_WROT0_SOF 263 +#define CMDQ_EVENT_MDP_WROT1_SOF 264 +#define CMDQ_EVENT_MDP_TDSHP0_SOF 265 +#define CMDQ_EVENT_MDP_TDSHP1_SOF 266 +#define CMDQ_EVENT_IMG_DL_RELAY0_SOF 267 +#define CMDQ_EVENT_IMG_DL_RELAY1_SOF 268 +#define CMDQ_EVENT_MDP_COLOR0_SOF 269 +#define CMDQ_EVENT_MDP_WROT3_FRAME_DONE 288 +#define CMDQ_EVENT_MDP_WROT2_FRAME_DONE 289 +#define CMDQ_EVENT_MDP_WROT1_FRAME_DONE 290 +#define CMDQ_EVENT_MDP_WROT0_FRAME_DONE 291 +#define CMDQ_EVENT_MDP_TDSHP3_FRAME_DONE 292 +#define CMDQ_EVENT_MDP_TDSHP2_FRAME_DONE 293 +#define CMDQ_EVENT_MDP_TDSHP1_FRAME_DONE 294 +#define CMDQ_EVENT_MDP_TDSHP0_FRAME_DONE 295 +#define CMDQ_EVENT_MDP_RSZ3_FRAME_DONE 296 +#define CMDQ_EVENT_MDP_RSZ2_FRAME_DONE 297 +#define CMDQ_EVENT_MDP_RSZ1_FRAME_DONE 298 +#define CMDQ_EVENT_MDP_RSZ0_FRAME_DONE 299 +#define CMDQ_EVENT_MDP_RDMA3_FRAME_DONE 300 +#define CMDQ_EVENT_MDP_RDMA2_FRAME_DONE 301 +#define CMDQ_EVENT_MDP_RDMA1_FRAME_DONE 302 +#define CMDQ_EVENT_MDP_RDMA0_FRAME_DONE 303 +#define CMDQ_EVENT_MDP_HDR1_FRAME_DONE 304 +#define CMDQ_EVENT_MDP_HDR0_FRAME_DONE 305 +#define CMDQ_EVENT_MDP_COLOR0_FRAME_DONE 306 +#define CMDQ_EVENT_MDP_AAL3_FRAME_DONE 307 +#define CMDQ_EVENT_MDP_AAL2_FRAME_DONE 308 +#define CMDQ_EVENT_MDP_AAL1_FRAME_DONE 309 +#define CMDQ_EVENT_MDP_AAL0_FRAME_DONE 310 +#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_0 320 +#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_1 321 +#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_2 322 +#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_3 323 +#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_4 324 +#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_5 325 +#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_6 326 +#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_7 327 +#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_8 328 +#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_9 329 +#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_10 330 +#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_11 331 +#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_12 332 +#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_13 333 +#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_14 334 +#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_15 335 +#define CMDQ_EVENT_MDP_WROT3_SW_RST_DONE_ENG_EVENT 336 +#define CMDQ_EVENT_MDP_WROT2_SW_RST_DONE_ENG_EVENT 337 +#define CMDQ_EVENT_MDP_WROT1_SW_RST_DONE_ENG_EVENT 338 +#define CMDQ_EVENT_MDP_WROT0_SW_RST_DONE_ENG_EVENT 339 +#define CMDQ_EVENT_MDP_RDMA3_SW_RST_DONE_ENG_EVENT 340 +#define CMDQ_EVENT_MDP_RDMA2_SW_RST_DONE_ENG_EVENT 341 +#define CMDQ_EVENT_MDP_RDMA1_SW_RST_DONE_ENG_EVENT 342 +#define CMDQ_EVENT_MDP_RDMA0_SW_RST_DONE_ENG_EVENT 343 +/* DISP */ +#define CMDQ_EVENT_DISP_OVL0_SOF 384 +#define CMDQ_EVENT_DISP_OVL0_2L_SOF 385 +#define CMDQ_EVENT_DISP_RDMA0_SOF 386 +#define CMDQ_EVENT_DISP_RSZ0_SOF 387 +#define CMDQ_EVENT_DISP_COLOR0_SOF 388 +#define CMDQ_EVENT_DISP_CCORR0_SOF 389 +#define CMDQ_EVENT_DISP_CCORR1_SOF 390 +#define CMDQ_EVENT_DISP_AAL0_SOF 391 +#define CMDQ_EVENT_DISP_GAMMA0_SOF 392 +#define CMDQ_EVENT_DISP_POSTMASK0_SOF 393 +#define CMDQ_EVENT_DISP_DITHER0_SOF 394 +#define CMDQ_EVENT_DISP_CM0_SOF 395 +#define CMDQ_EVENT_DISP_SPR0_SOF 396 +#define CMDQ_EVENT_DISP_DSC_WRAP0_SOF 397 +#define CMDQ_EVENT_DSI0_SOF 398 +#define CMDQ_EVENT_DISP_WDMA0_SOF 399 +#define CMDQ_EVENT_DISP_PWM0_SOF 400 +#define CMDQ_EVENT_DSI0_FRAME_DONE 410 +#define CMDQ_EVENT_DISP_WDMA0_FRAME_DONE 411 +#define CMDQ_EVENT_DISP_SPR0_FRAME_DONE 412 +#define CMDQ_EVENT_DISP_RSZ0_FRAME_DONE 413 +#define CMDQ_EVENT_DISP_RDMA0_FRAME_DONE 414 +#define CMDQ_EVENT_DISP_POSTMASK0_FRAME_DONE 415 +#define CMDQ_EVENT_DISP_OVL0_FRAME_DONE 416 +#define CMDQ_EVENT_DISP_OVL0_2L_FRAME_DONE 417 +#define CMDQ_EVENT_DISP_GAMMA0_FRAME_DONE 418 +#define CMDQ_EVENT_DISP_DSC_WRAP0_CORE0_FRAME_DONE 420 +#define CMDQ_EVENT_DISP_DITHER0_FRAME_DONE 421 +#define CMDQ_EVENT_DISP_COLOR0_FRAME_DONE 422 +#define CMDQ_EVENT_DISP_CM0_FRAME_DONE 423 +#define CMDQ_EVENT_DISP_CCORR1_FRAME_DONE 424 +#define CMDQ_EVENT_DISP_CCORR0_FRAME_DONE 425 +#define CMDQ_EVENT_DISP_AAL0_FRAME_DONE 426 +#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0 434 +#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1 435 +#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_2 436 +#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_3 437 +#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_4 438 +#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_5 439 +#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_6 440 +#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_7 441 +#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_8 442 +#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_9 443 +#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_10 444 +#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_11 445 +#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_12 446 +#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_13 447 +#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_14 448 +#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_15 449 +#define CMDQ_EVENT_DSI0_TE_ENG_EVENT 450 +#define CMDQ_EVENT_DSI0_IRQ_ENG_EVENT 451 +#define CMDQ_EVENT_DSI0_DONE_ENG_EVENT 452 +#define CMDQ_EVENT_DISP_WDMA0_SW_RST_DONE_ENG_EVENT 453 +#define CMDQ_EVENT_DISP_SMIASSERT_ENG_EVENT 454 +#define CMDQ_EVENT_DISP_POSTMASK0_RST_DONE_ENG_EVENT 455 +#define CMDQ_EVENT_DISP_OVL0_RST_DONE_ENG_EVENT 456 +#define CMDQ_EVENT_DISP_OVL0_2L_RST_DONE_ENG_EVENT 457 +#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_0 458 +#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_1 459 +#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_2 460 +#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_3 461 +#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_4 462 +#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_5 463 +#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_6 464 +#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_7 465 +#define CMDQ_EVENT_OUT_EVENT_0 898 + +/* CMDQ sw tokens + * Following definitions are gce sw token which may use by clients + * event operation API. + * Note that token 512 to 639 may set secure + */ + +/* end of hw event and begin of sw token */ +#define CMDQ_MAX_HW_EVENT 512 + +/* Config thread notify trigger thread */ +#define CMDQ_SYNC_TOKEN_CONFIG_DIRTY 640 +/* Trigger thread notify config thread */ +#define CMDQ_SYNC_TOKEN_STREAM_EOF 641 +/* Block Trigger thread until the ESD check finishes. */ +#define CMDQ_SYNC_TOKEN_ESD_EOF 642 +#define CMDQ_SYNC_TOKEN_STREAM_BLOCK 643 +/* check CABC setup finish */ +#define CMDQ_SYNC_TOKEN_CABC_EOF 644 + +/* Notify normal CMDQ there are some secure task done + * MUST NOT CHANGE, this token sync with secure world + */ +#define CMDQ_SYNC_SECURE_THR_EOF 647 + +/* CMDQ use sw token */ +#define CMDQ_SYNC_TOKEN_USER_0 649 +#define CMDQ_SYNC_TOKEN_USER_1 650 +#define CMDQ_SYNC_TOKEN_POLL_MONITOR 651 +#define CMDQ_SYNC_TOKEN_TPR_LOCK 652 + +/* ISP sw token */ +#define CMDQ_SYNC_TOKEN_MSS 665 +#define CMDQ_SYNC_TOKEN_MSF 666 + +/* DISP sw token */ +#define CMDQ_SYNC_TOKEN_SODI 671 + +/* GPR access tokens (for register backup) + * There are 15 32-bit GPR, 3 GPR form a set + * (64-bit for address, 32-bit for value) + * MUST NOT CHANGE, these tokens sync with MDP + */ +#define CMDQ_SYNC_TOKEN_GPR_SET_0 700 +#define CMDQ_SYNC_TOKEN_GPR_SET_1 701 +#define CMDQ_SYNC_TOKEN_GPR_SET_2 702 +#define CMDQ_SYNC_TOKEN_GPR_SET_3 703 +#define CMDQ_SYNC_TOKEN_GPR_SET_4 704 + +/* Resource lock event to control resource in GCE thread */ +#define CMDQ_SYNC_RESOURCE_WROT0 710 +#define CMDQ_SYNC_RESOURCE_WROT1 711 + +/* event for gpr timer, used in sleep and poll with timeout */ +#define CMDQ_TOKEN_GPR_TIMER_R0 994 +#define CMDQ_TOKEN_GPR_TIMER_R1 995 +#define CMDQ_TOKEN_GPR_TIMER_R2 996 +#define CMDQ_TOKEN_GPR_TIMER_R3 997 +#define CMDQ_TOKEN_GPR_TIMER_R4 998 +#define CMDQ_TOKEN_GPR_TIMER_R5 999 +#define CMDQ_TOKEN_GPR_TIMER_R6 1000 +#define CMDQ_TOKEN_GPR_TIMER_R7 1001 +#define CMDQ_TOKEN_GPR_TIMER_R8 1002 +#define CMDQ_TOKEN_GPR_TIMER_R9 1003 +#define CMDQ_TOKEN_GPR_TIMER_R10 1004 +#define CMDQ_TOKEN_GPR_TIMER_R11 1005 +#define CMDQ_TOKEN_GPR_TIMER_R12 1006 +#define CMDQ_TOKEN_GPR_TIMER_R13 1007 +#define CMDQ_TOKEN_GPR_TIMER_R14 1008 +#define CMDQ_TOKEN_GPR_TIMER_R15 1009 + +#define CMDQ_EVENT_MAX 0x3FF +/* CMDQ sw tokens END */ + +#endif diff --git a/include/dt-bindings/gce/mt8192-gce.h b/include/dt-bindings/gce/mt8192-gce.h new file mode 100644 index 000000000000..9e5a0eb040a0 --- /dev/null +++ b/include/dt-bindings/gce/mt8192-gce.h @@ -0,0 +1,335 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 MediaTek Inc. + * Author: Yongqiang Niu <yongqiang.niu@mediatek.com> + */ + +#ifndef _DT_BINDINGS_GCE_MT8192_H +#define _DT_BINDINGS_GCE_MT8192_H + +/* assign timeout 0 also means default */ +#define CMDQ_NO_TIMEOUT 0xffffffff +#define CMDQ_TIMEOUT_DEFAULT 1000 + +/* GCE thread priority */ +#define CMDQ_THR_PRIO_LOWEST 0 +#define CMDQ_THR_PRIO_1 1 +#define CMDQ_THR_PRIO_2 2 +#define CMDQ_THR_PRIO_3 3 +#define CMDQ_THR_PRIO_4 4 +#define CMDQ_THR_PRIO_5 5 +#define CMDQ_THR_PRIO_6 6 +#define CMDQ_THR_PRIO_HIGHEST 7 + +/* CPR count in 32bit register */ +#define GCE_CPR_COUNT 1312 + +/* GCE subsys table */ +#define SUBSYS_1300XXXX 0 +#define SUBSYS_1400XXXX 1 +#define SUBSYS_1401XXXX 2 +#define SUBSYS_1402XXXX 3 +#define SUBSYS_1502XXXX 4 +#define SUBSYS_1880XXXX 5 +#define SUBSYS_1881XXXX 6 +#define SUBSYS_1882XXXX 7 +#define SUBSYS_1883XXXX 8 +#define SUBSYS_1884XXXX 9 +#define SUBSYS_1000XXXX 10 +#define SUBSYS_1001XXXX 11 +#define SUBSYS_1002XXXX 12 +#define SUBSYS_1003XXXX 13 +#define SUBSYS_1004XXXX 14 +#define SUBSYS_1005XXXX 15 +#define SUBSYS_1020XXXX 16 +#define SUBSYS_1028XXXX 17 +#define SUBSYS_1700XXXX 18 +#define SUBSYS_1701XXXX 19 +#define SUBSYS_1702XXXX 20 +#define SUBSYS_1703XXXX 21 +#define SUBSYS_1800XXXX 22 +#define SUBSYS_1801XXXX 23 +#define SUBSYS_1802XXXX 24 +#define SUBSYS_1804XXXX 25 +#define SUBSYS_1805XXXX 26 +#define SUBSYS_1808XXXX 27 +#define SUBSYS_180aXXXX 28 +#define SUBSYS_180bXXXX 29 + +#define CMDQ_EVENT_VDEC_LAT_SOF_0 0 +#define CMDQ_EVENT_VDEC_LAT_FRAME_DONE_0 1 +#define CMDQ_EVENT_VDEC_LAT_FRAME_DONE_1 2 +#define CMDQ_EVENT_VDEC_LAT_FRAME_DONE_2 3 +#define CMDQ_EVENT_VDEC_LAT_FRAME_DONE_3 4 +#define CMDQ_EVENT_VDEC_LAT_FRAME_DONE_4 5 +#define CMDQ_EVENT_VDEC_LAT_FRAME_DONE_5 6 +#define CMDQ_EVENT_VDEC_LAT_FRAME_DONE_6 7 +#define CMDQ_EVENT_VDEC_LAT_ENG_EVENT_0 8 +#define CMDQ_EVENT_VDEC_LAT_ENG_EVENT_1 9 +#define CMDQ_EVENT_VDEC_LAT_ENG_EVENT_2 10 +#define CMDQ_EVENT_VDEC_LAT_ENG_EVENT_3 11 +#define CMDQ_EVENT_VDEC_LAT_ENG_EVENT_4 12 +#define CMDQ_EVENT_VDEC_LAT_ENG_EVENT_5 13 +#define CMDQ_EVENT_VDEC_LAT_ENG_EVENT_6 14 +#define CMDQ_EVENT_VDEC_LAT_ENG_EVENT_7 15 + +#define CMDQ_EVENT_ISP_FRAME_DONE_A 65 +#define CMDQ_EVENT_ISP_FRAME_DONE_B 66 +#define CMDQ_EVENT_ISP_FRAME_DONE_C 67 +#define CMDQ_EVENT_CAMSV0_PASS1_DONE 68 +#define CMDQ_EVENT_CAMSV02_PASS1_DONE 69 +#define CMDQ_EVENT_CAMSV1_PASS1_DONE 70 +#define CMDQ_EVENT_CAMSV2_PASS1_DONE 71 +#define CMDQ_EVENT_CAMSV3_PASS1_DONE 72 +#define CMDQ_EVENT_MRAW_0_PASS1_DONE 73 +#define CMDQ_EVENT_MRAW_1_PASS1_DONE 74 +#define CMDQ_EVENT_SENINF_CAM0_FIFO_FULL 75 +#define CMDQ_EVENT_SENINF_CAM1_FIFO_FULL 76 +#define CMDQ_EVENT_SENINF_CAM2_FIFO_FULL 77 +#define CMDQ_EVENT_SENINF_CAM3_FIFO_FULL 78 +#define CMDQ_EVENT_SENINF_CAM4_FIFO_FULL 79 +#define CMDQ_EVENT_SENINF_CAM5_FIFO_FULL 80 +#define CMDQ_EVENT_SENINF_CAM6_FIFO_FULL 81 +#define CMDQ_EVENT_SENINF_CAM7_FIFO_FULL 82 +#define CMDQ_EVENT_SENINF_CAM8_FIFO_FULL 83 +#define CMDQ_EVENT_SENINF_CAM9_FIFO_FULL 84 +#define CMDQ_EVENT_SENINF_CAM10_FIFO_FULL 85 +#define CMDQ_EVENT_SENINF_CAM11_FIFO_FULL 86 +#define CMDQ_EVENT_SENINF_CAM12_FIFO_FULL 87 +#define CMDQ_EVENT_TG_OVRUN_A_INT 88 +#define CMDQ_EVENT_DMA_R1_ERROR_A_INT 89 +#define CMDQ_EVENT_TG_OVRUN_B_INT 90 +#define CMDQ_EVENT_DMA_R1_ERROR_B_INT 91 +#define CMDQ_EVENT_TG_OVRUN_C_INT 92 +#define CMDQ_EVENT_DMA_R1_ERROR_C_INT 93 +#define CMDQ_EVENT_TG_OVRUN_M0_INT 94 +#define CMDQ_EVENT_DMA_R1_ERROR_M0_INT 95 +#define CMDQ_EVENT_TG_GRABERR_M0_INT 96 +#define CMDQ_EVENT_TG_GRABERR_M1_INT 97 +#define CMDQ_EVENT_TG_GRABERR_A_INT 98 +#define CMDQ_EVENT_CQ_VR_SNAP_A_INT 99 +#define CMDQ_EVENT_TG_GRABERR_B_INT 100 +#define CMDQ_EVENT_CQ_VR_SNAP_B_INT 101 +#define CMDQ_EVENT_TG_GRABERR_C_INT 102 +#define CMDQ_EVENT_CQ_VR_SNAP_C_INT 103 + +#define CMDQ_EVENT_VENC_CMDQ_FRAME_DONE 129 +#define CMDQ_EVENT_VENC_CMDQ_PAUSE_DONE 130 +#define CMDQ_EVENT_JPGENC_CMDQ_DONE 131 +#define CMDQ_EVENT_VENC_CMDQ_MB_DONE 132 +#define CMDQ_EVENT_VENC_CMDQ_128BYTE_CNT_DONE 133 +#define CMDQ_EVENT_VENC_C0_CMDQ_WP_2ND_STAGE_DONE 134 +#define CMDQ_EVENT_VENC_C0_CMDQ_WP_3RD_STAGE_DONE 135 +#define CMDQ_EVENT_VENC_CMDQ_PPS_DONE 136 +#define CMDQ_EVENT_VENC_CMDQ_SPS_DONE 137 +#define CMDQ_EVENT_VENC_CMDQ_VPS_DONE 138 + +#define CMDQ_EVENT_VDEC_CORE0_SOF_0 160 +#define CMDQ_EVENT_VDEC_CORE0_FRAME_DONE_0 161 +#define CMDQ_EVENT_VDEC_CORE0_FRAME_DONE_1 162 +#define CMDQ_EVENT_VDEC_CORE0_FRAME_DONE_2 163 +#define CMDQ_EVENT_VDEC_CORE0_FRAME_DONE_3 164 +#define CMDQ_EVENT_VDEC_CORE0_FRAME_DONE_4 165 +#define CMDQ_EVENT_VDEC_CORE0_FRAME_DONE_5 166 +#define CMDQ_EVENT_VDEC_CORE0_FRAME_DONE_6 167 +#define CMDQ_EVENT_VDEC_CORE0_ENG_EVENT_0 168 +#define CMDQ_EVENT_VDEC_CORE0_ENG_EVENT_1 169 +#define CMDQ_EVENT_VDEC_CORE0_ENG_EVENT_2 170 +#define CMDQ_EVENT_VDEC_CORE0_ENG_EVENT_3 171 +#define CMDQ_EVENT_VDEC_CORE0_ENG_EVENT_4 172 +#define CMDQ_EVENT_VDEC_CORE0_ENG_EVENT_5 173 +#define CMDQ_EVENT_VDEC_CORE0_ENG_EVENT_6 174 +#define CMDQ_EVENT_VDEC_CORE0_ENG_EVENT_7 175 +#define CMDQ_EVENT_FDVT_DONE 177 +#define CMDQ_EVENT_FE_DONE 178 +#define CMDQ_EVENT_RSC_DONE 179 +#define CMDQ_EVENT_DVS_DONE_ASYNC_SHOT 180 +#define CMDQ_EVENT_DVP_DONE_ASYNC_SHOT 181 + +#define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_0 193 +#define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_1 194 +#define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_2 195 +#define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_3 196 +#define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_4 197 +#define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_5 198 +#define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_6 199 +#define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_7 200 +#define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_8 201 +#define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_9 202 +#define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_10 203 +#define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_11 204 +#define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_12 205 +#define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_13 206 +#define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_14 207 +#define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_15 208 +#define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_16 209 +#define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_17 210 +#define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_18 211 +#define CMDQ_EVENT_IMG2_DIP_DMA_ERR_EVENT 212 +#define CMDQ_EVENT_IMG2_AMD_FRAME_DONE 213 +#define CMDQ_EVENT_IMG2_MFB_DONE_LINK_MISC 214 +#define CMDQ_EVENT_IMG2_WPE_A_DONE_LINK_MISC 215 +#define CMDQ_EVENT_IMG2_MSS_DONE_LINK_MISC 216 + +#define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_0 225 +#define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_1 226 +#define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_2 227 +#define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_3 228 +#define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_4 229 +#define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_5 230 +#define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_6 231 +#define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_7 232 +#define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_8 233 +#define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_9 234 +#define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_10 235 +#define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_11 236 +#define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_12 237 +#define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_13 238 +#define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_14 239 +#define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_15 240 +#define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_16 241 +#define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_17 242 +#define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_18 243 +#define CMDQ_EVENT_IMG1_DIP_DMA_ERR_EVENT 244 +#define CMDQ_EVENT_IMG1_AMD_FRAME_DONE 245 +#define CMDQ_EVENT_IMG1_MFB_DONE_LINK_MISC 246 +#define CMDQ_EVENT_IMG1_WPE_A_DONE_LINK_MISC 247 +#define CMDQ_EVENT_IMG1_MSS_DONE_LINK_MISC 248 + +#define CMDQ_EVENT_MDP_RDMA0_SOF 256 +#define CMDQ_EVENT_MDP_RDMA1_SOF 257 +#define CMDQ_EVENT_MDP_AAL0_SOF 258 +#define CMDQ_EVENT_MDP_AAL1_SOF 259 +#define CMDQ_EVENT_MDP_HDR0_SOF 260 +#define CMDQ_EVENT_MDP_HDR1_SOF 261 +#define CMDQ_EVENT_MDP_RSZ0_SOF 262 +#define CMDQ_EVENT_MDP_RSZ1_SOF 263 +#define CMDQ_EVENT_MDP_WROT0_SOF 264 +#define CMDQ_EVENT_MDP_WROT1_SOF 265 +#define CMDQ_EVENT_MDP_TDSHP0_SOF 266 +#define CMDQ_EVENT_MDP_TDSHP1_SOF 267 +#define CMDQ_EVENT_IMG_DL_RELAY0_SOF 268 +#define CMDQ_EVENT_IMG_DL_RELAY1_SOF 269 +#define CMDQ_EVENT_MDP_COLOR0_SOF 270 +#define CMDQ_EVENT_MDP_COLOR1_SOF 271 +#define CMDQ_EVENT_MDP_WROT1_FRAME_DONE 290 +#define CMDQ_EVENT_MDP_WROT0_FRAME_DONE 291 +#define CMDQ_EVENT_MDP_TDSHP1_FRAME_DONE 294 +#define CMDQ_EVENT_MDP_TDSHP0_FRAME_DONE 295 +#define CMDQ_EVENT_MDP_RSZ1_FRAME_DONE 302 +#define CMDQ_EVENT_MDP_RSZ0_FRAME_DONE 303 +#define CMDQ_EVENT_MDP_RDMA1_FRAME_DONE 306 +#define CMDQ_EVENT_MDP_RDMA0_FRAME_DONE 307 +#define CMDQ_EVENT_MDP_HDR1_FRAME_DONE 308 +#define CMDQ_EVENT_MDP_HDR0_FRAME_DONE 309 +#define CMDQ_EVENT_MDP_COLOR1_FRAME_DONE 312 +#define CMDQ_EVENT_MDP_COLOR0_FRAME_DONE 313 +#define CMDQ_EVENT_MDP_AAL1_FRAME_DONE 316 +#define CMDQ_EVENT_MDP_AAL0_FRAME_DONE 317 +#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_0 320 +#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_1 321 +#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_2 322 +#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_3 323 +#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_4 324 +#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_5 325 +#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_6 326 +#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_7 327 +#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_8 328 +#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_9 329 +#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_10 330 +#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_11 331 +#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_12 332 +#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_13 333 +#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_14 334 +#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_15 335 +#define CMDQ_EVENT_MDP_WROT1_SW_RST_DONE_ENG_EVENT 338 +#define CMDQ_EVENT_MDP_WROT0_SW_RST_DONE_ENG_EVENT 339 +#define CMDQ_EVENT_MDP_RDMA1_SW_RST_DONE_ENG_EVENT 342 +#define CMDQ_EVENT_MDP_RDMA0_SW_RST_DONE_ENG_EVENT 343 + +#define CMDQ_EVENT_DISP_OVL0_SOF 384 +#define CMDQ_EVENT_DISP_OVL0_2L_SOF 385 +#define CMDQ_EVENT_DISP_RDMA0_SOF 386 +#define CMDQ_EVENT_DISP_RSZ0_SOF 387 +#define CMDQ_EVENT_DISP_COLOR0_SOF 388 +#define CMDQ_EVENT_DISP_CCORR0_SOF 389 +#define CMDQ_EVENT_DISP_AAL0_SOF 390 +#define CMDQ_EVENT_DISP_GAMMA0_SOF 391 +#define CMDQ_EVENT_DISP_POSTMASK0_SOF 392 +#define CMDQ_EVENT_DISP_DITHER0_SOF 393 +#define CMDQ_EVENT_DISP_DSC_WRAP0_CORE0_SOF 394 +#define CMDQ_EVENT_DISP_DSC_WRAP0_CORE1_SOF 395 +#define CMDQ_EVENT_DSI0_SOF 396 +#define CMDQ_EVENT_DISP_WDMA0_SOF 397 +#define CMDQ_EVENT_DISP_UFBC_WDMA0_SOF 398 +#define CMDQ_EVENT_DISP_PWM0_SOF 399 +#define CMDQ_EVENT_DISP_OVL2_2L_SOF 400 +#define CMDQ_EVENT_DISP_RDMA4_SOF 401 +#define CMDQ_EVENT_DISP_DPI0_SOF 402 +#define CMDQ_EVENT_MDP_RDMA4_SOF 403 +#define CMDQ_EVENT_MDP_HDR4_SOF 404 +#define CMDQ_EVENT_MDP_RSZ4_SOF 405 +#define CMDQ_EVENT_MDP_AAL4_SOF 406 +#define CMDQ_EVENT_MDP_TDSHP4_SOF 407 +#define CMDQ_EVENT_MDP_COLOR4_SOF 408 +#define CMDQ_EVENT_DISP_Y2R0_SOF 409 +#define CMDQ_EVENT_MDP_TDSHP4_FRAME_DONE 410 +#define CMDQ_EVENT_MDP_RSZ4_FRAME_DONE 411 +#define CMDQ_EVENT_MDP_RDMA4_FRAME_DONE 412 +#define CMDQ_EVENT_MDP_HDR4_FRAME_DONE 413 +#define CMDQ_EVENT_MDP_COLOR4_FRAME_DONE 414 +#define CMDQ_EVENT_MDP_AAL4_FRAME_DONE 415 +#define CMDQ_EVENT_DSI0_FRAME_DONE 416 +#define CMDQ_EVENT_DISP_WDMA0_FRAME_DONE 417 +#define CMDQ_EVENT_DISP_UFBC_WDMA0_FRAME_DONE 418 +#define CMDQ_EVENT_DISP_RSZ0_FRAME_DONE 419 +#define CMDQ_EVENT_DISP_RDMA4_FRAME_DONE 420 +#define CMDQ_EVENT_DISP_RDMA0_FRAME_DONE 421 +#define CMDQ_EVENT_DISP_POSTMASK0_FRAME_DONE 422 +#define CMDQ_EVENT_DISP_OVL2_2L_FRAME_DONE 423 +#define CMDQ_EVENT_DISP_OVL0_FRAME_DONE 424 +#define CMDQ_EVENT_DISP_OVL0_2L_FRAME_DONE 425 +#define CMDQ_EVENT_DISP_GAMMA0_FRAME_DONE 426 +#define CMDQ_EVENT_DISP_DSC_WRAP0_CORE1_FRAME_DONE 427 +#define CMDQ_EVENT_DISP_DSC_WRAP0_CORE0_FRAME_DONE 428 +#define CMDQ_EVENT_DISP_DPI0_FRAME_DONE 429 +#define CMDQ_EVENT_DISP_DITHER0_FRAME_DONE 430 +#define CMDQ_EVENT_DISP_COLOR0_FRAME_DONE 431 +#define CMDQ_EVENT_DISP_CCORR0_FRAME_DONE 432 +#define CMDQ_EVENT_DISP_AAL0_FRAME_DONE 433 +#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0 434 +#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1 435 +#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_2 436 +#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_3 437 +#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_4 438 +#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_5 439 +#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_6 440 +#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_7 441 +#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_8 442 +#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_9 443 +#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_10 444 +#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_11 445 +#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_12 446 +#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_13 447 +#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_14 448 +#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_15 449 +#define CMDQ_EVENT_DSI0_TE_ENG_EVENT 450 +#define CMDQ_EVENT_DSI0_IRQ_ENG_EVENT 451 +#define CMDQ_EVENT_DSI0_DONE_ENG_EVENT 452 +#define CMDQ_EVENT_DISP_WDMA0_SW_RST_DONE_ENG_EVENT 453 +#define CMDQ_EVENT_DISP_SMIASSERT_ENG_EVENT 454 +#define CMDQ_EVENT_DISP_POSTMASK0_RST_DONE_ENG_EVENT 455 +#define CMDQ_EVENT_DISP_OVL2_2L_RST_DONE_ENG_EVENT 456 +#define CMDQ_EVENT_DISP_OVL0_RST_DONE_ENG_EVENT 457 +#define CMDQ_EVENT_DISP_OVL0_2L_RST_DONE_ENG_EVENT 458 +#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_0 459 +#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_1 460 +#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_2 461 +#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_3 462 +#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_4 463 +#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_5 464 +#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_6 465 +#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_7 466 +#define CMDQ_MAX_HW_EVENT 512 + +#endif diff --git a/include/dt-bindings/gce/mt8195-gce.h b/include/dt-bindings/gce/mt8195-gce.h new file mode 100644 index 000000000000..dcfb302b8a5b --- /dev/null +++ b/include/dt-bindings/gce/mt8195-gce.h @@ -0,0 +1,812 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2021 MediaTek Inc. + * Author: Jason-JH Lin <jason0jh.lin@mediatek.com> + */ + +#ifndef _DT_BINDINGS_GCE_MT8195_H +#define _DT_BINDINGS_GCE_MT8195_H + +/* assign timeout 0 also means default */ +#define CMDQ_NO_TIMEOUT 0xffffffff +#define CMDQ_TIMEOUT_DEFAULT 1000 + +/* GCE thread priority */ +#define CMDQ_THR_PRIO_LOWEST 0 +#define CMDQ_THR_PRIO_1 1 +#define CMDQ_THR_PRIO_2 2 +#define CMDQ_THR_PRIO_3 3 +#define CMDQ_THR_PRIO_4 4 +#define CMDQ_THR_PRIO_5 5 +#define CMDQ_THR_PRIO_6 6 +#define CMDQ_THR_PRIO_HIGHEST 7 + +/* CPR count in 32bit register */ +#define GCE_CPR_COUNT 1312 + +/* GCE subsys table */ +#define SUBSYS_1400XXXX 0 +#define SUBSYS_1401XXXX 1 +#define SUBSYS_1402XXXX 2 +#define SUBSYS_1c00XXXX 3 +#define SUBSYS_1c01XXXX 4 +#define SUBSYS_1c02XXXX 5 +#define SUBSYS_1c10XXXX 6 +#define SUBSYS_1c11XXXX 7 +#define SUBSYS_1c12XXXX 8 +#define SUBSYS_14f0XXXX 9 +#define SUBSYS_14f1XXXX 10 +#define SUBSYS_14f2XXXX 11 +#define SUBSYS_1800XXXX 12 +#define SUBSYS_1801XXXX 13 +#define SUBSYS_1802XXXX 14 +#define SUBSYS_1803XXXX 15 +#define SUBSYS_1032XXXX 16 +#define SUBSYS_1033XXXX 17 +#define SUBSYS_1600XXXX 18 +#define SUBSYS_1601XXXX 19 +#define SUBSYS_14e0XXXX 20 +#define SUBSYS_1c20XXXX 21 +#define SUBSYS_1c30XXXX 22 +#define SUBSYS_1c40XXXX 23 +#define SUBSYS_1c50XXXX 24 +#define SUBSYS_1c60XXXX 25 + +/* GCE General Purpose Register (GPR) support */ +#define GCE_GPR_R00 0x0 +#define GCE_GPR_R01 0x1 +#define GCE_GPR_R02 0x2 +#define GCE_GPR_R03 0x3 +#define GCE_GPR_R04 0x4 +#define GCE_GPR_R05 0x5 +#define GCE_GPR_R06 0x6 +#define GCE_GPR_R07 0x7 +#define GCE_GPR_R08 0x8 +#define GCE_GPR_R09 0x9 +#define GCE_GPR_R10 0xa +#define GCE_GPR_R11 0xb +#define GCE_GPR_R12 0xc +#define GCE_GPR_R13 0xd +#define GCE_GPR_R14 0xe +#define GCE_GPR_R15 0xf + +/* GCE hw event id */ +#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_0 1 +#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_1 2 +#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_2 3 +#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_3 4 +#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_4 5 +#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_5 6 +#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_6 7 +#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_7 8 +#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_8 9 +#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_9 10 +#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_10 11 +#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_11 12 +#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_12 13 +#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_13 14 +#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_14 15 +#define CMDQ_EVENT_TRAW0_DMA_ERROR_INT 16 +#define CMDQ_EVENT_CQ_THR_DONE_TRAW1_0 17 +#define CMDQ_EVENT_CQ_THR_DONE_TRAW1_1 18 +#define CMDQ_EVENT_CQ_THR_DONE_TRAW1_2 19 +#define CMDQ_EVENT_CQ_THR_DONE_TRAW1_3 20 +#define CMDQ_EVENT_CQ_THR_DONE_TRAW1_4 21 +#define CMDQ_EVENT_CQ_THR_DONE_TRAW1_5 22 +#define CMDQ_EVENT_CQ_THR_DONE_TRAW1_6 23 +#define CMDQ_EVENT_CQ_THR_DONE_TRAW1_7 24 +#define CMDQ_EVENT_CQ_THR_DONE_TRAW1_8 25 +#define CMDQ_EVENT_CQ_THR_DONE_TRAW1_9 26 +#define CMDQ_EVENT_CQ_THR_DONE_TRAW1_10 27 +#define CMDQ_EVENT_CQ_THR_DONE_TRAW1_11 28 +#define CMDQ_EVENT_CQ_THR_DONE_TRAW1_12 29 +#define CMDQ_EVENT_CQ_THR_DONE_TRAW1_13 30 +#define CMDQ_EVENT_CQ_THR_DONE_TRAW1_14 31 +#define CMDQ_EVENT_TRAW1_DMA_ERROR_INT 32 + +#define CMDQ_EVENT_DIP0_FRAME_DONE_P2_0 65 +#define CMDQ_EVENT_DIP0_FRAME_DONE_P2_1 66 +#define CMDQ_EVENT_DIP0_FRAME_DONE_P2_2 67 +#define CMDQ_EVENT_DIP0_FRAME_DONE_P2_3 68 +#define CMDQ_EVENT_DIP0_FRAME_DONE_P2_4 69 +#define CMDQ_EVENT_DIP0_FRAME_DONE_P2_5 70 +#define CMDQ_EVENT_DIP0_FRAME_DONE_P2_6 71 +#define CMDQ_EVENT_DIP0_FRAME_DONE_P2_7 72 +#define CMDQ_EVENT_DIP0_FRAME_DONE_P2_8 73 +#define CMDQ_EVENT_DIP0_FRAME_DONE_P2_9 74 +#define CMDQ_EVENT_DIP0_FRAME_DONE_P2_10 75 +#define CMDQ_EVENT_DIP0_FRAME_DONE_P2_11 76 +#define CMDQ_EVENT_DIP0_FRAME_DONE_P2_12 77 +#define CMDQ_EVENT_DIP0_FRAME_DONE_P2_13 78 +#define CMDQ_EVENT_DIP0_FRAME_DONE_P2_14 79 +#define CMDQ_EVENT_DIP0_DMA_ERR 80 +#define CMDQ_EVENT_PQA0_FRAME_DONE_P2_0 81 +#define CMDQ_EVENT_PQA0_FRAME_DONE_P2_1 82 +#define CMDQ_EVENT_PQA0_FRAME_DONE_P2_2 83 +#define CMDQ_EVENT_PQA0_FRAME_DONE_P2_3 84 +#define CMDQ_EVENT_PQA0_FRAME_DONE_P2_4 85 +#define CMDQ_EVENT_PQA0_FRAME_DONE_P2_5 86 +#define CMDQ_EVENT_PQA0_FRAME_DONE_P2_6 87 +#define CMDQ_EVENT_PQA0_FRAME_DONE_P2_7 88 +#define CMDQ_EVENT_PQA0_FRAME_DONE_P2_8 89 +#define CMDQ_EVENT_PQA0_FRAME_DONE_P2_9 90 +#define CMDQ_EVENT_PQA0_FRAME_DONE_P2_10 91 +#define CMDQ_EVENT_PQA0_FRAME_DONE_P2_11 92 +#define CMDQ_EVENT_PQA0_FRAME_DONE_P2_12 93 +#define CMDQ_EVENT_PQA0_FRAME_DONE_P2_13 94 +#define CMDQ_EVENT_PQA0_FRAME_DONE_P2_14 95 +#define CMDQ_EVENT_PQA0_DMA_ERR 96 +#define CMDQ_EVENT_PQB0_FRAME_DONE_P2_0 97 +#define CMDQ_EVENT_PQB0_FRAME_DONE_P2_1 98 +#define CMDQ_EVENT_PQB0_FRAME_DONE_P2_2 99 +#define CMDQ_EVENT_PQB0_FRAME_DONE_P2_3 100 +#define CMDQ_EVENT_PQB0_FRAME_DONE_P2_4 101 +#define CMDQ_EVENT_PQB0_FRAME_DONE_P2_5 102 +#define CMDQ_EVENT_PQB0_FRAME_DONE_P2_6 103 +#define CMDQ_EVENT_PQB0_FRAME_DONE_P2_7 104 +#define CMDQ_EVENT_PQB0_FRAME_DONE_P2_8 105 +#define CMDQ_EVENT_PQB0_FRAME_DONE_P2_9 106 +#define CMDQ_EVENT_PQB0_FRAME_DONE_P2_10 107 +#define CMDQ_EVENT_PQB0_FRAME_DONE_P2_11 108 +#define CMDQ_EVENT_PQB0_FRAME_DONE_P2_12 109 +#define CMDQ_EVENT_PQB0_FRAME_DONE_P2_13 110 +#define CMDQ_EVENT_PQB0_FRAME_DONE_P2_14 111 +#define CMDQ_EVENT_PQB0_DMA_ERR 112 +#define CMDQ_EVENT_DIP0_DUMMY_0 113 +#define CMDQ_EVENT_DIP0_DUMMY_1 114 +#define CMDQ_EVENT_DIP0_DUMMY_2 115 +#define CMDQ_EVENT_DIP0_DUMMY_3 116 +#define CMDQ_EVENT_WPE0_EIS_GCE_FRAME_DONE 117 +#define CMDQ_EVENT_WPE0_EIS_DONE_SYNC_OUT 118 +#define CMDQ_EVENT_WPE0_TNR_GCE_FRAME_DONE 119 +#define CMDQ_EVENT_WPE0_TNR_DONE_SYNC_OUT 120 +#define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_0 121 +#define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_1 122 +#define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_2 123 +#define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_3 124 +#define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_4 125 +#define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_5 126 +#define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_6 127 +#define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_7 128 +#define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_8 129 +#define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_9 130 +#define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_10 131 +#define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_11 132 +#define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_12 133 +#define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_13 134 +#define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_14 135 +#define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_0 136 +#define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_1 137 +#define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_2 138 +#define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_3 139 +#define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_4 140 +#define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_5 141 +#define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_6 142 +#define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_7 143 +#define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_8 144 +#define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_9 145 +#define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_10 146 +#define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_11 147 +#define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_12 148 +#define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_13 149 +#define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_14 150 +#define CMDQ_EVENT_WPE0_DUMMY_0 151 +#define CMDQ_EVENT_IMGSYS_IPE_DUMMY 152 +#define CMDQ_EVENT_IMGSYS_IPE_FDVT_DONE 153 +#define CMDQ_EVENT_IMGSYS_IPE_ME_DONE 154 +#define CMDQ_EVENT_IMGSYS_IPE_DVS_DONE 155 +#define CMDQ_EVENT_IMGSYS_IPE_DVP_DONE 156 + +#define CMDQ_EVENT_TPR_0 194 +#define CMDQ_EVENT_TPR_1 195 +#define CMDQ_EVENT_TPR_2 196 +#define CMDQ_EVENT_TPR_3 197 +#define CMDQ_EVENT_TPR_4 198 +#define CMDQ_EVENT_TPR_5 199 +#define CMDQ_EVENT_TPR_6 200 +#define CMDQ_EVENT_TPR_7 201 +#define CMDQ_EVENT_TPR_8 202 +#define CMDQ_EVENT_TPR_9 203 +#define CMDQ_EVENT_TPR_10 204 +#define CMDQ_EVENT_TPR_11 205 +#define CMDQ_EVENT_TPR_12 206 +#define CMDQ_EVENT_TPR_13 207 +#define CMDQ_EVENT_TPR_14 208 +#define CMDQ_EVENT_TPR_15 209 +#define CMDQ_EVENT_TPR_16 210 +#define CMDQ_EVENT_TPR_17 211 +#define CMDQ_EVENT_TPR_18 212 +#define CMDQ_EVENT_TPR_19 213 +#define CMDQ_EVENT_TPR_20 214 +#define CMDQ_EVENT_TPR_21 215 +#define CMDQ_EVENT_TPR_22 216 +#define CMDQ_EVENT_TPR_23 217 +#define CMDQ_EVENT_TPR_24 218 +#define CMDQ_EVENT_TPR_25 219 +#define CMDQ_EVENT_TPR_26 220 +#define CMDQ_EVENT_TPR_27 221 +#define CMDQ_EVENT_TPR_28 222 +#define CMDQ_EVENT_TPR_29 223 +#define CMDQ_EVENT_TPR_30 224 +#define CMDQ_EVENT_TPR_31 225 +#define CMDQ_EVENT_TPR_TIMEOUT_0 226 +#define CMDQ_EVENT_TPR_TIMEOUT_1 227 +#define CMDQ_EVENT_TPR_TIMEOUT_2 228 +#define CMDQ_EVENT_TPR_TIMEOUT_3 229 +#define CMDQ_EVENT_TPR_TIMEOUT_4 230 +#define CMDQ_EVENT_TPR_TIMEOUT_5 231 +#define CMDQ_EVENT_TPR_TIMEOUT_6 232 +#define CMDQ_EVENT_TPR_TIMEOUT_7 233 +#define CMDQ_EVENT_TPR_TIMEOUT_8 234 +#define CMDQ_EVENT_TPR_TIMEOUT_9 235 +#define CMDQ_EVENT_TPR_TIMEOUT_10 236 +#define CMDQ_EVENT_TPR_TIMEOUT_11 237 +#define CMDQ_EVENT_TPR_TIMEOUT_12 238 +#define CMDQ_EVENT_TPR_TIMEOUT_13 239 +#define CMDQ_EVENT_TPR_TIMEOUT_14 240 +#define CMDQ_EVENT_TPR_TIMEOUT_15 241 + +#define CMDQ_EVENT_VPP0_MDP_RDMA_SOF 256 +#define CMDQ_EVENT_VPP0_MDP_FG_SOF 257 +#define CMDQ_EVENT_VPP0_STITCH_SOF 258 +#define CMDQ_EVENT_VPP0_MDP_HDR_SOF 259 +#define CMDQ_EVENT_VPP0_MDP_AAL_SOF 260 +#define CMDQ_EVENT_VPP0_MDP_RSZ_IN_RSZ_SOF 261 +#define CMDQ_EVENT_VPP0_MDP_TDSHP_SOF 262 +#define CMDQ_EVENT_VPP0_DISP_COLOR_SOF 263 +#define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_SOF 264 +#define CMDQ_EVENT_VPP0_VPP_PADDING_IN_PADDING_SOF 265 +#define CMDQ_EVENT_VPP0_MDP_TCC_IN_SOF 266 +#define CMDQ_EVENT_VPP0_MDP_WROT_SOF 267 + +#define CMDQ_EVENT_VPP0_WARP0_MMSYS_TOP_RELAY_SOF_PRE 269 +#define CMDQ_EVENT_VPP0_WARP1_MMSYS_TOP_RELAY_SOF_PRE 270 +#define CMDQ_EVENT_VPP0_VPP1_MMSYS_TOP_RELAY_SOF 271 +#define CMDQ_EVENT_VPP0_VPP1_IN_MMSYS_TOP_RELAY_SOF_PRE 272 + +#define CMDQ_EVENT_VPP0_MDP_RDMA_FRAME_DONE 288 +#define CMDQ_EVENT_VPP0_MDP_FG_TILE_DONE 289 +#define CMDQ_EVENT_VPP0_STITCH_FRAME_DONE 290 +#define CMDQ_EVENT_VPP0_MDP_HDR_FRAME_DONE 291 +#define CMDQ_EVENT_VPP0_MDP_AAL_FRAME_DONE 292 +#define CMDQ_EVENT_VPP0_MDP_RSZ_FRAME_DONE 293 +#define CMDQ_EVENT_VPP0_MDP_TDSHP_FRAME_DONE 294 +#define CMDQ_EVENT_VPP0_DISP_COLOR_FRAME_DONE 295 +#define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_FRAME_DONE 296 +#define CMDQ_EVENT_VPP0_VPP_PADDING_IN_PADDING_FRAME_DONE 297 +#define CMDQ_EVENT_VPP0_MDP_TCC_TCC_FRAME_DONE 298 +#define CMDQ_EVENT_VPP0_MDP_WROT_VIDO_WDONE 299 + +#define CMDQ_EVENT_VPP0_STREAM_DONE_0 320 +#define CMDQ_EVENT_VPP0_STREAM_DONE_1 321 +#define CMDQ_EVENT_VPP0_STREAM_DONE_2 322 +#define CMDQ_EVENT_VPP0_STREAM_DONE_3 323 +#define CMDQ_EVENT_VPP0_STREAM_DONE_4 324 +#define CMDQ_EVENT_VPP0_STREAM_DONE_5 325 +#define CMDQ_EVENT_VPP0_STREAM_DONE_6 326 +#define CMDQ_EVENT_VPP0_STREAM_DONE_7 327 +#define CMDQ_EVENT_VPP0_STREAM_DONE_8 328 +#define CMDQ_EVENT_VPP0_STREAM_DONE_9 329 +#define CMDQ_EVENT_VPP0_STREAM_DONE_10 330 +#define CMDQ_EVENT_VPP0_STREAM_DONE_11 331 +#define CMDQ_EVENT_VPP0_STREAM_DONE_12 332 +#define CMDQ_EVENT_VPP0_STREAM_DONE_13 333 +#define CMDQ_EVENT_VPP0_STREAM_DONE_14 334 +#define CMDQ_EVENT_VPP0_STREAM_DONE_15 335 +#define CMDQ_EVENT_VPP0_BUF_UNDERRUN_0 336 +#define CMDQ_EVENT_VPP0_BUF_UNDERRUN_1 337 +#define CMDQ_EVENT_VPP0_BUF_UNDERRUN_2 338 +#define CMDQ_EVENT_VPP0_BUF_UNDERRUN_3 339 +#define CMDQ_EVENT_VPP0_BUF_UNDERRUN_4 340 +#define CMDQ_EVENT_VPP0_BUF_UNDERRUN_5 341 +#define CMDQ_EVENT_VPP0_BUF_UNDERRUN_6 342 +#define CMDQ_EVENT_VPP0_BUF_UNDERRUN_7 343 +#define CMDQ_EVENT_VPP0_BUF_UNDERRUN_8 344 +#define CMDQ_EVENT_VPP0_BUF_UNDERRUN_9 345 +#define CMDQ_EVENT_VPP0_BUF_UNDERRUN_10 346 +#define CMDQ_EVENT_VPP0_BUF_UNDERRUN_11 347 +#define CMDQ_EVENT_VPP0_BUF_UNDERRUN_12 348 +#define CMDQ_EVENT_VPP0_BUF_UNDERRUN_13 349 +#define CMDQ_EVENT_VPP0_BUF_UNDERRUN_14 350 +#define CMDQ_EVENT_VPP0_BUF_UNDERRUN_15 351 +#define CMDQ_EVENT_VPP0_MDP_RDMA_SW_RST_DONE 352 +#define CMDQ_EVENT_VPP0_MDP_RDMA_PM_VALID 353 +#define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_FRAME_RESET_DONE_PULSE 354 +#define CMDQ_EVENT_VPP0_MDP_WROT_SW_RST_DONE 355 + +#define CMDQ_EVENT_VPP1_HDMI_META_SOF 384 +#define CMDQ_EVENT_VPP1_DGI_SOF 385 +#define CMDQ_EVENT_VPP1_VPP_SPLIT_SOF 386 +#define CMDQ_EVENT_VPP1_SVPP1_MDP_TCC_SOF 387 +#define CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_SOF 388 +#define CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_SOF 389 +#define CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_SOF 390 +#define CMDQ_EVENT_VPP1_SVPP1_MDP_FG_SOF 391 +#define CMDQ_EVENT_VPP1_SVPP2_MDP_FG_SOF 392 +#define CMDQ_EVENT_VPP1_SVPP3_MDP_FG_SOF 393 +#define CMDQ_EVENT_VPP1_SVPP1_MDP_HDR_SOF 394 +#define CMDQ_EVENT_VPP1_SVPP2_MDP_HDR_SOF 395 +#define CMDQ_EVENT_VPP1_SVPP3_MDP_HDR_SOF 396 +#define CMDQ_EVENT_VPP1_SVPP1_MDP_AAL_SOF 397 +#define CMDQ_EVENT_VPP1_SVPP2_MDP_AAL_SOF 398 +#define CMDQ_EVENT_VPP1_SVPP3_MDP_AAL_SOF 399 +#define CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_SOF 400 +#define CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_SOF 401 +#define CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_SOF 402 +#define CMDQ_EVENT_VPP1_SVPP1_TDSHP_SOF 403 +#define CMDQ_EVENT_VPP1_SVPP2_TDSHP_SOF 404 +#define CMDQ_EVENT_VPP1_SVPP3_TDSHP_SOF 405 +#define CMDQ_EVENT_VPP1_SVPP2_VPP_MERGE_SOF 406 +#define CMDQ_EVENT_VPP1_SVPP3_VPP_MERGE_SOF 407 +#define CMDQ_EVENT_VPP1_SVPP1_MDP_COLOR_SOF 408 +#define CMDQ_EVENT_VPP1_SVPP2_MDP_COLOR_SOF 409 +#define CMDQ_EVENT_VPP1_SVPP3_MDP_COLOR_SOF 410 +#define CMDQ_EVENT_VPP1_SVPP1_MDP_OVL_SOF 411 +#define CMDQ_EVENT_VPP1_SVPP1_VPP_PAD_SOF 412 +#define CMDQ_EVENT_VPP1_SVPP2_VPP_PAD_SOF 413 +#define CMDQ_EVENT_VPP1_SVPP3_VPP_PAD_SOF 414 +#define CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_SOF 415 +#define CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_SOF 416 +#define CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_SOF 417 +#define CMDQ_EVENT_VPP1_VPP0_DL_IRLY_SOF 418 +#define CMDQ_EVENT_VPP1_VPP0_DL_ORLY_SOF 419 +#define CMDQ_EVENT_VPP1_VDO0_DL_ORLY_0_SOF 420 +#define CMDQ_EVENT_VPP1_VDO0_DL_ORLY_1_SOF 421 +#define CMDQ_EVENT_VPP1_VDO1_DL_ORLY_0_SOF 422 +#define CMDQ_EVENT_VPP1_VDO1_DL_ORLY_1_SOF 423 +#define CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_FRAME_DONE 424 +#define CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_FRAME_DONE 425 +#define CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_FRAME_DONE 426 +#define CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_FRAME_DONE 427 +#define CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_FRAME_DONE 428 +#define CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_FRAME_DONE 429 +#define CMDQ_EVENT_VPP1_SVPP1_MDP_OVL_FRAME_DONE 430 +#define CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_FRAME_DONE 431 +#define CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_FRAME_DONE 432 +#define CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_FRAME_DONE 433 +#define CMDQ_EVENT_VPP1_FRAME_DONE_10 434 +#define CMDQ_EVENT_VPP1_FRAME_DONE_11 435 +#define CMDQ_EVENT_VPP1_FRAME_DONE_12 436 +#define CMDQ_EVENT_VPP1_FRAME_DONE_13 437 +#define CMDQ_EVENT_VPP1_FRAME_DONE_14 438 +#define CMDQ_EVENT_VPP1_STREAM_DONE_0 439 +#define CMDQ_EVENT_VPP1_STREAM_DONE_1 440 +#define CMDQ_EVENT_VPP1_STREAM_DONE_2 441 +#define CMDQ_EVENT_VPP1_STREAM_DONE_3 442 +#define CMDQ_EVENT_VPP1_STREAM_DONE_4 443 +#define CMDQ_EVENT_VPP1_STREAM_DONE_5 444 +#define CMDQ_EVENT_VPP1_STREAM_DONE_6 445 +#define CMDQ_EVENT_VPP1_STREAM_DONE_7 446 +#define CMDQ_EVENT_VPP1_STREAM_DONE_8 447 +#define CMDQ_EVENT_VPP1_STREAM_DONE_9 448 +#define CMDQ_EVENT_VPP1_STREAM_DONE_10 449 +#define CMDQ_EVENT_VPP1_STREAM_DONE_11 450 +#define CMDQ_EVENT_VPP1_STREAM_DONE_12 451 +#define CMDQ_EVENT_VPP1_STREAM_DONE_13 452 +#define CMDQ_EVENT_VPP1_STREAM_DONE_14 453 +#define CMDQ_EVENT_VPP1_STREAM_DONE_15 454 +#define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_0 455 +#define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_1 456 +#define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_2 457 +#define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_3 458 +#define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_4 459 +#define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_5 460 +#define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_6 461 +#define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_7 462 +#define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_8 463 +#define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_9 464 +#define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_10 465 +#define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_11 466 +#define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_12 467 +#define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_13 468 +#define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_14 469 +#define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_15 470 +#define CMDQ_EVENT_VPP1_DGI_0 471 +#define CMDQ_EVENT_VPP1_DGI_1 472 +#define CMDQ_EVENT_VPP1_DGI_2 473 +#define CMDQ_EVENT_VPP1_DGI_3 474 +#define CMDQ_EVENT_VPP1_DGI_4 475 +#define CMDQ_EVENT_VPP1_DGI_5 476 +#define CMDQ_EVENT_VPP1_DGI_6 477 +#define CMDQ_EVENT_VPP1_DGI_7 478 +#define CMDQ_EVENT_VPP1_DGI_8 479 +#define CMDQ_EVENT_VPP1_DGI_9 480 +#define CMDQ_EVENT_VPP1_DGI_10 481 +#define CMDQ_EVENT_VPP1_DGI_11 482 +#define CMDQ_EVENT_VPP1_DGI_12 483 +#define CMDQ_EVENT_VPP1_DGI_13 484 +#define CMDQ_EVENT_VPP1_SVPP3_VPP_MERGE 485 +#define CMDQ_EVENT_VPP1_SVPP2_VPP_MERGE 486 +#define CMDQ_EVENT_VPP1_MDP_OVL_FRAME_RESET_DONE_PULSE 487 +#define CMDQ_EVENT_VPP1_VPP_SPLIT_DGI 488 +#define CMDQ_EVENT_VPP1_VPP_SPLIT_HDMI 489 +#define CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_SW_RST_DONE 490 +#define CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_SW_RST_DONE 491 +#define CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_SW_RST_DONE 492 +#define CMDQ_EVENT_VPP1_SVPP3_MDP_FG_TILE_DONE 493 +#define CMDQ_EVENT_VPP1_SVPP2_MDP_FG_TILE_DONE 494 +#define CMDQ_EVENT_VPP1_SVPP1_MDP_FG_TILE_DONE 495 + +#define CMDQ_EVENT_VDO0_DISP_OVL0_SOF 512 +#define CMDQ_EVENT_VDO0_DISP_WDMA0_SOF 513 +#define CMDQ_EVENT_VDO0_DISP_RDMA0_SOF 514 +#define CMDQ_EVENT_VDO0_DISP_COLOR0_SOF 515 +#define CMDQ_EVENT_VDO0_DISP_CCORR0_SOF 516 +#define CMDQ_EVENT_VDO0_DISP_AAL0_SOF 517 +#define CMDQ_EVENT_VDO0_DISP_GAMMA0_SOF 518 +#define CMDQ_EVENT_VDO0_DISP_DITHER0_SOF 519 +#define CMDQ_EVENT_VDO0_DSI0_SOF 520 +#define CMDQ_EVENT_VDO0_DSC_WRAP0C0_SOF 521 +#define CMDQ_EVENT_VDO0_DISP_OVL1_SOF 522 +#define CMDQ_EVENT_VDO0_DISP_WDMA1_SOF 523 +#define CMDQ_EVENT_VDO0_DISP_RDMA1_SOF 524 +#define CMDQ_EVENT_VDO0_DISP_COLOR1_SOF 525 +#define CMDQ_EVENT_VDO0_DISP_CCORR1_SOF 526 +#define CMDQ_EVENT_VDO0_DISP_AAL1_SOF 527 +#define CMDQ_EVENT_VDO0_DISP_GAMMA1_SOF 528 +#define CMDQ_EVENT_VDO0_DISP_DITHER1_SOF 529 +#define CMDQ_EVENT_VDO0_DSI1_SOF 530 +#define CMDQ_EVENT_VDO0_DSC_WRAP0C1_SOF 531 +#define CMDQ_EVENT_VDO0_VPP_MERGE0_SOF 532 +#define CMDQ_EVENT_VDO0_DP_INTF0_SOF 533 +#define CMDQ_EVENT_VDO0_VPP1_DL_RELAY0_SOF 534 +#define CMDQ_EVENT_VDO0_VPP1_DL_RELAY1_SOF 535 +#define CMDQ_EVENT_VDO0_VDO1_DL_RELAY2_SOF 536 +#define CMDQ_EVENT_VDO0_VDO0_DL_RELAY3_SOF 537 +#define CMDQ_EVENT_VDO0_VDO0_DL_RELAY4_SOF 538 +#define CMDQ_EVENT_VDO0_DISP_PWM0_SOF 539 +#define CMDQ_EVENT_VDO0_DISP_PWM1_SOF 540 + +#define CMDQ_EVENT_VDO0_DISP_OVL0_FRAME_DONE 544 +#define CMDQ_EVENT_VDO0_DISP_WDMA0_FRAME_DONE 545 +#define CMDQ_EVENT_VDO0_DISP_RDMA0_FRAME_DONE 546 +#define CMDQ_EVENT_VDO0_DISP_COLOR0_FRAME_DONE 547 +#define CMDQ_EVENT_VDO0_DISP_CCORR0_FRAME_DONE 548 +#define CMDQ_EVENT_VDO0_DISP_AAL0_FRAME_DONE 549 +#define CMDQ_EVENT_VDO0_DISP_GAMMA0_FRAME_DONE 550 +#define CMDQ_EVENT_VDO0_DISP_DITHER0_FRAME_DONE 551 +#define CMDQ_EVENT_VDO0_DSI0_FRAME_DONE 552 +#define CMDQ_EVENT_VDO0_DSC_WRAP0C0_FRAME_DONE 553 +#define CMDQ_EVENT_VDO0_DISP_OVL1_FRAME_DONE 554 +#define CMDQ_EVENT_VDO0_DISP_WDMA1_FRAME_DONE 555 +#define CMDQ_EVENT_VDO0_DISP_RDMA1_FRAME_DONE 556 +#define CMDQ_EVENT_VDO0_DISP_COLOR1_FRAME_DONE 557 +#define CMDQ_EVENT_VDO0_DISP_CCORR1_FRAME_DONE 558 +#define CMDQ_EVENT_VDO0_DISP_AAL1_FRAME_DONE 559 +#define CMDQ_EVENT_VDO0_DISP_GAMMA1_FRAME_DONE 560 +#define CMDQ_EVENT_VDO0_DISP_DITHER1_FRAME_DONE 561 +#define CMDQ_EVENT_VDO0_DSI1_FRAME_DONE 562 +#define CMDQ_EVENT_VDO0_DSC_WRAP0C1_FRAME_DONE 563 + +#define CMDQ_EVENT_VDO0_DP_INTF0_FRAME_DONE 565 + +#define CMDQ_EVENT_VDO0_DISP_SMIASSERT_ENG 576 +#define CMDQ_EVENT_VDO0_DSI0_IRQ_ENG_EVENT_MM 577 +#define CMDQ_EVENT_VDO0_DSI0_TE_ENG_EVENT_MM 578 +#define CMDQ_EVENT_VDO0_DSI0_DONE_ENG_EVENT_MM 579 +#define CMDQ_EVENT_VDO0_DSI0_SOF_ENG_EVENT_MM 580 +#define CMDQ_EVENT_VDO0_DSI0_VACTL_ENG_EVENT_MM 581 +#define CMDQ_EVENT_VDO0_DSI1_IRQ_ENG_EVENT_MM 582 +#define CMDQ_EVENT_VDO0_DSI1_TE_ENG_EVENT_MM 583 +#define CMDQ_EVENT_VDO0_DSI1_DONE_ENG_EVENT_MM 584 +#define CMDQ_EVENT_VDO0_DSI1_SOF_ENG_EVENT_MM 585 +#define CMDQ_EVENT_VDO0_DSI1_VACTL_ENG_EVENT_MM 586 +#define CMDQ_EVENT_VDO0_DISP_WDMA0_SW_RST_DONE_ENG 587 +#define CMDQ_EVENT_VDO0_DISP_WDMA1_SW_RST_DONE_ENG 588 +#define CMDQ_EVENT_VDO0_DISP_OVL0_RST_DONE_ENG 589 +#define CMDQ_EVENT_VDO0_DISP_OVL1_RST_DONE_ENG 590 +#define CMDQ_EVENT_VDO0_DP_INTF0_VSYNC_START_ENG_EVENT_MM 591 +#define CMDQ_EVENT_VDO0_DP_INTF0_VSYNC_END_ENG_EVENT_MM 592 +#define CMDQ_EVENT_VDO0_DP_INTF0_VDE_START_ENG_EVENT_MM 593 +#define CMDQ_EVENT_VDO0_DP_INTF0_VDE_END_ENG_EVENT_MM 594 +#define CMDQ_EVENT_VDO0_DP_INTF0_TARGET_LINE_ENG_EVENT_MM 595 +#define CMDQ_EVENT_VDO0_VPP_MERGE0_ENG 596 +#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0 597 +#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_1 598 +#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_2 599 +#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_3 600 +#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_4 601 +#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_5 602 +#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_6 603 +#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_7 604 +#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_8 605 +#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_9 606 +#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_10 607 +#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_11 608 +#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_12 609 +#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_13 610 +#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_14 611 +#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_15 612 +#define CMDQ_EVENT_VDO0_DISP_BUF_UNDERRUN_0 613 +#define CMDQ_EVENT_VDO0_DISP_BUF_UNDERRUN_1 614 +#define CMDQ_EVENT_VDO0_DISP_BUF_UNDERRUN_2 615 +#define CMDQ_EVENT_VDO0_DISP_BUF_UNDERRUN_3 616 +#define CMDQ_EVENT_VDO0_DISP_BUF_UNDERRUN_4 617 +#define CMDQ_EVENT_VDO0_DISP_BUF_UNDERRUN_5 618 +#define CMDQ_EVENT_VDO0_DISP_BUF_UNDERRUN_6 619 +#define CMDQ_EVENT_VDO0_DISP_BUF_UNDERRUN_7 620 +#define CMDQ_EVENT_VDO0_DISP_BUF_UNDERRUN_8 621 +#define CMDQ_EVENT_VDO0_DISP_BUF_UNDERRUN_9 622 +#define CMDQ_EVENT_VDO0_DISP_BUF_UNDERRUN_10 623 +#define CMDQ_EVENT_VDO0_DISP_BUF_UNDERRUN_11 624 +#define CMDQ_EVENT_VDO0_DISP_BUF_UNDERRUN_12 625 +#define CMDQ_EVENT_VDO0_DISP_BUF_UNDERRUN_13 626 +#define CMDQ_EVENT_VDO0_DISP_BUF_UNDERRUN_14 627 +#define CMDQ_EVENT_VDO0_DISP_BUF_UNDERRUN_15 628 + +#define CMDQ_EVENT_VDO1_MDP_RDMA0_SOF 640 +#define CMDQ_EVENT_VDO1_MDP_RDMA1_SOF 641 +#define CMDQ_EVENT_VDO1_MDP_RDMA2_SOF 642 +#define CMDQ_EVENT_VDO1_MDP_RDMA3_SOF 643 +#define CMDQ_EVENT_VDO1_MDP_RDMA4_SOF 644 +#define CMDQ_EVENT_VDO1_MDP_RDMA5_SOF 645 +#define CMDQ_EVENT_VDO1_MDP_RDMA6_SOF 646 +#define CMDQ_EVENT_VDO1_MDP_RDMA7_SOF 647 +#define CMDQ_EVENT_VDO1_VPP_MERGE0_SOF 648 +#define CMDQ_EVENT_VDO1_VPP_MERGE1_SOF 649 +#define CMDQ_EVENT_VDO1_VPP_MERGE2_SOF 650 +#define CMDQ_EVENT_VDO1_VPP_MERGE3_SOF 651 +#define CMDQ_EVENT_VDO1_VPP_MERGE4_SOF 652 +#define CMDQ_EVENT_VDO1_VPP2_DL_RELAY_SOF 653 +#define CMDQ_EVENT_VDO1_VPP3_DL_RELAY_SOF 654 +#define CMDQ_EVENT_VDO1_VDO0_DSC_DL_ASYNC_SOF 655 +#define CMDQ_EVENT_VDO1_VDO0_MERGE_DL_ASYNC_SOF 656 +#define CMDQ_EVENT_VDO1_OUT_DL_RELAY_SOF 657 +#define CMDQ_EVENT_VDO1_DISP_MIXER_SOF 658 +#define CMDQ_EVENT_VDO1_HDR_VDO_FE0_SOF 659 +#define CMDQ_EVENT_VDO1_HDR_VDO_FE1_SOF 660 +#define CMDQ_EVENT_VDO1_HDR_GFX_FE0_SOF 661 +#define CMDQ_EVENT_VDO1_HDR_GFX_FE1_SOF 662 +#define CMDQ_EVENT_VDO1_HDR_VDO_BE0_SOF 663 +#define CMDQ_EVENT_VDO1_HDR_MLOAD_SOF 664 + +#define CMDQ_EVENT_VDO1_MDP_RDMA0_FRAME_DONE 672 +#define CMDQ_EVENT_VDO1_MDP_RDMA1_FRAME_DONE 673 +#define CMDQ_EVENT_VDO1_MDP_RDMA2_FRAME_DONE 674 +#define CMDQ_EVENT_VDO1_MDP_RDMA3_FRAME_DONE 675 +#define CMDQ_EVENT_VDO1_MDP_RDMA4_FRAME_DONE 676 +#define CMDQ_EVENT_VDO1_MDP_RDMA5_FRAME_DONE 677 +#define CMDQ_EVENT_VDO1_MDP_RDMA6_FRAME_DONE 678 +#define CMDQ_EVENT_VDO1_MDP_RDMA7_FRAME_DONE 679 +#define CMDQ_EVENT_VDO1_VPP_MERGE0_FRAME_DONE 680 +#define CMDQ_EVENT_VDO1_VPP_MERGE1_FRAME_DONE 681 +#define CMDQ_EVENT_VDO1_VPP_MERGE2_FRAME_DONE 682 +#define CMDQ_EVENT_VDO1_VPP_MERGE3_FRAME_DONE 683 +#define CMDQ_EVENT_VDO1_VPP_MERGE4_FRAME_DONE 684 +#define CMDQ_EVENT_VDO1_DPI0_FRAME_DONE 685 +#define CMDQ_EVENT_VDO1_DPI1_FRAME_DONE 686 +#define CMDQ_EVENT_VDO1_DP_INTF0_FRAME_DONE 687 +#define CMDQ_EVENT_VDO1_DISP_MIXER_FRAME_DONE_MM 688 + +#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0 704 +#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_1 705 +#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_2 706 +#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_3 707 +#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_4 708 +#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_5 709 +#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_6 710 +#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_7 711 +#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_8 712 +#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_9 713 +#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_10 714 +#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_11 715 +#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_12 716 +#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_13 717 +#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_14 718 +#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_15 719 +#define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_0 720 +#define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_1 721 +#define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_2 722 +#define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_3 723 +#define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_4 724 +#define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_5 725 +#define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_6 726 +#define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_7 727 +#define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_8 728 +#define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_9 729 +#define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_10 730 +#define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_11 731 +#define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_12 732 +#define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_13 733 +#define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_14 734 +#define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_15 735 +#define CMDQ_EVENT_VDO1_MDP_RDMA0_SW_RST_DONE 736 +#define CMDQ_EVENT_VDO1_MDP_RDMA1_SW_RST_DONE 737 +#define CMDQ_EVENT_VDO1_MDP_RDMA2_SW_RST_DONE 738 +#define CMDQ_EVENT_VDO1_MDP_RDMA3_SW_RST_DONE 739 +#define CMDQ_EVENT_VDO1_MDP_RDMA4_SW_RST_DONE 740 +#define CMDQ_EVENT_VDO1_MDP_RDMA5_SW_RST_DONE 741 +#define CMDQ_EVENT_VDO1_MDP_RDMA6_SW_RST_DONE 742 +#define CMDQ_EVENT_VDO1_MDP_RDMA7_SW_RST_DONE 743 + +#define CMDQ_EVENT_VDO1_DP0_VDE_END_ENG_EVENT_MM 745 +#define CMDQ_EVENT_VDO1_DP0_VDE_START_ENG_EVENT_MM 746 +#define CMDQ_EVENT_VDO1_DP0_VSYNC_END_ENG_EVENT_MM 747 +#define CMDQ_EVENT_VDO1_DP0_VSYNC_START_ENG_EVENT_MM 748 +#define CMDQ_EVENT_VDO1_DP0_TARGET_LINE_ENG_EVENT_MM 749 +#define CMDQ_EVENT_VDO1_VPP_MERGE0 750 +#define CMDQ_EVENT_VDO1_VPP_MERGE1 751 +#define CMDQ_EVENT_VDO1_VPP_MERGE2 752 +#define CMDQ_EVENT_VDO1_VPP_MERGE3 753 +#define CMDQ_EVENT_VDO1_VPP_MERGE4 754 +#define CMDQ_EVENT_VDO1_HDMITX 755 +#define CMDQ_EVENT_VDO1_HDR_VDO_BE0_ADL_TRIG_EVENT_MM 756 +#define CMDQ_EVENT_VDO1_HDR_GFX_FE1_THDR_ADL_TRIG_EVENT_MM 757 +#define CMDQ_EVENT_VDO1_HDR_GFX_FE1_DM_ADL_TRIG_EVENT_MM 758 +#define CMDQ_EVENT_VDO1_HDR_GFX_FE0_THDR_ADL_TRIG_EVENT_MM 759 +#define CMDQ_EVENT_VDO1_HDR_GFX_FE0_DM_ADL_TRIG_EVENT_MM 760 +#define CMDQ_EVENT_VDO1_HDR_VDO_FE1_ADL_TRIG_EVENT_MM 761 +#define CMDQ_EVENT_VDO1_HDR_VDO_FE1_AD0_TRIG_EVENT_MM 762 + +#define CMDQ_EVENT_CAM_A_PASS1_DONE 769 +#define CMDQ_EVENT_CAM_B_PASS1_DONE 770 +#define CMDQ_EVENT_GCAMSV_A_PASS1_DONE 771 +#define CMDQ_EVENT_GCAMSV_B_PASS1_DONE 772 +#define CMDQ_EVENT_MRAW_0_PASS1_DONE 773 +#define CMDQ_EVENT_MRAW_1_PASS1_DONE 774 +#define CMDQ_EVENT_MRAW_2_PASS1_DONE 775 +#define CMDQ_EVENT_MRAW_3_PASS1_DONE 776 +#define CMDQ_EVENT_SENINF_CAM0_FIFO_FULL_X 777 +#define CMDQ_EVENT_SENINF_CAM1_FIFO_FULL_X 778 +#define CMDQ_EVENT_SENINF_CAM2_FIFO_FULL 779 +#define CMDQ_EVENT_SENINF_CAM3_FIFO_FULL 780 +#define CMDQ_EVENT_SENINF_CAM4_FIFO_FULL 781 +#define CMDQ_EVENT_SENINF_CAM5_FIFO_FULL 782 +#define CMDQ_EVENT_SENINF_CAM6_FIFO_FULL 783 +#define CMDQ_EVENT_SENINF_CAM7_FIFO_FULL 784 +#define CMDQ_EVENT_SENINF_CAM8_FIFO_FULL 785 +#define CMDQ_EVENT_SENINF_CAM9_FIFO_FULL 786 +#define CMDQ_EVENT_SENINF_CAM10_FIFO_FULL_X 787 +#define CMDQ_EVENT_SENINF_CAM11_FIFO_FULL_X 788 +#define CMDQ_EVENT_SENINF_CAM12_FIFO_FULL_X 789 +#define CMDQ_EVENT_SENINF_CAM13_FIFO_FULL_X 790 +#define CMDQ_EVENT_TG_OVRUN_MRAW0_INT_X0 791 +#define CMDQ_EVENT_TG_OVRUN_MRAW1_INT_X0 792 +#define CMDQ_EVENT_TG_OVRUN_MRAW2_INT 793 +#define CMDQ_EVENT_TG_OVRUN_MRAW3_INT 794 +#define CMDQ_EVENT_DMA_R1_ERROR_MRAW0_INT 795 +#define CMDQ_EVENT_DMA_R1_ERROR_MRAW1_INT 796 +#define CMDQ_EVENT_DMA_R1_ERROR_MRAW2_INT 797 +#define CMDQ_EVENT_DMA_R1_ERROR_MRAW3_INT 798 +#define CMDQ_EVENT_U_CAMSYS_PDA_IRQO_EVENT_DONE_D1 799 +#define CMDQ_EVENT_SUBB_TG_INT4 800 +#define CMDQ_EVENT_SUBB_TG_INT3 801 +#define CMDQ_EVENT_SUBB_TG_INT2 802 +#define CMDQ_EVENT_SUBB_TG_INT1 803 +#define CMDQ_EVENT_SUBA_TG_INT4 804 +#define CMDQ_EVENT_SUBA_TG_INT3 805 +#define CMDQ_EVENT_SUBA_TG_INT2 806 +#define CMDQ_EVENT_SUBA_TG_INT1 807 +#define CMDQ_EVENT_SUBB_DRZS4NO_R1_LOW_LATENCY_LINE_CNT_INT 808 +#define CMDQ_EVENT_SUBB_YUVO_R3_LOW_LATENCY_LINE_CNT_INT 809 +#define CMDQ_EVENT_SUBB_YUVO_R1_LOW_LATENCY_LINE_CNT_INT 810 +#define CMDQ_EVENT_SUBB_IMGO_R1_LOW_LATENCY_LINE_CNT_INT 811 +#define CMDQ_EVENT_SUBA_DRZS4NO_R1_LOW_LATENCY_LINE_CNT_INT 812 +#define CMDQ_EVENT_SUBA_YUVO_R3_LOW_LATENCY_LINE_CNT_INT 813 +#define CMDQ_EVENT_SUBA_YUVO_R1_LOW_LATENCY_LINE_CNT_INT 814 +#define CMDQ_EVENT_SUBA_IMGO_R1_LOW_LATENCY_LINE_CNT_INT 815 +#define CMDQ_EVENT_GCE1_SOF_0 816 +#define CMDQ_EVENT_GCE1_SOF_1 817 +#define CMDQ_EVENT_GCE1_SOF_2 818 +#define CMDQ_EVENT_GCE1_SOF_3 819 +#define CMDQ_EVENT_GCE1_SOF_4 820 +#define CMDQ_EVENT_GCE1_SOF_5 821 +#define CMDQ_EVENT_GCE1_SOF_6 822 +#define CMDQ_EVENT_GCE1_SOF_7 823 +#define CMDQ_EVENT_GCE1_SOF_8 824 +#define CMDQ_EVENT_GCE1_SOF_9 825 +#define CMDQ_EVENT_GCE1_SOF_10 826 +#define CMDQ_EVENT_GCE1_SOF_11 827 +#define CMDQ_EVENT_GCE1_SOF_12 828 +#define CMDQ_EVENT_GCE1_SOF_13 829 +#define CMDQ_EVENT_GCE1_SOF_14 830 +#define CMDQ_EVENT_GCE1_SOF_15 831 + +#define CMDQ_EVENT_VDEC_LAT_LINE_COUNT_THRESHOLD_INTERRUPT 832 +#define CMDQ_EVENT_VDEC_LAT_VDEC_INT 833 +#define CMDQ_EVENT_VDEC_LAT_VDEC_PAUSE 834 +#define CMDQ_EVENT_VDEC_LAT_VDEC_DEC_ERROR 835 +#define CMDQ_EVENT_VDEC_LAT_MC_BUSY_OVERFLOW_MDEC_TIMEOUT 836 +#define CMDQ_EVENT_VDEC_LAT_VDEC_FRAME_DONE 837 +#define CMDQ_EVENT_VDEC_LAT_INI_FETCH_RDY 838 +#define CMDQ_EVENT_VDEC_LAT_PROCESS_FLAG 839 +#define CMDQ_EVENT_VDEC_LAT_SEARCH_START_CODE_DONE 840 +#define CMDQ_EVENT_VDEC_LAT_REF_REORDER_DONE 841 +#define CMDQ_EVENT_VDEC_LAT_WP_TBLE_DONE 842 +#define CMDQ_EVENT_VDEC_LAT_COUNT_SRAM_CLR_DONE_AND_CTX_SRAM_CLR_DONE 843 +#define CMDQ_EVENT_VDEC_LAT_GCE_CNT_OP_THRESHOLD 847 + +#define CMDQ_EVENT_VDEC_LAT1_LINE_COUNT_THRESHOLD_INTERRUPT 848 +#define CMDQ_EVENT_VDEC_LAT1_VDEC_INT 849 +#define CMDQ_EVENT_VDEC_LAT1_VDEC_PAUSE 850 +#define CMDQ_EVENT_VDEC_LAT1_VDEC_DEC_ERROR 851 +#define CMDQ_EVENT_VDEC_LAT1_MC_BUSY_OVERFLOW_MDEC_TIMEOUT 852 +#define CMDQ_EVENT_VDEC_LAT1_VDEC_FRAME_DONE 853 +#define CMDQ_EVENT_VDEC_LAT1_INI_FETCH_RDY 854 +#define CMDQ_EVENT_VDEC_LAT1_PROCESS_FLAG 855 +#define CMDQ_EVENT_VDEC_LAT1_SEARCH_START_CODE_DONE 856 +#define CMDQ_EVENT_VDEC_LAT1_REF_REORDER_DONE 857 +#define CMDQ_EVENT_VDEC_LAT1_WP_TBLE_DONE 858 +#define CMDQ_EVENT_VDEC_LAT1_COUNT_SRAM_CLR_DONE_AND_CTX_SRAM_CLR_DONE 859 +#define CMDQ_EVENT_VDEC_LAT1_GCE_CNT_OP_THRESHOLD 863 + +#define CMDQ_EVENT_VDEC_SOC_GLOBAL_CON_250_0 864 +#define CMDQ_EVENT_VDEC_SOC_GLOBAL_CON_250_1 865 + +#define CMDQ_EVENT_VDEC_SOC_GLOBAL_CON_250_8 872 +#define CMDQ_EVENT_VDEC_SOC_GLOBAL_CON_250_9 873 + +#define CMDQ_EVENT_VDEC_CORE_LINE_COUNT_THRESHOLD_INTERRUPT 896 +#define CMDQ_EVENT_VDEC_CORE_VDEC_INT 897 +#define CMDQ_EVENT_VDEC_CORE_VDEC_PAUSE 898 +#define CMDQ_EVENT_VDEC_CORE_VDEC_DEC_ERROR 899 +#define CMDQ_EVENT_VDEC_CORE_MC_BUSY_OVERFLOW_MDEC_TIMEOUT 900 +#define CMDQ_EVENT_VDEC_CORE_VDEC_FRAME_DONE 901 +#define CMDQ_EVENT_VDEC_CORE_INI_FETCH_RDY 902 +#define CMDQ_EVENT_VDEC_CORE_PROCESS_FLAG 903 +#define CMDQ_EVENT_VDEC_CORE_SEARCH_START_CODE_DONE 904 +#define CMDQ_EVENT_VDEC_CORE_REF_REORDER_DONE 905 +#define CMDQ_EVENT_VDEC_CORE_WP_TBLE_DONE 906 +#define CMDQ_EVENT_VDEC_CORE_COUNT_SRAM_CLR_DONE_AND_CTX_SRAM_CLR_DONE 907 +#define CMDQ_EVENT_VDEC_CORE_GCE_CNT_OP_THRESHOLD 911 + +#define CMDQ_EVENT_VDEC_CORE1_LINE_COUNT_THRESHOLD_INTERRUPT 912 +#define CMDQ_EVENT_VDEC_CORE1_VDEC_INT 913 +#define CMDQ_EVENT_VDEC_CORE1_VDEC_PAUSE 914 +#define CMDQ_EVENT_VDEC_CORE1_VDEC_DEC_ERROR 915 +#define CMDQ_EVENT_VDEC_CORE1_MC_BUSY_OVERFLOW_MDEC_TIMEOUT 916 +#define CMDQ_EVENT_VDEC_CORE1_VDEC_FRAME_DONE 917 +#define CMDQ_EVENT_VDEC_CORE1_INI_FETCH_RDY 918 +#define CMDQ_EVENT_VDEC_CORE1_PROCESS_FLAG 919 +#define CMDQ_EVENT_VDEC_CORE1_SEARCH_START_CODE_DONE 920 +#define CMDQ_EVENT_VDEC_CORE1_REF_REORDER_DONE 921 +#define CMDQ_EVENT_VDEC_CORE1_WP_TBLE_DONE 922 +#define CMDQ_EVENT_VDEC_CORE1_COUNT_SRAM_CLR_DONE_AND_CTX_SRAM_CLR_DONE 923 +#define CMDQ_EVENT_VDEC_CORE1_CNT_OP_THRESHOLD 927 + +#define CMDQ_EVENT_VENC_TOP_FRAME_DONE 929 +#define CMDQ_EVENT_VENC_TOP_PAUSE_DONE 930 +#define CMDQ_EVENT_VENC_TOP_JPGENC_DONE 931 +#define CMDQ_EVENT_VENC_TOP_MB_DONE 932 +#define CMDQ_EVENT_VENC_TOP_128BYTE_DONE 933 +#define CMDQ_EVENT_VENC_TOP_JPGDEC_DONE 934 +#define CMDQ_EVENT_VENC_TOP_JPGDEC_C1_DONE 935 +#define CMDQ_EVENT_VENC_TOP_JPGDEC_INSUFF_DONE 936 +#define CMDQ_EVENT_VENC_TOP_JPGDEC_C1_INSUFF_DONE 937 +#define CMDQ_EVENT_VENC_TOP_WP_2ND_STAGE_DONE 938 +#define CMDQ_EVENT_VENC_TOP_WP_3RD_STAGE_DONE 939 +#define CMDQ_EVENT_VENC_TOP_PPS_HEADER_DONE 940 +#define CMDQ_EVENT_VENC_TOP_SPS_HEADER_DONE 941 +#define CMDQ_EVENT_VENC_TOP_VPS_HEADER_DONE 942 + +#define CMDQ_EVENT_VENC_CORE1_TOP_FRAME_DONE 945 +#define CMDQ_EVENT_VENC_CORE1_TOP_PAUSE_DONE 946 +#define CMDQ_EVENT_VENC_CORE1_TOP_JPGENC_DONE 947 +#define CMDQ_EVENT_VENC_CORE1_TOP_MB_DONE 948 +#define CMDQ_EVENT_VENC_CORE1_TOP_128BYTE_DONE 949 +#define CMDQ_EVENT_VENC_CORE1_TOP_JPGDEC_DONE 950 +#define CMDQ_EVENT_VENC_CORE1_TOP_JPGDEC_C1_DONE 951 +#define CMDQ_EVENT_VENC_CORE1_TOP_JPGDEC_INSUFF_DONE 952 +#define CMDQ_EVENT_VENC_CORE1_TOP_JPGDEC_C1_INSUFF_DONE 953 +#define CMDQ_EVENT_VENC_CORE1_TOP_WP_2ND_STAGE_DONE 954 +#define CMDQ_EVENT_VENC_CORE1_TOP_WP_3RD_STAGE_DONE 955 +#define CMDQ_EVENT_VENC_CORE1_TOP_PPS_HEADER_DONE 956 +#define CMDQ_EVENT_VENC_CORE1_TOP_SPS_HEADER_DONE 957 +#define CMDQ_EVENT_VENC_CORE1_TOP_VPS_HEADER_DONE 958 + +#define CMDQ_EVENT_WPE_VPP0_WPE_GCE_FRAME_DONE 962 +#define CMDQ_EVENT_WPE_VPP0_WPE_DONE_SYNC_OUT 963 + +#define CMDQ_EVENT_WPE_VPP1_WPE_GCE_FRAME_DONE 969 +#define CMDQ_EVENT_WPE_VPP1_WPE_DONE_SYNC_OUT 970 + +#define CMDQ_EVENT_DP_TX_VBLANK_FALLING 994 +#define CMDQ_EVENT_DP_TX_VSC_FINISH 995 + +#define CMDQ_EVENT_OUTPIN_0 1018 +#define CMDQ_EVENT_OUTPIN_1 1019 + +/* end of hw event */ +#define CMDQ_MAX_HW_EVENT 1019 + +#endif diff --git a/include/dt-bindings/gpio/gpio.h b/include/dt-bindings/gpio/gpio.h index c029467e828b..5566e58196a2 100644 --- a/include/dt-bindings/gpio/gpio.h +++ b/include/dt-bindings/gpio/gpio.h @@ -39,4 +39,7 @@ /* Bit 5 express pull down */ #define GPIO_PULL_DOWN 32 +/* Bit 6 express pull disable */ +#define GPIO_PULL_DISABLE 64 + #endif diff --git a/include/dt-bindings/gpio/meson-s4-gpio.h b/include/dt-bindings/gpio/meson-s4-gpio.h new file mode 100644 index 000000000000..35aee21b94f1 --- /dev/null +++ b/include/dt-bindings/gpio/meson-s4-gpio.h @@ -0,0 +1,99 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2021 Amlogic, Inc. All rights reserved. + * Author: Qianggui Song <qianggui.song@amlogic.com> + */ + +#ifndef _DT_BINDINGS_MESON_S4_GPIO_H +#define _DT_BINDINGS_MESON_S4_GPIO_H + +#define GPIOB_0 0 +#define GPIOB_1 1 +#define GPIOB_2 2 +#define GPIOB_3 3 +#define GPIOB_4 4 +#define GPIOB_5 5 +#define GPIOB_6 6 +#define GPIOB_7 7 +#define GPIOB_8 8 +#define GPIOB_9 9 +#define GPIOB_10 10 +#define GPIOB_11 11 +#define GPIOB_12 12 +#define GPIOB_13 13 + +#define GPIOC_0 14 +#define GPIOC_1 15 +#define GPIOC_2 16 +#define GPIOC_3 17 +#define GPIOC_4 18 +#define GPIOC_5 19 +#define GPIOC_6 20 +#define GPIOC_7 21 + +#define GPIOE_0 22 +#define GPIOE_1 23 + +#define GPIOD_0 24 +#define GPIOD_1 25 +#define GPIOD_2 26 +#define GPIOD_3 27 +#define GPIOD_4 28 +#define GPIOD_5 29 +#define GPIOD_6 30 +#define GPIOD_7 31 +#define GPIOD_8 32 +#define GPIOD_9 33 +#define GPIOD_10 34 +#define GPIOD_11 35 + +#define GPIOH_0 36 +#define GPIOH_1 37 +#define GPIOH_2 38 +#define GPIOH_3 39 +#define GPIOH_4 40 +#define GPIOH_5 41 +#define GPIOH_6 42 +#define GPIOH_7 43 +#define GPIOH_8 44 +#define GPIOH_9 45 +#define GPIOH_10 46 +#define GPIOH_11 47 + +#define GPIOX_0 48 +#define GPIOX_1 49 +#define GPIOX_2 50 +#define GPIOX_3 51 +#define GPIOX_4 52 +#define GPIOX_5 53 +#define GPIOX_6 54 +#define GPIOX_7 55 +#define GPIOX_8 56 +#define GPIOX_9 57 +#define GPIOX_10 58 +#define GPIOX_11 59 +#define GPIOX_12 60 +#define GPIOX_13 61 +#define GPIOX_14 62 +#define GPIOX_15 63 +#define GPIOX_16 64 +#define GPIOX_17 65 +#define GPIOX_18 66 +#define GPIOX_19 67 + +#define GPIOZ_0 68 +#define GPIOZ_1 69 +#define GPIOZ_2 70 +#define GPIOZ_3 71 +#define GPIOZ_4 72 +#define GPIOZ_5 73 +#define GPIOZ_6 74 +#define GPIOZ_7 75 +#define GPIOZ_8 76 +#define GPIOZ_9 77 +#define GPIOZ_10 78 +#define GPIOZ_11 79 +#define GPIOZ_12 80 + +#define GPIO_TEST_N 81 +#endif /* _DT_BINDINGS_MESON_S4_GPIO_H */ diff --git a/include/dt-bindings/gpio/msc313-gpio.h b/include/dt-bindings/gpio/msc313-gpio.h new file mode 100644 index 000000000000..5458c6580a02 --- /dev/null +++ b/include/dt-bindings/gpio/msc313-gpio.h @@ -0,0 +1,124 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * GPIO definitions for MStar/SigmaStar MSC313 and later SoCs + * + * Copyright (C) 2020 Daniel Palmer <daniel@thingy.jp> + */ + +#ifndef _DT_BINDINGS_MSC313_GPIO_H +#define _DT_BINDINGS_MSC313_GPIO_H + +#define MSC313_GPIO_FUART 0 +#define MSC313_GPIO_FUART_RX (MSC313_GPIO_FUART + 0) +#define MSC313_GPIO_FUART_TX (MSC313_GPIO_FUART + 1) +#define MSC313_GPIO_FUART_CTS (MSC313_GPIO_FUART + 2) +#define MSC313_GPIO_FUART_RTS (MSC313_GPIO_FUART + 3) + +#define MSC313_GPIO_SR (MSC313_GPIO_FUART_RTS + 1) +#define MSC313_GPIO_SR_IO2 (MSC313_GPIO_SR + 0) +#define MSC313_GPIO_SR_IO3 (MSC313_GPIO_SR + 1) +#define MSC313_GPIO_SR_IO4 (MSC313_GPIO_SR + 2) +#define MSC313_GPIO_SR_IO5 (MSC313_GPIO_SR + 3) +#define MSC313_GPIO_SR_IO6 (MSC313_GPIO_SR + 4) +#define MSC313_GPIO_SR_IO7 (MSC313_GPIO_SR + 5) +#define MSC313_GPIO_SR_IO8 (MSC313_GPIO_SR + 6) +#define MSC313_GPIO_SR_IO9 (MSC313_GPIO_SR + 7) +#define MSC313_GPIO_SR_IO10 (MSC313_GPIO_SR + 8) +#define MSC313_GPIO_SR_IO11 (MSC313_GPIO_SR + 9) +#define MSC313_GPIO_SR_IO12 (MSC313_GPIO_SR + 10) +#define MSC313_GPIO_SR_IO13 (MSC313_GPIO_SR + 11) +#define MSC313_GPIO_SR_IO14 (MSC313_GPIO_SR + 12) +#define MSC313_GPIO_SR_IO15 (MSC313_GPIO_SR + 13) +#define MSC313_GPIO_SR_IO16 (MSC313_GPIO_SR + 14) +#define MSC313_GPIO_SR_IO17 (MSC313_GPIO_SR + 15) + +#define MSC313_GPIO_SD (MSC313_GPIO_SR_IO17 + 1) +#define MSC313_GPIO_SD_CLK (MSC313_GPIO_SD + 0) +#define MSC313_GPIO_SD_CMD (MSC313_GPIO_SD + 1) +#define MSC313_GPIO_SD_D0 (MSC313_GPIO_SD + 2) +#define MSC313_GPIO_SD_D1 (MSC313_GPIO_SD + 3) +#define MSC313_GPIO_SD_D2 (MSC313_GPIO_SD + 4) +#define MSC313_GPIO_SD_D3 (MSC313_GPIO_SD + 5) + +#define MSC313_GPIO_I2C1 (MSC313_GPIO_SD_D3 + 1) +#define MSC313_GPIO_I2C1_SCL (MSC313_GPIO_I2C1 + 0) +#define MSC313_GPIO_I2C1_SDA (MSC313_GPIO_I2C1 + 1) + +#define MSC313_GPIO_SPI0 (MSC313_GPIO_I2C1_SDA + 1) +#define MSC313_GPIO_SPI0_CZ (MSC313_GPIO_SPI0 + 0) +#define MSC313_GPIO_SPI0_CK (MSC313_GPIO_SPI0 + 1) +#define MSC313_GPIO_SPI0_DI (MSC313_GPIO_SPI0 + 2) +#define MSC313_GPIO_SPI0_DO (MSC313_GPIO_SPI0 + 3) + +/* SSD20x */ +#define SSD20XD_GPIO_FUART 0 +#define SSD20XD_GPIO_FUART_RX (SSD20XD_GPIO_FUART + 0) +#define SSD20XD_GPIO_FUART_TX (SSD20XD_GPIO_FUART + 1) +#define SSD20XD_GPIO_FUART_CTS (SSD20XD_GPIO_FUART + 2) +#define SSD20XD_GPIO_FUART_RTS (SSD20XD_GPIO_FUART + 3) + +#define SSD20XD_GPIO_SD (SSD20XD_GPIO_FUART_RTS + 1) +#define SSD20XD_GPIO_SD_CLK (SSD20XD_GPIO_SD + 0) +#define SSD20XD_GPIO_SD_CMD (SSD20XD_GPIO_SD + 1) +#define SSD20XD_GPIO_SD_D0 (SSD20XD_GPIO_SD + 2) +#define SSD20XD_GPIO_SD_D1 (SSD20XD_GPIO_SD + 3) +#define SSD20XD_GPIO_SD_D2 (SSD20XD_GPIO_SD + 4) +#define SSD20XD_GPIO_SD_D3 (SSD20XD_GPIO_SD + 5) + +#define SSD20XD_GPIO_UART0 (SSD20XD_GPIO_SD_D3 + 1) +#define SSD20XD_GPIO_UART0_RX (SSD20XD_GPIO_UART0 + 0) +#define SSD20XD_GPIO_UART0_TX (SSD20XD_GPIO_UART0 + 1) + +#define SSD20XD_GPIO_UART1 (SSD20XD_GPIO_UART0_TX + 1) +#define SSD20XD_GPIO_UART1_RX (SSD20XD_GPIO_UART1 + 0) +#define SSD20XD_GPIO_UART1_TX (SSD20XD_GPIO_UART1 + 1) + +#define SSD20XD_GPIO_TTL (SSD20XD_GPIO_UART1_TX + 1) +#define SSD20XD_GPIO_TTL0 (SSD20XD_GPIO_TTL + 0) +#define SSD20XD_GPIO_TTL1 (SSD20XD_GPIO_TTL + 1) +#define SSD20XD_GPIO_TTL2 (SSD20XD_GPIO_TTL + 2) +#define SSD20XD_GPIO_TTL3 (SSD20XD_GPIO_TTL + 3) +#define SSD20XD_GPIO_TTL4 (SSD20XD_GPIO_TTL + 4) +#define SSD20XD_GPIO_TTL5 (SSD20XD_GPIO_TTL + 5) +#define SSD20XD_GPIO_TTL6 (SSD20XD_GPIO_TTL + 6) +#define SSD20XD_GPIO_TTL7 (SSD20XD_GPIO_TTL + 7) +#define SSD20XD_GPIO_TTL8 (SSD20XD_GPIO_TTL + 8) +#define SSD20XD_GPIO_TTL9 (SSD20XD_GPIO_TTL + 9) +#define SSD20XD_GPIO_TTL10 (SSD20XD_GPIO_TTL + 10) +#define SSD20XD_GPIO_TTL11 (SSD20XD_GPIO_TTL + 11) +#define SSD20XD_GPIO_TTL12 (SSD20XD_GPIO_TTL + 12) +#define SSD20XD_GPIO_TTL13 (SSD20XD_GPIO_TTL + 13) +#define SSD20XD_GPIO_TTL14 (SSD20XD_GPIO_TTL + 14) +#define SSD20XD_GPIO_TTL15 (SSD20XD_GPIO_TTL + 15) +#define SSD20XD_GPIO_TTL16 (SSD20XD_GPIO_TTL + 16) +#define SSD20XD_GPIO_TTL17 (SSD20XD_GPIO_TTL + 17) +#define SSD20XD_GPIO_TTL18 (SSD20XD_GPIO_TTL + 18) +#define SSD20XD_GPIO_TTL19 (SSD20XD_GPIO_TTL + 19) +#define SSD20XD_GPIO_TTL20 (SSD20XD_GPIO_TTL + 20) +#define SSD20XD_GPIO_TTL21 (SSD20XD_GPIO_TTL + 21) +#define SSD20XD_GPIO_TTL22 (SSD20XD_GPIO_TTL + 22) +#define SSD20XD_GPIO_TTL23 (SSD20XD_GPIO_TTL + 23) +#define SSD20XD_GPIO_TTL24 (SSD20XD_GPIO_TTL + 24) +#define SSD20XD_GPIO_TTL25 (SSD20XD_GPIO_TTL + 25) +#define SSD20XD_GPIO_TTL26 (SSD20XD_GPIO_TTL + 26) +#define SSD20XD_GPIO_TTL27 (SSD20XD_GPIO_TTL + 27) + +#define SSD20XD_GPIO_GPIO (SSD20XD_GPIO_TTL27 + 1) +#define SSD20XD_GPIO_GPIO0 (SSD20XD_GPIO_GPIO + 0) +#define SSD20XD_GPIO_GPIO1 (SSD20XD_GPIO_GPIO + 1) +#define SSD20XD_GPIO_GPIO2 (SSD20XD_GPIO_GPIO + 2) +#define SSD20XD_GPIO_GPIO3 (SSD20XD_GPIO_GPIO + 3) +#define SSD20XD_GPIO_GPIO4 (SSD20XD_GPIO_GPIO + 4) +#define SSD20XD_GPIO_GPIO5 (SSD20XD_GPIO_GPIO + 5) +#define SSD20XD_GPIO_GPIO6 (SSD20XD_GPIO_GPIO + 6) +#define SSD20XD_GPIO_GPIO7 (SSD20XD_GPIO_GPIO + 7) +#define SSD20XD_GPIO_GPIO10 (SSD20XD_GPIO_GPIO + 8) +#define SSD20XD_GPIO_GPIO11 (SSD20XD_GPIO_GPIO + 9) +#define SSD20XD_GPIO_GPIO12 (SSD20XD_GPIO_GPIO + 10) +#define SSD20XD_GPIO_GPIO13 (SSD20XD_GPIO_GPIO + 11) +#define SSD20XD_GPIO_GPIO14 (SSD20XD_GPIO_GPIO + 12) +#define SSD20XD_GPIO_GPIO85 (SSD20XD_GPIO_GPIO + 13) +#define SSD20XD_GPIO_GPIO86 (SSD20XD_GPIO_GPIO + 14) +#define SSD20XD_GPIO_GPIO90 (SSD20XD_GPIO_GPIO + 15) + +#endif /* _DT_BINDINGS_MSC313_GPIO_H */ diff --git a/include/dt-bindings/gpio/tegra186-gpio.h b/include/dt-bindings/gpio/tegra186-gpio.h index 0782b05e2775..af0d9583be70 100644 --- a/include/dt-bindings/gpio/tegra186-gpio.h +++ b/include/dt-bindings/gpio/tegra186-gpio.h @@ -8,8 +8,8 @@ * The second cell contains standard flag values specified in gpio.h. */ -#ifndef _DT_BINDINGS_GPIO_TEGRA_GPIO_H -#define _DT_BINDINGS_GPIO_TEGRA_GPIO_H +#ifndef _DT_BINDINGS_GPIO_TEGRA186_GPIO_H +#define _DT_BINDINGS_GPIO_TEGRA186_GPIO_H #include <dt-bindings/gpio/gpio.h> diff --git a/include/dt-bindings/gpio/tegra234-gpio.h b/include/dt-bindings/gpio/tegra234-gpio.h new file mode 100644 index 000000000000..d7a1f2e298e8 --- /dev/null +++ b/include/dt-bindings/gpio/tegra234-gpio.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. */ + +/* + * This header provides constants for binding nvidia,tegra234-gpio*. + * + * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below + * provide names for this. + * + * The second cell contains standard flag values specified in gpio.h. + */ + +#ifndef _DT_BINDINGS_GPIO_TEGRA234_GPIO_H +#define _DT_BINDINGS_GPIO_TEGRA234_GPIO_H + +#include <dt-bindings/gpio/gpio.h> + +/* GPIOs implemented by main GPIO controller */ +#define TEGRA234_MAIN_GPIO_PORT_A 0 +#define TEGRA234_MAIN_GPIO_PORT_B 1 +#define TEGRA234_MAIN_GPIO_PORT_C 2 +#define TEGRA234_MAIN_GPIO_PORT_D 3 +#define TEGRA234_MAIN_GPIO_PORT_E 4 +#define TEGRA234_MAIN_GPIO_PORT_F 5 +#define TEGRA234_MAIN_GPIO_PORT_G 6 +#define TEGRA234_MAIN_GPIO_PORT_H 7 +#define TEGRA234_MAIN_GPIO_PORT_I 8 +#define TEGRA234_MAIN_GPIO_PORT_J 9 +#define TEGRA234_MAIN_GPIO_PORT_K 10 +#define TEGRA234_MAIN_GPIO_PORT_L 11 +#define TEGRA234_MAIN_GPIO_PORT_M 12 +#define TEGRA234_MAIN_GPIO_PORT_N 13 +#define TEGRA234_MAIN_GPIO_PORT_P 14 +#define TEGRA234_MAIN_GPIO_PORT_Q 15 +#define TEGRA234_MAIN_GPIO_PORT_R 16 +#define TEGRA234_MAIN_GPIO_PORT_S 17 +#define TEGRA234_MAIN_GPIO_PORT_T 18 +#define TEGRA234_MAIN_GPIO_PORT_U 19 +#define TEGRA234_MAIN_GPIO_PORT_V 20 +#define TEGRA234_MAIN_GPIO_PORT_X 21 +#define TEGRA234_MAIN_GPIO_PORT_Y 22 +#define TEGRA234_MAIN_GPIO_PORT_Z 23 +#define TEGRA234_MAIN_GPIO_PORT_AC 24 +#define TEGRA234_MAIN_GPIO_PORT_AD 25 +#define TEGRA234_MAIN_GPIO_PORT_AE 26 +#define TEGRA234_MAIN_GPIO_PORT_AF 27 +#define TEGRA234_MAIN_GPIO_PORT_AG 28 + +#define TEGRA234_MAIN_GPIO(port, offset) \ + ((TEGRA234_MAIN_GPIO_PORT_##port * 8) + offset) + +/* GPIOs implemented by AON GPIO controller */ +#define TEGRA234_AON_GPIO_PORT_AA 0 +#define TEGRA234_AON_GPIO_PORT_BB 1 +#define TEGRA234_AON_GPIO_PORT_CC 2 +#define TEGRA234_AON_GPIO_PORT_DD 3 +#define TEGRA234_AON_GPIO_PORT_EE 4 +#define TEGRA234_AON_GPIO_PORT_GG 5 + +#define TEGRA234_AON_GPIO(port, offset) \ + ((TEGRA234_AON_GPIO_PORT_##port * 8) + offset) + +#endif diff --git a/include/dt-bindings/gpio/tegra241-gpio.h b/include/dt-bindings/gpio/tegra241-gpio.h new file mode 100644 index 000000000000..80cee3016be6 --- /dev/null +++ b/include/dt-bindings/gpio/tegra241-gpio.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. */ + +/* + * This header provides constants for the nvidia,tegra241-gpio DT binding. + * + * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below + * provide names for this. + * + * The second cell contains standard flag values specified in gpio.h. + */ + +#ifndef _DT_BINDINGS_GPIO_TEGRA241_GPIO_H +#define _DT_BINDINGS_GPIO_TEGRA241_GPIO_H + +#include <dt-bindings/gpio/gpio.h> + +/* GPIOs implemented by main GPIO controller */ +#define TEGRA241_MAIN_GPIO_PORT_A 0 +#define TEGRA241_MAIN_GPIO_PORT_B 1 +#define TEGRA241_MAIN_GPIO_PORT_C 2 +#define TEGRA241_MAIN_GPIO_PORT_D 3 +#define TEGRA241_MAIN_GPIO_PORT_E 4 +#define TEGRA241_MAIN_GPIO_PORT_F 5 +#define TEGRA241_MAIN_GPIO_PORT_G 6 +#define TEGRA241_MAIN_GPIO_PORT_H 7 +#define TEGRA241_MAIN_GPIO_PORT_I 8 +#define TEGRA241_MAIN_GPIO_PORT_J 9 +#define TEGRA241_MAIN_GPIO_PORT_K 10 +#define TEGRA241_MAIN_GPIO_PORT_L 11 + +#define TEGRA241_MAIN_GPIO(port, offset) \ + ((TEGRA241_MAIN_GPIO_PORT_##port * 8) + (offset)) + +/* GPIOs implemented by AON GPIO controller */ +#define TEGRA241_AON_GPIO_PORT_AA 0 +#define TEGRA241_AON_GPIO_PORT_BB 1 + +#define TEGRA241_AON_GPIO(port, offset) \ + ((TEGRA241_AON_GPIO_PORT_##port * 8) + (offset)) + +#endif diff --git a/include/dt-bindings/iio/adc/at91-sama5d2_adc.h b/include/dt-bindings/iio/adc/at91-sama5d2_adc.h index 70f99dbdbb42..866d36530583 100644 --- a/include/dt-bindings/iio/adc/at91-sama5d2_adc.h +++ b/include/dt-bindings/iio/adc/at91-sama5d2_adc.h @@ -13,4 +13,7 @@ /* pressure channel index */ #define AT91_SAMA5D2_ADC_P_CHANNEL 26 +/* SAMA7G5 Temperature sensor channel index. */ +#define AT91_SAMA7G5_ADC_TEMP_CHANNEL 31 + #endif diff --git a/include/dt-bindings/iio/adc/ingenic,adc.h b/include/dt-bindings/iio/adc/ingenic,adc.h index 42f871ab3272..a6ccc031635b 100644 --- a/include/dt-bindings/iio/adc/ingenic,adc.h +++ b/include/dt-bindings/iio/adc/ingenic,adc.h @@ -7,5 +7,12 @@ #define INGENIC_ADC_AUX 0 #define INGENIC_ADC_BATTERY 1 #define INGENIC_ADC_AUX2 2 +#define INGENIC_ADC_TOUCH_XP 3 +#define INGENIC_ADC_TOUCH_YP 4 +#define INGENIC_ADC_TOUCH_XN 5 +#define INGENIC_ADC_TOUCH_YN 6 +#define INGENIC_ADC_TOUCH_XD 7 +#define INGENIC_ADC_TOUCH_YD 8 +#define INGENIC_ADC_AUX0 9 #endif diff --git a/include/dt-bindings/iio/adc/mediatek,mt6370_adc.h b/include/dt-bindings/iio/adc/mediatek,mt6370_adc.h new file mode 100644 index 000000000000..6ee725547763 --- /dev/null +++ b/include/dt-bindings/iio/adc/mediatek,mt6370_adc.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ + +#ifndef __DT_BINDINGS_MEDIATEK_MT6370_ADC_H__ +#define __DT_BINDINGS_MEDIATEK_MT6370_ADC_H__ + +/* ADC Channel Index */ +#define MT6370_CHAN_VBUSDIV5 0 +#define MT6370_CHAN_VBUSDIV2 1 +#define MT6370_CHAN_VSYS 2 +#define MT6370_CHAN_VBAT 3 +#define MT6370_CHAN_TS_BAT 4 +#define MT6370_CHAN_IBUS 5 +#define MT6370_CHAN_IBAT 6 +#define MT6370_CHAN_CHG_VDDP 7 +#define MT6370_CHAN_TEMP_JC 8 +#define MT6370_CHAN_MAX 9 + +#endif diff --git a/include/dt-bindings/iio/addac/adi,ad74413r.h b/include/dt-bindings/iio/addac/adi,ad74413r.h new file mode 100644 index 000000000000..204f92bbd79f --- /dev/null +++ b/include/dt-bindings/iio/addac/adi,ad74413r.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef _DT_BINDINGS_ADI_AD74413R_H +#define _DT_BINDINGS_ADI_AD74413R_H + +#define CH_FUNC_HIGH_IMPEDANCE 0x0 +#define CH_FUNC_VOLTAGE_OUTPUT 0x1 +#define CH_FUNC_CURRENT_OUTPUT 0x2 +#define CH_FUNC_VOLTAGE_INPUT 0x3 +#define CH_FUNC_CURRENT_INPUT_EXT_POWER 0x4 +#define CH_FUNC_CURRENT_INPUT_LOOP_POWER 0x5 +#define CH_FUNC_RESISTANCE_INPUT 0x6 +#define CH_FUNC_DIGITAL_INPUT_LOGIC 0x7 +#define CH_FUNC_DIGITAL_INPUT_LOOP_POWER 0x8 +#define CH_FUNC_CURRENT_INPUT_EXT_POWER_HART 0x9 +#define CH_FUNC_CURRENT_INPUT_LOOP_POWER_HART 0xA + +#define CH_FUNC_MIN CH_FUNC_HIGH_IMPEDANCE +#define CH_FUNC_MAX CH_FUNC_CURRENT_INPUT_LOOP_POWER_HART + +#endif /* _DT_BINDINGS_ADI_AD74413R_H */ diff --git a/include/dt-bindings/iio/qcom,spmi-adc7-pm8350.h b/include/dt-bindings/iio/qcom,spmi-adc7-pm8350.h new file mode 100644 index 000000000000..9426f27a1946 --- /dev/null +++ b/include/dt-bindings/iio/qcom,spmi-adc7-pm8350.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H +#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H + +#ifndef PM8350_SID +#define PM8350_SID 1 +#endif + +/* ADC channels for PM8350_ADC for PMIC7 */ +#define PM8350_ADC7_REF_GND (PM8350_SID << 8 | 0x0) +#define PM8350_ADC7_1P25VREF (PM8350_SID << 8 | 0x01) +#define PM8350_ADC7_VREF_VADC (PM8350_SID << 8 | 0x02) +#define PM8350_ADC7_DIE_TEMP (PM8350_SID << 8 | 0x03) + +#define PM8350_ADC7_AMUX_THM1 (PM8350_SID << 8 | 0x04) +#define PM8350_ADC7_AMUX_THM2 (PM8350_SID << 8 | 0x05) +#define PM8350_ADC7_AMUX_THM3 (PM8350_SID << 8 | 0x06) +#define PM8350_ADC7_AMUX_THM4 (PM8350_SID << 8 | 0x07) +#define PM8350_ADC7_AMUX_THM5 (PM8350_SID << 8 | 0x08) +#define PM8350_ADC7_GPIO1 (PM8350_SID << 8 | 0x0a) +#define PM8350_ADC7_GPIO2 (PM8350_SID << 8 | 0x0b) +#define PM8350_ADC7_GPIO3 (PM8350_SID << 8 | 0x0c) +#define PM8350_ADC7_GPIO4 (PM8350_SID << 8 | 0x0d) + +/* 30k pull-up1 */ +#define PM8350_ADC7_AMUX_THM1_30K_PU (PM8350_SID << 8 | 0x24) +#define PM8350_ADC7_AMUX_THM2_30K_PU (PM8350_SID << 8 | 0x25) +#define PM8350_ADC7_AMUX_THM3_30K_PU (PM8350_SID << 8 | 0x26) +#define PM8350_ADC7_AMUX_THM4_30K_PU (PM8350_SID << 8 | 0x27) +#define PM8350_ADC7_AMUX_THM5_30K_PU (PM8350_SID << 8 | 0x28) +#define PM8350_ADC7_GPIO1_30K_PU (PM8350_SID << 8 | 0x2a) +#define PM8350_ADC7_GPIO2_30K_PU (PM8350_SID << 8 | 0x2b) +#define PM8350_ADC7_GPIO3_30K_PU (PM8350_SID << 8 | 0x2c) +#define PM8350_ADC7_GPIO4_30K_PU (PM8350_SID << 8 | 0x2d) + +/* 100k pull-up2 */ +#define PM8350_ADC7_AMUX_THM1_100K_PU (PM8350_SID << 8 | 0x44) +#define PM8350_ADC7_AMUX_THM2_100K_PU (PM8350_SID << 8 | 0x45) +#define PM8350_ADC7_AMUX_THM3_100K_PU (PM8350_SID << 8 | 0x46) +#define PM8350_ADC7_AMUX_THM4_100K_PU (PM8350_SID << 8 | 0x47) +#define PM8350_ADC7_AMUX_THM5_100K_PU (PM8350_SID << 8 | 0x48) +#define PM8350_ADC7_GPIO1_100K_PU (PM8350_SID << 8 | 0x4a) +#define PM8350_ADC7_GPIO2_100K_PU (PM8350_SID << 8 | 0x4b) +#define PM8350_ADC7_GPIO3_100K_PU (PM8350_SID << 8 | 0x4c) +#define PM8350_ADC7_GPIO4_100K_PU (PM8350_SID << 8 | 0x4d) + +/* 400k pull-up3 */ +#define PM8350_ADC7_AMUX_THM1_400K_PU (PM8350_SID << 8 | 0x64) +#define PM8350_ADC7_AMUX_THM2_400K_PU (PM8350_SID << 8 | 0x65) +#define PM8350_ADC7_AMUX_THM3_400K_PU (PM8350_SID << 8 | 0x66) +#define PM8350_ADC7_AMUX_THM4_400K_PU (PM8350_SID << 8 | 0x67) +#define PM8350_ADC7_AMUX_THM5_400K_PU (PM8350_SID << 8 | 0x68) +#define PM8350_ADC7_GPIO1_400K_PU (PM8350_SID << 8 | 0x6a) +#define PM8350_ADC7_GPIO2_400K_PU (PM8350_SID << 8 | 0x6b) +#define PM8350_ADC7_GPIO3_400K_PU (PM8350_SID << 8 | 0x6c) +#define PM8350_ADC7_GPIO4_400K_PU (PM8350_SID << 8 | 0x6d) + +/* 1/3 Divider */ +#define PM8350_ADC7_GPIO4_DIV3 (PM8350_SID << 8 | 0x8d) + +#define PM8350_ADC7_VPH_PWR (PM8350_SID << 8 | 0x8e) + +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H */ diff --git a/include/dt-bindings/iio/qcom,spmi-adc7-pm8350b.h b/include/dt-bindings/iio/qcom,spmi-adc7-pm8350b.h new file mode 100644 index 000000000000..dc2497c27e16 --- /dev/null +++ b/include/dt-bindings/iio/qcom,spmi-adc7-pm8350b.h @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8350B_H +#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8350B_H + +#ifndef PM8350B_SID +#define PM8350B_SID 3 +#endif + +/* ADC channels for PM8350B_ADC for PMIC7 */ +#define PM8350B_ADC7_REF_GND (PM8350B_SID << 8 | 0x0) +#define PM8350B_ADC7_1P25VREF (PM8350B_SID << 8 | 0x01) +#define PM8350B_ADC7_VREF_VADC (PM8350B_SID << 8 | 0x02) +#define PM8350B_ADC7_DIE_TEMP (PM8350B_SID << 8 | 0x03) + +#define PM8350B_ADC7_AMUX_THM1 (PM8350B_SID << 8 | 0x04) +#define PM8350B_ADC7_AMUX_THM2 (PM8350B_SID << 8 | 0x05) +#define PM8350B_ADC7_AMUX_THM3 (PM8350B_SID << 8 | 0x06) +#define PM8350B_ADC7_AMUX_THM4 (PM8350B_SID << 8 | 0x07) +#define PM8350B_ADC7_AMUX_THM5 (PM8350B_SID << 8 | 0x08) +#define PM8350B_ADC7_AMUX_THM6 (PM8350B_SID << 8 | 0x09) +#define PM8350B_ADC7_GPIO1 (PM8350B_SID << 8 | 0x0a) +#define PM8350B_ADC7_GPIO2 (PM8350B_SID << 8 | 0x0b) +#define PM8350B_ADC7_GPIO3 (PM8350B_SID << 8 | 0x0c) +#define PM8350B_ADC7_GPIO4 (PM8350B_SID << 8 | 0x0d) + +#define PM8350B_ADC7_CHG_TEMP (PM8350B_SID << 8 | 0x10) +#define PM8350B_ADC7_USB_IN_V_16 (PM8350B_SID << 8 | 0x11) +#define PM8350B_ADC7_VDC_16 (PM8350B_SID << 8 | 0x12) +#define PM8350B_ADC7_CC1_ID (PM8350B_SID << 8 | 0x13) +#define PM8350B_ADC7_VREF_BAT_THERM (PM8350B_SID << 8 | 0x15) +#define PM8350B_ADC7_IIN_FB (PM8350B_SID << 8 | 0x17) + +/* 30k pull-up1 */ +#define PM8350B_ADC7_AMUX_THM1_30K_PU (PM8350B_SID << 8 | 0x24) +#define PM8350B_ADC7_AMUX_THM2_30K_PU (PM8350B_SID << 8 | 0x25) +#define PM8350B_ADC7_AMUX_THM3_30K_PU (PM8350B_SID << 8 | 0x26) +#define PM8350B_ADC7_AMUX_THM4_30K_PU (PM8350B_SID << 8 | 0x27) +#define PM8350B_ADC7_AMUX_THM5_30K_PU (PM8350B_SID << 8 | 0x28) +#define PM8350B_ADC7_AMUX_THM6_30K_PU (PM8350B_SID << 8 | 0x29) +#define PM8350B_ADC7_GPIO1_30K_PU (PM8350B_SID << 8 | 0x2a) +#define PM8350B_ADC7_GPIO2_30K_PU (PM8350B_SID << 8 | 0x2b) +#define PM8350B_ADC7_GPIO3_30K_PU (PM8350B_SID << 8 | 0x2c) +#define PM8350B_ADC7_GPIO4_30K_PU (PM8350B_SID << 8 | 0x2d) +#define PM8350B_ADC7_CC1_ID_30K_PU (PM8350B_SID << 8 | 0x33) + +/* 100k pull-up2 */ +#define PM8350B_ADC7_AMUX_THM1_100K_PU (PM8350B_SID << 8 | 0x44) +#define PM8350B_ADC7_AMUX_THM2_100K_PU (PM8350B_SID << 8 | 0x45) +#define PM8350B_ADC7_AMUX_THM3_100K_PU (PM8350B_SID << 8 | 0x46) +#define PM8350B_ADC7_AMUX_THM4_100K_PU (PM8350B_SID << 8 | 0x47) +#define PM8350B_ADC7_AMUX_THM5_100K_PU (PM8350B_SID << 8 | 0x48) +#define PM8350B_ADC7_AMUX_THM6_100K_PU (PM8350B_SID << 8 | 0x49) +#define PM8350B_ADC7_GPIO1_100K_PU (PM8350B_SID << 8 | 0x4a) +#define PM8350B_ADC7_GPIO2_100K_PU (PM8350B_SID << 8 | 0x4b) +#define PM8350B_ADC7_GPIO3_100K_PU (PM8350B_SID << 8 | 0x4c) +#define PM8350B_ADC7_GPIO4_100K_PU (PM8350B_SID << 8 | 0x4d) +#define PM8350B_ADC7_CC1_ID_100K_PU (PM8350B_SID << 8 | 0x53) + +/* 400k pull-up3 */ +#define PM8350B_ADC7_AMUX_THM1_400K_PU (PM8350B_SID << 8 | 0x64) +#define PM8350B_ADC7_AMUX_THM2_400K_PU (PM8350B_SID << 8 | 0x65) +#define PM8350B_ADC7_AMUX_THM3_400K_PU (PM8350B_SID << 8 | 0x66) +#define PM8350B_ADC7_AMUX_THM4_400K_PU (PM8350B_SID << 8 | 0x67) +#define PM8350B_ADC7_AMUX_THM5_400K_PU (PM8350B_SID << 8 | 0x68) +#define PM8350B_ADC7_AMUX_THM6_400K_PU (PM8350B_SID << 8 | 0x69) +#define PM8350B_ADC7_GPIO1_400K_PU (PM8350B_SID << 8 | 0x6a) +#define PM8350B_ADC7_GPIO2_400K_PU (PM8350B_SID << 8 | 0x6b) +#define PM8350B_ADC7_GPIO3_400K_PU (PM8350B_SID << 8 | 0x6c) +#define PM8350B_ADC7_GPIO4_400K_PU (PM8350B_SID << 8 | 0x6d) +#define PM8350B_ADC7_CC1_ID_400K_PU (PM8350B_SID << 8 | 0x73) + +/* 1/3 Divider */ +#define PM8350B_ADC7_GPIO1_DIV3 (PM8350B_SID << 8 | 0x8a) +#define PM8350B_ADC7_GPIO2_DIV3 (PM8350B_SID << 8 | 0x8b) +#define PM8350B_ADC7_GPIO3_DIV3 (PM8350B_SID << 8 | 0x8c) +#define PM8350B_ADC7_GPIO4_DIV3 (PM8350B_SID << 8 | 0x8d) + +#define PM8350B_ADC7_VPH_PWR (PM8350B_SID << 8 | 0x8e) +#define PM8350B_ADC7_VBAT_SNS (PM8350B_SID << 8 | 0x8f) + +#define PM8350B_ADC7_SBUx (PM8350B_SID << 8 | 0x94) +#define PM8350B_ADC7_VBAT_2S_MID (PM8350B_SID << 8 | 0x96) + +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8350B_H */ diff --git a/include/dt-bindings/iio/qcom,spmi-adc7-pmk8350.h b/include/dt-bindings/iio/qcom,spmi-adc7-pmk8350.h new file mode 100644 index 000000000000..6c296870e95b --- /dev/null +++ b/include/dt-bindings/iio/qcom,spmi-adc7-pmk8350.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMK8350_H +#define _DT_BINDINGS_QCOM_SPMI_VADC_PMK8350_H + +#ifndef PMK8350_SID +#define PMK8350_SID 0 +#endif + +/* ADC channels for PMK8350_ADC for PMIC7 */ +#define PMK8350_ADC7_REF_GND (PMK8350_SID << 8 | 0x0) +#define PMK8350_ADC7_1P25VREF (PMK8350_SID << 8 | 0x01) +#define PMK8350_ADC7_VREF_VADC (PMK8350_SID << 8 | 0x02) +#define PMK8350_ADC7_DIE_TEMP (PMK8350_SID << 8 | 0x03) + +#define PMK8350_ADC7_AMUX_THM1 (PMK8350_SID << 8 | 0x04) +#define PMK8350_ADC7_AMUX_THM2 (PMK8350_SID << 8 | 0x05) +#define PMK8350_ADC7_AMUX_THM3 (PMK8350_SID << 8 | 0x06) +#define PMK8350_ADC7_AMUX_THM4 (PMK8350_SID << 8 | 0x07) +#define PMK8350_ADC7_AMUX_THM5 (PMK8350_SID << 8 | 0x08) + +/* 30k pull-up1 */ +#define PMK8350_ADC7_AMUX_THM1_30K_PU (PMK8350_SID << 8 | 0x24) +#define PMK8350_ADC7_AMUX_THM2_30K_PU (PMK8350_SID << 8 | 0x25) +#define PMK8350_ADC7_AMUX_THM3_30K_PU (PMK8350_SID << 8 | 0x26) +#define PMK8350_ADC7_AMUX_THM4_30K_PU (PMK8350_SID << 8 | 0x27) +#define PMK8350_ADC7_AMUX_THM5_30K_PU (PMK8350_SID << 8 | 0x28) + +/* 100k pull-up2 */ +#define PMK8350_ADC7_AMUX_THM1_100K_PU (PMK8350_SID << 8 | 0x44) +#define PMK8350_ADC7_AMUX_THM2_100K_PU (PMK8350_SID << 8 | 0x45) +#define PMK8350_ADC7_AMUX_THM3_100K_PU (PMK8350_SID << 8 | 0x46) +#define PMK8350_ADC7_AMUX_THM4_100K_PU (PMK8350_SID << 8 | 0x47) +#define PMK8350_ADC7_AMUX_THM5_100K_PU (PMK8350_SID << 8 | 0x48) + +/* 400k pull-up3 */ +#define PMK8350_ADC7_AMUX_THM1_400K_PU (PMK8350_SID << 8 | 0x64) +#define PMK8350_ADC7_AMUX_THM2_400K_PU (PMK8350_SID << 8 | 0x65) +#define PMK8350_ADC7_AMUX_THM3_400K_PU (PMK8350_SID << 8 | 0x66) +#define PMK8350_ADC7_AMUX_THM4_400K_PU (PMK8350_SID << 8 | 0x67) +#define PMK8350_ADC7_AMUX_THM5_400K_PU (PMK8350_SID << 8 | 0x68) + +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMK8350_H */ diff --git a/include/dt-bindings/iio/qcom,spmi-adc7-pmr735a.h b/include/dt-bindings/iio/qcom,spmi-adc7-pmr735a.h new file mode 100644 index 000000000000..d6df1b19e5ff --- /dev/null +++ b/include/dt-bindings/iio/qcom,spmi-adc7-pmr735a.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMR735A_H +#define _DT_BINDINGS_QCOM_SPMI_VADC_PMR735A_H + +#ifndef PMR735A_SID +#define PMR735A_SID 4 +#endif + +/* ADC channels for PMR735A_ADC for PMIC7 */ +#define PMR735A_ADC7_REF_GND (PMR735A_SID << 8 | 0x0) +#define PMR735A_ADC7_1P25VREF (PMR735A_SID << 8 | 0x01) +#define PMR735A_ADC7_VREF_VADC (PMR735A_SID << 8 | 0x02) +#define PMR735A_ADC7_DIE_TEMP (PMR735A_SID << 8 | 0x03) + +#define PMR735A_ADC7_GPIO1 (PMR735A_SID << 8 | 0x0a) +#define PMR735A_ADC7_GPIO2 (PMR735A_SID << 8 | 0x0b) +#define PMR735A_ADC7_GPIO3 (PMR735A_SID << 8 | 0x0c) + +/* 100k pull-up2 */ +#define PMR735A_ADC7_GPIO1_100K_PU (PMR735A_SID << 8 | 0x4a) +#define PMR735A_ADC7_GPIO2_100K_PU (PMR735A_SID << 8 | 0x4b) +#define PMR735A_ADC7_GPIO3_100K_PU (PMR735A_SID << 8 | 0x4c) + +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMR735A_H */ diff --git a/include/dt-bindings/iio/qcom,spmi-adc7-pmr735b.h b/include/dt-bindings/iio/qcom,spmi-adc7-pmr735b.h new file mode 100644 index 000000000000..8da0e7dab315 --- /dev/null +++ b/include/dt-bindings/iio/qcom,spmi-adc7-pmr735b.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMR735B_H +#define _DT_BINDINGS_QCOM_SPMI_VADC_PMR735B_H + +#ifndef PMR735B_SID +#define PMR735B_SID 5 +#endif + +/* ADC channels for PMR735B_ADC for PMIC7 */ +#define PMR735B_ADC7_REF_GND (PMR735B_SID << 8 | 0x0) +#define PMR735B_ADC7_1P25VREF (PMR735B_SID << 8 | 0x01) +#define PMR735B_ADC7_VREF_VADC (PMR735B_SID << 8 | 0x02) +#define PMR735B_ADC7_DIE_TEMP (PMR735B_SID << 8 | 0x03) + +#define PMR735B_ADC7_GPIO1 (PMR735B_SID << 8 | 0x0a) +#define PMR735B_ADC7_GPIO2 (PMR735B_SID << 8 | 0x0b) +#define PMR735B_ADC7_GPIO3 (PMR735B_SID << 8 | 0x0c) + +/* 100k pull-up2 */ +#define PMR735B_ADC7_GPIO1_100K_PU (PMR735B_SID << 8 | 0x4a) +#define PMR735B_ADC7_GPIO2_100K_PU (PMR735B_SID << 8 | 0x4b) +#define PMR735B_ADC7_GPIO3_100K_PU (PMR735B_SID << 8 | 0x4c) + +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMR735B_H */ diff --git a/include/dt-bindings/iio/qcom,spmi-vadc.h b/include/dt-bindings/iio/qcom,spmi-vadc.h index 61d556db1542..08adfe25964c 100644 --- a/include/dt-bindings/iio/qcom,spmi-vadc.h +++ b/include/dt-bindings/iio/qcom,spmi-vadc.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (c) 2012-2014,2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2014,2018,2020 The Linux Foundation. All rights reserved. */ #ifndef _DT_BINDINGS_QCOM_SPMI_VADC_H @@ -221,4 +221,80 @@ #define ADC5_MAX_CHANNEL 0xc0 +/* ADC channels for ADC for PMIC7 */ + +#define ADC7_REF_GND 0x00 +#define ADC7_1P25VREF 0x01 +#define ADC7_VREF_VADC 0x02 +#define ADC7_DIE_TEMP 0x03 + +#define ADC7_AMUX_THM1 0x04 +#define ADC7_AMUX_THM2 0x05 +#define ADC7_AMUX_THM3 0x06 +#define ADC7_AMUX_THM4 0x07 +#define ADC7_AMUX_THM5 0x08 +#define ADC7_AMUX_THM6 0x09 +#define ADC7_GPIO1 0x0a +#define ADC7_GPIO2 0x0b +#define ADC7_GPIO3 0x0c +#define ADC7_GPIO4 0x0d + +#define ADC7_CHG_TEMP 0x10 +#define ADC7_USB_IN_V_16 0x11 +#define ADC7_VDC_16 0x12 +#define ADC7_CC1_ID 0x13 +#define ADC7_VREF_BAT_THERM 0x15 +#define ADC7_IIN_FB 0x17 + +/* 30k pull-up1 */ +#define ADC7_AMUX_THM1_30K_PU 0x24 +#define ADC7_AMUX_THM2_30K_PU 0x25 +#define ADC7_AMUX_THM3_30K_PU 0x26 +#define ADC7_AMUX_THM4_30K_PU 0x27 +#define ADC7_AMUX_THM5_30K_PU 0x28 +#define ADC7_AMUX_THM6_30K_PU 0x29 +#define ADC7_GPIO1_30K_PU 0x2a +#define ADC7_GPIO2_30K_PU 0x2b +#define ADC7_GPIO3_30K_PU 0x2c +#define ADC7_GPIO4_30K_PU 0x2d +#define ADC7_CC1_ID_30K_PU 0x33 + +/* 100k pull-up2 */ +#define ADC7_AMUX_THM1_100K_PU 0x44 +#define ADC7_AMUX_THM2_100K_PU 0x45 +#define ADC7_AMUX_THM3_100K_PU 0x46 +#define ADC7_AMUX_THM4_100K_PU 0x47 +#define ADC7_AMUX_THM5_100K_PU 0x48 +#define ADC7_AMUX_THM6_100K_PU 0x49 +#define ADC7_GPIO1_100K_PU 0x4a +#define ADC7_GPIO2_100K_PU 0x4b +#define ADC7_GPIO3_100K_PU 0x4c +#define ADC7_GPIO4_100K_PU 0x4d +#define ADC7_CC1_ID_100K_PU 0x53 + +/* 400k pull-up3 */ +#define ADC7_AMUX_THM1_400K_PU 0x64 +#define ADC7_AMUX_THM2_400K_PU 0x65 +#define ADC7_AMUX_THM3_400K_PU 0x66 +#define ADC7_AMUX_THM4_400K_PU 0x67 +#define ADC7_AMUX_THM5_400K_PU 0x68 +#define ADC7_AMUX_THM6_400K_PU 0x69 +#define ADC7_GPIO1_400K_PU 0x6a +#define ADC7_GPIO2_400K_PU 0x6b +#define ADC7_GPIO3_400K_PU 0x6c +#define ADC7_GPIO4_400K_PU 0x6d +#define ADC7_CC1_ID_400K_PU 0x73 + +/* 1/3 Divider */ +#define ADC7_GPIO1_DIV3 0x8a +#define ADC7_GPIO2_DIV3 0x8b +#define ADC7_GPIO3_DIV3 0x8c +#define ADC7_GPIO4_DIV3 0x8d + +#define ADC7_VPH_PWR 0x8e +#define ADC7_VBAT_SNS 0x8f + +#define ADC7_SBUx 0x94 +#define ADC7_VBAT_2S_MID 0x96 + #endif /* _DT_BINDINGS_QCOM_SPMI_VADC_H */ diff --git a/include/dt-bindings/input/atmel-maxtouch.h b/include/dt-bindings/input/atmel-maxtouch.h new file mode 100644 index 000000000000..7345ab32224d --- /dev/null +++ b/include/dt-bindings/input/atmel-maxtouch.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef _DT_BINDINGS_ATMEL_MAXTOUCH_H +#define _DT_BINDINGS_ATMEL_MAXTOUCH_H + +#define ATMEL_MXT_WAKEUP_NONE 0 +#define ATMEL_MXT_WAKEUP_I2C_SCL 1 +#define ATMEL_MXT_WAKEUP_GPIO 2 + +#endif /* _DT_BINDINGS_ATMEL_MAXTOUCH_H */ diff --git a/include/dt-bindings/input/cros-ec-keyboard.h b/include/dt-bindings/input/cros-ec-keyboard.h new file mode 100644 index 000000000000..f0ae03634a96 --- /dev/null +++ b/include/dt-bindings/input/cros-ec-keyboard.h @@ -0,0 +1,103 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides the constants of the standard Chrome OS key matrix + * for cros-ec keyboard-controller bindings. + * + * Copyright (c) 2021 Google, Inc + */ + +#ifndef _CROS_EC_KEYBOARD_H +#define _CROS_EC_KEYBOARD_H + +#define CROS_STD_TOP_ROW_KEYMAP \ + MATRIX_KEY(0x00, 0x02, KEY_F1) \ + MATRIX_KEY(0x03, 0x02, KEY_F2) \ + MATRIX_KEY(0x02, 0x02, KEY_F3) \ + MATRIX_KEY(0x01, 0x02, KEY_F4) \ + MATRIX_KEY(0x03, 0x04, KEY_F5) \ + MATRIX_KEY(0x02, 0x04, KEY_F6) \ + MATRIX_KEY(0x01, 0x04, KEY_F7) \ + MATRIX_KEY(0x02, 0x09, KEY_F8) \ + MATRIX_KEY(0x01, 0x09, KEY_F9) \ + MATRIX_KEY(0x00, 0x04, KEY_F10) + +#define CROS_STD_MAIN_KEYMAP \ + MATRIX_KEY(0x00, 0x01, KEY_LEFTMETA) \ + MATRIX_KEY(0x00, 0x03, KEY_B) \ + MATRIX_KEY(0x00, 0x05, KEY_RO) \ + MATRIX_KEY(0x00, 0x06, KEY_N) \ + MATRIX_KEY(0x00, 0x08, KEY_EQUAL) \ + MATRIX_KEY(0x00, 0x0a, KEY_RIGHTALT) \ + MATRIX_KEY(0x01, 0x01, KEY_ESC) \ + MATRIX_KEY(0x01, 0x03, KEY_G) \ + MATRIX_KEY(0x01, 0x06, KEY_H) \ + MATRIX_KEY(0x01, 0x08, KEY_APOSTROPHE) \ + MATRIX_KEY(0x01, 0x0b, KEY_BACKSPACE) \ + MATRIX_KEY(0x01, 0x0c, KEY_HENKAN) \ + \ + MATRIX_KEY(0x02, 0x00, KEY_LEFTCTRL) \ + MATRIX_KEY(0x02, 0x01, KEY_TAB) \ + MATRIX_KEY(0x02, 0x03, KEY_T) \ + MATRIX_KEY(0x02, 0x05, KEY_RIGHTBRACE) \ + MATRIX_KEY(0x02, 0x06, KEY_Y) \ + MATRIX_KEY(0x02, 0x07, KEY_102ND) \ + MATRIX_KEY(0x02, 0x08, KEY_LEFTBRACE) \ + MATRIX_KEY(0x02, 0x0a, KEY_YEN) \ + \ + MATRIX_KEY(0x03, 0x00, KEY_LEFTMETA) \ + MATRIX_KEY(0x03, 0x01, KEY_GRAVE) \ + MATRIX_KEY(0x03, 0x03, KEY_5) \ + MATRIX_KEY(0x03, 0x06, KEY_6) \ + MATRIX_KEY(0x03, 0x08, KEY_MINUS) \ + MATRIX_KEY(0x03, 0x09, KEY_SLEEP) \ + MATRIX_KEY(0x03, 0x0b, KEY_BACKSLASH) \ + MATRIX_KEY(0x03, 0x0c, KEY_MUHENKAN) \ + \ + MATRIX_KEY(0x04, 0x00, KEY_RIGHTCTRL) \ + MATRIX_KEY(0x04, 0x01, KEY_A) \ + MATRIX_KEY(0x04, 0x02, KEY_D) \ + MATRIX_KEY(0x04, 0x03, KEY_F) \ + MATRIX_KEY(0x04, 0x04, KEY_S) \ + MATRIX_KEY(0x04, 0x05, KEY_K) \ + MATRIX_KEY(0x04, 0x06, KEY_J) \ + MATRIX_KEY(0x04, 0x08, KEY_SEMICOLON) \ + MATRIX_KEY(0x04, 0x09, KEY_L) \ + MATRIX_KEY(0x04, 0x0a, KEY_BACKSLASH) \ + MATRIX_KEY(0x04, 0x0b, KEY_ENTER) \ + \ + MATRIX_KEY(0x05, 0x01, KEY_Z) \ + MATRIX_KEY(0x05, 0x02, KEY_C) \ + MATRIX_KEY(0x05, 0x03, KEY_V) \ + MATRIX_KEY(0x05, 0x04, KEY_X) \ + MATRIX_KEY(0x05, 0x05, KEY_COMMA) \ + MATRIX_KEY(0x05, 0x06, KEY_M) \ + MATRIX_KEY(0x05, 0x07, KEY_LEFTSHIFT) \ + MATRIX_KEY(0x05, 0x08, KEY_SLASH) \ + MATRIX_KEY(0x05, 0x09, KEY_DOT) \ + MATRIX_KEY(0x05, 0x0b, KEY_SPACE) \ + \ + MATRIX_KEY(0x06, 0x01, KEY_1) \ + MATRIX_KEY(0x06, 0x02, KEY_3) \ + MATRIX_KEY(0x06, 0x03, KEY_4) \ + MATRIX_KEY(0x06, 0x04, KEY_2) \ + MATRIX_KEY(0x06, 0x05, KEY_8) \ + MATRIX_KEY(0x06, 0x06, KEY_7) \ + MATRIX_KEY(0x06, 0x08, KEY_0) \ + MATRIX_KEY(0x06, 0x09, KEY_9) \ + MATRIX_KEY(0x06, 0x0a, KEY_LEFTALT) \ + MATRIX_KEY(0x06, 0x0b, KEY_DOWN) \ + MATRIX_KEY(0x06, 0x0c, KEY_RIGHT) \ + \ + MATRIX_KEY(0x07, 0x01, KEY_Q) \ + MATRIX_KEY(0x07, 0x02, KEY_E) \ + MATRIX_KEY(0x07, 0x03, KEY_R) \ + MATRIX_KEY(0x07, 0x04, KEY_W) \ + MATRIX_KEY(0x07, 0x05, KEY_I) \ + MATRIX_KEY(0x07, 0x06, KEY_U) \ + MATRIX_KEY(0x07, 0x07, KEY_RIGHTSHIFT) \ + MATRIX_KEY(0x07, 0x08, KEY_P) \ + MATRIX_KEY(0x07, 0x09, KEY_O) \ + MATRIX_KEY(0x07, 0x0b, KEY_UP) \ + MATRIX_KEY(0x07, 0x0c, KEY_LEFT) + +#endif /* _CROS_EC_KEYBOARD_H */ diff --git a/include/dt-bindings/interconnect/fsl,imx8mp.h b/include/dt-bindings/interconnect/fsl,imx8mp.h new file mode 100644 index 000000000000..7357d417529a --- /dev/null +++ b/include/dt-bindings/interconnect/fsl,imx8mp.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Interconnect framework driver for i.MX SoC + * + * Copyright 2022 NXP + * Peng Fan <peng.fan@nxp.com> + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_IMX8MP_H +#define __DT_BINDINGS_INTERCONNECT_IMX8MP_H + +#define IMX8MP_ICN_NOC 0 +#define IMX8MP_ICN_MAIN 1 +#define IMX8MP_ICS_DRAM 2 +#define IMX8MP_ICS_OCRAM 3 +#define IMX8MP_ICM_A53 4 +#define IMX8MP_ICM_SUPERMIX 5 +#define IMX8MP_ICM_GIC 6 +#define IMX8MP_ICM_MLMIX 7 + +#define IMX8MP_ICN_AUDIO 8 +#define IMX8MP_ICM_DSP 9 +#define IMX8MP_ICM_SDMA2PER 10 +#define IMX8MP_ICM_SDMA2BURST 11 +#define IMX8MP_ICM_SDMA3PER 12 +#define IMX8MP_ICM_SDMA3BURST 13 +#define IMX8MP_ICM_EDMA 14 + +#define IMX8MP_ICN_GPU 15 +#define IMX8MP_ICM_GPU2D 16 +#define IMX8MP_ICM_GPU3D 17 + +#define IMX8MP_ICN_HDMI 18 +#define IMX8MP_ICM_HRV 19 +#define IMX8MP_ICM_LCDIF_HDMI 20 +#define IMX8MP_ICM_HDCP 21 + +#define IMX8MP_ICN_HSIO 22 +#define IMX8MP_ICM_NOC_PCIE 23 +#define IMX8MP_ICM_USB1 24 +#define IMX8MP_ICM_USB2 25 +#define IMX8MP_ICM_PCIE 26 + +#define IMX8MP_ICN_MEDIA 27 +#define IMX8MP_ICM_LCDIF_RD 28 +#define IMX8MP_ICM_LCDIF_WR 29 +#define IMX8MP_ICM_ISI0 30 +#define IMX8MP_ICM_ISI1 31 +#define IMX8MP_ICM_ISI2 32 +#define IMX8MP_ICM_ISP0 33 +#define IMX8MP_ICM_ISP1 34 +#define IMX8MP_ICM_DWE 35 + +#define IMX8MP_ICN_VIDEO 36 +#define IMX8MP_ICM_VPU_G1 37 +#define IMX8MP_ICM_VPU_G2 38 +#define IMX8MP_ICM_VPU_H1 39 + +#endif /* __DT_BINDINGS_INTERCONNECT_IMX8MP_H */ diff --git a/include/dt-bindings/interconnect/imx8mm.h b/include/dt-bindings/interconnect/imx8mm.h new file mode 100644 index 000000000000..8f10bb06cb59 --- /dev/null +++ b/include/dt-bindings/interconnect/imx8mm.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Interconnect framework driver for i.MX SoC + * + * Copyright (c) 2019, BayLibre + * Copyright (c) 2019-2020, NXP + * Author: Alexandre Bailon <abailon@baylibre.com> + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_IMX8MM_H +#define __DT_BINDINGS_INTERCONNECT_IMX8MM_H + +#define IMX8MM_ICN_NOC 1 +#define IMX8MM_ICS_DRAM 2 +#define IMX8MM_ICS_OCRAM 3 +#define IMX8MM_ICM_A53 4 + +#define IMX8MM_ICM_VPU_H1 5 +#define IMX8MM_ICM_VPU_G1 6 +#define IMX8MM_ICM_VPU_G2 7 +#define IMX8MM_ICN_VIDEO 8 + +#define IMX8MM_ICM_GPU2D 9 +#define IMX8MM_ICM_GPU3D 10 +#define IMX8MM_ICN_GPU 11 + +#define IMX8MM_ICM_CSI 12 +#define IMX8MM_ICM_LCDIF 13 +#define IMX8MM_ICN_MIPI 14 + +#define IMX8MM_ICM_USB1 15 +#define IMX8MM_ICM_USB2 16 +#define IMX8MM_ICM_PCIE 17 +#define IMX8MM_ICN_HSIO 18 + +#define IMX8MM_ICM_SDMA2 19 +#define IMX8MM_ICM_SDMA3 20 +#define IMX8MM_ICN_AUDIO 21 + +#define IMX8MM_ICN_ENET 22 +#define IMX8MM_ICM_ENET 23 + +#define IMX8MM_ICN_MAIN 24 +#define IMX8MM_ICM_NAND 25 +#define IMX8MM_ICM_SDMA1 26 +#define IMX8MM_ICM_USDHC1 27 +#define IMX8MM_ICM_USDHC2 28 +#define IMX8MM_ICM_USDHC3 29 + +#endif /* __DT_BINDINGS_INTERCONNECT_IMX8MM_H */ diff --git a/include/dt-bindings/interconnect/imx8mn.h b/include/dt-bindings/interconnect/imx8mn.h new file mode 100644 index 000000000000..307b977100b6 --- /dev/null +++ b/include/dt-bindings/interconnect/imx8mn.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Interconnect framework driver for i.MX SoC + * + * Copyright (c) 2019-2020, NXP + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_IMX8MN_H +#define __DT_BINDINGS_INTERCONNECT_IMX8MN_H + +#define IMX8MN_ICN_NOC 1 +#define IMX8MN_ICS_DRAM 2 +#define IMX8MN_ICS_OCRAM 3 +#define IMX8MN_ICM_A53 4 + +#define IMX8MN_ICM_GPU 5 +#define IMX8MN_ICN_GPU 6 + +#define IMX8MN_ICM_CSI1 7 +#define IMX8MN_ICM_CSI2 8 +#define IMX8MN_ICM_ISI 9 +#define IMX8MN_ICM_LCDIF 10 +#define IMX8MN_ICN_MIPI 11 + +#define IMX8MN_ICM_USB 12 + +#define IMX8MN_ICM_SDMA2 13 +#define IMX8MN_ICM_SDMA3 14 +#define IMX8MN_ICN_AUDIO 15 + +#define IMX8MN_ICN_ENET 16 +#define IMX8MN_ICM_ENET 17 + +#define IMX8MN_ICM_NAND 18 +#define IMX8MN_ICM_SDMA1 19 +#define IMX8MN_ICM_USDHC1 20 +#define IMX8MN_ICM_USDHC2 21 +#define IMX8MN_ICM_USDHC3 22 +#define IMX8MN_ICN_MAIN 23 + +#endif /* __DT_BINDINGS_INTERCONNECT_IMX8MN_H */ diff --git a/include/dt-bindings/interconnect/imx8mq.h b/include/dt-bindings/interconnect/imx8mq.h new file mode 100644 index 000000000000..1a4cae7f8be2 --- /dev/null +++ b/include/dt-bindings/interconnect/imx8mq.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Interconnect framework driver for i.MX SoC + * + * Copyright (c) 2019-2020, NXP + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_IMX8MQ_H +#define __DT_BINDINGS_INTERCONNECT_IMX8MQ_H + +#define IMX8MQ_ICN_NOC 1 +#define IMX8MQ_ICS_DRAM 2 +#define IMX8MQ_ICS_OCRAM 3 +#define IMX8MQ_ICM_A53 4 + +#define IMX8MQ_ICM_VPU 5 +#define IMX8MQ_ICN_VIDEO 6 + +#define IMX8MQ_ICM_GPU 7 +#define IMX8MQ_ICN_GPU 8 + +#define IMX8MQ_ICM_DCSS 9 +#define IMX8MQ_ICN_DCSS 10 + +#define IMX8MQ_ICM_USB1 11 +#define IMX8MQ_ICM_USB2 12 +#define IMX8MQ_ICN_USB 13 + +#define IMX8MQ_ICM_CSI1 14 +#define IMX8MQ_ICM_CSI2 15 +#define IMX8MQ_ICM_LCDIF 16 +#define IMX8MQ_ICN_DISPLAY 17 + +#define IMX8MQ_ICM_SDMA2 18 +#define IMX8MQ_ICN_AUDIO 19 + +#define IMX8MQ_ICN_ENET 20 +#define IMX8MQ_ICM_ENET 21 + +#define IMX8MQ_ICM_SDMA1 22 +#define IMX8MQ_ICM_NAND 23 +#define IMX8MQ_ICM_USDHC1 24 +#define IMX8MQ_ICM_USDHC2 25 +#define IMX8MQ_ICM_PCIE1 26 +#define IMX8MQ_ICM_PCIE2 27 +#define IMX8MQ_ICN_MAIN 28 + +#endif /* __DT_BINDINGS_INTERCONNECT_IMX8MQ_H */ diff --git a/include/dt-bindings/interconnect/qcom,icc.h b/include/dt-bindings/interconnect/qcom,icc.h new file mode 100644 index 000000000000..cd34f36daaaa --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,icc.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_ICC_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_ICC_H + +/* + * The AMC bucket denotes constraints that are applied to hardware when + * icc_set_bw() completes, whereas the WAKE and SLEEP constraints are applied + * when the execution environment transitions between active and low power mode. + */ +#define QCOM_ICC_BUCKET_AMC 0 +#define QCOM_ICC_BUCKET_WAKE 1 +#define QCOM_ICC_BUCKET_SLEEP 2 +#define QCOM_ICC_NUM_BUCKETS 3 + +#define QCOM_ICC_TAG_AMC (1 << QCOM_ICC_BUCKET_AMC) +#define QCOM_ICC_TAG_WAKE (1 << QCOM_ICC_BUCKET_WAKE) +#define QCOM_ICC_TAG_SLEEP (1 << QCOM_ICC_BUCKET_SLEEP) +#define QCOM_ICC_TAG_ACTIVE_ONLY (QCOM_ICC_TAG_AMC | QCOM_ICC_TAG_WAKE) +#define QCOM_ICC_TAG_ALWAYS (QCOM_ICC_TAG_AMC | QCOM_ICC_TAG_WAKE |\ + QCOM_ICC_TAG_SLEEP) + +#endif diff --git a/include/dt-bindings/interconnect/qcom,msm8939.h b/include/dt-bindings/interconnect/qcom,msm8939.h new file mode 100644 index 000000000000..c22369a4b9f5 --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,msm8939.h @@ -0,0 +1,105 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Qualcomm interconnect IDs + * + * Copyright (c) 2020, Linaro Ltd. + * Author: Jun Nie <jun.nie@linaro.org> + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8939_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8939_H + +#define BIMC_SNOC_SLV 0 +#define MASTER_QDSS_BAM 1 +#define MASTER_QDSS_ETR 2 +#define MASTER_SNOC_CFG 3 +#define PCNOC_SNOC_SLV 4 +#define SLAVE_APSS 5 +#define SLAVE_CATS_128 6 +#define SLAVE_OCMEM_64 7 +#define SLAVE_IMEM 8 +#define SLAVE_QDSS_STM 9 +#define SLAVE_SRVC_SNOC 10 +#define SNOC_BIMC_0_MAS 11 +#define SNOC_BIMC_1_MAS 12 +#define SNOC_BIMC_2_MAS 13 +#define SNOC_INT_0 14 +#define SNOC_INT_1 15 +#define SNOC_INT_BIMC 16 +#define SNOC_PCNOC_MAS 17 +#define SNOC_QDSS_INT 18 + +#define MASTER_VIDEO_P0 0 +#define MASTER_JPEG 1 +#define MASTER_VFE 2 +#define MASTER_MDP_PORT0 3 +#define MASTER_MDP_PORT1 4 +#define MASTER_CPP 5 +#define SNOC_MM_INT_0 6 +#define SNOC_MM_INT_1 7 +#define SNOC_MM_INT_2 8 + +#define BIMC_SNOC_MAS 0 +#define MASTER_AMPSS_M0 1 +#define MASTER_GRAPHICS_3D 2 +#define MASTER_TCU0 3 +#define SLAVE_AMPSS_L2 4 +#define SLAVE_EBI_CH0 5 +#define SNOC_BIMC_0_SLV 6 +#define SNOC_BIMC_1_SLV 7 +#define SNOC_BIMC_2_SLV 8 + +#define MASTER_BLSP_1 0 +#define MASTER_DEHR 1 +#define MASTER_LPASS 2 +#define MASTER_CRYPTO_CORE0 3 +#define MASTER_SDCC_1 4 +#define MASTER_SDCC_2 5 +#define MASTER_SPDM 6 +#define MASTER_USB_HS1 7 +#define MASTER_USB_HS2 8 +#define PCNOC_INT_0 9 +#define PCNOC_INT_1 10 +#define PCNOC_MAS_0 11 +#define PCNOC_MAS_1 12 +#define PCNOC_SLV_0 13 +#define PCNOC_SLV_1 14 +#define PCNOC_SLV_2 15 +#define PCNOC_SLV_3 16 +#define PCNOC_SLV_4 17 +#define PCNOC_SLV_8 18 +#define PCNOC_SLV_9 19 +#define PCNOC_SNOC_MAS 20 +#define SLAVE_BIMC_CFG 21 +#define SLAVE_BLSP_1 22 +#define SLAVE_BOOT_ROM 23 +#define SLAVE_CAMERA_CFG 24 +#define SLAVE_CLK_CTL 25 +#define SLAVE_CRYPTO_0_CFG 26 +#define SLAVE_DEHR_CFG 27 +#define SLAVE_DISPLAY_CFG 28 +#define SLAVE_GRAPHICS_3D_CFG 29 +#define SLAVE_IMEM_CFG 30 +#define SLAVE_LPASS 31 +#define SLAVE_MPM 32 +#define SLAVE_MSG_RAM 33 +#define SLAVE_MSS 34 +#define SLAVE_PDM 35 +#define SLAVE_PMIC_ARB 36 +#define SLAVE_PCNOC_CFG 37 +#define SLAVE_PRNG 38 +#define SLAVE_QDSS_CFG 39 +#define SLAVE_RBCPR_CFG 40 +#define SLAVE_SDCC_1 41 +#define SLAVE_SDCC_2 42 +#define SLAVE_SECURITY 43 +#define SLAVE_SNOC_CFG 44 +#define SLAVE_SPDM 45 +#define SLAVE_TCSR 46 +#define SLAVE_TLMM 47 +#define SLAVE_USB_HS1 48 +#define SLAVE_USB_HS2 49 +#define SLAVE_VENUS_CFG 50 +#define SNOC_PCNOC_SLV 51 + +#endif diff --git a/include/dt-bindings/interconnect/qcom,msm8996.h b/include/dt-bindings/interconnect/qcom,msm8996.h new file mode 100644 index 000000000000..a0b7c0ec7bed --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,msm8996.h @@ -0,0 +1,163 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * Qualcomm MSM8996 interconnect IDs + * + * Copyright (c) 2021 Yassine Oudjana <y.oudjana@protonmail.com> + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8996_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8996_H + +/* A0NOC */ +#define MASTER_PCIE_0 0 +#define MASTER_PCIE_1 1 +#define MASTER_PCIE_2 2 + +/* A1NOC */ +#define MASTER_CNOC_A1NOC 0 +#define MASTER_CRYPTO_CORE0 1 +#define MASTER_PNOC_A1NOC 2 + +/* A2NOC */ +#define MASTER_USB3 0 +#define MASTER_IPA 1 +#define MASTER_UFS 2 + +/* BIMC */ +#define MASTER_AMPSS_M0 0 +#define MASTER_GRAPHICS_3D 1 +#define MASTER_MNOC_BIMC 2 +#define MASTER_SNOC_BIMC 3 +#define SLAVE_EBI_CH0 4 +#define SLAVE_HMSS_L3 5 +#define SLAVE_BIMC_SNOC_0 6 +#define SLAVE_BIMC_SNOC_1 7 + +/* CNOC */ +#define MASTER_SNOC_CNOC 0 +#define MASTER_QDSS_DAP 1 +#define SLAVE_CNOC_A1NOC 2 +#define SLAVE_CLK_CTL 3 +#define SLAVE_TCSR 4 +#define SLAVE_TLMM 5 +#define SLAVE_CRYPTO_0_CFG 6 +#define SLAVE_MPM 7 +#define SLAVE_PIMEM_CFG 8 +#define SLAVE_IMEM_CFG 9 +#define SLAVE_MESSAGE_RAM 10 +#define SLAVE_BIMC_CFG 11 +#define SLAVE_PMIC_ARB 12 +#define SLAVE_PRNG 13 +#define SLAVE_DCC_CFG 14 +#define SLAVE_RBCPR_MX 15 +#define SLAVE_QDSS_CFG 16 +#define SLAVE_RBCPR_CX 17 +#define SLAVE_QDSS_RBCPR_APU 18 +#define SLAVE_CNOC_MNOC_CFG 19 +#define SLAVE_SNOC_CFG 20 +#define SLAVE_SNOC_MPU_CFG 21 +#define SLAVE_EBI1_PHY_CFG 22 +#define SLAVE_A0NOC_CFG 23 +#define SLAVE_PCIE_1_CFG 24 +#define SLAVE_PCIE_2_CFG 25 +#define SLAVE_PCIE_0_CFG 26 +#define SLAVE_PCIE20_AHB2PHY 27 +#define SLAVE_A0NOC_MPU_CFG 28 +#define SLAVE_UFS_CFG 29 +#define SLAVE_A1NOC_CFG 30 +#define SLAVE_A1NOC_MPU_CFG 31 +#define SLAVE_A2NOC_CFG 32 +#define SLAVE_A2NOC_MPU_CFG 33 +#define SLAVE_SSC_CFG 34 +#define SLAVE_A0NOC_SMMU_CFG 35 +#define SLAVE_A1NOC_SMMU_CFG 36 +#define SLAVE_A2NOC_SMMU_CFG 37 +#define SLAVE_LPASS_SMMU_CFG 38 +#define SLAVE_CNOC_MNOC_MMSS_CFG 39 + +/* MNOC */ +#define MASTER_CNOC_MNOC_CFG 0 +#define MASTER_CPP 1 +#define MASTER_JPEG 2 +#define MASTER_MDP_PORT0 3 +#define MASTER_MDP_PORT1 4 +#define MASTER_ROTATOR 5 +#define MASTER_VIDEO_P0 6 +#define MASTER_VFE 7 +#define MASTER_SNOC_VMEM 8 +#define MASTER_VIDEO_P0_OCMEM 9 +#define MASTER_CNOC_MNOC_MMSS_CFG 10 +#define SLAVE_MNOC_BIMC 11 +#define SLAVE_VMEM 12 +#define SLAVE_SERVICE_MNOC 13 +#define SLAVE_MMAGIC_CFG 14 +#define SLAVE_CPR_CFG 15 +#define SLAVE_MISC_CFG 16 +#define SLAVE_VENUS_THROTTLE_CFG 17 +#define SLAVE_VENUS_CFG 18 +#define SLAVE_VMEM_CFG 19 +#define SLAVE_DSA_CFG 20 +#define SLAVE_MMSS_CLK_CFG 21 +#define SLAVE_DSA_MPU_CFG 22 +#define SLAVE_MNOC_MPU_CFG 23 +#define SLAVE_DISPLAY_CFG 24 +#define SLAVE_DISPLAY_THROTTLE_CFG 25 +#define SLAVE_CAMERA_CFG 26 +#define SLAVE_CAMERA_THROTTLE_CFG 27 +#define SLAVE_GRAPHICS_3D_CFG 28 +#define SLAVE_SMMU_MDP_CFG 29 +#define SLAVE_SMMU_ROT_CFG 30 +#define SLAVE_SMMU_VENUS_CFG 31 +#define SLAVE_SMMU_CPP_CFG 32 +#define SLAVE_SMMU_JPEG_CFG 33 +#define SLAVE_SMMU_VFE_CFG 34 + +/* PNOC */ +#define MASTER_SNOC_PNOC 0 +#define MASTER_SDCC_1 1 +#define MASTER_SDCC_2 2 +#define MASTER_SDCC_4 3 +#define MASTER_USB_HS 4 +#define MASTER_BLSP_1 5 +#define MASTER_BLSP_2 6 +#define MASTER_TSIF 7 +#define SLAVE_PNOC_A1NOC 8 +#define SLAVE_USB_HS 9 +#define SLAVE_SDCC_2 10 +#define SLAVE_SDCC_4 11 +#define SLAVE_TSIF 12 +#define SLAVE_BLSP_2 13 +#define SLAVE_SDCC_1 14 +#define SLAVE_BLSP_1 15 +#define SLAVE_PDM 16 +#define SLAVE_AHB2PHY 17 + +/* SNOC */ +#define MASTER_HMSS 0 +#define MASTER_QDSS_BAM 1 +#define MASTER_SNOC_CFG 2 +#define MASTER_BIMC_SNOC_0 3 +#define MASTER_BIMC_SNOC_1 4 +#define MASTER_A0NOC_SNOC 5 +#define MASTER_A1NOC_SNOC 6 +#define MASTER_A2NOC_SNOC 7 +#define MASTER_QDSS_ETR 8 +#define SLAVE_A0NOC_SNOC 9 +#define SLAVE_A1NOC_SNOC 10 +#define SLAVE_A2NOC_SNOC 11 +#define SLAVE_HMSS 12 +#define SLAVE_LPASS 13 +#define SLAVE_USB3 14 +#define SLAVE_SNOC_BIMC 15 +#define SLAVE_SNOC_CNOC 16 +#define SLAVE_IMEM 17 +#define SLAVE_PIMEM 18 +#define SLAVE_SNOC_VMEM 19 +#define SLAVE_SNOC_PNOC 20 +#define SLAVE_QDSS_STM 21 +#define SLAVE_PCIE_0 22 +#define SLAVE_PCIE_1 23 +#define SLAVE_PCIE_2 24 +#define SLAVE_SERVICE_SNOC 25 + +#endif diff --git a/include/dt-bindings/interconnect/qcom,osm-l3.h b/include/dt-bindings/interconnect/qcom,osm-l3.h new file mode 100644 index 000000000000..61ef649ae565 --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,osm-l3.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 The Linux Foundation. All rights reserved. + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_OSM_L3_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_OSM_L3_H + +#define MASTER_OSM_L3_APPS 0 +#define SLAVE_OSM_L3 1 + +#define MASTER_EPSS_L3_APPS 0 +#define SLAVE_EPSS_L3_SHARED 1 + +#endif diff --git a/include/dt-bindings/interconnect/qcom,qcm2290.h b/include/dt-bindings/interconnect/qcom,qcm2290.h new file mode 100644 index 000000000000..6cbbb7fe0bd3 --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,qcm2290.h @@ -0,0 +1,94 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* QCM2290 interconnect IDs */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_QCM2290_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_QCM2290_H + +/* BIMC */ +#define MASTER_APPSS_PROC 0 +#define MASTER_SNOC_BIMC_RT 1 +#define MASTER_SNOC_BIMC_NRT 2 +#define MASTER_SNOC_BIMC 3 +#define MASTER_TCU_0 4 +#define MASTER_GFX3D 5 +#define SLAVE_EBI1 6 +#define SLAVE_BIMC_SNOC 7 + +/* CNOC */ +#define MASTER_SNOC_CNOC 0 +#define MASTER_QDSS_DAP 1 +#define SLAVE_BIMC_CFG 2 +#define SLAVE_CAMERA_NRT_THROTTLE_CFG 3 +#define SLAVE_CAMERA_RT_THROTTLE_CFG 4 +#define SLAVE_CAMERA_CFG 5 +#define SLAVE_CLK_CTL 6 +#define SLAVE_CRYPTO_0_CFG 7 +#define SLAVE_DISPLAY_CFG 8 +#define SLAVE_DISPLAY_THROTTLE_CFG 9 +#define SLAVE_GPU_CFG 10 +#define SLAVE_HWKM 11 +#define SLAVE_IMEM_CFG 12 +#define SLAVE_IPA_CFG 13 +#define SLAVE_LPASS 14 +#define SLAVE_MESSAGE_RAM 15 +#define SLAVE_PDM 16 +#define SLAVE_PIMEM_CFG 17 +#define SLAVE_PKA_WRAPPER 18 +#define SLAVE_PMIC_ARB 19 +#define SLAVE_PRNG 20 +#define SLAVE_QDSS_CFG 21 +#define SLAVE_QM_CFG 22 +#define SLAVE_QM_MPU_CFG 23 +#define SLAVE_QPIC 24 +#define SLAVE_QUP_0 25 +#define SLAVE_SDCC_1 26 +#define SLAVE_SDCC_2 27 +#define SLAVE_SNOC_CFG 28 +#define SLAVE_TCSR 29 +#define SLAVE_USB3 30 +#define SLAVE_VENUS_CFG 31 +#define SLAVE_VENUS_THROTTLE_CFG 32 +#define SLAVE_VSENSE_CTRL_CFG 33 +#define SLAVE_SERVICE_CNOC 34 + +/* SNOC */ +#define MASTER_CRYPTO_CORE0 0 +#define MASTER_SNOC_CFG 1 +#define MASTER_TIC 2 +#define MASTER_ANOC_SNOC 3 +#define MASTER_BIMC_SNOC 4 +#define MASTER_PIMEM 5 +#define MASTER_QDSS_BAM 6 +#define MASTER_QUP_0 7 +#define MASTER_IPA 8 +#define MASTER_QDSS_ETR 9 +#define MASTER_SDCC_1 10 +#define MASTER_SDCC_2 11 +#define MASTER_QPIC 12 +#define MASTER_USB3_0 13 +#define SLAVE_APPSS 14 +#define SLAVE_SNOC_CNOC 15 +#define SLAVE_IMEM 16 +#define SLAVE_PIMEM 17 +#define SLAVE_SNOC_BIMC 18 +#define SLAVE_SERVICE_SNOC 19 +#define SLAVE_QDSS_STM 20 +#define SLAVE_TCU 21 +#define SLAVE_ANOC_SNOC 22 + +/* QUP Virtual */ +#define MASTER_QUP_CORE_0 0 +#define SLAVE_QUP_CORE_0 1 + +/* MMNRT Virtual */ +#define MASTER_CAMNOC_SF 0 +#define MASTER_VIDEO_P0 1 +#define MASTER_VIDEO_PROC 2 +#define SLAVE_SNOC_BIMC_NRT 3 + +/* MMRT Virtual */ +#define MASTER_CAMNOC_HF 0 +#define MASTER_MDP0 1 +#define SLAVE_SNOC_BIMC_RT 2 + +#endif diff --git a/include/dt-bindings/interconnect/qcom,sc7180.h b/include/dt-bindings/interconnect/qcom,sc7180.h new file mode 100644 index 000000000000..f9970f6032eb --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,sc7180.h @@ -0,0 +1,161 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Qualcomm SC7180 interconnect IDs + * + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SC7180_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_SC7180_H + +#define MASTER_A1NOC_CFG 0 +#define MASTER_QSPI 1 +#define MASTER_QUP_0 2 +#define MASTER_SDCC_2 3 +#define MASTER_EMMC 4 +#define MASTER_UFS_MEM 5 +#define SLAVE_A1NOC_SNOC 6 +#define SLAVE_SERVICE_A1NOC 7 + +#define MASTER_A2NOC_CFG 0 +#define MASTER_QDSS_BAM 1 +#define MASTER_QUP_1 2 +#define MASTER_USB3 3 +#define MASTER_CRYPTO 4 +#define MASTER_IPA 5 +#define MASTER_QDSS_ETR 6 +#define SLAVE_A2NOC_SNOC 7 +#define SLAVE_SERVICE_A2NOC 8 + +#define MASTER_CAMNOC_HF0_UNCOMP 0 +#define MASTER_CAMNOC_HF1_UNCOMP 1 +#define MASTER_CAMNOC_SF_UNCOMP 2 +#define SLAVE_CAMNOC_UNCOMP 3 + +#define MASTER_NPU 0 +#define MASTER_NPU_PROC 1 +#define SLAVE_CDSP_GEM_NOC 2 + +#define MASTER_SNOC_CNOC 0 +#define MASTER_QDSS_DAP 1 +#define SLAVE_A1NOC_CFG 2 +#define SLAVE_A2NOC_CFG 3 +#define SLAVE_AHB2PHY_SOUTH 4 +#define SLAVE_AHB2PHY_CENTER 5 +#define SLAVE_AOP 6 +#define SLAVE_AOSS 7 +#define SLAVE_BOOT_ROM 8 +#define SLAVE_CAMERA_CFG 9 +#define SLAVE_CAMERA_NRT_THROTTLE_CFG 10 +#define SLAVE_CAMERA_RT_THROTTLE_CFG 11 +#define SLAVE_CLK_CTL 12 +#define SLAVE_RBCPR_CX_CFG 13 +#define SLAVE_RBCPR_MX_CFG 14 +#define SLAVE_CRYPTO_0_CFG 15 +#define SLAVE_DCC_CFG 16 +#define SLAVE_CNOC_DDRSS 17 +#define SLAVE_DISPLAY_CFG 18 +#define SLAVE_DISPLAY_RT_THROTTLE_CFG 19 +#define SLAVE_DISPLAY_THROTTLE_CFG 20 +#define SLAVE_EMMC_CFG 21 +#define SLAVE_GLM 22 +#define SLAVE_GFX3D_CFG 23 +#define SLAVE_IMEM_CFG 24 +#define SLAVE_IPA_CFG 25 +#define SLAVE_CNOC_MNOC_CFG 26 +#define SLAVE_CNOC_MSS 27 +#define SLAVE_NPU_CFG 28 +#define SLAVE_NPU_DMA_BWMON_CFG 29 +#define SLAVE_NPU_PROC_BWMON_CFG 30 +#define SLAVE_PDM 31 +#define SLAVE_PIMEM_CFG 32 +#define SLAVE_PRNG 33 +#define SLAVE_QDSS_CFG 34 +#define SLAVE_QM_CFG 35 +#define SLAVE_QM_MPU_CFG 36 +#define SLAVE_QSPI_0 37 +#define SLAVE_QUP_0 38 +#define SLAVE_QUP_1 39 +#define SLAVE_SDCC_2 40 +#define SLAVE_SECURITY 41 +#define SLAVE_SNOC_CFG 42 +#define SLAVE_TCSR 43 +#define SLAVE_TLMM_WEST 44 +#define SLAVE_TLMM_NORTH 45 +#define SLAVE_TLMM_SOUTH 46 +#define SLAVE_UFS_MEM_CFG 47 +#define SLAVE_USB3 48 +#define SLAVE_VENUS_CFG 49 +#define SLAVE_VENUS_THROTTLE_CFG 50 +#define SLAVE_VSENSE_CTRL_CFG 51 +#define SLAVE_SERVICE_CNOC 52 + +#define MASTER_CNOC_DC_NOC 0 +#define SLAVE_GEM_NOC_CFG 1 +#define SLAVE_LLCC_CFG 2 + +#define MASTER_APPSS_PROC 0 +#define MASTER_SYS_TCU 1 +#define MASTER_GEM_NOC_CFG 2 +#define MASTER_COMPUTE_NOC 3 +#define MASTER_MNOC_HF_MEM_NOC 4 +#define MASTER_MNOC_SF_MEM_NOC 5 +#define MASTER_SNOC_GC_MEM_NOC 6 +#define MASTER_SNOC_SF_MEM_NOC 7 +#define MASTER_GFX3D 8 +#define SLAVE_MSS_PROC_MS_MPU_CFG 9 +#define SLAVE_GEM_NOC_SNOC 10 +#define SLAVE_LLCC 11 +#define SLAVE_SERVICE_GEM_NOC 12 + +#define MASTER_IPA_CORE 0 +#define SLAVE_IPA_CORE 1 + +#define MASTER_LLCC 0 +#define SLAVE_EBI1 1 + +#define MASTER_CNOC_MNOC_CFG 0 +#define MASTER_CAMNOC_HF0 1 +#define MASTER_CAMNOC_HF1 2 +#define MASTER_CAMNOC_SF 3 +#define MASTER_MDP0 4 +#define MASTER_ROTATOR 5 +#define MASTER_VIDEO_P0 6 +#define MASTER_VIDEO_PROC 7 +#define SLAVE_MNOC_HF_MEM_NOC 8 +#define SLAVE_MNOC_SF_MEM_NOC 9 +#define SLAVE_SERVICE_MNOC 10 + +#define MASTER_NPU_SYS 0 +#define MASTER_NPU_NOC_CFG 1 +#define SLAVE_NPU_CAL_DP0 2 +#define SLAVE_NPU_CP 3 +#define SLAVE_NPU_INT_DMA_BWMON_CFG 4 +#define SLAVE_NPU_DPM 5 +#define SLAVE_ISENSE_CFG 6 +#define SLAVE_NPU_LLM_CFG 7 +#define SLAVE_NPU_TCM 8 +#define SLAVE_NPU_COMPUTE_NOC 9 +#define SLAVE_SERVICE_NPU_NOC 10 + +#define MASTER_QUP_CORE_0 0 +#define MASTER_QUP_CORE_1 1 +#define SLAVE_QUP_CORE_0 2 +#define SLAVE_QUP_CORE_1 3 + +#define MASTER_SNOC_CFG 0 +#define MASTER_A1NOC_SNOC 1 +#define MASTER_A2NOC_SNOC 2 +#define MASTER_GEM_NOC_SNOC 3 +#define MASTER_PIMEM 4 +#define SLAVE_APPSS 5 +#define SLAVE_SNOC_CNOC 6 +#define SLAVE_SNOC_GEM_NOC_GC 7 +#define SLAVE_SNOC_GEM_NOC_SF 8 +#define SLAVE_IMEM 9 +#define SLAVE_PIMEM 10 +#define SLAVE_SERVICE_SNOC 11 +#define SLAVE_QDSS_STM 12 +#define SLAVE_TCU 13 + +#endif diff --git a/include/dt-bindings/interconnect/qcom,sc7280.h b/include/dt-bindings/interconnect/qcom,sc7280.h new file mode 100644 index 000000000000..21b000443999 --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,sc7280.h @@ -0,0 +1,165 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Qualcomm SC7280 interconnect IDs + * + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SC7280_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_SC7280_H + +#define MASTER_QSPI_0 0 +#define MASTER_QUP_0 1 +#define MASTER_QUP_1 2 +#define MASTER_A1NOC_CFG 3 +#define MASTER_PCIE_0 4 +#define MASTER_PCIE_1 5 +#define MASTER_SDCC_1 6 +#define MASTER_SDCC_2 7 +#define MASTER_SDCC_4 8 +#define MASTER_UFS_MEM 9 +#define MASTER_USB2 10 +#define MASTER_USB3_0 11 +#define SLAVE_A1NOC_SNOC 12 +#define SLAVE_ANOC_PCIE_GEM_NOC 13 +#define SLAVE_SERVICE_A1NOC 14 + +#define MASTER_QDSS_BAM 0 +#define MASTER_A2NOC_CFG 1 +#define MASTER_CNOC_A2NOC 2 +#define MASTER_CRYPTO 3 +#define MASTER_IPA 4 +#define MASTER_QDSS_ETR 5 +#define SLAVE_A2NOC_SNOC 6 +#define SLAVE_SERVICE_A2NOC 7 + +#define MASTER_QUP_CORE_0 0 +#define MASTER_QUP_CORE_1 1 +#define SLAVE_QUP_CORE_0 2 +#define SLAVE_QUP_CORE_1 3 + +#define MASTER_CNOC3_CNOC2 0 +#define MASTER_QDSS_DAP 1 +#define SLAVE_AHB2PHY_SOUTH 2 +#define SLAVE_AHB2PHY_NORTH 3 +#define SLAVE_CAMERA_CFG 4 +#define SLAVE_CLK_CTL 5 +#define SLAVE_CDSP_CFG 6 +#define SLAVE_RBCPR_CX_CFG 7 +#define SLAVE_RBCPR_MX_CFG 8 +#define SLAVE_CRYPTO_0_CFG 9 +#define SLAVE_CX_RDPM 10 +#define SLAVE_DCC_CFG 11 +#define SLAVE_DISPLAY_CFG 12 +#define SLAVE_GFX3D_CFG 13 +#define SLAVE_HWKM 14 +#define SLAVE_IMEM_CFG 15 +#define SLAVE_IPA_CFG 16 +#define SLAVE_IPC_ROUTER_CFG 17 +#define SLAVE_LPASS 18 +#define SLAVE_CNOC_MSS 19 +#define SLAVE_MX_RDPM 20 +#define SLAVE_PCIE_0_CFG 21 +#define SLAVE_PCIE_1_CFG 22 +#define SLAVE_PDM 23 +#define SLAVE_PIMEM_CFG 24 +#define SLAVE_PKA_WRAPPER_CFG 25 +#define SLAVE_PMU_WRAPPER_CFG 26 +#define SLAVE_QDSS_CFG 27 +#define SLAVE_QSPI_0 28 +#define SLAVE_QUP_0 29 +#define SLAVE_QUP_1 30 +#define SLAVE_SDCC_1 31 +#define SLAVE_SDCC_2 32 +#define SLAVE_SDCC_4 33 +#define SLAVE_SECURITY 34 +#define SLAVE_TCSR 35 +#define SLAVE_TLMM 36 +#define SLAVE_UFS_MEM_CFG 37 +#define SLAVE_USB2 38 +#define SLAVE_USB3_0 39 +#define SLAVE_VENUS_CFG 40 +#define SLAVE_VSENSE_CTRL_CFG 41 +#define SLAVE_A1NOC_CFG 42 +#define SLAVE_A2NOC_CFG 43 +#define SLAVE_CNOC2_CNOC3 44 +#define SLAVE_CNOC_MNOC_CFG 45 +#define SLAVE_SNOC_CFG 46 + +#define MASTER_CNOC2_CNOC3 0 +#define MASTER_GEM_NOC_CNOC 1 +#define MASTER_GEM_NOC_PCIE_SNOC 2 +#define SLAVE_AOSS 3 +#define SLAVE_APPSS 4 +#define SLAVE_CNOC3_CNOC2 5 +#define SLAVE_CNOC_A2NOC 6 +#define SLAVE_DDRSS_CFG 7 +#define SLAVE_BOOT_IMEM 8 +#define SLAVE_IMEM 9 +#define SLAVE_PIMEM 10 +#define SLAVE_PCIE_0 11 +#define SLAVE_PCIE_1 12 +#define SLAVE_QDSS_STM 13 +#define SLAVE_TCU 14 + +#define MASTER_CNOC_DC_NOC 0 +#define SLAVE_LLCC_CFG 1 +#define SLAVE_GEM_NOC_CFG 2 + +#define MASTER_GPU_TCU 0 +#define MASTER_SYS_TCU 1 +#define MASTER_APPSS_PROC 2 +#define MASTER_COMPUTE_NOC 3 +#define MASTER_GEM_NOC_CFG 4 +#define MASTER_GFX3D 5 +#define MASTER_MNOC_HF_MEM_NOC 6 +#define MASTER_MNOC_SF_MEM_NOC 7 +#define MASTER_ANOC_PCIE_GEM_NOC 8 +#define MASTER_SNOC_GC_MEM_NOC 9 +#define MASTER_SNOC_SF_MEM_NOC 10 +#define SLAVE_MSS_PROC_MS_MPU_CFG 11 +#define SLAVE_MCDMA_MS_MPU_CFG 12 +#define SLAVE_GEM_NOC_CNOC 13 +#define SLAVE_LLCC 14 +#define SLAVE_MEM_NOC_PCIE_SNOC 15 +#define SLAVE_SERVICE_GEM_NOC_1 16 +#define SLAVE_SERVICE_GEM_NOC_2 17 +#define SLAVE_SERVICE_GEM_NOC 18 + +#define MASTER_CNOC_LPASS_AG_NOC 0 +#define SLAVE_LPASS_CORE_CFG 1 +#define SLAVE_LPASS_LPI_CFG 2 +#define SLAVE_LPASS_MPU_CFG 3 +#define SLAVE_LPASS_TOP_CFG 4 +#define SLAVE_SERVICES_LPASS_AML_NOC 5 +#define SLAVE_SERVICE_LPASS_AG_NOC 6 + +#define MASTER_LLCC 0 +#define SLAVE_EBI1 1 + +#define MASTER_CNOC_MNOC_CFG 0 +#define MASTER_VIDEO_P0 1 +#define MASTER_VIDEO_PROC 2 +#define MASTER_CAMNOC_HF 3 +#define MASTER_CAMNOC_ICP 4 +#define MASTER_CAMNOC_SF 5 +#define MASTER_MDP0 6 +#define SLAVE_MNOC_HF_MEM_NOC 7 +#define SLAVE_MNOC_SF_MEM_NOC 8 +#define SLAVE_SERVICE_MNOC 9 + +#define MASTER_CDSP_NOC_CFG 0 +#define MASTER_CDSP_PROC 1 +#define SLAVE_CDSP_MEM_NOC 2 +#define SLAVE_SERVICE_NSP_NOC 3 + +#define MASTER_A1NOC_SNOC 0 +#define MASTER_A2NOC_SNOC 1 +#define MASTER_SNOC_CFG 2 +#define MASTER_PIMEM 3 +#define MASTER_GIC 4 +#define SLAVE_SNOC_GEM_NOC_GC 5 +#define SLAVE_SNOC_GEM_NOC_SF 6 +#define SLAVE_SERVICE_SNOC 7 + +#endif diff --git a/include/dt-bindings/interconnect/qcom,sc8180x.h b/include/dt-bindings/interconnect/qcom,sc8180x.h new file mode 100644 index 000000000000..e84cfec5afdd --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,sc8180x.h @@ -0,0 +1,192 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Qualcomm SC8180x interconnect IDs + * + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SC8180X_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_SC8180X_H + +#define MASTER_A1NOC_CFG 0 +#define MASTER_UFS_CARD 1 +#define MASTER_UFS_GEN4 2 +#define MASTER_UFS_MEM 3 +#define MASTER_USB3 4 +#define MASTER_USB3_1 5 +#define MASTER_USB3_2 6 +#define A1NOC_SNOC_SLV 7 +#define SLAVE_SERVICE_A1NOC 8 + +#define MASTER_A2NOC_CFG 0 +#define MASTER_QDSS_BAM 1 +#define MASTER_QSPI_0 2 +#define MASTER_QSPI_1 3 +#define MASTER_QUP_0 4 +#define MASTER_QUP_1 5 +#define MASTER_QUP_2 6 +#define MASTER_SENSORS_AHB 7 +#define MASTER_CRYPTO_CORE_0 8 +#define MASTER_IPA 9 +#define MASTER_EMAC 10 +#define MASTER_PCIE 11 +#define MASTER_PCIE_1 12 +#define MASTER_PCIE_2 13 +#define MASTER_PCIE_3 14 +#define MASTER_QDSS_ETR 15 +#define MASTER_SDCC_2 16 +#define MASTER_SDCC_4 17 +#define A2NOC_SNOC_SLV 18 +#define SLAVE_ANOC_PCIE_GEM_NOC 19 +#define SLAVE_SERVICE_A2NOC 20 + +#define MASTER_CAMNOC_HF0_UNCOMP 0 +#define MASTER_CAMNOC_HF1_UNCOMP 1 +#define MASTER_CAMNOC_SF_UNCOMP 2 +#define SLAVE_CAMNOC_UNCOMP 3 + +#define MASTER_NPU 0 +#define SLAVE_CDSP_MEM_NOC 1 + +#define SNOC_CNOC_MAS 0 +#define SLAVE_A1NOC_CFG 1 +#define SLAVE_A2NOC_CFG 2 +#define SLAVE_AHB2PHY_CENTER 3 +#define SLAVE_AHB2PHY_EAST 4 +#define SLAVE_AHB2PHY_WEST 5 +#define SLAVE_AHB2PHY_SOUTH 6 +#define SLAVE_AOP 7 +#define SLAVE_AOSS 8 +#define SLAVE_CAMERA_CFG 9 +#define SLAVE_CLK_CTL 10 +#define SLAVE_CDSP_CFG 11 +#define SLAVE_RBCPR_CX_CFG 12 +#define SLAVE_RBCPR_MMCX_CFG 13 +#define SLAVE_RBCPR_MX_CFG 14 +#define SLAVE_CRYPTO_0_CFG 15 +#define SLAVE_CNOC_DDRSS 16 +#define SLAVE_DISPLAY_CFG 17 +#define SLAVE_EMAC_CFG 18 +#define SLAVE_GLM 19 +#define SLAVE_GRAPHICS_3D_CFG 20 +#define SLAVE_IMEM_CFG 21 +#define SLAVE_IPA_CFG 22 +#define SLAVE_CNOC_MNOC_CFG 23 +#define SLAVE_NPU_CFG 24 +#define SLAVE_PCIE_0_CFG 25 +#define SLAVE_PCIE_1_CFG 26 +#define SLAVE_PCIE_2_CFG 27 +#define SLAVE_PCIE_3_CFG 28 +#define SLAVE_PDM 29 +#define SLAVE_PIMEM_CFG 30 +#define SLAVE_PRNG 31 +#define SLAVE_QDSS_CFG 32 +#define SLAVE_QSPI_0 33 +#define SLAVE_QSPI_1 34 +#define SLAVE_QUP_1 35 +#define SLAVE_QUP_2 36 +#define SLAVE_QUP_0 37 +#define SLAVE_SDCC_2 38 +#define SLAVE_SDCC_4 39 +#define SLAVE_SECURITY 40 +#define SLAVE_SNOC_CFG 41 +#define SLAVE_SPSS_CFG 42 +#define SLAVE_TCSR 43 +#define SLAVE_TLMM_EAST 44 +#define SLAVE_TLMM_SOUTH 45 +#define SLAVE_TLMM_WEST 46 +#define SLAVE_TSIF 47 +#define SLAVE_UFS_CARD_CFG 48 +#define SLAVE_UFS_MEM_0_CFG 49 +#define SLAVE_UFS_MEM_1_CFG 50 +#define SLAVE_USB3 51 +#define SLAVE_USB3_1 52 +#define SLAVE_USB3_2 53 +#define SLAVE_VENUS_CFG 54 +#define SLAVE_VSENSE_CTRL_CFG 55 +#define SLAVE_SERVICE_CNOC 56 + +#define MASTER_CNOC_DC_NOC 0 +#define SLAVE_GEM_NOC_CFG 1 +#define SLAVE_LLCC_CFG 2 + +#define MASTER_AMPSS_M0 0 +#define MASTER_GPU_TCU 1 +#define MASTER_SYS_TCU 2 +#define MASTER_GEM_NOC_CFG 3 +#define MASTER_COMPUTE_NOC 4 +#define MASTER_GRAPHICS_3D 5 +#define MASTER_MNOC_HF_MEM_NOC 6 +#define MASTER_MNOC_SF_MEM_NOC 7 +#define MASTER_GEM_NOC_PCIE_SNOC 8 +#define MASTER_SNOC_GC_MEM_NOC 9 +#define MASTER_SNOC_SF_MEM_NOC 10 +#define MASTER_ECC 11 +#define SLAVE_MSS_PROC_MS_MPU_CFG 12 +#define SLAVE_ECC 13 +#define SLAVE_GEM_NOC_SNOC 14 +#define SLAVE_LLCC 15 +#define SLAVE_SERVICE_GEM_NOC 16 +#define SLAVE_SERVICE_GEM_NOC_1 17 + +#define MASTER_IPA_CORE 0 +#define SLAVE_IPA_CORE 1 + +#define MASTER_LLCC 0 +#define SLAVE_EBI_CH0 1 + +#define MASTER_CNOC_MNOC_CFG 0 +#define MASTER_CAMNOC_HF0 1 +#define MASTER_CAMNOC_HF1 2 +#define MASTER_CAMNOC_SF 3 +#define MASTER_MDP_PORT0 4 +#define MASTER_MDP_PORT1 5 +#define MASTER_ROTATOR 6 +#define MASTER_VIDEO_P0 7 +#define MASTER_VIDEO_P1 8 +#define MASTER_VIDEO_PROC 9 +#define SLAVE_MNOC_SF_MEM_NOC 10 +#define SLAVE_MNOC_HF_MEM_NOC 11 +#define SLAVE_SERVICE_MNOC 12 + +#define MASTER_SNOC_CFG 0 +#define A1NOC_SNOC_MAS 1 +#define A2NOC_SNOC_MAS 2 +#define MASTER_GEM_NOC_SNOC 3 +#define MASTER_PIMEM 4 +#define MASTER_GIC 5 +#define SLAVE_APPSS 6 +#define SNOC_CNOC_SLV 7 +#define SLAVE_SNOC_GEM_NOC_GC 8 +#define SLAVE_SNOC_GEM_NOC_SF 9 +#define SLAVE_OCIMEM 10 +#define SLAVE_PIMEM 11 +#define SLAVE_SERVICE_SNOC 12 +#define SLAVE_PCIE_0 13 +#define SLAVE_PCIE_1 14 +#define SLAVE_PCIE_2 15 +#define SLAVE_PCIE_3 16 +#define SLAVE_QDSS_STM 17 +#define SLAVE_TCU 18 + +#define MASTER_MNOC_HF_MEM_NOC_DISPLAY 0 +#define MASTER_MNOC_SF_MEM_NOC_DISPLAY 1 +#define SLAVE_LLCC_DISPLAY 2 + +#define MASTER_LLCC_DISPLAY 0 +#define SLAVE_EBI_CH0_DISPLAY 1 + +#define MASTER_MDP_PORT0_DISPLAY 0 +#define MASTER_MDP_PORT1_DISPLAY 1 +#define MASTER_ROTATOR_DISPLAY 2 +#define SLAVE_MNOC_SF_MEM_NOC_DISPLAY 3 +#define SLAVE_MNOC_HF_MEM_NOC_DISPLAY 4 + +#define MASTER_QUP_CORE_0 0 +#define MASTER_QUP_CORE_1 1 +#define MASTER_QUP_CORE_2 2 +#define SLAVE_QUP_CORE_0 3 +#define SLAVE_QUP_CORE_1 4 +#define SLAVE_QUP_CORE_2 5 + +#endif diff --git a/include/dt-bindings/interconnect/qcom,sc8280xp.h b/include/dt-bindings/interconnect/qcom,sc8280xp.h new file mode 100644 index 000000000000..a3e5fda7c127 --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,sc8280xp.h @@ -0,0 +1,232 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Linaro Ltd. + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SC8280XP_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_SC8280XP_H + +/* aggre1_noc */ +#define MASTER_QSPI_0 0 +#define MASTER_QUP_1 1 +#define MASTER_QUP_2 2 +#define MASTER_A1NOC_CFG 3 +#define MASTER_IPA 4 +#define MASTER_EMAC_1 5 +#define MASTER_SDCC_4 6 +#define MASTER_UFS_MEM 7 +#define MASTER_USB3_0 8 +#define MASTER_USB3_1 9 +#define MASTER_USB3_MP 10 +#define MASTER_USB4_0 11 +#define MASTER_USB4_1 12 +#define SLAVE_A1NOC_SNOC 13 +#define SLAVE_USB_NOC_SNOC 14 +#define SLAVE_SERVICE_A1NOC 15 + +/* aggre2_noc */ +#define MASTER_QDSS_BAM 0 +#define MASTER_QUP_0 1 +#define MASTER_A2NOC_CFG 2 +#define MASTER_CRYPTO 3 +#define MASTER_SENSORS_PROC 4 +#define MASTER_SP 5 +#define MASTER_EMAC 6 +#define MASTER_PCIE_0 7 +#define MASTER_PCIE_1 8 +#define MASTER_PCIE_2A 9 +#define MASTER_PCIE_2B 10 +#define MASTER_PCIE_3A 11 +#define MASTER_PCIE_3B 12 +#define MASTER_PCIE_4 13 +#define MASTER_QDSS_ETR 14 +#define MASTER_SDCC_2 15 +#define MASTER_UFS_CARD 16 +#define SLAVE_A2NOC_SNOC 17 +#define SLAVE_ANOC_PCIE_GEM_NOC 18 +#define SLAVE_SERVICE_A2NOC 19 + +/* clk_virt */ +#define MASTER_IPA_CORE 0 +#define MASTER_QUP_CORE_0 1 +#define MASTER_QUP_CORE_1 2 +#define MASTER_QUP_CORE_2 3 +#define SLAVE_IPA_CORE 4 +#define SLAVE_QUP_CORE_0 5 +#define SLAVE_QUP_CORE_1 6 +#define SLAVE_QUP_CORE_2 7 + +/* config_noc */ +#define MASTER_GEM_NOC_CNOC 0 +#define MASTER_GEM_NOC_PCIE_SNOC 1 +#define SLAVE_AHB2PHY_0 2 +#define SLAVE_AHB2PHY_1 3 +#define SLAVE_AHB2PHY_2 4 +#define SLAVE_AOSS 5 +#define SLAVE_APPSS 6 +#define SLAVE_CAMERA_CFG 7 +#define SLAVE_CLK_CTL 8 +#define SLAVE_CDSP_CFG 9 +#define SLAVE_CDSP1_CFG 10 +#define SLAVE_RBCPR_CX_CFG 11 +#define SLAVE_RBCPR_MMCX_CFG 12 +#define SLAVE_RBCPR_MX_CFG 13 +#define SLAVE_CPR_NSPCX 14 +#define SLAVE_CRYPTO_0_CFG 15 +#define SLAVE_CX_RDPM 16 +#define SLAVE_DCC_CFG 17 +#define SLAVE_DISPLAY_CFG 18 +#define SLAVE_DISPLAY1_CFG 19 +#define SLAVE_EMAC_CFG 20 +#define SLAVE_EMAC1_CFG 21 +#define SLAVE_GFX3D_CFG 22 +#define SLAVE_HWKM 23 +#define SLAVE_IMEM_CFG 24 +#define SLAVE_IPA_CFG 25 +#define SLAVE_IPC_ROUTER_CFG 26 +#define SLAVE_LPASS 27 +#define SLAVE_MX_RDPM 28 +#define SLAVE_MXC_RDPM 29 +#define SLAVE_PCIE_0_CFG 30 +#define SLAVE_PCIE_1_CFG 31 +#define SLAVE_PCIE_2A_CFG 32 +#define SLAVE_PCIE_2B_CFG 33 +#define SLAVE_PCIE_3A_CFG 34 +#define SLAVE_PCIE_3B_CFG 35 +#define SLAVE_PCIE_4_CFG 36 +#define SLAVE_PCIE_RSC_CFG 37 +#define SLAVE_PDM 38 +#define SLAVE_PIMEM_CFG 39 +#define SLAVE_PKA_WRAPPER_CFG 40 +#define SLAVE_PMU_WRAPPER_CFG 41 +#define SLAVE_QDSS_CFG 42 +#define SLAVE_QSPI_0 43 +#define SLAVE_QUP_0 44 +#define SLAVE_QUP_1 45 +#define SLAVE_QUP_2 46 +#define SLAVE_SDCC_2 47 +#define SLAVE_SDCC_4 48 +#define SLAVE_SECURITY 49 +#define SLAVE_SMMUV3_CFG 50 +#define SLAVE_SMSS_CFG 51 +#define SLAVE_SPSS_CFG 52 +#define SLAVE_TCSR 53 +#define SLAVE_TLMM 54 +#define SLAVE_UFS_CARD_CFG 55 +#define SLAVE_UFS_MEM_CFG 56 +#define SLAVE_USB3_0 57 +#define SLAVE_USB3_1 58 +#define SLAVE_USB3_MP 59 +#define SLAVE_USB4_0 60 +#define SLAVE_USB4_1 61 +#define SLAVE_VENUS_CFG 62 +#define SLAVE_VSENSE_CTRL_CFG 63 +#define SLAVE_VSENSE_CTRL_R_CFG 64 +#define SLAVE_A1NOC_CFG 65 +#define SLAVE_A2NOC_CFG 66 +#define SLAVE_ANOC_PCIE_BRIDGE_CFG 67 +#define SLAVE_DDRSS_CFG 68 +#define SLAVE_CNOC_MNOC_CFG 69 +#define SLAVE_SNOC_CFG 70 +#define SLAVE_SNOC_SF_BRIDGE_CFG 71 +#define SLAVE_IMEM 72 +#define SLAVE_PIMEM 73 +#define SLAVE_SERVICE_CNOC 74 +#define SLAVE_PCIE_0 75 +#define SLAVE_PCIE_1 76 +#define SLAVE_PCIE_2A 77 +#define SLAVE_PCIE_2B 78 +#define SLAVE_PCIE_3A 79 +#define SLAVE_PCIE_3B 80 +#define SLAVE_PCIE_4 81 +#define SLAVE_QDSS_STM 82 +#define SLAVE_SMSS 83 +#define SLAVE_TCU 84 + +/* dc_noc */ +#define MASTER_CNOC_DC_NOC 0 +#define SLAVE_LLCC_CFG 1 +#define SLAVE_GEM_NOC_CFG 2 + +/* gem_noc */ +#define MASTER_GPU_TCU 0 +#define MASTER_PCIE_TCU 1 +#define MASTER_SYS_TCU 2 +#define MASTER_APPSS_PROC 3 +#define MASTER_COMPUTE_NOC 4 +#define MASTER_COMPUTE_NOC_1 5 +#define MASTER_GEM_NOC_CFG 6 +#define MASTER_GFX3D 7 +#define MASTER_MNOC_HF_MEM_NOC 8 +#define MASTER_MNOC_SF_MEM_NOC 9 +#define MASTER_ANOC_PCIE_GEM_NOC 10 +#define MASTER_SNOC_GC_MEM_NOC 11 +#define MASTER_SNOC_SF_MEM_NOC 12 +#define SLAVE_GEM_NOC_CNOC 13 +#define SLAVE_LLCC 14 +#define SLAVE_GEM_NOC_PCIE_CNOC 15 +#define SLAVE_SERVICE_GEM_NOC_1 16 +#define SLAVE_SERVICE_GEM_NOC_2 17 +#define SLAVE_SERVICE_GEM_NOC 18 + +/* lpass_ag_noc */ +#define MASTER_CNOC_LPASS_AG_NOC 0 +#define MASTER_LPASS_PROC 1 +#define SLAVE_LPASS_CORE_CFG 2 +#define SLAVE_LPASS_LPI_CFG 3 +#define SLAVE_LPASS_MPU_CFG 4 +#define SLAVE_LPASS_TOP_CFG 5 +#define SLAVE_LPASS_SNOC 6 +#define SLAVE_SERVICES_LPASS_AML_NOC 7 +#define SLAVE_SERVICE_LPASS_AG_NOC 8 + +/* mc_virt */ +#define MASTER_LLCC 0 +#define SLAVE_EBI1 1 + +/*mmss_noc */ +#define MASTER_CAMNOC_HF 0 +#define MASTER_MDP0 1 +#define MASTER_MDP1 2 +#define MASTER_MDP_CORE1_0 3 +#define MASTER_MDP_CORE1_1 4 +#define MASTER_CNOC_MNOC_CFG 5 +#define MASTER_ROTATOR 6 +#define MASTER_ROTATOR_1 7 +#define MASTER_VIDEO_P0 8 +#define MASTER_VIDEO_P1 9 +#define MASTER_VIDEO_PROC 10 +#define MASTER_CAMNOC_ICP 11 +#define MASTER_CAMNOC_SF 12 +#define SLAVE_MNOC_HF_MEM_NOC 13 +#define SLAVE_MNOC_SF_MEM_NOC 14 +#define SLAVE_SERVICE_MNOC 15 + +/* nspa_noc */ +#define MASTER_CDSP_NOC_CFG 0 +#define MASTER_CDSP_PROC 1 +#define SLAVE_CDSP_MEM_NOC 2 +#define SLAVE_NSP_XFR 3 +#define SLAVE_SERVICE_NSP_NOC 4 + +/* nspb_noc */ +#define MASTER_CDSPB_NOC_CFG 0 +#define MASTER_CDSP_PROC_B 1 +#define SLAVE_CDSPB_MEM_NOC 2 +#define SLAVE_NSPB_XFR 3 +#define SLAVE_SERVICE_NSPB_NOC 4 + +/* system_noc */ +#define MASTER_A1NOC_SNOC 0 +#define MASTER_A2NOC_SNOC 1 +#define MASTER_USB_NOC_SNOC 2 +#define MASTER_LPASS_ANOC 3 +#define MASTER_SNOC_CFG 4 +#define MASTER_PIMEM 5 +#define MASTER_GIC 6 +#define SLAVE_SNOC_GEM_NOC_GC 7 +#define SLAVE_SNOC_GEM_NOC_SF 8 +#define SLAVE_SERVICE_SNOC 9 + +#endif diff --git a/include/dt-bindings/interconnect/qcom,sdm660.h b/include/dt-bindings/interconnect/qcom,sdm660.h new file mode 100644 index 000000000000..62e8d8670d5e --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,sdm660.h @@ -0,0 +1,116 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* SDM660 interconnect IDs */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SDM660_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_SDM660_H + +/* A2NOC */ +#define MASTER_IPA 0 +#define MASTER_CNOC_A2NOC 1 +#define MASTER_SDCC_1 2 +#define MASTER_SDCC_2 3 +#define MASTER_BLSP_1 4 +#define MASTER_BLSP_2 5 +#define MASTER_UFS 6 +#define MASTER_USB_HS 7 +#define MASTER_USB3 8 +#define MASTER_CRYPTO_C0 9 +#define SLAVE_A2NOC_SNOC 10 + +/* BIMC */ +#define MASTER_GNOC_BIMC 0 +#define MASTER_OXILI 1 +#define MASTER_MNOC_BIMC 2 +#define MASTER_SNOC_BIMC 3 +#define MASTER_PIMEM 4 +#define SLAVE_EBI 5 +#define SLAVE_HMSS_L3 6 +#define SLAVE_BIMC_SNOC 7 + +/* CNOC */ +#define MASTER_SNOC_CNOC 0 +#define MASTER_QDSS_DAP 1 +#define SLAVE_CNOC_A2NOC 2 +#define SLAVE_MPM 3 +#define SLAVE_PMIC_ARB 4 +#define SLAVE_TLMM_NORTH 5 +#define SLAVE_TCSR 6 +#define SLAVE_PIMEM_CFG 7 +#define SLAVE_IMEM_CFG 8 +#define SLAVE_MESSAGE_RAM 9 +#define SLAVE_GLM 10 +#define SLAVE_BIMC_CFG 11 +#define SLAVE_PRNG 12 +#define SLAVE_SPDM 13 +#define SLAVE_QDSS_CFG 14 +#define SLAVE_CNOC_MNOC_CFG 15 +#define SLAVE_SNOC_CFG 16 +#define SLAVE_QM_CFG 17 +#define SLAVE_CLK_CTL 18 +#define SLAVE_MSS_CFG 19 +#define SLAVE_TLMM_SOUTH 20 +#define SLAVE_UFS_CFG 21 +#define SLAVE_A2NOC_CFG 22 +#define SLAVE_A2NOC_SMMU_CFG 23 +#define SLAVE_GPUSS_CFG 24 +#define SLAVE_AHB2PHY 25 +#define SLAVE_BLSP_1 26 +#define SLAVE_SDCC_1 27 +#define SLAVE_SDCC_2 28 +#define SLAVE_TLMM_CENTER 29 +#define SLAVE_BLSP_2 30 +#define SLAVE_PDM 31 +#define SLAVE_CNOC_MNOC_MMSS_CFG 32 +#define SLAVE_USB_HS 33 +#define SLAVE_USB3_0 34 +#define SLAVE_SRVC_CNOC 35 + +/* GNOC */ +#define MASTER_APSS_PROC 0 +#define SLAVE_GNOC_BIMC 1 +#define SLAVE_GNOC_SNOC 2 + +/* MNOC */ +#define MASTER_CPP 0 +#define MASTER_JPEG 1 +#define MASTER_MDP_P0 2 +#define MASTER_MDP_P1 3 +#define MASTER_VENUS 4 +#define MASTER_VFE 5 +#define SLAVE_MNOC_BIMC 6 +#define MASTER_CNOC_MNOC_MMSS_CFG 7 +#define MASTER_CNOC_MNOC_CFG 8 +#define SLAVE_CAMERA_CFG 9 +#define SLAVE_CAMERA_THROTTLE_CFG 10 +#define SLAVE_MISC_CFG 11 +#define SLAVE_VENUS_THROTTLE_CFG 12 +#define SLAVE_VENUS_CFG 13 +#define SLAVE_MMSS_CLK_XPU_CFG 14 +#define SLAVE_MMSS_CLK_CFG 15 +#define SLAVE_MNOC_MPU_CFG 16 +#define SLAVE_DISPLAY_CFG 17 +#define SLAVE_CSI_PHY_CFG 18 +#define SLAVE_DISPLAY_THROTTLE_CFG 19 +#define SLAVE_SMMU_CFG 20 +#define SLAVE_SRVC_MNOC 21 + +/* SNOC */ +#define MASTER_QDSS_ETR 0 +#define MASTER_QDSS_BAM 1 +#define MASTER_SNOC_CFG 2 +#define MASTER_BIMC_SNOC 3 +#define MASTER_A2NOC_SNOC 4 +#define MASTER_GNOC_SNOC 5 +#define SLAVE_HMSS 6 +#define SLAVE_LPASS 7 +#define SLAVE_WLAN 8 +#define SLAVE_CDSP 9 +#define SLAVE_IPA 10 +#define SLAVE_SNOC_BIMC 11 +#define SLAVE_SNOC_CNOC 12 +#define SLAVE_IMEM 13 +#define SLAVE_PIMEM 14 +#define SLAVE_QDSS_STM 15 +#define SLAVE_SRVC_SNOC 16 + +#endif diff --git a/include/dt-bindings/interconnect/qcom,sdm845.h b/include/dt-bindings/interconnect/qcom,sdm845.h index 7b2393be7361..67b500e24915 100644 --- a/include/dt-bindings/interconnect/qcom,sdm845.h +++ b/include/dt-bindings/interconnect/qcom,sdm845.h @@ -10,134 +10,141 @@ #define __DT_BINDINGS_INTERCONNECT_QCOM_SDM845_H #define MASTER_A1NOC_CFG 0 -#define MASTER_BLSP_1 1 -#define MASTER_TSIF 2 -#define MASTER_SDCC_2 3 -#define MASTER_SDCC_4 4 -#define MASTER_UFS_CARD 5 -#define MASTER_UFS_MEM 6 -#define MASTER_PCIE_0 7 -#define MASTER_A2NOC_CFG 8 -#define MASTER_QDSS_BAM 9 -#define MASTER_BLSP_2 10 -#define MASTER_CNOC_A2NOC 11 -#define MASTER_CRYPTO 12 -#define MASTER_IPA 13 -#define MASTER_PCIE_1 14 -#define MASTER_QDSS_ETR 15 -#define MASTER_USB3_0 16 -#define MASTER_USB3_1 17 -#define MASTER_CAMNOC_HF0_UNCOMP 18 -#define MASTER_CAMNOC_HF1_UNCOMP 19 -#define MASTER_CAMNOC_SF_UNCOMP 20 -#define MASTER_SPDM 21 -#define MASTER_TIC 22 -#define MASTER_SNOC_CNOC 23 -#define MASTER_QDSS_DAP 24 -#define MASTER_CNOC_DC_NOC 25 -#define MASTER_APPSS_PROC 26 -#define MASTER_GNOC_CFG 27 -#define MASTER_LLCC 28 -#define MASTER_TCU_0 29 -#define MASTER_MEM_NOC_CFG 30 -#define MASTER_GNOC_MEM_NOC 31 -#define MASTER_MNOC_HF_MEM_NOC 32 -#define MASTER_MNOC_SF_MEM_NOC 33 -#define MASTER_SNOC_GC_MEM_NOC 34 -#define MASTER_SNOC_SF_MEM_NOC 35 -#define MASTER_GFX3D 36 -#define MASTER_CNOC_MNOC_CFG 37 -#define MASTER_CAMNOC_HF0 38 -#define MASTER_CAMNOC_HF1 39 -#define MASTER_CAMNOC_SF 40 -#define MASTER_MDP0 41 -#define MASTER_MDP1 42 -#define MASTER_ROTATOR 43 -#define MASTER_VIDEO_P0 44 -#define MASTER_VIDEO_P1 45 -#define MASTER_VIDEO_PROC 46 -#define MASTER_SNOC_CFG 47 -#define MASTER_A1NOC_SNOC 48 -#define MASTER_A2NOC_SNOC 49 -#define MASTER_GNOC_SNOC 50 -#define MASTER_MEM_NOC_SNOC 51 -#define MASTER_ANOC_PCIE_SNOC 52 -#define MASTER_PIMEM 53 -#define MASTER_GIC 54 -#define SLAVE_A1NOC_SNOC 55 -#define SLAVE_SERVICE_A1NOC 56 -#define SLAVE_ANOC_PCIE_A1NOC_SNOC 57 -#define SLAVE_A2NOC_SNOC 58 -#define SLAVE_ANOC_PCIE_SNOC 59 -#define SLAVE_SERVICE_A2NOC 60 -#define SLAVE_CAMNOC_UNCOMP 61 -#define SLAVE_A1NOC_CFG 62 -#define SLAVE_A2NOC_CFG 63 -#define SLAVE_AOP 64 -#define SLAVE_AOSS 65 -#define SLAVE_CAMERA_CFG 66 -#define SLAVE_CLK_CTL 67 -#define SLAVE_CDSP_CFG 68 -#define SLAVE_RBCPR_CX_CFG 69 -#define SLAVE_CRYPTO_0_CFG 70 -#define SLAVE_DCC_CFG 71 -#define SLAVE_CNOC_DDRSS 72 -#define SLAVE_DISPLAY_CFG 73 -#define SLAVE_GLM 74 -#define SLAVE_GFX3D_CFG 75 -#define SLAVE_IMEM_CFG 76 -#define SLAVE_IPA_CFG 77 -#define SLAVE_CNOC_MNOC_CFG 78 -#define SLAVE_PCIE_0_CFG 79 -#define SLAVE_PCIE_1_CFG 80 -#define SLAVE_PDM 81 -#define SLAVE_SOUTH_PHY_CFG 82 -#define SLAVE_PIMEM_CFG 83 -#define SLAVE_PRNG 84 -#define SLAVE_QDSS_CFG 85 -#define SLAVE_BLSP_2 86 -#define SLAVE_BLSP_1 87 -#define SLAVE_SDCC_2 88 -#define SLAVE_SDCC_4 89 -#define SLAVE_SNOC_CFG 90 -#define SLAVE_SPDM_WRAPPER 91 -#define SLAVE_SPSS_CFG 92 -#define SLAVE_TCSR 93 -#define SLAVE_TLMM_NORTH 94 -#define SLAVE_TLMM_SOUTH 95 -#define SLAVE_TSIF 96 -#define SLAVE_UFS_CARD_CFG 97 -#define SLAVE_UFS_MEM_CFG 98 -#define SLAVE_USB3_0 99 -#define SLAVE_USB3_1 100 -#define SLAVE_VENUS_CFG 101 -#define SLAVE_VSENSE_CTRL_CFG 102 -#define SLAVE_CNOC_A2NOC 103 -#define SLAVE_SERVICE_CNOC 104 -#define SLAVE_LLCC_CFG 105 -#define SLAVE_MEM_NOC_CFG 106 -#define SLAVE_GNOC_SNOC 107 -#define SLAVE_GNOC_MEM_NOC 108 -#define SLAVE_SERVICE_GNOC 109 -#define SLAVE_EBI1 110 -#define SLAVE_MSS_PROC_MS_MPU_CFG 111 -#define SLAVE_MEM_NOC_GNOC 112 -#define SLAVE_LLCC 113 -#define SLAVE_MEM_NOC_SNOC 114 -#define SLAVE_SERVICE_MEM_NOC 115 -#define SLAVE_MNOC_SF_MEM_NOC 116 -#define SLAVE_MNOC_HF_MEM_NOC 117 -#define SLAVE_SERVICE_MNOC 118 -#define SLAVE_APPSS 119 -#define SLAVE_SNOC_CNOC 120 -#define SLAVE_SNOC_MEM_NOC_GC 121 -#define SLAVE_SNOC_MEM_NOC_SF 122 -#define SLAVE_IMEM 123 -#define SLAVE_PCIE_0 124 -#define SLAVE_PCIE_1 125 -#define SLAVE_PIMEM 126 -#define SLAVE_SERVICE_SNOC 127 -#define SLAVE_QDSS_STM 128 -#define SLAVE_TCU 129 +#define MASTER_TSIF 1 +#define MASTER_SDCC_2 2 +#define MASTER_SDCC_4 3 +#define MASTER_UFS_CARD 4 +#define MASTER_UFS_MEM 5 +#define MASTER_PCIE_0 6 +#define SLAVE_A1NOC_SNOC 7 +#define SLAVE_SERVICE_A1NOC 8 +#define SLAVE_ANOC_PCIE_A1NOC_SNOC 9 +#define MASTER_QUP_1 10 + +#define MASTER_A2NOC_CFG 0 +#define MASTER_QDSS_BAM 1 +#define MASTER_CNOC_A2NOC 2 +#define MASTER_CRYPTO 3 +#define MASTER_IPA 4 +#define MASTER_PCIE_1 5 +#define MASTER_QDSS_ETR 6 +#define MASTER_USB3_0 7 +#define MASTER_USB3_1 8 +#define SLAVE_A2NOC_SNOC 9 +#define SLAVE_ANOC_PCIE_SNOC 10 +#define SLAVE_SERVICE_A2NOC 11 +#define MASTER_QUP_2 12 + +#define MASTER_SPDM 0 +#define MASTER_TIC 1 +#define MASTER_SNOC_CNOC 2 +#define MASTER_QDSS_DAP 3 +#define SLAVE_A1NOC_CFG 4 +#define SLAVE_A2NOC_CFG 5 +#define SLAVE_AOP 6 +#define SLAVE_AOSS 7 +#define SLAVE_CAMERA_CFG 8 +#define SLAVE_CLK_CTL 9 +#define SLAVE_CDSP_CFG 10 +#define SLAVE_RBCPR_CX_CFG 11 +#define SLAVE_CRYPTO_0_CFG 12 +#define SLAVE_DCC_CFG 13 +#define SLAVE_CNOC_DDRSS 14 +#define SLAVE_DISPLAY_CFG 15 +#define SLAVE_GLM 16 +#define SLAVE_GFX3D_CFG 17 +#define SLAVE_IMEM_CFG 18 +#define SLAVE_IPA_CFG 19 +#define SLAVE_CNOC_MNOC_CFG 20 +#define SLAVE_PCIE_0_CFG 21 +#define SLAVE_PCIE_1_CFG 22 +#define SLAVE_PDM 23 +#define SLAVE_SOUTH_PHY_CFG 24 +#define SLAVE_PIMEM_CFG 25 +#define SLAVE_PRNG 26 +#define SLAVE_QDSS_CFG 27 +#define SLAVE_BLSP_2 28 +#define SLAVE_BLSP_1 29 +#define SLAVE_SDCC_2 30 +#define SLAVE_SDCC_4 31 +#define SLAVE_SNOC_CFG 32 +#define SLAVE_SPDM_WRAPPER 33 +#define SLAVE_SPSS_CFG 34 +#define SLAVE_TCSR 35 +#define SLAVE_TLMM_NORTH 36 +#define SLAVE_TLMM_SOUTH 37 +#define SLAVE_TSIF 38 +#define SLAVE_UFS_CARD_CFG 39 +#define SLAVE_UFS_MEM_CFG 40 +#define SLAVE_USB3_0 41 +#define SLAVE_USB3_1 42 +#define SLAVE_VENUS_CFG 43 +#define SLAVE_VSENSE_CTRL_CFG 44 +#define SLAVE_CNOC_A2NOC 45 +#define SLAVE_SERVICE_CNOC 46 + +#define MASTER_CNOC_DC_NOC 0 +#define SLAVE_LLCC_CFG 1 +#define SLAVE_MEM_NOC_CFG 2 + +#define MASTER_APPSS_PROC 0 +#define MASTER_GNOC_CFG 1 +#define SLAVE_GNOC_SNOC 2 +#define SLAVE_GNOC_MEM_NOC 3 +#define SLAVE_SERVICE_GNOC 4 + +#define MASTER_TCU_0 0 +#define MASTER_MEM_NOC_CFG 1 +#define MASTER_GNOC_MEM_NOC 2 +#define MASTER_MNOC_HF_MEM_NOC 3 +#define MASTER_MNOC_SF_MEM_NOC 4 +#define MASTER_SNOC_GC_MEM_NOC 5 +#define MASTER_SNOC_SF_MEM_NOC 6 +#define MASTER_GFX3D 7 +#define SLAVE_MSS_PROC_MS_MPU_CFG 8 +#define SLAVE_MEM_NOC_GNOC 9 +#define SLAVE_LLCC 10 +#define SLAVE_MEM_NOC_SNOC 11 +#define SLAVE_SERVICE_MEM_NOC 12 +#define MASTER_LLCC 13 +#define SLAVE_EBI1 14 + +#define MASTER_CNOC_MNOC_CFG 0 +#define MASTER_CAMNOC_HF0 1 +#define MASTER_CAMNOC_HF1 2 +#define MASTER_CAMNOC_SF 3 +#define MASTER_MDP0 4 +#define MASTER_MDP1 5 +#define MASTER_ROTATOR 6 +#define MASTER_VIDEO_P0 7 +#define MASTER_VIDEO_P1 8 +#define MASTER_VIDEO_PROC 9 +#define SLAVE_MNOC_SF_MEM_NOC 10 +#define SLAVE_MNOC_HF_MEM_NOC 11 +#define SLAVE_SERVICE_MNOC 12 +#define MASTER_CAMNOC_HF0_UNCOMP 13 +#define MASTER_CAMNOC_HF1_UNCOMP 14 +#define MASTER_CAMNOC_SF_UNCOMP 15 +#define SLAVE_CAMNOC_UNCOMP 16 + +#define MASTER_SNOC_CFG 0 +#define MASTER_A1NOC_SNOC 1 +#define MASTER_A2NOC_SNOC 2 +#define MASTER_GNOC_SNOC 3 +#define MASTER_MEM_NOC_SNOC 4 +#define MASTER_ANOC_PCIE_SNOC 5 +#define MASTER_PIMEM 6 +#define MASTER_GIC 7 +#define SLAVE_APPSS 8 +#define SLAVE_SNOC_CNOC 9 +#define SLAVE_SNOC_MEM_NOC_GC 10 +#define SLAVE_SNOC_MEM_NOC_SF 11 +#define SLAVE_IMEM 12 +#define SLAVE_PCIE_0 13 +#define SLAVE_PCIE_1 14 +#define SLAVE_PIMEM 15 +#define SLAVE_SERVICE_SNOC 16 +#define SLAVE_QDSS_STM 17 +#define SLAVE_TCU 18 #endif diff --git a/include/dt-bindings/interconnect/qcom,sdx55.h b/include/dt-bindings/interconnect/qcom,sdx55.h new file mode 100644 index 000000000000..bfb6524a2d90 --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,sdx55.h @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Qualcomm SDX55 interconnect IDs + * + * Copyright (c) 2021, Linaro Ltd. + * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SDX55_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_SDX55_H + +#define MASTER_LLCC 0 +#define SLAVE_EBI_CH0 1 + +#define MASTER_TCU_0 0 +#define MASTER_SNOC_GC_MEM_NOC 1 +#define MASTER_AMPSS_M0 2 +#define SLAVE_LLCC 3 +#define SLAVE_MEM_NOC_SNOC 4 +#define SLAVE_MEM_NOC_PCIE_SNOC 5 + +#define MASTER_AUDIO 0 +#define MASTER_BLSP_1 1 +#define MASTER_QDSS_BAM 2 +#define MASTER_QPIC 3 +#define MASTER_SNOC_CFG 4 +#define MASTER_SPMI_FETCHER 5 +#define MASTER_ANOC_SNOC 6 +#define MASTER_IPA 7 +#define MASTER_MEM_NOC_SNOC 8 +#define MASTER_MEM_NOC_PCIE_SNOC 9 +#define MASTER_CRYPTO_CORE_0 10 +#define MASTER_EMAC 11 +#define MASTER_IPA_PCIE 12 +#define MASTER_PCIE 13 +#define MASTER_QDSS_ETR 14 +#define MASTER_SDCC_1 15 +#define MASTER_USB3 16 +#define SLAVE_AOP 17 +#define SLAVE_AOSS 18 +#define SLAVE_APPSS 19 +#define SLAVE_AUDIO 20 +#define SLAVE_BLSP_1 21 +#define SLAVE_CLK_CTL 22 +#define SLAVE_CRYPTO_0_CFG 23 +#define SLAVE_CNOC_DDRSS 24 +#define SLAVE_ECC_CFG 25 +#define SLAVE_EMAC_CFG 26 +#define SLAVE_IMEM_CFG 27 +#define SLAVE_IPA_CFG 28 +#define SLAVE_CNOC_MSS 29 +#define SLAVE_PCIE_PARF 30 +#define SLAVE_PDM 31 +#define SLAVE_PRNG 32 +#define SLAVE_QDSS_CFG 33 +#define SLAVE_QPIC 34 +#define SLAVE_SDCC_1 35 +#define SLAVE_SNOC_CFG 36 +#define SLAVE_SPMI_FETCHER 37 +#define SLAVE_SPMI_VGI_COEX 38 +#define SLAVE_TCSR 39 +#define SLAVE_TLMM 40 +#define SLAVE_USB3 41 +#define SLAVE_USB3_PHY_CFG 42 +#define SLAVE_ANOC_SNOC 43 +#define SLAVE_SNOC_MEM_NOC_GC 44 +#define SLAVE_OCIMEM 45 +#define SLAVE_SERVICE_SNOC 46 +#define SLAVE_PCIE_0 47 +#define SLAVE_QDSS_STM 48 +#define SLAVE_TCU 49 + +#define MASTER_IPA_CORE 0 +#define SLAVE_IPA_CORE 1 + +#endif diff --git a/include/dt-bindings/interconnect/qcom,sdx65.h b/include/dt-bindings/interconnect/qcom,sdx65.h new file mode 100644 index 000000000000..b25288aa7d74 --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,sdx65.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */ +/* + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SDX65_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_SDX65_H + +#define MASTER_LLCC 0 +#define SLAVE_EBI1 1 + +#define MASTER_TCU_0 0 +#define MASTER_SNOC_GC_MEM_NOC 1 +#define MASTER_APPSS_PROC 2 +#define SLAVE_LLCC 3 +#define SLAVE_MEM_NOC_SNOC 4 +#define SLAVE_MEM_NOC_PCIE_SNOC 5 + +#define MASTER_AUDIO 0 +#define MASTER_BLSP_1 1 +#define MASTER_QDSS_BAM 2 +#define MASTER_QPIC 3 +#define MASTER_SNOC_CFG 4 +#define MASTER_SPMI_FETCHER 5 +#define MASTER_ANOC_SNOC 6 +#define MASTER_IPA 7 +#define MASTER_MEM_NOC_SNOC 8 +#define MASTER_MEM_NOC_PCIE_SNOC 9 +#define MASTER_CRYPTO 10 +#define MASTER_IPA_PCIE 11 +#define MASTER_PCIE_0 12 +#define MASTER_QDSS_ETR 13 +#define MASTER_SDCC_1 14 +#define MASTER_USB3 15 +#define SLAVE_AOSS 16 +#define SLAVE_APPSS 17 +#define SLAVE_AUDIO 18 +#define SLAVE_BLSP_1 19 +#define SLAVE_CLK_CTL 20 +#define SLAVE_CRYPTO_0_CFG 21 +#define SLAVE_CNOC_DDRSS 22 +#define SLAVE_ECC_CFG 23 +#define SLAVE_IMEM_CFG 24 +#define SLAVE_IPA_CFG 25 +#define SLAVE_CNOC_MSS 26 +#define SLAVE_PCIE_PARF 27 +#define SLAVE_PDM 28 +#define SLAVE_PRNG 29 +#define SLAVE_QDSS_CFG 30 +#define SLAVE_QPIC 31 +#define SLAVE_SDCC_1 32 +#define SLAVE_SNOC_CFG 33 +#define SLAVE_SPMI_FETCHER 34 +#define SLAVE_SPMI_VGI_COEX 35 +#define SLAVE_TCSR 36 +#define SLAVE_TLMM 37 +#define SLAVE_USB3 38 +#define SLAVE_USB3_PHY_CFG 39 +#define SLAVE_ANOC_SNOC 40 +#define SLAVE_SNOC_MEM_NOC_GC 41 +#define SLAVE_IMEM 42 +#define SLAVE_SERVICE_SNOC 43 +#define SLAVE_PCIE_0 44 +#define SLAVE_QDSS_STM 45 +#define SLAVE_TCU 46 + +#endif diff --git a/include/dt-bindings/interconnect/qcom,sm6350.h b/include/dt-bindings/interconnect/qcom,sm6350.h new file mode 100644 index 000000000000..e662cede9aaa --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,sm6350.h @@ -0,0 +1,148 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ +/* + * Qualcomm SM6350 interconnect IDs + * + * Copyright (C) 2022 Luca Weiss <luca.weiss@fairphone.com> + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM6350_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_SM6350_H + +#define MASTER_A1NOC_CFG 0 +#define MASTER_QUP_0 1 +#define MASTER_EMMC 2 +#define MASTER_UFS_MEM 3 +#define A1NOC_SNOC_SLV 4 +#define SLAVE_SERVICE_A1NOC 5 + +#define MASTER_A2NOC_CFG 0 +#define MASTER_QDSS_BAM 1 +#define MASTER_QUP_1 2 +#define MASTER_CRYPTO_CORE_0 3 +#define MASTER_IPA 4 +#define MASTER_QDSS_ETR 5 +#define MASTER_SDCC_2 6 +#define MASTER_USB3 7 +#define A2NOC_SNOC_SLV 8 +#define SLAVE_SERVICE_A2NOC 9 + +#define MASTER_CAMNOC_HF0_UNCOMP 0 +#define MASTER_CAMNOC_ICP_UNCOMP 1 +#define MASTER_CAMNOC_SF_UNCOMP 2 +#define MASTER_QUP_CORE_0 3 +#define MASTER_QUP_CORE_1 4 +#define MASTER_LLCC 5 +#define SLAVE_CAMNOC_UNCOMP 6 +#define SLAVE_QUP_CORE_0 7 +#define SLAVE_QUP_CORE_1 8 +#define SLAVE_EBI_CH0 9 + +#define MASTER_NPU 0 +#define MASTER_NPU_PROC 1 +#define SLAVE_CDSP_GEM_NOC 2 + +#define SNOC_CNOC_MAS 0 +#define MASTER_QDSS_DAP 1 +#define SLAVE_A1NOC_CFG 2 +#define SLAVE_A2NOC_CFG 3 +#define SLAVE_AHB2PHY 4 +#define SLAVE_AHB2PHY_2 5 +#define SLAVE_AOSS 6 +#define SLAVE_BOOT_ROM 7 +#define SLAVE_CAMERA_CFG 8 +#define SLAVE_CAMERA_NRT_THROTTLE_CFG 9 +#define SLAVE_CAMERA_RT_THROTTLE_CFG 10 +#define SLAVE_CLK_CTL 11 +#define SLAVE_RBCPR_CX_CFG 12 +#define SLAVE_RBCPR_MX_CFG 13 +#define SLAVE_CRYPTO_0_CFG 14 +#define SLAVE_DCC_CFG 15 +#define SLAVE_CNOC_DDRSS 16 +#define SLAVE_DISPLAY_CFG 17 +#define SLAVE_DISPLAY_THROTTLE_CFG 18 +#define SLAVE_EMMC_CFG 19 +#define SLAVE_GLM 20 +#define SLAVE_GRAPHICS_3D_CFG 21 +#define SLAVE_IMEM_CFG 22 +#define SLAVE_IPA_CFG 23 +#define SLAVE_CNOC_MNOC_CFG 24 +#define SLAVE_CNOC_MSS 25 +#define SLAVE_NPU_CFG 26 +#define SLAVE_PDM 27 +#define SLAVE_PIMEM_CFG 28 +#define SLAVE_PRNG 29 +#define SLAVE_QDSS_CFG 30 +#define SLAVE_QM_CFG 31 +#define SLAVE_QM_MPU_CFG 32 +#define SLAVE_QUP_0 33 +#define SLAVE_QUP_1 34 +#define SLAVE_SDCC_2 35 +#define SLAVE_SECURITY 36 +#define SLAVE_SNOC_CFG 37 +#define SLAVE_TCSR 38 +#define SLAVE_UFS_MEM_CFG 39 +#define SLAVE_USB3 40 +#define SLAVE_VENUS_CFG 41 +#define SLAVE_VENUS_THROTTLE_CFG 42 +#define SLAVE_VSENSE_CTRL_CFG 43 +#define SLAVE_SERVICE_CNOC 44 + +#define MASTER_CNOC_DC_NOC 0 +#define SLAVE_GEM_NOC_CFG 1 +#define SLAVE_LLCC_CFG 2 + +#define MASTER_AMPSS_M0 0 +#define MASTER_SYS_TCU 1 +#define MASTER_GEM_NOC_CFG 2 +#define MASTER_COMPUTE_NOC 3 +#define MASTER_MNOC_HF_MEM_NOC 4 +#define MASTER_MNOC_SF_MEM_NOC 5 +#define MASTER_SNOC_GC_MEM_NOC 6 +#define MASTER_SNOC_SF_MEM_NOC 7 +#define MASTER_GRAPHICS_3D 8 +#define SLAVE_MCDMA_MS_MPU_CFG 9 +#define SLAVE_MSS_PROC_MS_MPU_CFG 10 +#define SLAVE_GEM_NOC_SNOC 11 +#define SLAVE_LLCC 12 +#define SLAVE_SERVICE_GEM_NOC 13 + +#define MASTER_CNOC_MNOC_CFG 0 +#define MASTER_VIDEO_P0 1 +#define MASTER_VIDEO_PROC 2 +#define MASTER_CAMNOC_HF 3 +#define MASTER_CAMNOC_ICP 4 +#define MASTER_CAMNOC_SF 5 +#define MASTER_MDP_PORT0 6 +#define SLAVE_MNOC_HF_MEM_NOC 7 +#define SLAVE_MNOC_SF_MEM_NOC 8 +#define SLAVE_SERVICE_MNOC 9 + +#define MASTER_NPU_SYS 0 +#define MASTER_NPU_NOC_CFG 1 +#define SLAVE_NPU_CAL_DP0 2 +#define SLAVE_NPU_CP 3 +#define SLAVE_NPU_INT_DMA_BWMON_CFG 4 +#define SLAVE_NPU_DPM 5 +#define SLAVE_ISENSE_CFG 6 +#define SLAVE_NPU_LLM_CFG 7 +#define SLAVE_NPU_TCM 8 +#define SLAVE_NPU_COMPUTE_NOC 9 +#define SLAVE_SERVICE_NPU_NOC 10 + +#define MASTER_SNOC_CFG 0 +#define A1NOC_SNOC_MAS 1 +#define A2NOC_SNOC_MAS 2 +#define MASTER_GEM_NOC_SNOC 3 +#define MASTER_PIMEM 4 +#define MASTER_GIC 5 +#define SLAVE_APPSS 6 +#define SNOC_CNOC_SLV 7 +#define SLAVE_SNOC_GEM_NOC_GC 8 +#define SLAVE_SNOC_GEM_NOC_SF 9 +#define SLAVE_OCIMEM 10 +#define SLAVE_PIMEM 11 +#define SLAVE_SERVICE_SNOC 12 +#define SLAVE_QDSS_STM 13 +#define SLAVE_TCU 14 + +#endif diff --git a/include/dt-bindings/interconnect/qcom,sm8150.h b/include/dt-bindings/interconnect/qcom,sm8150.h new file mode 100644 index 000000000000..a25684680c42 --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,sm8150.h @@ -0,0 +1,162 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Qualcomm SM8150 interconnect IDs + * + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM8150_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_SM8150_H + +#define MASTER_A1NOC_CFG 0 +#define MASTER_QUP_0 1 +#define MASTER_EMAC 2 +#define MASTER_UFS_MEM 3 +#define MASTER_USB3 4 +#define MASTER_USB3_1 5 +#define A1NOC_SNOC_SLV 6 +#define SLAVE_SERVICE_A1NOC 7 + +#define MASTER_A2NOC_CFG 0 +#define MASTER_QDSS_BAM 1 +#define MASTER_QSPI 2 +#define MASTER_QUP_1 3 +#define MASTER_QUP_2 4 +#define MASTER_SENSORS_AHB 5 +#define MASTER_TSIF 6 +#define MASTER_CNOC_A2NOC 7 +#define MASTER_CRYPTO_CORE_0 8 +#define MASTER_IPA 9 +#define MASTER_PCIE 10 +#define MASTER_PCIE_1 11 +#define MASTER_QDSS_ETR 12 +#define MASTER_SDCC_2 13 +#define MASTER_SDCC_4 14 +#define A2NOC_SNOC_SLV 15 +#define SLAVE_ANOC_PCIE_GEM_NOC 16 +#define SLAVE_SERVICE_A2NOC 17 + +#define MASTER_CAMNOC_HF0_UNCOMP 0 +#define MASTER_CAMNOC_HF1_UNCOMP 1 +#define MASTER_CAMNOC_SF_UNCOMP 2 +#define SLAVE_CAMNOC_UNCOMP 3 + +#define MASTER_NPU 0 +#define SLAVE_CDSP_MEM_NOC 1 + +#define MASTER_SPDM 0 +#define SNOC_CNOC_MAS 1 +#define MASTER_QDSS_DAP 2 +#define SLAVE_A1NOC_CFG 3 +#define SLAVE_A2NOC_CFG 4 +#define SLAVE_AHB2PHY_SOUTH 5 +#define SLAVE_AOP 6 +#define SLAVE_AOSS 7 +#define SLAVE_CAMERA_CFG 8 +#define SLAVE_CLK_CTL 9 +#define SLAVE_CDSP_CFG 10 +#define SLAVE_RBCPR_CX_CFG 11 +#define SLAVE_RBCPR_MMCX_CFG 12 +#define SLAVE_RBCPR_MX_CFG 13 +#define SLAVE_CRYPTO_0_CFG 14 +#define SLAVE_CNOC_DDRSS 15 +#define SLAVE_DISPLAY_CFG 16 +#define SLAVE_EMAC_CFG 17 +#define SLAVE_GLM 18 +#define SLAVE_GRAPHICS_3D_CFG 19 +#define SLAVE_IMEM_CFG 20 +#define SLAVE_IPA_CFG 21 +#define SLAVE_CNOC_MNOC_CFG 22 +#define SLAVE_NPU_CFG 23 +#define SLAVE_PCIE_0_CFG 24 +#define SLAVE_PCIE_1_CFG 25 +#define SLAVE_NORTH_PHY_CFG 26 +#define SLAVE_PIMEM_CFG 27 +#define SLAVE_PRNG 28 +#define SLAVE_QDSS_CFG 29 +#define SLAVE_QSPI 30 +#define SLAVE_QUP_2 31 +#define SLAVE_QUP_1 32 +#define SLAVE_QUP_0 33 +#define SLAVE_SDCC_2 34 +#define SLAVE_SDCC_4 35 +#define SLAVE_SNOC_CFG 36 +#define SLAVE_SPDM_WRAPPER 37 +#define SLAVE_SPSS_CFG 38 +#define SLAVE_SSC_CFG 39 +#define SLAVE_TCSR 40 +#define SLAVE_TLMM_EAST 41 +#define SLAVE_TLMM_NORTH 42 +#define SLAVE_TLMM_SOUTH 43 +#define SLAVE_TLMM_WEST 44 +#define SLAVE_TSIF 45 +#define SLAVE_UFS_CARD_CFG 46 +#define SLAVE_UFS_MEM_CFG 47 +#define SLAVE_USB3 48 +#define SLAVE_USB3_1 49 +#define SLAVE_VENUS_CFG 50 +#define SLAVE_VSENSE_CTRL_CFG 51 +#define SLAVE_CNOC_A2NOC 52 +#define SLAVE_SERVICE_CNOC 53 + +#define MASTER_CNOC_DC_NOC 0 +#define SLAVE_LLCC_CFG 1 +#define SLAVE_GEM_NOC_CFG 2 + +#define MASTER_AMPSS_M0 0 +#define MASTER_GPU_TCU 1 +#define MASTER_SYS_TCU 2 +#define MASTER_GEM_NOC_CFG 3 +#define MASTER_COMPUTE_NOC 4 +#define MASTER_GRAPHICS_3D 5 +#define MASTER_MNOC_HF_MEM_NOC 6 +#define MASTER_MNOC_SF_MEM_NOC 7 +#define MASTER_GEM_NOC_PCIE_SNOC 8 +#define MASTER_SNOC_GC_MEM_NOC 9 +#define MASTER_SNOC_SF_MEM_NOC 10 +#define MASTER_ECC 11 +#define SLAVE_MSS_PROC_MS_MPU_CFG 12 +#define SLAVE_ECC 13 +#define SLAVE_GEM_NOC_SNOC 14 +#define SLAVE_LLCC 15 +#define SLAVE_SERVICE_GEM_NOC 16 + +#define MASTER_IPA_CORE 0 +#define SLAVE_IPA_CORE 1 + +#define MASTER_LLCC 0 +#define SLAVE_EBI_CH0 1 + +#define MASTER_CNOC_MNOC_CFG 0 +#define MASTER_CAMNOC_HF0 1 +#define MASTER_CAMNOC_HF1 2 +#define MASTER_CAMNOC_SF 3 +#define MASTER_MDP_PORT0 4 +#define MASTER_MDP_PORT1 5 +#define MASTER_ROTATOR 6 +#define MASTER_VIDEO_P0 7 +#define MASTER_VIDEO_P1 8 +#define MASTER_VIDEO_PROC 9 +#define SLAVE_MNOC_SF_MEM_NOC 10 +#define SLAVE_MNOC_HF_MEM_NOC 11 +#define SLAVE_SERVICE_MNOC 12 + +#define MASTER_SNOC_CFG 0 +#define A1NOC_SNOC_MAS 1 +#define A2NOC_SNOC_MAS 2 +#define MASTER_GEM_NOC_SNOC 3 +#define MASTER_PIMEM 4 +#define MASTER_GIC 5 +#define SLAVE_APPSS 6 +#define SNOC_CNOC_SLV 7 +#define SLAVE_SNOC_GEM_NOC_GC 8 +#define SLAVE_SNOC_GEM_NOC_SF 9 +#define SLAVE_OCIMEM 10 +#define SLAVE_PIMEM 11 +#define SLAVE_SERVICE_SNOC 12 +#define SLAVE_PCIE_0 13 +#define SLAVE_PCIE_1 14 +#define SLAVE_QDSS_STM 15 +#define SLAVE_TCU 16 + +#endif diff --git a/include/dt-bindings/interconnect/qcom,sm8250.h b/include/dt-bindings/interconnect/qcom,sm8250.h new file mode 100644 index 000000000000..1b4d9fbe888d --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,sm8250.h @@ -0,0 +1,172 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Qualcomm SM8250 interconnect IDs + * + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM8250_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_SM8250_H + +#define MASTER_A1NOC_CFG 0 +#define MASTER_QSPI_0 1 +#define MASTER_QUP_1 2 +#define MASTER_QUP_2 3 +#define MASTER_TSIF 4 +#define MASTER_PCIE_2 5 +#define MASTER_SDCC_4 6 +#define MASTER_UFS_MEM 7 +#define MASTER_USB3 8 +#define MASTER_USB3_1 9 +#define A1NOC_SNOC_SLV 10 +#define SLAVE_ANOC_PCIE_GEM_NOC_1 11 +#define SLAVE_SERVICE_A1NOC 12 + +#define MASTER_A2NOC_CFG 0 +#define MASTER_QDSS_BAM 1 +#define MASTER_QUP_0 2 +#define MASTER_CNOC_A2NOC 3 +#define MASTER_CRYPTO_CORE_0 4 +#define MASTER_IPA 5 +#define MASTER_PCIE 6 +#define MASTER_PCIE_1 7 +#define MASTER_QDSS_ETR 8 +#define MASTER_SDCC_2 9 +#define MASTER_UFS_CARD 10 +#define A2NOC_SNOC_SLV 11 +#define SLAVE_ANOC_PCIE_GEM_NOC 12 +#define SLAVE_SERVICE_A2NOC 13 + +#define MASTER_NPU 0 +#define SLAVE_CDSP_MEM_NOC 1 + +#define SNOC_CNOC_MAS 0 +#define MASTER_QDSS_DAP 1 +#define SLAVE_A1NOC_CFG 2 +#define SLAVE_A2NOC_CFG 3 +#define SLAVE_AHB2PHY_SOUTH 4 +#define SLAVE_AHB2PHY_NORTH 5 +#define SLAVE_AOSS 6 +#define SLAVE_CAMERA_CFG 7 +#define SLAVE_CLK_CTL 8 +#define SLAVE_CDSP_CFG 9 +#define SLAVE_RBCPR_CX_CFG 10 +#define SLAVE_RBCPR_MMCX_CFG 11 +#define SLAVE_RBCPR_MX_CFG 12 +#define SLAVE_CRYPTO_0_CFG 13 +#define SLAVE_CX_RDPM 14 +#define SLAVE_DCC_CFG 15 +#define SLAVE_CNOC_DDRSS 16 +#define SLAVE_DISPLAY_CFG 17 +#define SLAVE_GRAPHICS_3D_CFG 18 +#define SLAVE_IMEM_CFG 19 +#define SLAVE_IPA_CFG 20 +#define SLAVE_IPC_ROUTER_CFG 21 +#define SLAVE_LPASS 22 +#define SLAVE_CNOC_MNOC_CFG 23 +#define SLAVE_NPU_CFG 24 +#define SLAVE_PCIE_0_CFG 25 +#define SLAVE_PCIE_1_CFG 26 +#define SLAVE_PCIE_2_CFG 27 +#define SLAVE_PDM 28 +#define SLAVE_PIMEM_CFG 29 +#define SLAVE_PRNG 30 +#define SLAVE_QDSS_CFG 31 +#define SLAVE_QSPI_0 32 +#define SLAVE_QUP_0 33 +#define SLAVE_QUP_1 34 +#define SLAVE_QUP_2 35 +#define SLAVE_SDCC_2 36 +#define SLAVE_SDCC_4 37 +#define SLAVE_SNOC_CFG 38 +#define SLAVE_TCSR 39 +#define SLAVE_TLMM_NORTH 40 +#define SLAVE_TLMM_SOUTH 41 +#define SLAVE_TLMM_WEST 42 +#define SLAVE_TSIF 43 +#define SLAVE_UFS_CARD_CFG 44 +#define SLAVE_UFS_MEM_CFG 45 +#define SLAVE_USB3 46 +#define SLAVE_USB3_1 47 +#define SLAVE_VENUS_CFG 48 +#define SLAVE_VSENSE_CTRL_CFG 49 +#define SLAVE_CNOC_A2NOC 50 +#define SLAVE_SERVICE_CNOC 51 + +#define MASTER_CNOC_DC_NOC 0 +#define SLAVE_LLCC_CFG 1 +#define SLAVE_GEM_NOC_CFG 2 + +#define MASTER_GPU_TCU 0 +#define MASTER_SYS_TCU 1 +#define MASTER_AMPSS_M0 2 +#define MASTER_GEM_NOC_CFG 3 +#define MASTER_COMPUTE_NOC 4 +#define MASTER_GRAPHICS_3D 5 +#define MASTER_MNOC_HF_MEM_NOC 6 +#define MASTER_MNOC_SF_MEM_NOC 7 +#define MASTER_ANOC_PCIE_GEM_NOC 8 +#define MASTER_SNOC_GC_MEM_NOC 9 +#define MASTER_SNOC_SF_MEM_NOC 10 +#define SLAVE_GEM_NOC_SNOC 11 +#define SLAVE_LLCC 12 +#define SLAVE_MEM_NOC_PCIE_SNOC 13 +#define SLAVE_SERVICE_GEM_NOC_1 14 +#define SLAVE_SERVICE_GEM_NOC_2 15 +#define SLAVE_SERVICE_GEM_NOC 16 + +#define MASTER_IPA_CORE 0 +#define SLAVE_IPA_CORE 1 + +#define MASTER_LLCC 0 +#define SLAVE_EBI_CH0 1 + +#define MASTER_CNOC_MNOC_CFG 0 +#define MASTER_CAMNOC_HF 1 +#define MASTER_CAMNOC_ICP 2 +#define MASTER_CAMNOC_SF 3 +#define MASTER_VIDEO_P0 4 +#define MASTER_VIDEO_P1 5 +#define MASTER_VIDEO_PROC 6 +#define MASTER_MDP_PORT0 7 +#define MASTER_MDP_PORT1 8 +#define MASTER_ROTATOR 9 +#define SLAVE_MNOC_HF_MEM_NOC 10 +#define SLAVE_MNOC_SF_MEM_NOC 11 +#define SLAVE_SERVICE_MNOC 12 + +#define MASTER_NPU_SYS 0 +#define MASTER_NPU_CDP 1 +#define MASTER_NPU_NOC_CFG 2 +#define SLAVE_NPU_CAL_DP0 3 +#define SLAVE_NPU_CAL_DP1 4 +#define SLAVE_NPU_CP 5 +#define SLAVE_NPU_INT_DMA_BWMON_CFG 6 +#define SLAVE_NPU_DPM 7 +#define SLAVE_ISENSE_CFG 8 +#define SLAVE_NPU_LLM_CFG 9 +#define SLAVE_NPU_TCM 10 +#define SLAVE_NPU_COMPUTE_NOC 11 +#define SLAVE_SERVICE_NPU_NOC 12 + +#define MASTER_SNOC_CFG 0 +#define A1NOC_SNOC_MAS 1 +#define A2NOC_SNOC_MAS 2 +#define MASTER_GEM_NOC_SNOC 3 +#define MASTER_GEM_NOC_PCIE_SNOC 4 +#define MASTER_PIMEM 5 +#define MASTER_GIC 6 +#define SLAVE_APPSS 7 +#define SNOC_CNOC_SLV 8 +#define SLAVE_SNOC_GEM_NOC_GC 9 +#define SLAVE_SNOC_GEM_NOC_SF 10 +#define SLAVE_OCIMEM 11 +#define SLAVE_PIMEM 12 +#define SLAVE_SERVICE_SNOC 13 +#define SLAVE_PCIE_0 14 +#define SLAVE_PCIE_1 15 +#define SLAVE_PCIE_2 16 +#define SLAVE_QDSS_STM 17 +#define SLAVE_TCU 18 + +#endif diff --git a/include/dt-bindings/interconnect/qcom,sm8350.h b/include/dt-bindings/interconnect/qcom,sm8350.h new file mode 100644 index 000000000000..c7f7ed315aeb --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,sm8350.h @@ -0,0 +1,172 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Qualcomm SM8350 interconnect IDs + * + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2021, Linaro Limited + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM8350_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_SM8350_H + +#define MASTER_QSPI_0 0 +#define MASTER_QUP_1 1 +#define MASTER_A1NOC_CFG 2 +#define MASTER_SDCC_4 3 +#define MASTER_UFS_MEM 4 +#define MASTER_USB3_0 5 +#define MASTER_USB3_1 6 +#define SLAVE_A1NOC_SNOC 7 +#define SLAVE_SERVICE_A1NOC 8 + +#define MASTER_QDSS_BAM 0 +#define MASTER_QUP_0 1 +#define MASTER_QUP_2 2 +#define MASTER_A2NOC_CFG 3 +#define MASTER_CRYPTO 4 +#define MASTER_IPA 5 +#define MASTER_PCIE_0 6 +#define MASTER_PCIE_1 7 +#define MASTER_QDSS_ETR 8 +#define MASTER_SDCC_2 9 +#define MASTER_UFS_CARD 10 +#define SLAVE_A2NOC_SNOC 11 +#define SLAVE_ANOC_PCIE_GEM_NOC 12 +#define SLAVE_SERVICE_A2NOC 13 + +#define MASTER_GEM_NOC_CNOC 0 +#define MASTER_GEM_NOC_PCIE_SNOC 1 +#define MASTER_QDSS_DAP 2 +#define SLAVE_AHB2PHY_SOUTH 3 +#define SLAVE_AHB2PHY_NORTH 4 +#define SLAVE_AOSS 5 +#define SLAVE_APPSS 6 +#define SLAVE_CAMERA_CFG 7 +#define SLAVE_CLK_CTL 8 +#define SLAVE_CDSP_CFG 9 +#define SLAVE_RBCPR_CX_CFG 10 +#define SLAVE_RBCPR_MMCX_CFG 11 +#define SLAVE_RBCPR_MX_CFG 12 +#define SLAVE_CRYPTO_0_CFG 13 +#define SLAVE_CX_RDPM 14 +#define SLAVE_DCC_CFG 15 +#define SLAVE_DISPLAY_CFG 16 +#define SLAVE_GFX3D_CFG 17 +#define SLAVE_HWKM 18 +#define SLAVE_IMEM_CFG 19 +#define SLAVE_IPA_CFG 20 +#define SLAVE_IPC_ROUTER_CFG 21 +#define SLAVE_LPASS 22 +#define SLAVE_CNOC_MSS 23 +#define SLAVE_MX_RDPM 24 +#define SLAVE_PCIE_0_CFG 25 +#define SLAVE_PCIE_1_CFG 26 +#define SLAVE_PDM 27 +#define SLAVE_PIMEM_CFG 28 +#define SLAVE_PKA_WRAPPER_CFG 29 +#define SLAVE_PMU_WRAPPER_CFG 30 +#define SLAVE_QDSS_CFG 31 +#define SLAVE_QSPI_0 32 +#define SLAVE_QUP_0 33 +#define SLAVE_QUP_1 34 +#define SLAVE_QUP_2 35 +#define SLAVE_SDCC_2 36 +#define SLAVE_SDCC_4 37 +#define SLAVE_SECURITY 38 +#define SLAVE_SPSS_CFG 39 +#define SLAVE_TCSR 40 +#define SLAVE_TLMM 41 +#define SLAVE_UFS_CARD_CFG 42 +#define SLAVE_UFS_MEM_CFG 43 +#define SLAVE_USB3_0 44 +#define SLAVE_USB3_1 45 +#define SLAVE_VENUS_CFG 46 +#define SLAVE_VSENSE_CTRL_CFG 47 +#define SLAVE_A1NOC_CFG 48 +#define SLAVE_A2NOC_CFG 49 +#define SLAVE_DDRSS_CFG 50 +#define SLAVE_CNOC_MNOC_CFG 51 +#define SLAVE_SNOC_CFG 52 +#define SLAVE_BOOT_IMEM 53 +#define SLAVE_IMEM 54 +#define SLAVE_PIMEM 55 +#define SLAVE_SERVICE_CNOC 56 +#define SLAVE_PCIE_0 57 +#define SLAVE_PCIE_1 58 +#define SLAVE_QDSS_STM 59 +#define SLAVE_TCU 60 + +#define MASTER_CNOC_DC_NOC 0 +#define SLAVE_LLCC_CFG 1 +#define SLAVE_GEM_NOC_CFG 2 + +#define MASTER_GPU_TCU 0 +#define MASTER_SYS_TCU 1 +#define MASTER_APPSS_PROC 2 +#define MASTER_COMPUTE_NOC 3 +#define MASTER_GEM_NOC_CFG 4 +#define MASTER_GFX3D 5 +#define MASTER_MNOC_HF_MEM_NOC 6 +#define MASTER_MNOC_SF_MEM_NOC 7 +#define MASTER_ANOC_PCIE_GEM_NOC 8 +#define MASTER_SNOC_GC_MEM_NOC 9 +#define MASTER_SNOC_SF_MEM_NOC 10 +#define SLAVE_MSS_PROC_MS_MPU_CFG 11 +#define SLAVE_MCDMA_MS_MPU_CFG 12 +#define SLAVE_GEM_NOC_CNOC 13 +#define SLAVE_LLCC 14 +#define SLAVE_MEM_NOC_PCIE_SNOC 15 +#define SLAVE_SERVICE_GEM_NOC_1 16 +#define SLAVE_SERVICE_GEM_NOC_2 17 +#define SLAVE_SERVICE_GEM_NOC 18 +#define MASTER_MNOC_HF_MEM_NOC_DISP 19 +#define MASTER_MNOC_SF_MEM_NOC_DISP 20 +#define SLAVE_LLCC_DISP 21 + +#define MASTER_CNOC_LPASS_AG_NOC 0 +#define SLAVE_LPASS_CORE_CFG 1 +#define SLAVE_LPASS_LPI_CFG 2 +#define SLAVE_LPASS_MPU_CFG 3 +#define SLAVE_LPASS_TOP_CFG 4 +#define SLAVE_SERVICES_LPASS_AML_NOC 5 +#define SLAVE_SERVICE_LPASS_AG_NOC 6 + +#define MASTER_LLCC 0 +#define SLAVE_EBI1 1 +#define MASTER_LLCC_DISP 2 +#define SLAVE_EBI1_DISP 3 + +#define MASTER_CAMNOC_HF 0 +#define MASTER_CAMNOC_ICP 1 +#define MASTER_CAMNOC_SF 2 +#define MASTER_CNOC_MNOC_CFG 3 +#define MASTER_VIDEO_P0 4 +#define MASTER_VIDEO_P1 5 +#define MASTER_VIDEO_PROC 6 +#define MASTER_MDP0 7 +#define MASTER_MDP1 8 +#define MASTER_ROTATOR 9 +#define SLAVE_MNOC_HF_MEM_NOC 10 +#define SLAVE_MNOC_SF_MEM_NOC 11 +#define SLAVE_SERVICE_MNOC 12 +#define MASTER_MDP0_DISP 13 +#define MASTER_MDP1_DISP 14 +#define MASTER_ROTATOR_DISP 15 +#define SLAVE_MNOC_HF_MEM_NOC_DISP 16 +#define SLAVE_MNOC_SF_MEM_NOC_DISP 17 + +#define MASTER_CDSP_NOC_CFG 0 +#define MASTER_CDSP_PROC 1 +#define SLAVE_CDSP_MEM_NOC 2 +#define SLAVE_SERVICE_NSP_NOC 3 + +#define MASTER_A1NOC_SNOC 0 +#define MASTER_A2NOC_SNOC 1 +#define MASTER_SNOC_CFG 2 +#define MASTER_PIMEM 3 +#define MASTER_GIC 4 +#define SLAVE_SNOC_GEM_NOC_GC 5 +#define SLAVE_SNOC_GEM_NOC_SF 6 +#define SLAVE_SERVICE_SNOC 7 + +#endif diff --git a/include/dt-bindings/interconnect/qcom,sm8450.h b/include/dt-bindings/interconnect/qcom,sm8450.h new file mode 100644 index 000000000000..8f3c5e1fb4c4 --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,sm8450.h @@ -0,0 +1,171 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2021, Linaro Limited + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM8450_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_SM8450_H + +#define MASTER_QSPI_0 0 +#define MASTER_QUP_1 1 +#define MASTER_A1NOC_CFG 2 +#define MASTER_SDCC_4 3 +#define MASTER_UFS_MEM 4 +#define MASTER_USB3_0 5 +#define SLAVE_A1NOC_SNOC 6 +#define SLAVE_SERVICE_A1NOC 7 + +#define MASTER_QDSS_BAM 0 +#define MASTER_QUP_0 1 +#define MASTER_QUP_2 2 +#define MASTER_A2NOC_CFG 3 +#define MASTER_CRYPTO 4 +#define MASTER_IPA 5 +#define MASTER_SENSORS_PROC 6 +#define MASTER_SP 7 +#define MASTER_QDSS_ETR 8 +#define MASTER_QDSS_ETR_1 9 +#define MASTER_SDCC_2 10 +#define SLAVE_A2NOC_SNOC 11 +#define SLAVE_SERVICE_A2NOC 12 + +#define MASTER_QUP_CORE_0 0 +#define MASTER_QUP_CORE_1 1 +#define MASTER_QUP_CORE_2 2 +#define SLAVE_QUP_CORE_0 3 +#define SLAVE_QUP_CORE_1 4 +#define SLAVE_QUP_CORE_2 5 + +#define MASTER_GEM_NOC_CNOC 0 +#define MASTER_GEM_NOC_PCIE_SNOC 1 +#define SLAVE_AHB2PHY_SOUTH 2 +#define SLAVE_AHB2PHY_NORTH 3 +#define SLAVE_AOSS 4 +#define SLAVE_CAMERA_CFG 5 +#define SLAVE_CLK_CTL 6 +#define SLAVE_CDSP_CFG 7 +#define SLAVE_RBCPR_CX_CFG 8 +#define SLAVE_RBCPR_MMCX_CFG 9 +#define SLAVE_RBCPR_MXA_CFG 10 +#define SLAVE_RBCPR_MXC_CFG 11 +#define SLAVE_CRYPTO_0_CFG 12 +#define SLAVE_CX_RDPM 13 +#define SLAVE_DISPLAY_CFG 14 +#define SLAVE_GFX3D_CFG 15 +#define SLAVE_IMEM_CFG 16 +#define SLAVE_IPA_CFG 17 +#define SLAVE_IPC_ROUTER_CFG 18 +#define SLAVE_LPASS 19 +#define SLAVE_CNOC_MSS 20 +#define SLAVE_MX_RDPM 21 +#define SLAVE_PCIE_0_CFG 22 +#define SLAVE_PCIE_1_CFG 23 +#define SLAVE_PDM 24 +#define SLAVE_PIMEM_CFG 25 +#define SLAVE_PRNG 26 +#define SLAVE_QDSS_CFG 27 +#define SLAVE_QSPI_0 28 +#define SLAVE_QUP_0 29 +#define SLAVE_QUP_1 30 +#define SLAVE_QUP_2 31 +#define SLAVE_SDCC_2 32 +#define SLAVE_SDCC_4 33 +#define SLAVE_SPSS_CFG 34 +#define SLAVE_TCSR 35 +#define SLAVE_TLMM 36 +#define SLAVE_TME_CFG 37 +#define SLAVE_UFS_MEM_CFG 38 +#define SLAVE_USB3_0 39 +#define SLAVE_VENUS_CFG 40 +#define SLAVE_VSENSE_CTRL_CFG 41 +#define SLAVE_A1NOC_CFG 42 +#define SLAVE_A2NOC_CFG 43 +#define SLAVE_DDRSS_CFG 44 +#define SLAVE_CNOC_MNOC_CFG 45 +#define SLAVE_PCIE_ANOC_CFG 46 +#define SLAVE_SNOC_CFG 47 +#define SLAVE_IMEM 48 +#define SLAVE_PIMEM 49 +#define SLAVE_SERVICE_CNOC 50 +#define SLAVE_PCIE_0 51 +#define SLAVE_PCIE_1 52 +#define SLAVE_QDSS_STM 53 +#define SLAVE_TCU 54 + +#define MASTER_GPU_TCU 0 +#define MASTER_SYS_TCU 1 +#define MASTER_APPSS_PROC 2 +#define MASTER_GFX3D 3 +#define MASTER_MSS_PROC 4 +#define MASTER_MNOC_HF_MEM_NOC 5 +#define MASTER_MNOC_SF_MEM_NOC 6 +#define MASTER_COMPUTE_NOC 7 +#define MASTER_ANOC_PCIE_GEM_NOC 8 +#define MASTER_SNOC_GC_MEM_NOC 9 +#define MASTER_SNOC_SF_MEM_NOC 10 +#define SLAVE_GEM_NOC_CNOC 11 +#define SLAVE_LLCC 12 +#define SLAVE_MEM_NOC_PCIE_SNOC 13 +#define MASTER_MNOC_HF_MEM_NOC_DISP 14 +#define MASTER_MNOC_SF_MEM_NOC_DISP 15 +#define MASTER_ANOC_PCIE_GEM_NOC_DISP 16 +#define SLAVE_LLCC_DISP 17 + +#define MASTER_CNOC_LPASS_AG_NOC 0 +#define MASTER_LPASS_PROC 1 +#define SLAVE_LPASS_CORE_CFG 2 +#define SLAVE_LPASS_LPI_CFG 3 +#define SLAVE_LPASS_MPU_CFG 4 +#define SLAVE_LPASS_TOP_CFG 5 +#define SLAVE_LPASS_SNOC 6 +#define SLAVE_SERVICES_LPASS_AML_NOC 7 +#define SLAVE_SERVICE_LPASS_AG_NOC 8 + +#define MASTER_LLCC 0 +#define SLAVE_EBI1 1 +#define MASTER_LLCC_DISP 2 +#define SLAVE_EBI1_DISP 3 + +#define MASTER_CAMNOC_HF 0 +#define MASTER_CAMNOC_ICP 1 +#define MASTER_CAMNOC_SF 2 +#define MASTER_MDP 3 +#define MASTER_CNOC_MNOC_CFG 4 +#define MASTER_ROTATOR 5 +#define MASTER_CDSP_HCP 6 +#define MASTER_VIDEO 7 +#define MASTER_VIDEO_CV_PROC 8 +#define MASTER_VIDEO_PROC 9 +#define MASTER_VIDEO_V_PROC 10 +#define SLAVE_MNOC_HF_MEM_NOC 11 +#define SLAVE_MNOC_SF_MEM_NOC 12 +#define SLAVE_SERVICE_MNOC 13 +#define MASTER_MDP_DISP 14 +#define MASTER_ROTATOR_DISP 15 +#define SLAVE_MNOC_HF_MEM_NOC_DISP 16 +#define SLAVE_MNOC_SF_MEM_NOC_DISP 17 + +#define MASTER_CDSP_NOC_CFG 0 +#define MASTER_CDSP_PROC 1 +#define SLAVE_CDSP_MEM_NOC 2 +#define SLAVE_SERVICE_NSP_NOC 3 + +#define MASTER_PCIE_ANOC_CFG 0 +#define MASTER_PCIE_0 1 +#define MASTER_PCIE_1 2 +#define SLAVE_ANOC_PCIE_GEM_NOC 3 +#define SLAVE_SERVICE_PCIE_ANOC 4 + +#define MASTER_GIC_AHB 0 +#define MASTER_A1NOC_SNOC 1 +#define MASTER_A2NOC_SNOC 2 +#define MASTER_LPASS_ANOC 3 +#define MASTER_SNOC_CFG 4 +#define MASTER_PIMEM 5 +#define MASTER_GIC 6 +#define SLAVE_SNOC_GEM_NOC_GC 7 +#define SLAVE_SNOC_GEM_NOC_SF 8 +#define SLAVE_SERVICE_SNOC 9 + +#endif diff --git a/include/dt-bindings/interrupt-controller/apple-aic.h b/include/dt-bindings/interrupt-controller/apple-aic.h new file mode 100644 index 000000000000..bf3aac0e5491 --- /dev/null +++ b/include/dt-bindings/interrupt-controller/apple-aic.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0+ OR MIT */ +#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_APPLE_AIC_H +#define _DT_BINDINGS_INTERRUPT_CONTROLLER_APPLE_AIC_H + +#include <dt-bindings/interrupt-controller/irq.h> + +#define AIC_IRQ 0 +#define AIC_FIQ 1 + +#define AIC_TMR_HV_PHYS 0 +#define AIC_TMR_HV_VIRT 1 +#define AIC_TMR_GUEST_PHYS 2 +#define AIC_TMR_GUEST_VIRT 3 +#define AIC_CPU_PMU_E 4 +#define AIC_CPU_PMU_P 5 + +#endif diff --git a/include/dt-bindings/interrupt-controller/irqc-rzg2l.h b/include/dt-bindings/interrupt-controller/irqc-rzg2l.h new file mode 100644 index 000000000000..34ce778885a1 --- /dev/null +++ b/include/dt-bindings/interrupt-controller/irqc-rzg2l.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * This header provides constants for Renesas RZ/G2L family IRQC bindings. + * + * Copyright (C) 2022 Renesas Electronics Corp. + * + */ + +#ifndef __DT_BINDINGS_IRQC_RZG2L_H +#define __DT_BINDINGS_IRQC_RZG2L_H + +/* NMI maps to SPI0 */ +#define RZG2L_NMI 0 + +/* IRQ0-7 map to SPI1-8 */ +#define RZG2L_IRQ0 1 +#define RZG2L_IRQ1 2 +#define RZG2L_IRQ2 3 +#define RZG2L_IRQ3 4 +#define RZG2L_IRQ4 5 +#define RZG2L_IRQ5 6 +#define RZG2L_IRQ6 7 +#define RZG2L_IRQ7 8 + +#endif /* __DT_BINDINGS_IRQC_RZG2L_H */ diff --git a/include/dt-bindings/leds/common.h b/include/dt-bindings/leds/common.h index 9e1256a7c1bf..9a0d33d027ff 100644 --- a/include/dt-bindings/leds/common.h +++ b/include/dt-bindings/leds/common.h @@ -6,6 +6,7 @@ * Author: Jacek Anaszewski <j.anaszewski@samsung.com> * * Copyright (C) 2019 Jacek Anaszewski <jacek.anaszewski@gmail.com> + * Copyright (C) 2020 Pavel Machek <pavel@ucw.cz> */ #ifndef __DT_BINDINGS_LEDS_H @@ -29,19 +30,56 @@ #define LED_COLOR_ID_VIOLET 5 #define LED_COLOR_ID_YELLOW 6 #define LED_COLOR_ID_IR 7 -#define LED_COLOR_ID_MAX 8 +#define LED_COLOR_ID_MULTI 8 /* For multicolor LEDs */ +#define LED_COLOR_ID_RGB 9 /* For multicolor LEDs that can do arbitrary color, + so this would include RGBW and similar */ +#define LED_COLOR_ID_PURPLE 10 +#define LED_COLOR_ID_ORANGE 11 +#define LED_COLOR_ID_PINK 12 +#define LED_COLOR_ID_CYAN 13 +#define LED_COLOR_ID_LIME 14 +#define LED_COLOR_ID_MAX 15 /* Standard LED functions */ +/* Keyboard LEDs, usually it would be input4::capslock etc. */ +/* Obsolete equivalent: "shift-key-light" */ +#define LED_FUNCTION_CAPSLOCK "capslock" +#define LED_FUNCTION_SCROLLLOCK "scrolllock" +#define LED_FUNCTION_NUMLOCK "numlock" +/* Obsolete equivalents: "tpacpi::thinklight" (IBM/Lenovo Thinkpads), + "lp5523:kb{1,2,3,4,5,6}" (Nokia N900) */ +#define LED_FUNCTION_KBD_BACKLIGHT "kbd_backlight" + +/* System LEDs, usually found on system body. + platform::mute (etc) is sometimes seen, :mute would be better */ +#define LED_FUNCTION_POWER "power" +#define LED_FUNCTION_DISK "disk" + +/* Obsolete: "platform:*:charging" (allwinner sun50i) */ +#define LED_FUNCTION_CHARGING "charging" +/* Used RGB notification LEDs common on phones. + Obsolete equivalents: "status-led:{red,green,blue}" (Motorola Droid 4), + "lp5523:{r,g,b}" (Nokia N900) */ +#define LED_FUNCTION_STATUS "status" + +#define LED_FUNCTION_MICMUTE "micmute" +#define LED_FUNCTION_MUTE "mute" + +/* Used for player LEDs as found on game controllers from e.g. Nintendo, Sony. */ +#define LED_FUNCTION_PLAYER1 "player-1" +#define LED_FUNCTION_PLAYER2 "player-2" +#define LED_FUNCTION_PLAYER3 "player-3" +#define LED_FUNCTION_PLAYER4 "player-4" +#define LED_FUNCTION_PLAYER5 "player-5" + +/* Miscelleaus functions. Use functions above if you can. */ #define LED_FUNCTION_ACTIVITY "activity" #define LED_FUNCTION_ALARM "alarm" #define LED_FUNCTION_BACKLIGHT "backlight" #define LED_FUNCTION_BLUETOOTH "bluetooth" #define LED_FUNCTION_BOOT "boot" #define LED_FUNCTION_CPU "cpu" -#define LED_FUNCTION_CAPSLOCK "capslock" -#define LED_FUNCTION_CHARGING "charging" #define LED_FUNCTION_DEBUG "debug" -#define LED_FUNCTION_DISK "disk" #define LED_FUNCTION_DISK_ACTIVITY "disk-activity" #define LED_FUNCTION_DISK_ERR "disk-err" #define LED_FUNCTION_DISK_READ "disk-read" @@ -50,21 +88,14 @@ #define LED_FUNCTION_FLASH "flash" #define LED_FUNCTION_HEARTBEAT "heartbeat" #define LED_FUNCTION_INDICATOR "indicator" -#define LED_FUNCTION_KBD_BACKLIGHT "kbd_backlight" #define LED_FUNCTION_LAN "lan" #define LED_FUNCTION_MAIL "mail" #define LED_FUNCTION_MTD "mtd" -#define LED_FUNCTION_MICMUTE "micmute" -#define LED_FUNCTION_MUTE "mute" -#define LED_FUNCTION_NUMLOCK "numlock" #define LED_FUNCTION_PANIC "panic" #define LED_FUNCTION_PROGRAMMING "programming" -#define LED_FUNCTION_POWER "power" #define LED_FUNCTION_RX "rx" #define LED_FUNCTION_SD "sd" -#define LED_FUNCTION_SCROLLLOCK "scrolllock" #define LED_FUNCTION_STANDBY "standby" -#define LED_FUNCTION_STATUS "status" #define LED_FUNCTION_TORCH "torch" #define LED_FUNCTION_TX "tx" #define LED_FUNCTION_USB "usb" diff --git a/include/dt-bindings/leds/rt4831-backlight.h b/include/dt-bindings/leds/rt4831-backlight.h new file mode 100644 index 000000000000..125c6351bba0 --- /dev/null +++ b/include/dt-bindings/leds/rt4831-backlight.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * This header provides constants for rt4831 backlight bindings. + * + * Copyright (C) 2020, Richtek Technology Corp. + * Author: ChiYuan Huang <cy_huang@richtek.com> + */ + +#ifndef _DT_BINDINGS_RT4831_BACKLIGHT_H +#define _DT_BINDINGS_RT4831_BACKLIGHT_H + +#define RT4831_BLOVPLVL_17V 0 +#define RT4831_BLOVPLVL_21V 1 +#define RT4831_BLOVPLVL_25V 2 +#define RT4831_BLOVPLVL_29V 3 + +#define RT4831_BLED_CH1EN (1 << 0) +#define RT4831_BLED_CH2EN (1 << 1) +#define RT4831_BLED_CH3EN (1 << 2) +#define RT4831_BLED_CH4EN (1 << 3) +#define RT4831_BLED_ALLCHEN ((1 << 4) - 1) + +#endif /* _DT_BINDINGS_RT4831_BACKLIGHT_H */ diff --git a/include/dt-bindings/mailbox/qcom-ipcc.h b/include/dt-bindings/mailbox/qcom-ipcc.h new file mode 100644 index 000000000000..fbfa3febc66d --- /dev/null +++ b/include/dt-bindings/mailbox/qcom-ipcc.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ +/* + * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef __DT_BINDINGS_MAILBOX_IPCC_H +#define __DT_BINDINGS_MAILBOX_IPCC_H + +/* Signal IDs for MPROC protocol */ +#define IPCC_MPROC_SIGNAL_GLINK_QMP 0 +#define IPCC_MPROC_SIGNAL_TZ 1 +#define IPCC_MPROC_SIGNAL_SMP2P 2 +#define IPCC_MPROC_SIGNAL_PING 3 + +/* Client IDs */ +#define IPCC_CLIENT_AOP 0 +#define IPCC_CLIENT_TZ 1 +#define IPCC_CLIENT_MPSS 2 +#define IPCC_CLIENT_LPASS 3 +#define IPCC_CLIENT_SLPI 4 +#define IPCC_CLIENT_SDC 5 +#define IPCC_CLIENT_CDSP 6 +#define IPCC_CLIENT_NPU 7 +#define IPCC_CLIENT_APSS 8 +#define IPCC_CLIENT_GPU 9 +#define IPCC_CLIENT_CVP 10 +#define IPCC_CLIENT_CAM 11 +#define IPCC_CLIENT_VPU 12 +#define IPCC_CLIENT_PCIE0 13 +#define IPCC_CLIENT_PCIE1 14 +#define IPCC_CLIENT_PCIE2 15 +#define IPCC_CLIENT_SPSS 16 +#define IPCC_CLIENT_NSP1 18 +#define IPCC_CLIENT_TME 23 +#define IPCC_CLIENT_WPSS 24 + +#endif diff --git a/include/dt-bindings/mailbox/tegra186-hsp.h b/include/dt-bindings/mailbox/tegra186-hsp.h index 3bdec7a84d35..b9ccae2aa9e2 100644 --- a/include/dt-bindings/mailbox/tegra186-hsp.h +++ b/include/dt-bindings/mailbox/tegra186-hsp.h @@ -16,6 +16,11 @@ #define TEGRA_HSP_MBOX_TYPE_AS 0x3 /* + * These define the types of shared mailbox supported based on data size. + */ +#define TEGRA_HSP_MBOX_TYPE_SM_128BIT (1 << 8) + +/* * These defines represent the bit associated with the given master ID in the * doorbell registers. */ diff --git a/include/dt-bindings/media/tvp5150.h b/include/dt-bindings/media/tvp5150.h index 01eedf4985b8..dda00c038530 100644 --- a/include/dt-bindings/media/tvp5150.h +++ b/include/dt-bindings/media/tvp5150.h @@ -14,8 +14,6 @@ #define TVP5150_COMPOSITE1 1 #define TVP5150_SVIDEO 2 -#define TVP5150_INPUT_NUM 3 - /* TVP5150 HW outputs */ #define TVP5150_NORMAL 0 #define TVP5150_BLACK_SCREEN 1 diff --git a/include/dt-bindings/memory/mt2701-larb-port.h b/include/dt-bindings/memory/mt2701-larb-port.h index 2d85c2ec6cfd..25d03526f142 100644 --- a/include/dt-bindings/memory/mt2701-larb-port.h +++ b/include/dt-bindings/memory/mt2701-larb-port.h @@ -4,8 +4,8 @@ * Author: Honghui Zhang <honghui.zhang@mediatek.com> */ -#ifndef _MT2701_LARB_PORT_H_ -#define _MT2701_LARB_PORT_H_ +#ifndef _DT_BINDINGS_MEMORY_MT2701_LARB_PORT_H_ +#define _DT_BINDINGS_MEMORY_MT2701_LARB_PORT_H_ /* * Mediatek m4u generation 1 such as mt2701 has flat m4u port numbers, diff --git a/include/dt-bindings/memory/mt2712-larb-port.h b/include/dt-bindings/memory/mt2712-larb-port.h index 6f9aa7349cef..e41a2841bcff 100644 --- a/include/dt-bindings/memory/mt2712-larb-port.h +++ b/include/dt-bindings/memory/mt2712-larb-port.h @@ -3,10 +3,10 @@ * Copyright (c) 2017 MediaTek Inc. * Author: Yong Wu <yong.wu@mediatek.com> */ -#ifndef __DTS_IOMMU_PORT_MT2712_H -#define __DTS_IOMMU_PORT_MT2712_H +#ifndef _DT_BINDINGS_MEMORY_MT2712_LARB_PORT_H_ +#define _DT_BINDINGS_MEMORY_MT2712_LARB_PORT_H_ -#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port)) +#include <dt-bindings/memory/mtk-memory-port.h> #define M4U_LARB0_ID 0 #define M4U_LARB1_ID 1 diff --git a/include/dt-bindings/memory/mt6779-larb-port.h b/include/dt-bindings/memory/mt6779-larb-port.h new file mode 100644 index 000000000000..3fb438a96e35 --- /dev/null +++ b/include/dt-bindings/memory/mt6779-larb-port.h @@ -0,0 +1,206 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2019 MediaTek Inc. + * Author: Chao Hao <chao.hao@mediatek.com> + */ + +#ifndef _DT_BINDINGS_MEMORY_MT6779_LARB_PORT_H_ +#define _DT_BINDINGS_MEMORY_MT6779_LARB_PORT_H_ + +#include <dt-bindings/memory/mtk-memory-port.h> + +#define M4U_LARB0_ID 0 +#define M4U_LARB1_ID 1 +#define M4U_LARB2_ID 2 +#define M4U_LARB3_ID 3 +#define M4U_LARB4_ID 4 +#define M4U_LARB5_ID 5 +#define M4U_LARB6_ID 6 +#define M4U_LARB7_ID 7 +#define M4U_LARB8_ID 8 +#define M4U_LARB9_ID 9 +#define M4U_LARB10_ID 10 +#define M4U_LARB11_ID 11 + +/* larb0 */ +#define M4U_PORT_DISP_POSTMASK0 MTK_M4U_ID(M4U_LARB0_ID, 0) +#define M4U_PORT_DISP_OVL0_HDR MTK_M4U_ID(M4U_LARB0_ID, 1) +#define M4U_PORT_DISP_OVL1_HDR MTK_M4U_ID(M4U_LARB0_ID, 2) +#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 3) +#define M4U_PORT_DISP_OVL1 MTK_M4U_ID(M4U_LARB0_ID, 4) +#define M4U_PORT_DISP_PVRIC0 MTK_M4U_ID(M4U_LARB0_ID, 5) +#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 6) +#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 7) +#define M4U_PORT_DISP_FAKE0 MTK_M4U_ID(M4U_LARB0_ID, 8) + +/* larb1 */ +#define M4U_PORT_DISP_OVL0_2L_HDR MTK_M4U_ID(M4U_LARB1_ID, 0) +#define M4U_PORT_DISP_OVL1_2L_HDR MTK_M4U_ID(M4U_LARB1_ID, 1) +#define M4U_PORT_DISP_OVL0_2L MTK_M4U_ID(M4U_LARB1_ID, 2) +#define M4U_PORT_DISP_OVL1_2L MTK_M4U_ID(M4U_LARB1_ID, 3) +#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB1_ID, 4) +#define M4U_PORT_MDP_PVRIC0 MTK_M4U_ID(M4U_LARB1_ID, 5) +#define M4U_PORT_MDP_PVRIC1 MTK_M4U_ID(M4U_LARB1_ID, 6) +#define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB1_ID, 7) +#define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(M4U_LARB1_ID, 8) +#define M4U_PORT_MDP_WROT0_R MTK_M4U_ID(M4U_LARB1_ID, 9) +#define M4U_PORT_MDP_WROT0_W MTK_M4U_ID(M4U_LARB1_ID, 10) +#define M4U_PORT_MDP_WROT1_R MTK_M4U_ID(M4U_LARB1_ID, 11) +#define M4U_PORT_MDP_WROT1_W MTK_M4U_ID(M4U_LARB1_ID, 12) +#define M4U_PORT_DISP_FAKE1 MTK_M4U_ID(M4U_LARB1_ID, 13) + +/* larb2-VDEC */ +#define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB2_ID, 0) +#define M4U_PORT_HW_VDEC_UFO_EXT MTK_M4U_ID(M4U_LARB2_ID, 1) +#define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB2_ID, 2) +#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB2_ID, 3) +#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB2_ID, 4) +#define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB2_ID, 5) +#define M4U_PORT_HW_VDEC_TILE_EXT MTK_M4U_ID(M4U_LARB2_ID, 6) +#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB2_ID, 7) +#define M4U_PORT_HW_VDEC_VLD2_EXT MTK_M4U_ID(M4U_LARB2_ID, 8) +#define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB2_ID, 9) +#define M4U_PORT_HW_VDEC_UFO_ENC_EXT MTK_M4U_ID(M4U_LARB2_ID, 10) +#define M4U_PORT_HW_VDEC_RG_CTRL_DMA_EXT MTK_M4U_ID(M4U_LARB2_ID, 11) + +/* larb3-VENC */ +#define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB3_ID, 0) +#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB3_ID, 1) +#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 2) +#define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB3_ID, 3) +#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB3_ID, 4) +#define M4U_PORT_VENC_NBM_RDMA MTK_M4U_ID(M4U_LARB3_ID, 5) +#define M4U_PORT_VENC_NBM_RDMA_LITE MTK_M4U_ID(M4U_LARB3_ID, 6) +#define M4U_PORT_JPGENC_Y_RDMA MTK_M4U_ID(M4U_LARB3_ID, 7) +#define M4U_PORT_JPGENC_C_RDMA MTK_M4U_ID(M4U_LARB3_ID, 8) +#define M4U_PORT_JPGENC_Q_TABLE MTK_M4U_ID(M4U_LARB3_ID, 9) +#define M4U_PORT_JPGENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 10) +#define M4U_PORT_JPGDEC_WDMA MTK_M4U_ID(M4U_LARB3_ID, 11) +#define M4U_PORT_JPGDEC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 12) +#define M4U_PORT_VENC_NBM_WDMA MTK_M4U_ID(M4U_LARB3_ID, 13) +#define M4U_PORT_VENC_NBM_WDMA_LITE MTK_M4U_ID(M4U_LARB3_ID, 14) +#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB3_ID, 15) +#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 16) +#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB3_ID, 17) +#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 18) + +/* larb4-dummy */ + +/* larb5-IMG */ +#define M4U_PORT_IMGI_D1 MTK_M4U_ID(M4U_LARB5_ID, 0) +#define M4U_PORT_IMGBI_D1 MTK_M4U_ID(M4U_LARB5_ID, 1) +#define M4U_PORT_DMGI_D1 MTK_M4U_ID(M4U_LARB5_ID, 2) +#define M4U_PORT_DEPI_D1 MTK_M4U_ID(M4U_LARB5_ID, 3) +#define M4U_PORT_LCEI_D1 MTK_M4U_ID(M4U_LARB5_ID, 4) +#define M4U_PORT_SMTI_D1 MTK_M4U_ID(M4U_LARB5_ID, 5) +#define M4U_PORT_SMTO_D2 MTK_M4U_ID(M4U_LARB5_ID, 6) +#define M4U_PORT_SMTO_D1 MTK_M4U_ID(M4U_LARB5_ID, 7) +#define M4U_PORT_CRZO_D1 MTK_M4U_ID(M4U_LARB5_ID, 8) +#define M4U_PORT_IMG3O_D1 MTK_M4U_ID(M4U_LARB5_ID, 9) +#define M4U_PORT_VIPI_D1 MTK_M4U_ID(M4U_LARB5_ID, 10) +#define M4U_PORT_WPE_RDMA1 MTK_M4U_ID(M4U_LARB5_ID, 11) +#define M4U_PORT_WPE_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 12) +#define M4U_PORT_WPE_WDMA MTK_M4U_ID(M4U_LARB5_ID, 13) +#define M4U_PORT_TIMGO_D1 MTK_M4U_ID(M4U_LARB5_ID, 14) +#define M4U_PORT_MFB_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 15) +#define M4U_PORT_MFB_RDMA1 MTK_M4U_ID(M4U_LARB5_ID, 16) +#define M4U_PORT_MFB_RDMA2 MTK_M4U_ID(M4U_LARB5_ID, 17) +#define M4U_PORT_MFB_RDMA3 MTK_M4U_ID(M4U_LARB5_ID, 18) +#define M4U_PORT_MFB_WDMA MTK_M4U_ID(M4U_LARB5_ID, 19) +#define M4U_PORT_RESERVE1 MTK_M4U_ID(M4U_LARB5_ID, 20) +#define M4U_PORT_RESERVE2 MTK_M4U_ID(M4U_LARB5_ID, 21) +#define M4U_PORT_RESERVE3 MTK_M4U_ID(M4U_LARB5_ID, 22) +#define M4U_PORT_RESERVE4 MTK_M4U_ID(M4U_LARB5_ID, 23) +#define M4U_PORT_RESERVE5 MTK_M4U_ID(M4U_LARB5_ID, 24) +#define M4U_PORT_RESERVE6 MTK_M4U_ID(M4U_LARB5_ID, 25) + +/* larb6-IMG-VPU */ +#define M4U_PORT_IMG_IPUO MTK_M4U_ID(M4U_LARB6_ID, 0) +#define M4U_PORT_IMG_IPU3O MTK_M4U_ID(M4U_LARB6_ID, 1) +#define M4U_PORT_IMG_IPUI MTK_M4U_ID(M4U_LARB6_ID, 2) + +/* larb7-DVS */ +#define M4U_PORT_DVS_RDMA MTK_M4U_ID(M4U_LARB7_ID, 0) +#define M4U_PORT_DVS_WDMA MTK_M4U_ID(M4U_LARB7_ID, 1) +#define M4U_PORT_DVP_RDMA MTK_M4U_ID(M4U_LARB7_ID, 2) +#define M4U_PORT_DVP_WDMA MTK_M4U_ID(M4U_LARB7_ID, 3) + +/* larb8-IPESYS */ +#define M4U_PORT_FDVT_RDA MTK_M4U_ID(M4U_LARB8_ID, 0) +#define M4U_PORT_FDVT_RDB MTK_M4U_ID(M4U_LARB8_ID, 1) +#define M4U_PORT_FDVT_WRA MTK_M4U_ID(M4U_LARB8_ID, 2) +#define M4U_PORT_FDVT_WRB MTK_M4U_ID(M4U_LARB8_ID, 3) +#define M4U_PORT_FE_RD0 MTK_M4U_ID(M4U_LARB8_ID, 4) +#define M4U_PORT_FE_RD1 MTK_M4U_ID(M4U_LARB8_ID, 5) +#define M4U_PORT_FE_WR0 MTK_M4U_ID(M4U_LARB8_ID, 6) +#define M4U_PORT_FE_WR1 MTK_M4U_ID(M4U_LARB8_ID, 7) +#define M4U_PORT_RSC_RDMA0 MTK_M4U_ID(M4U_LARB8_ID, 8) +#define M4U_PORT_RSC_WDMA MTK_M4U_ID(M4U_LARB8_ID, 9) + +/* larb9-CAM */ +#define M4U_PORT_CAM_IMGO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 0) +#define M4U_PORT_CAM_RRZO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 1) +#define M4U_PORT_CAM_LSCI_R1_C MTK_M4U_ID(M4U_LARB9_ID, 2) +#define M4U_PORT_CAM_BPCI_R1_C MTK_M4U_ID(M4U_LARB9_ID, 3) +#define M4U_PORT_CAM_YUVO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 4) +#define M4U_PORT_CAM_UFDI_R2_C MTK_M4U_ID(M4U_LARB9_ID, 5) +#define M4U_PORT_CAM_RAWI_R2_C MTK_M4U_ID(M4U_LARB9_ID, 6) +#define M4U_PORT_CAM_RAWI_R5_C MTK_M4U_ID(M4U_LARB9_ID, 7) +#define M4U_PORT_CAM_CAMSV_1 MTK_M4U_ID(M4U_LARB9_ID, 8) +#define M4U_PORT_CAM_CAMSV_2 MTK_M4U_ID(M4U_LARB9_ID, 9) +#define M4U_PORT_CAM_CAMSV_3 MTK_M4U_ID(M4U_LARB9_ID, 10) +#define M4U_PORT_CAM_CAMSV_4 MTK_M4U_ID(M4U_LARB9_ID, 11) +#define M4U_PORT_CAM_CAMSV_5 MTK_M4U_ID(M4U_LARB9_ID, 12) +#define M4U_PORT_CAM_CAMSV_6 MTK_M4U_ID(M4U_LARB9_ID, 13) +#define M4U_PORT_CAM_AAO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 14) +#define M4U_PORT_CAM_AFO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 15) +#define M4U_PORT_CAM_FLKO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 16) +#define M4U_PORT_CAM_LCESO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 17) +#define M4U_PORT_CAM_CRZO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 18) +#define M4U_PORT_CAM_LTMSO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 19) +#define M4U_PORT_CAM_RSSO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 20) +#define M4U_PORT_CAM_CCUI MTK_M4U_ID(M4U_LARB9_ID, 21) +#define M4U_PORT_CAM_CCUO MTK_M4U_ID(M4U_LARB9_ID, 22) +#define M4U_PORT_CAM_FAKE MTK_M4U_ID(M4U_LARB9_ID, 23) + +/* larb10-CAM_A */ +#define M4U_PORT_CAM_IMGO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 0) +#define M4U_PORT_CAM_RRZO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 1) +#define M4U_PORT_CAM_LSCI_R1_A MTK_M4U_ID(M4U_LARB10_ID, 2) +#define M4U_PORT_CAM_BPCI_R1_A MTK_M4U_ID(M4U_LARB10_ID, 3) +#define M4U_PORT_CAM_YUVO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 4) +#define M4U_PORT_CAM_UFDI_R2_A MTK_M4U_ID(M4U_LARB10_ID, 5) +#define M4U_PORT_CAM_RAWI_R2_A MTK_M4U_ID(M4U_LARB10_ID, 6) +#define M4U_PORT_CAM_RAWI_R5_A MTK_M4U_ID(M4U_LARB10_ID, 7) +#define M4U_PORT_CAM_IMGO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 8) +#define M4U_PORT_CAM_RRZO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 9) +#define M4U_PORT_CAM_LSCI_R1_B MTK_M4U_ID(M4U_LARB10_ID, 10) +#define M4U_PORT_CAM_BPCI_R1_B MTK_M4U_ID(M4U_LARB10_ID, 11) +#define M4U_PORT_CAM_YUVO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 12) +#define M4U_PORT_CAM_UFDI_R2_B MTK_M4U_ID(M4U_LARB10_ID, 13) +#define M4U_PORT_CAM_RAWI_R2_B MTK_M4U_ID(M4U_LARB10_ID, 14) +#define M4U_PORT_CAM_RAWI_R5_B MTK_M4U_ID(M4U_LARB10_ID, 15) +#define M4U_PORT_CAM_CAMSV_0 MTK_M4U_ID(M4U_LARB10_ID, 16) +#define M4U_PORT_CAM_AAO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 17) +#define M4U_PORT_CAM_AFO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 18) +#define M4U_PORT_CAM_FLKO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 19) +#define M4U_PORT_CAM_LCESO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 20) +#define M4U_PORT_CAM_CRZO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 21) +#define M4U_PORT_CAM_AAO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 22) +#define M4U_PORT_CAM_AFO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 23) +#define M4U_PORT_CAM_FLKO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 24) +#define M4U_PORT_CAM_LCESO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 25) +#define M4U_PORT_CAM_CRZO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 26) +#define M4U_PORT_CAM_LTMSO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 27) +#define M4U_PORT_CAM_RSSO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 28) +#define M4U_PORT_CAM_LTMSO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 29) +#define M4U_PORT_CAM_RSSO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 30) + +/* larb11-CAM-VPU */ +#define M4U_PORT_CAM_IPUO MTK_M4U_ID(M4U_LARB11_ID, 0) +#define M4U_PORT_CAM_IPU2O MTK_M4U_ID(M4U_LARB11_ID, 1) +#define M4U_PORT_CAM_IPU3O MTK_M4U_ID(M4U_LARB11_ID, 2) +#define M4U_PORT_CAM_IPUI MTK_M4U_ID(M4U_LARB11_ID, 3) +#define M4U_PORT_CAM_IPU2I MTK_M4U_ID(M4U_LARB11_ID, 4) + +#endif diff --git a/include/dt-bindings/memory/mt6795-larb-port.h b/include/dt-bindings/memory/mt6795-larb-port.h new file mode 100644 index 000000000000..58cf6a6b6372 --- /dev/null +++ b/include/dt-bindings/memory/mt6795-larb-port.h @@ -0,0 +1,95 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022 Collabora Ltd. + * Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> + */ + +#ifndef _DT_BINDINGS_MEMORY_MT6795_LARB_PORT_H_ +#define _DT_BINDINGS_MEMORY_MT6795_LARB_PORT_H_ + +#include <dt-bindings/memory/mtk-memory-port.h> + +#define M4U_LARB0_ID 0 +#define M4U_LARB1_ID 1 +#define M4U_LARB2_ID 2 +#define M4U_LARB3_ID 3 +#define M4U_LARB4_ID 4 + +/* larb0 */ +#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0) +#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 1) +#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 2) +#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 3) +#define M4U_PORT_DISP_OVL1 MTK_M4U_ID(M4U_LARB0_ID, 4) +#define M4U_PORT_DISP_RDMA2 MTK_M4U_ID(M4U_LARB0_ID, 5) +#define M4U_PORT_DISP_WDMA1 MTK_M4U_ID(M4U_LARB0_ID, 6) +#define M4U_PORT_DISP_OD_R MTK_M4U_ID(M4U_LARB0_ID, 7) +#define M4U_PORT_DISP_OD_W MTK_M4U_ID(M4U_LARB0_ID, 8) +#define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 9) +#define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 10) +#define M4U_PORT_MDP_WDMA MTK_M4U_ID(M4U_LARB0_ID, 11) +#define M4U_PORT_MDP_WROT0 MTK_M4U_ID(M4U_LARB0_ID, 12) +#define M4U_PORT_MDP_WROT1 MTK_M4U_ID(M4U_LARB0_ID, 13) + +/* larb1 */ +#define M4U_PORT_VDEC_MC MTK_M4U_ID(M4U_LARB1_ID, 0) +#define M4U_PORT_VDEC_PP MTK_M4U_ID(M4U_LARB1_ID, 1) +#define M4U_PORT_VDEC_UFO MTK_M4U_ID(M4U_LARB1_ID, 2) +#define M4U_PORT_VDEC_VLD MTK_M4U_ID(M4U_LARB1_ID, 3) +#define M4U_PORT_VDEC_VLD2 MTK_M4U_ID(M4U_LARB1_ID, 4) +#define M4U_PORT_VDEC_AVC_MV MTK_M4U_ID(M4U_LARB1_ID, 5) +#define M4U_PORT_VDEC_PRED_RD MTK_M4U_ID(M4U_LARB1_ID, 6) +#define M4U_PORT_VDEC_PRED_WR MTK_M4U_ID(M4U_LARB1_ID, 7) +#define M4U_PORT_VDEC_PPWRAP MTK_M4U_ID(M4U_LARB1_ID, 8) + +/* larb2 */ +#define M4U_PORT_CAM_IMGO MTK_M4U_ID(M4U_LARB2_ID, 0) +#define M4U_PORT_CAM_RRZO MTK_M4U_ID(M4U_LARB2_ID, 1) +#define M4U_PORT_CAM_AAO MTK_M4U_ID(M4U_LARB2_ID, 2) +#define M4U_PORT_CAM_LCSO MTK_M4U_ID(M4U_LARB2_ID, 3) +#define M4U_PORT_CAM_ESFKO MTK_M4U_ID(M4U_LARB2_ID, 4) +#define M4U_PORT_CAM_IMGO_S MTK_M4U_ID(M4U_LARB2_ID, 5) +#define M4U_PORT_CAM_LSCI MTK_M4U_ID(M4U_LARB2_ID, 6) +#define M4U_PORT_CAM_LSCI_D MTK_M4U_ID(M4U_LARB2_ID, 7) +#define M4U_PORT_CAM_BPCI MTK_M4U_ID(M4U_LARB2_ID, 8) +#define M4U_PORT_CAM_BPCI_D MTK_M4U_ID(M4U_LARB2_ID, 9) +#define M4U_PORT_CAM_UFDI MTK_M4U_ID(M4U_LARB2_ID, 10) +#define M4U_PORT_CAM_IMGI MTK_M4U_ID(M4U_LARB2_ID, 11) +#define M4U_PORT_CAM_IMG2O MTK_M4U_ID(M4U_LARB2_ID, 12) +#define M4U_PORT_CAM_IMG3O MTK_M4U_ID(M4U_LARB2_ID, 13) +#define M4U_PORT_CAM_VIPI MTK_M4U_ID(M4U_LARB2_ID, 14) +#define M4U_PORT_CAM_VIP2I MTK_M4U_ID(M4U_LARB2_ID, 15) +#define M4U_PORT_CAM_VIP3I MTK_M4U_ID(M4U_LARB2_ID, 16) +#define M4U_PORT_CAM_LCEI MTK_M4U_ID(M4U_LARB2_ID, 17) +#define M4U_PORT_CAM_RB MTK_M4U_ID(M4U_LARB2_ID, 18) +#define M4U_PORT_CAM_RP MTK_M4U_ID(M4U_LARB2_ID, 19) +#define M4U_PORT_CAM_WR MTK_M4U_ID(M4U_LARB2_ID, 20) + +/* larb3 */ +#define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB3_ID, 0) +#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB3_ID, 1) +#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 2) +#define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB3_ID, 3) +#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB3_ID, 4) +#define M4U_PORT_JPGENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 5) +#define M4U_PORT_REMDC_SDMA MTK_M4U_ID(M4U_LARB3_ID, 6) +#define M4U_PORT_REMDC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 7) +#define M4U_PORT_JPGENC_RDMA MTK_M4U_ID(M4U_LARB3_ID, 8) +#define M4U_PORT_JPGENC_SDMA MTK_M4U_ID(M4U_LARB3_ID, 9) +#define M4U_PORT_JPGDEC_WDMA MTK_M4U_ID(M4U_LARB3_ID, 10) +#define M4U_PORT_JPGDEC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 11) +#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB3_ID, 12) +#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 13) +#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB3_ID, 14) +#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 15) +#define M4U_PORT_REMDC_WDMA MTK_M4U_ID(M4U_LARB3_ID, 16) +#define M4U_PORT_VENC_NBM_RDMA MTK_M4U_ID(M4U_LARB3_ID, 17) +#define M4U_PORT_VENC_NBM_WDMA MTK_M4U_ID(M4U_LARB3_ID, 18) + +/* larb4 */ +#define M4U_PORT_MJC_MV_RD MTK_M4U_ID(M4U_LARB4_ID, 0) +#define M4U_PORT_MJC_MV_WR MTK_M4U_ID(M4U_LARB4_ID, 1) +#define M4U_PORT_MJC_DMA_RD MTK_M4U_ID(M4U_LARB4_ID, 2) +#define M4U_PORT_MJC_DMA_WR MTK_M4U_ID(M4U_LARB4_ID, 3) + +#endif diff --git a/include/dt-bindings/memory/mt8167-larb-port.h b/include/dt-bindings/memory/mt8167-larb-port.h new file mode 100644 index 000000000000..aae57d4824ca --- /dev/null +++ b/include/dt-bindings/memory/mt8167-larb-port.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 MediaTek Inc. + * Copyright (c) 2020 BayLibre, SAS + * Author: Honghui Zhang <honghui.zhang@mediatek.com> + * Author: Fabien Parent <fparent@baylibre.com> + */ +#ifndef _DT_BINDINGS_MEMORY_MT8167_LARB_PORT_H_ +#define _DT_BINDINGS_MEMORY_MT8167_LARB_PORT_H_ + +#include <dt-bindings/memory/mtk-memory-port.h> + +#define M4U_LARB0_ID 0 +#define M4U_LARB1_ID 1 +#define M4U_LARB2_ID 2 + +/* larb0 */ +#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0) +#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 1) +#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 2) +#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 3) +#define M4U_PORT_MDP_RDMA MTK_M4U_ID(M4U_LARB0_ID, 4) +#define M4U_PORT_MDP_WDMA MTK_M4U_ID(M4U_LARB0_ID, 5) +#define M4U_PORT_MDP_WROT MTK_M4U_ID(M4U_LARB0_ID, 6) +#define M4U_PORT_DISP_FAKE MTK_M4U_ID(M4U_LARB0_ID, 7) + +/* larb1*/ +#define M4U_PORT_CAM_IMGO MTK_M4U_ID(M4U_LARB1_ID, 0) +#define M4U_PORT_CAM_IMG2O MTK_M4U_ID(M4U_LARB1_ID, 1) +#define M4U_PORT_CAM_LSCI MTK_M4U_ID(M4U_LARB1_ID, 2) +#define M4U_PORT_CAM_ESFKO MTK_M4U_ID(M4U_LARB1_ID, 3) +#define M4U_PORT_CAM_AAO MTK_M4U_ID(M4U_LARB1_ID, 4) +#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB1_ID, 5) +#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB1_ID, 6) +#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB1_ID, 7) +#define M4U_PORT_CAM_IMGI MTK_M4U_ID(M4U_LARB1_ID, 8) +#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB1_ID, 9) +#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB1_ID, 10) +#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB1_ID, 11) +#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB1_ID, 12) + +/* larb2*/ +#define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB2_ID, 0) +#define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB2_ID, 1) +#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB2_ID, 2) +#define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB2_ID, 3) +#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB2_ID, 4) +#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB2_ID, 5) +#define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB2_ID, 6) + +#endif diff --git a/include/dt-bindings/memory/mt8173-larb-port.h b/include/dt-bindings/memory/mt8173-larb-port.h index 9f31ccfeca21..167a7fc51868 100644 --- a/include/dt-bindings/memory/mt8173-larb-port.h +++ b/include/dt-bindings/memory/mt8173-larb-port.h @@ -3,10 +3,10 @@ * Copyright (c) 2015-2016 MediaTek Inc. * Author: Yong Wu <yong.wu@mediatek.com> */ -#ifndef __DTS_IOMMU_PORT_MT8173_H -#define __DTS_IOMMU_PORT_MT8173_H +#ifndef _DT_BINDINGS_MEMORY_MT8173_LARB_PORT_H_ +#define _DT_BINDINGS_MEMORY_MT8173_LARB_PORT_H_ -#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port)) +#include <dt-bindings/memory/mtk-memory-port.h> #define M4U_LARB0_ID 0 #define M4U_LARB1_ID 1 diff --git a/include/dt-bindings/memory/mt8183-larb-port.h b/include/dt-bindings/memory/mt8183-larb-port.h index 2c579f305162..36abdf0ce5a2 100644 --- a/include/dt-bindings/memory/mt8183-larb-port.h +++ b/include/dt-bindings/memory/mt8183-larb-port.h @@ -3,10 +3,10 @@ * Copyright (c) 2018 MediaTek Inc. * Author: Yong Wu <yong.wu@mediatek.com> */ -#ifndef __DTS_IOMMU_PORT_MT8183_H -#define __DTS_IOMMU_PORT_MT8183_H +#ifndef _DT_BINDINGS_MEMORY_MT8183_LARB_PORT_H_ +#define _DT_BINDINGS_MEMORY_MT8183_LARB_PORT_H_ -#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port)) +#include <dt-bindings/memory/mtk-memory-port.h> #define M4U_LARB0_ID 0 #define M4U_LARB1_ID 1 diff --git a/include/dt-bindings/memory/mt8186-memory-port.h b/include/dt-bindings/memory/mt8186-memory-port.h new file mode 100644 index 000000000000..2bc6e4433048 --- /dev/null +++ b/include/dt-bindings/memory/mt8186-memory-port.h @@ -0,0 +1,217 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022 MediaTek Inc. + * + * Author: Anan Sun <anan.sun@mediatek.com> + * Author: Yong Wu <yong.wu@mediatek.com> + */ +#ifndef _DT_BINDINGS_MEMORY_MT8186_LARB_PORT_H_ +#define _DT_BINDINGS_MEMORY_MT8186_LARB_PORT_H_ + +#include <dt-bindings/memory/mtk-memory-port.h> + +/* + * MM IOMMU supports 16GB dma address. We separate it to four ranges: + * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters + * locate in anyone region. BUT: + * a) Make sure all the ports inside a larb are in one range. + * b) The iova of any master can NOT cross the 4G/8G/12G boundary. + * + * This is the suggested mapping in this SoC: + * + * modules dma-address-region larbs-ports + * disp 0 ~ 4G larb0/1/2 + * vcodec 4G ~ 8G larb4/7 + * cam/mdp 8G ~ 12G the other larbs. + * N/A 12G ~ 16G + * CCU0 0x24000_0000 ~ 0x243ff_ffff larb13: port 9/10 + * CCU1 0x24400_0000 ~ 0x247ff_ffff larb14: port 4/5 + */ + +/* MM IOMMU ports */ +/* LARB 0 -- MMSYS */ +#define IOMMU_PORT_L0_DISP_POSTMASK0 MTK_M4U_ID(0, 0) +#define IOMMU_PORT_L0_REVERSED MTK_M4U_ID(0, 1) +#define IOMMU_PORT_L0_OVL_RDMA0 MTK_M4U_ID(0, 2) +#define IOMMU_PORT_L0_DISP_FAKE0 MTK_M4U_ID(0, 3) + +/* LARB 1 -- MMSYS */ +#define IOMMU_PORT_L1_DISP_RDMA1 MTK_M4U_ID(1, 0) +#define IOMMU_PORT_L1_OVL_2L_RDMA0 MTK_M4U_ID(1, 1) +#define IOMMU_PORT_L1_DISP_RDMA0 MTK_M4U_ID(1, 2) +#define IOMMU_PORT_L1_DISP_WDMA0 MTK_M4U_ID(1, 3) +#define IOMMU_PORT_L1_DISP_FAKE1 MTK_M4U_ID(1, 4) + +/* LARB 2 -- MMSYS */ +#define IOMMU_PORT_L2_MDP_RDMA0 MTK_M4U_ID(2, 0) +#define IOMMU_PORT_L2_MDP_RDMA1 MTK_M4U_ID(2, 1) +#define IOMMU_PORT_L2_MDP_WROT0 MTK_M4U_ID(2, 2) +#define IOMMU_PORT_L2_MDP_WROT1 MTK_M4U_ID(2, 3) +#define IOMMU_PORT_L2_DISP_FAKE0 MTK_M4U_ID(2, 4) + +/* LARB 4 -- VDEC */ +#define IOMMU_PORT_L4_HW_VDEC_MC_EXT MTK_M4U_ID(4, 0) +#define IOMMU_PORT_L4_HW_VDEC_UFO_EXT MTK_M4U_ID(4, 1) +#define IOMMU_PORT_L4_HW_VDEC_PP_EXT MTK_M4U_ID(4, 2) +#define IOMMU_PORT_L4_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(4, 3) +#define IOMMU_PORT_L4_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(4, 4) +#define IOMMU_PORT_L4_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(4, 5) +#define IOMMU_PORT_L4_HW_VDEC_TILE_EXT MTK_M4U_ID(4, 6) +#define IOMMU_PORT_L4_HW_VDEC_VLD_EXT MTK_M4U_ID(4, 7) +#define IOMMU_PORT_L4_HW_VDEC_VLD2_EXT MTK_M4U_ID(4, 8) +#define IOMMU_PORT_L4_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(4, 9) +#define IOMMU_PORT_L4_HW_VDEC_UFO_ENC_EXT MTK_M4U_ID(4, 10) +#define IOMMU_PORT_L4_HW_VDEC_RG_CTRL_DMA_EXT MTK_M4U_ID(4, 11) +#define IOMMU_PORT_L4_HW_MINI_MDP_R0_EXT MTK_M4U_ID(4, 12) +#define IOMMU_PORT_L4_HW_MINI_MDP_W0_EXT MTK_M4U_ID(4, 13) + +/* LARB 7 -- VENC */ +#define IOMMU_PORT_L7_VENC_RCPU MTK_M4U_ID(7, 0) +#define IOMMU_PORT_L7_VENC_REC MTK_M4U_ID(7, 1) +#define IOMMU_PORT_L7_VENC_BSDMA MTK_M4U_ID(7, 2) +#define IOMMU_PORT_L7_VENC_SV_COMV MTK_M4U_ID(7, 3) +#define IOMMU_PORT_L7_VENC_RD_COMV MTK_M4U_ID(7, 4) +#define IOMMU_PORT_L7_VENC_CUR_LUMA MTK_M4U_ID(7, 5) +#define IOMMU_PORT_L7_VENC_CUR_CHROMA MTK_M4U_ID(7, 6) +#define IOMMU_PORT_L7_VENC_REF_LUMA MTK_M4U_ID(7, 7) +#define IOMMU_PORT_L7_VENC_REF_CHROMA MTK_M4U_ID(7, 8) +#define IOMMU_PORT_L7_JPGENC_Y_RDMA MTK_M4U_ID(7, 9) +#define IOMMU_PORT_L7_JPGENC_C_RDMA MTK_M4U_ID(7, 10) +#define IOMMU_PORT_L7_JPGENC_Q_TABLE MTK_M4U_ID(7, 11) +#define IOMMU_PORT_L7_JPGENC_BSDMA MTK_M4U_ID(7, 12) + +/* LARB 8 -- WPE */ +#define IOMMU_PORT_L8_WPE_RDMA_0 MTK_M4U_ID(8, 0) +#define IOMMU_PORT_L8_WPE_RDMA_1 MTK_M4U_ID(8, 1) +#define IOMMU_PORT_L8_WPE_WDMA_0 MTK_M4U_ID(8, 2) + +/* LARB 9 -- IMG-1 */ +#define IOMMU_PORT_L9_IMG_IMGI_D1 MTK_M4U_ID(9, 0) +#define IOMMU_PORT_L9_IMG_IMGBI_D1 MTK_M4U_ID(9, 1) +#define IOMMU_PORT_L9_IMG_DMGI_D1 MTK_M4U_ID(9, 2) +#define IOMMU_PORT_L9_IMG_DEPI_D1 MTK_M4U_ID(9, 3) +#define IOMMU_PORT_L9_IMG_LCE_D1 MTK_M4U_ID(9, 4) +#define IOMMU_PORT_L9_IMG_SMTI_D1 MTK_M4U_ID(9, 5) +#define IOMMU_PORT_L9_IMG_SMTO_D2 MTK_M4U_ID(9, 6) +#define IOMMU_PORT_L9_IMG_SMTO_D1 MTK_M4U_ID(9, 7) +#define IOMMU_PORT_L9_IMG_CRZO_D1 MTK_M4U_ID(9, 8) +#define IOMMU_PORT_L9_IMG_IMG3O_D1 MTK_M4U_ID(9, 9) +#define IOMMU_PORT_L9_IMG_VIPI_D1 MTK_M4U_ID(9, 10) +#define IOMMU_PORT_L9_IMG_SMTI_D5 MTK_M4U_ID(9, 11) +#define IOMMU_PORT_L9_IMG_TIMGO_D1 MTK_M4U_ID(9, 12) +#define IOMMU_PORT_L9_IMG_UFBC_W0 MTK_M4U_ID(9, 13) +#define IOMMU_PORT_L9_IMG_UFBC_R0 MTK_M4U_ID(9, 14) +#define IOMMU_PORT_L9_IMG_WPE_RDMA1 MTK_M4U_ID(9, 15) +#define IOMMU_PORT_L9_IMG_WPE_RDMA0 MTK_M4U_ID(9, 16) +#define IOMMU_PORT_L9_IMG_WPE_WDMA MTK_M4U_ID(9, 17) +#define IOMMU_PORT_L9_IMG_MFB_RDMA0 MTK_M4U_ID(9, 18) +#define IOMMU_PORT_L9_IMG_MFB_RDMA1 MTK_M4U_ID(9, 19) +#define IOMMU_PORT_L9_IMG_MFB_RDMA2 MTK_M4U_ID(9, 20) +#define IOMMU_PORT_L9_IMG_MFB_RDMA3 MTK_M4U_ID(9, 21) +#define IOMMU_PORT_L9_IMG_MFB_RDMA4 MTK_M4U_ID(9, 22) +#define IOMMU_PORT_L9_IMG_MFB_RDMA5 MTK_M4U_ID(9, 23) +#define IOMMU_PORT_L9_IMG_MFB_WDMA0 MTK_M4U_ID(9, 24) +#define IOMMU_PORT_L9_IMG_MFB_WDMA1 MTK_M4U_ID(9, 25) +#define IOMMU_PORT_L9_IMG_RESERVE6 MTK_M4U_ID(9, 26) +#define IOMMU_PORT_L9_IMG_RESERVE7 MTK_M4U_ID(9, 27) +#define IOMMU_PORT_L9_IMG_RESERVE8 MTK_M4U_ID(9, 28) + +/* LARB 11 -- IMG-2 */ +#define IOMMU_PORT_L11_IMG_IMGI_D1 MTK_M4U_ID(11, 0) +#define IOMMU_PORT_L11_IMG_IMGBI_D1 MTK_M4U_ID(11, 1) +#define IOMMU_PORT_L11_IMG_DMGI_D1 MTK_M4U_ID(11, 2) +#define IOMMU_PORT_L11_IMG_DEPI_D1 MTK_M4U_ID(11, 3) +#define IOMMU_PORT_L11_IMG_LCE_D1 MTK_M4U_ID(11, 4) +#define IOMMU_PORT_L11_IMG_SMTI_D1 MTK_M4U_ID(11, 5) +#define IOMMU_PORT_L11_IMG_SMTO_D2 MTK_M4U_ID(11, 6) +#define IOMMU_PORT_L11_IMG_SMTO_D1 MTK_M4U_ID(11, 7) +#define IOMMU_PORT_L11_IMG_CRZO_D1 MTK_M4U_ID(11, 8) +#define IOMMU_PORT_L11_IMG_IMG3O_D1 MTK_M4U_ID(11, 9) +#define IOMMU_PORT_L11_IMG_VIPI_D1 MTK_M4U_ID(11, 10) +#define IOMMU_PORT_L11_IMG_SMTI_D5 MTK_M4U_ID(11, 11) +#define IOMMU_PORT_L11_IMG_TIMGO_D1 MTK_M4U_ID(11, 12) +#define IOMMU_PORT_L11_IMG_UFBC_W0 MTK_M4U_ID(11, 13) +#define IOMMU_PORT_L11_IMG_UFBC_R0 MTK_M4U_ID(11, 14) +#define IOMMU_PORT_L11_IMG_WPE_RDMA1 MTK_M4U_ID(11, 15) +#define IOMMU_PORT_L11_IMG_WPE_RDMA0 MTK_M4U_ID(11, 16) +#define IOMMU_PORT_L11_IMG_WPE_WDMA MTK_M4U_ID(11, 17) +#define IOMMU_PORT_L11_IMG_MFB_RDMA0 MTK_M4U_ID(11, 18) +#define IOMMU_PORT_L11_IMG_MFB_RDMA1 MTK_M4U_ID(11, 19) +#define IOMMU_PORT_L11_IMG_MFB_RDMA2 MTK_M4U_ID(11, 20) +#define IOMMU_PORT_L11_IMG_MFB_RDMA3 MTK_M4U_ID(11, 21) +#define IOMMU_PORT_L11_IMG_MFB_RDMA4 MTK_M4U_ID(11, 22) +#define IOMMU_PORT_L11_IMG_MFB_RDMA5 MTK_M4U_ID(11, 23) +#define IOMMU_PORT_L11_IMG_MFB_WDMA0 MTK_M4U_ID(11, 24) +#define IOMMU_PORT_L11_IMG_MFB_WDMA1 MTK_M4U_ID(11, 25) +#define IOMMU_PORT_L11_IMG_RESERVE6 MTK_M4U_ID(11, 26) +#define IOMMU_PORT_L11_IMG_RESERVE7 MTK_M4U_ID(11, 27) +#define IOMMU_PORT_L11_IMG_RESERVE8 MTK_M4U_ID(11, 28) + +/* LARB 13 -- CAM */ +#define IOMMU_PORT_L13_CAM_MRAWI MTK_M4U_ID(13, 0) +#define IOMMU_PORT_L13_CAM_MRAWO_0 MTK_M4U_ID(13, 1) +#define IOMMU_PORT_L13_CAM_MRAWO_1 MTK_M4U_ID(13, 2) +#define IOMMU_PORT_L13_CAM_CAMSV_4 MTK_M4U_ID(13, 6) +#define IOMMU_PORT_L13_CAM_CAMSV_5 MTK_M4U_ID(13, 7) +#define IOMMU_PORT_L13_CAM_CAMSV_6 MTK_M4U_ID(13, 8) +#define IOMMU_PORT_L13_CAM_CCUI MTK_M4U_ID(13, 9) +#define IOMMU_PORT_L13_CAM_CCUO MTK_M4U_ID(13, 10) +#define IOMMU_PORT_L13_CAM_FAKE MTK_M4U_ID(13, 11) + +/* LARB 14 -- CAM */ +#define IOMMU_PORT_L14_CAM_CCUI MTK_M4U_ID(14, 4) +#define IOMMU_PORT_L14_CAM_CCUO MTK_M4U_ID(14, 5) + +/* LARB 16 -- RAW-A */ +#define IOMMU_PORT_L16_CAM_IMGO_R1_A MTK_M4U_ID(16, 0) +#define IOMMU_PORT_L16_CAM_RRZO_R1_A MTK_M4U_ID(16, 1) +#define IOMMU_PORT_L16_CAM_CQI_R1_A MTK_M4U_ID(16, 2) +#define IOMMU_PORT_L16_CAM_BPCI_R1_A MTK_M4U_ID(16, 3) +#define IOMMU_PORT_L16_CAM_YUVO_R1_A MTK_M4U_ID(16, 4) +#define IOMMU_PORT_L16_CAM_UFDI_R2_A MTK_M4U_ID(16, 5) +#define IOMMU_PORT_L16_CAM_RAWI_R2_A MTK_M4U_ID(16, 6) +#define IOMMU_PORT_L16_CAM_RAWI_R3_A MTK_M4U_ID(16, 7) +#define IOMMU_PORT_L16_CAM_AAO_R1_A MTK_M4U_ID(16, 8) +#define IOMMU_PORT_L16_CAM_AFO_R1_A MTK_M4U_ID(16, 9) +#define IOMMU_PORT_L16_CAM_FLKO_R1_A MTK_M4U_ID(16, 10) +#define IOMMU_PORT_L16_CAM_LCESO_R1_A MTK_M4U_ID(16, 11) +#define IOMMU_PORT_L16_CAM_CRZO_R1_A MTK_M4U_ID(16, 12) +#define IOMMU_PORT_L16_CAM_LTMSO_R1_A MTK_M4U_ID(16, 13) +#define IOMMU_PORT_L16_CAM_RSSO_R1_A MTK_M4U_ID(16, 14) +#define IOMMU_PORT_L16_CAM_AAHO_R1_A MTK_M4U_ID(16, 15) +#define IOMMU_PORT_L16_CAM_LSCI_R1_A MTK_M4U_ID(16, 16) + +/* LARB 17 -- RAW-B */ +#define IOMMU_PORT_L17_CAM_IMGO_R1_B MTK_M4U_ID(17, 0) +#define IOMMU_PORT_L17_CAM_RRZO_R1_B MTK_M4U_ID(17, 1) +#define IOMMU_PORT_L17_CAM_CQI_R1_B MTK_M4U_ID(17, 2) +#define IOMMU_PORT_L17_CAM_BPCI_R1_B MTK_M4U_ID(17, 3) +#define IOMMU_PORT_L17_CAM_YUVO_R1_B MTK_M4U_ID(17, 4) +#define IOMMU_PORT_L17_CAM_UFDI_R2_B MTK_M4U_ID(17, 5) +#define IOMMU_PORT_L17_CAM_RAWI_R2_B MTK_M4U_ID(17, 6) +#define IOMMU_PORT_L17_CAM_RAWI_R3_B MTK_M4U_ID(17, 7) +#define IOMMU_PORT_L17_CAM_AAO_R1_B MTK_M4U_ID(17, 8) +#define IOMMU_PORT_L17_CAM_AFO_R1_B MTK_M4U_ID(17, 9) +#define IOMMU_PORT_L17_CAM_FLKO_R1_B MTK_M4U_ID(17, 10) +#define IOMMU_PORT_L17_CAM_LCESO_R1_B MTK_M4U_ID(17, 11) +#define IOMMU_PORT_L17_CAM_CRZO_R1_B MTK_M4U_ID(17, 12) +#define IOMMU_PORT_L17_CAM_LTMSO_R1_B MTK_M4U_ID(17, 13) +#define IOMMU_PORT_L17_CAM_RSSO_R1_B MTK_M4U_ID(17, 14) +#define IOMMU_PORT_L17_CAM_AAHO_R1_B MTK_M4U_ID(17, 15) +#define IOMMU_PORT_L17_CAM_LSCI_R1_B MTK_M4U_ID(17, 16) + +/* LARB 19 -- IPE */ +#define IOMMU_PORT_L19_IPE_DVS_RDMA MTK_M4U_ID(19, 0) +#define IOMMU_PORT_L19_IPE_DVS_WDMA MTK_M4U_ID(19, 1) +#define IOMMU_PORT_L19_IPE_DVP_RDMA MTK_M4U_ID(19, 2) +#define IOMMU_PORT_L19_IPE_DVP_WDMA MTK_M4U_ID(19, 3) + +/* LARB 20 -- IPE */ +#define IOMMU_PORT_L20_IPE_FDVT_RDA MTK_M4U_ID(20, 0) +#define IOMMU_PORT_L20_IPE_FDVT_RDB MTK_M4U_ID(20, 1) +#define IOMMU_PORT_L20_IPE_FDVT_WRA MTK_M4U_ID(20, 2) +#define IOMMU_PORT_L20_IPE_FDVT_WRB MTK_M4U_ID(20, 3) +#define IOMMU_PORT_L20_IPE_RSC_RDMA0 MTK_M4U_ID(20, 4) +#define IOMMU_PORT_L20_IPE_RSC_WDMA MTK_M4U_ID(20, 5) + +#endif diff --git a/include/dt-bindings/memory/mt8192-larb-port.h b/include/dt-bindings/memory/mt8192-larb-port.h new file mode 100644 index 000000000000..23035a52c675 --- /dev/null +++ b/include/dt-bindings/memory/mt8192-larb-port.h @@ -0,0 +1,243 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020 MediaTek Inc. + * + * Author: Chao Hao <chao.hao@mediatek.com> + * Author: Yong Wu <yong.wu@mediatek.com> + */ +#ifndef _DT_BINDINGS_MEMORY_MT8192_LARB_PORT_H_ +#define _DT_BINDINGS_MEMORY_MT8192_LARB_PORT_H_ + +#include <dt-bindings/memory/mtk-memory-port.h> + +/* + * MM IOMMU supports 16GB dma address. + * + * The address will preassign like this: + * + * modules dma-address-region larbs-ports + * disp 0 ~ 4G larb0/1 + * vcodec 4G ~ 8G larb4/5/7 + * cam/mdp 8G ~ 12G larb2/9/11/13/14/16/17/18/19/20 + * CCU0 0x4000_0000 ~ 0x43ff_ffff larb13: port 9/10 + * CCU1 0x4400_0000 ~ 0x47ff_ffff larb14: port 4/5 + * + * larb3/6/8/10/12/15 is null. + */ + +/* larb0 */ +#define M4U_PORT_L0_DISP_POSTMASK0 MTK_M4U_ID(0, 0) +#define M4U_PORT_L0_OVL_RDMA0_HDR MTK_M4U_ID(0, 1) +#define M4U_PORT_L0_OVL_RDMA0 MTK_M4U_ID(0, 2) +#define M4U_PORT_L0_DISP_RDMA0 MTK_M4U_ID(0, 3) +#define M4U_PORT_L0_DISP_WDMA0 MTK_M4U_ID(0, 4) +#define M4U_PORT_L0_DISP_FAKE0 MTK_M4U_ID(0, 5) + +/* larb1 */ +#define M4U_PORT_L1_OVL_2L_RDMA0_HDR MTK_M4U_ID(1, 0) +#define M4U_PORT_L1_OVL_2L_RDMA2_HDR MTK_M4U_ID(1, 1) +#define M4U_PORT_L1_OVL_2L_RDMA0 MTK_M4U_ID(1, 2) +#define M4U_PORT_L1_OVL_2L_RDMA2 MTK_M4U_ID(1, 3) +#define M4U_PORT_L1_DISP_MDP_RDMA4 MTK_M4U_ID(1, 4) +#define M4U_PORT_L1_DISP_RDMA4 MTK_M4U_ID(1, 5) +#define M4U_PORT_L1_DISP_UFBC_WDMA0 MTK_M4U_ID(1, 6) +#define M4U_PORT_L1_DISP_FAKE1 MTK_M4U_ID(1, 7) + +/* larb2 */ +#define M4U_PORT_L2_MDP_RDMA0 MTK_M4U_ID(2, 0) +#define M4U_PORT_L2_MDP_RDMA1 MTK_M4U_ID(2, 1) +#define M4U_PORT_L2_MDP_WROT0 MTK_M4U_ID(2, 2) +#define M4U_PORT_L2_MDP_WROT1 MTK_M4U_ID(2, 3) +#define M4U_PORT_L2_MDP_DISP_FAKE0 MTK_M4U_ID(2, 4) + +/* larb3: null */ + +/* larb4 */ +#define M4U_PORT_L4_VDEC_MC_EXT MTK_M4U_ID(4, 0) +#define M4U_PORT_L4_VDEC_UFO_EXT MTK_M4U_ID(4, 1) +#define M4U_PORT_L4_VDEC_PP_EXT MTK_M4U_ID(4, 2) +#define M4U_PORT_L4_VDEC_PRED_RD_EXT MTK_M4U_ID(4, 3) +#define M4U_PORT_L4_VDEC_PRED_WR_EXT MTK_M4U_ID(4, 4) +#define M4U_PORT_L4_VDEC_PPWRAP_EXT MTK_M4U_ID(4, 5) +#define M4U_PORT_L4_VDEC_TILE_EXT MTK_M4U_ID(4, 6) +#define M4U_PORT_L4_VDEC_VLD_EXT MTK_M4U_ID(4, 7) +#define M4U_PORT_L4_VDEC_VLD2_EXT MTK_M4U_ID(4, 8) +#define M4U_PORT_L4_VDEC_AVC_MV_EXT MTK_M4U_ID(4, 9) +#define M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT MTK_M4U_ID(4, 10) + +/* larb5 */ +#define M4U_PORT_L5_VDEC_LAT0_VLD_EXT MTK_M4U_ID(5, 0) +#define M4U_PORT_L5_VDEC_LAT0_VLD2_EXT MTK_M4U_ID(5, 1) +#define M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT MTK_M4U_ID(5, 2) +#define M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT MTK_M4U_ID(5, 3) +#define M4U_PORT_L5_VDEC_LAT0_TILE_EXT MTK_M4U_ID(5, 4) +#define M4U_PORT_L5_VDEC_LAT0_WDMA_EXT MTK_M4U_ID(5, 5) +#define M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT MTK_M4U_ID(5, 6) +#define M4U_PORT_L5_VDEC_UFO_ENC_EXT MTK_M4U_ID(5, 7) + +/* larb6: null */ + +/* larb7 */ +#define M4U_PORT_L7_VENC_RCPU MTK_M4U_ID(7, 0) +#define M4U_PORT_L7_VENC_REC MTK_M4U_ID(7, 1) +#define M4U_PORT_L7_VENC_BSDMA MTK_M4U_ID(7, 2) +#define M4U_PORT_L7_VENC_SV_COMV MTK_M4U_ID(7, 3) +#define M4U_PORT_L7_VENC_RD_COMV MTK_M4U_ID(7, 4) +#define M4U_PORT_L7_VENC_CUR_LUMA MTK_M4U_ID(7, 5) +#define M4U_PORT_L7_VENC_CUR_CHROMA MTK_M4U_ID(7, 6) +#define M4U_PORT_L7_VENC_REF_LUMA MTK_M4U_ID(7, 7) +#define M4U_PORT_L7_VENC_REF_CHROMA MTK_M4U_ID(7, 8) +#define M4U_PORT_L7_JPGENC_Y_RDMA MTK_M4U_ID(7, 9) +#define M4U_PORT_L7_JPGENC_Q_RDMA MTK_M4U_ID(7, 10) +#define M4U_PORT_L7_JPGENC_C_TABLE MTK_M4U_ID(7, 11) +#define M4U_PORT_L7_JPGENC_BSDMA MTK_M4U_ID(7, 12) +#define M4U_PORT_L7_VENC_SUB_R_LUMA MTK_M4U_ID(7, 13) +#define M4U_PORT_L7_VENC_SUB_W_LUMA MTK_M4U_ID(7, 14) + +/* larb8: null */ + +/* larb9 */ +#define M4U_PORT_L9_IMG_IMGI_D1 MTK_M4U_ID(9, 0) +#define M4U_PORT_L9_IMG_IMGBI_D1 MTK_M4U_ID(9, 1) +#define M4U_PORT_L9_IMG_DMGI_D1 MTK_M4U_ID(9, 2) +#define M4U_PORT_L9_IMG_DEPI_D1 MTK_M4U_ID(9, 3) +#define M4U_PORT_L9_IMG_ICE_D1 MTK_M4U_ID(9, 4) +#define M4U_PORT_L9_IMG_SMTI_D1 MTK_M4U_ID(9, 5) +#define M4U_PORT_L9_IMG_SMTO_D2 MTK_M4U_ID(9, 6) +#define M4U_PORT_L9_IMG_SMTO_D1 MTK_M4U_ID(9, 7) +#define M4U_PORT_L9_IMG_CRZO_D1 MTK_M4U_ID(9, 8) +#define M4U_PORT_L9_IMG_IMG3O_D1 MTK_M4U_ID(9, 9) +#define M4U_PORT_L9_IMG_VIPI_D1 MTK_M4U_ID(9, 10) +#define M4U_PORT_L9_IMG_SMTI_D5 MTK_M4U_ID(9, 11) +#define M4U_PORT_L9_IMG_TIMGO_D1 MTK_M4U_ID(9, 12) +#define M4U_PORT_L9_IMG_UFBC_W0 MTK_M4U_ID(9, 13) +#define M4U_PORT_L9_IMG_UFBC_R0 MTK_M4U_ID(9, 14) + +/* larb10: null */ + +/* larb11 */ +#define M4U_PORT_L11_IMG_IMGI_D1 MTK_M4U_ID(11, 0) +#define M4U_PORT_L11_IMG_IMGBI_D1 MTK_M4U_ID(11, 1) +#define M4U_PORT_L11_IMG_DMGI_D1 MTK_M4U_ID(11, 2) +#define M4U_PORT_L11_IMG_DEPI_D1 MTK_M4U_ID(11, 3) +#define M4U_PORT_L11_IMG_ICE_D1 MTK_M4U_ID(11, 4) +#define M4U_PORT_L11_IMG_SMTI_D1 MTK_M4U_ID(11, 5) +#define M4U_PORT_L11_IMG_SMTO_D2 MTK_M4U_ID(11, 6) +#define M4U_PORT_L11_IMG_SMTO_D1 MTK_M4U_ID(11, 7) +#define M4U_PORT_L11_IMG_CRZO_D1 MTK_M4U_ID(11, 8) +#define M4U_PORT_L11_IMG_IMG3O_D1 MTK_M4U_ID(11, 9) +#define M4U_PORT_L11_IMG_VIPI_D1 MTK_M4U_ID(11, 10) +#define M4U_PORT_L11_IMG_SMTI_D5 MTK_M4U_ID(11, 11) +#define M4U_PORT_L11_IMG_TIMGO_D1 MTK_M4U_ID(11, 12) +#define M4U_PORT_L11_IMG_UFBC_W0 MTK_M4U_ID(11, 13) +#define M4U_PORT_L11_IMG_UFBC_R0 MTK_M4U_ID(11, 14) +#define M4U_PORT_L11_IMG_WPE_RDMA1 MTK_M4U_ID(11, 15) +#define M4U_PORT_L11_IMG_WPE_RDMA0 MTK_M4U_ID(11, 16) +#define M4U_PORT_L11_IMG_WPE_WDMA MTK_M4U_ID(11, 17) +#define M4U_PORT_L11_IMG_MFB_RDMA0 MTK_M4U_ID(11, 18) +#define M4U_PORT_L11_IMG_MFB_RDMA1 MTK_M4U_ID(11, 19) +#define M4U_PORT_L11_IMG_MFB_RDMA2 MTK_M4U_ID(11, 20) +#define M4U_PORT_L11_IMG_MFB_RDMA3 MTK_M4U_ID(11, 21) +#define M4U_PORT_L11_IMG_MFB_RDMA4 MTK_M4U_ID(11, 22) +#define M4U_PORT_L11_IMG_MFB_RDMA5 MTK_M4U_ID(11, 23) +#define M4U_PORT_L11_IMG_MFB_WDMA0 MTK_M4U_ID(11, 24) +#define M4U_PORT_L11_IMG_MFB_WDMA1 MTK_M4U_ID(11, 25) + +/* larb12: null */ + +/* larb13 */ +#define M4U_PORT_L13_CAM_MRAWI MTK_M4U_ID(13, 0) +#define M4U_PORT_L13_CAM_MRAWO0 MTK_M4U_ID(13, 1) +#define M4U_PORT_L13_CAM_MRAWO1 MTK_M4U_ID(13, 2) +#define M4U_PORT_L13_CAM_CAMSV1 MTK_M4U_ID(13, 3) +#define M4U_PORT_L13_CAM_CAMSV2 MTK_M4U_ID(13, 4) +#define M4U_PORT_L13_CAM_CAMSV3 MTK_M4U_ID(13, 5) +#define M4U_PORT_L13_CAM_CAMSV4 MTK_M4U_ID(13, 6) +#define M4U_PORT_L13_CAM_CAMSV5 MTK_M4U_ID(13, 7) +#define M4U_PORT_L13_CAM_CAMSV6 MTK_M4U_ID(13, 8) +#define M4U_PORT_L13_CAM_CCUI MTK_M4U_ID(13, 9) +#define M4U_PORT_L13_CAM_CCUO MTK_M4U_ID(13, 10) +#define M4U_PORT_L13_CAM_FAKE MTK_M4U_ID(13, 11) + +/* larb14 */ +#define M4U_PORT_L14_CAM_RESERVE1 MTK_M4U_ID(14, 0) +#define M4U_PORT_L14_CAM_RESERVE2 MTK_M4U_ID(14, 1) +#define M4U_PORT_L14_CAM_RESERVE3 MTK_M4U_ID(14, 2) +#define M4U_PORT_L14_CAM_CAMSV0 MTK_M4U_ID(14, 3) +#define M4U_PORT_L14_CAM_CCUI MTK_M4U_ID(14, 4) +#define M4U_PORT_L14_CAM_CCUO MTK_M4U_ID(14, 5) + +/* larb15: null */ + +/* larb16 */ +#define M4U_PORT_L16_CAM_IMGO_R1_A MTK_M4U_ID(16, 0) +#define M4U_PORT_L16_CAM_RRZO_R1_A MTK_M4U_ID(16, 1) +#define M4U_PORT_L16_CAM_CQI_R1_A MTK_M4U_ID(16, 2) +#define M4U_PORT_L16_CAM_BPCI_R1_A MTK_M4U_ID(16, 3) +#define M4U_PORT_L16_CAM_YUVO_R1_A MTK_M4U_ID(16, 4) +#define M4U_PORT_L16_CAM_UFDI_R2_A MTK_M4U_ID(16, 5) +#define M4U_PORT_L16_CAM_RAWI_R2_A MTK_M4U_ID(16, 6) +#define M4U_PORT_L16_CAM_RAWI_R3_A MTK_M4U_ID(16, 7) +#define M4U_PORT_L16_CAM_AAO_R1_A MTK_M4U_ID(16, 8) +#define M4U_PORT_L16_CAM_AFO_R1_A MTK_M4U_ID(16, 9) +#define M4U_PORT_L16_CAM_FLKO_R1_A MTK_M4U_ID(16, 10) +#define M4U_PORT_L16_CAM_LCESO_R1_A MTK_M4U_ID(16, 11) +#define M4U_PORT_L16_CAM_CRZO_R1_A MTK_M4U_ID(16, 12) +#define M4U_PORT_L16_CAM_LTMSO_R1_A MTK_M4U_ID(16, 13) +#define M4U_PORT_L16_CAM_RSSO_R1_A MTK_M4U_ID(16, 14) +#define M4U_PORT_L16_CAM_AAHO_R1_A MTK_M4U_ID(16, 15) +#define M4U_PORT_L16_CAM_LSCI_R1_A MTK_M4U_ID(16, 16) + +/* larb17 */ +#define M4U_PORT_L17_CAM_IMGO_R1_B MTK_M4U_ID(17, 0) +#define M4U_PORT_L17_CAM_RRZO_R1_B MTK_M4U_ID(17, 1) +#define M4U_PORT_L17_CAM_CQI_R1_B MTK_M4U_ID(17, 2) +#define M4U_PORT_L17_CAM_BPCI_R1_B MTK_M4U_ID(17, 3) +#define M4U_PORT_L17_CAM_YUVO_R1_B MTK_M4U_ID(17, 4) +#define M4U_PORT_L17_CAM_UFDI_R2_B MTK_M4U_ID(17, 5) +#define M4U_PORT_L17_CAM_RAWI_R2_B MTK_M4U_ID(17, 6) +#define M4U_PORT_L17_CAM_RAWI_R3_B MTK_M4U_ID(17, 7) +#define M4U_PORT_L17_CAM_AAO_R1_B MTK_M4U_ID(17, 8) +#define M4U_PORT_L17_CAM_AFO_R1_B MTK_M4U_ID(17, 9) +#define M4U_PORT_L17_CAM_FLKO_R1_B MTK_M4U_ID(17, 10) +#define M4U_PORT_L17_CAM_LCESO_R1_B MTK_M4U_ID(17, 11) +#define M4U_PORT_L17_CAM_CRZO_R1_B MTK_M4U_ID(17, 12) +#define M4U_PORT_L17_CAM_LTMSO_R1_B MTK_M4U_ID(17, 13) +#define M4U_PORT_L17_CAM_RSSO_R1_B MTK_M4U_ID(17, 14) +#define M4U_PORT_L17_CAM_AAHO_R1_B MTK_M4U_ID(17, 15) +#define M4U_PORT_L17_CAM_LSCI_R1_B MTK_M4U_ID(17, 16) + +/* larb18 */ +#define M4U_PORT_L18_CAM_IMGO_R1_C MTK_M4U_ID(18, 0) +#define M4U_PORT_L18_CAM_RRZO_R1_C MTK_M4U_ID(18, 1) +#define M4U_PORT_L18_CAM_CQI_R1_C MTK_M4U_ID(18, 2) +#define M4U_PORT_L18_CAM_BPCI_R1_C MTK_M4U_ID(18, 3) +#define M4U_PORT_L18_CAM_YUVO_R1_C MTK_M4U_ID(18, 4) +#define M4U_PORT_L18_CAM_UFDI_R2_C MTK_M4U_ID(18, 5) +#define M4U_PORT_L18_CAM_RAWI_R2_C MTK_M4U_ID(18, 6) +#define M4U_PORT_L18_CAM_RAWI_R3_C MTK_M4U_ID(18, 7) +#define M4U_PORT_L18_CAM_AAO_R1_C MTK_M4U_ID(18, 8) +#define M4U_PORT_L18_CAM_AFO_R1_C MTK_M4U_ID(18, 9) +#define M4U_PORT_L18_CAM_FLKO_R1_C MTK_M4U_ID(18, 10) +#define M4U_PORT_L18_CAM_LCESO_R1_C MTK_M4U_ID(18, 11) +#define M4U_PORT_L18_CAM_CRZO_R1_C MTK_M4U_ID(18, 12) +#define M4U_PORT_L18_CAM_LTMSO_R1_C MTK_M4U_ID(18, 13) +#define M4U_PORT_L18_CAM_RSSO_R1_C MTK_M4U_ID(18, 14) +#define M4U_PORT_L18_CAM_AAHO_R1_C MTK_M4U_ID(18, 15) +#define M4U_PORT_L18_CAM_LSCI_R1_C MTK_M4U_ID(18, 16) + +/* larb19 */ +#define M4U_PORT_L19_IPE_DVS_RDMA MTK_M4U_ID(19, 0) +#define M4U_PORT_L19_IPE_DVS_WDMA MTK_M4U_ID(19, 1) +#define M4U_PORT_L19_IPE_DVP_RDMA MTK_M4U_ID(19, 2) +#define M4U_PORT_L19_IPE_DVP_WDMA MTK_M4U_ID(19, 3) + +/* larb20 */ +#define M4U_PORT_L20_IPE_FDVT_RDA MTK_M4U_ID(20, 0) +#define M4U_PORT_L20_IPE_FDVT_RDB MTK_M4U_ID(20, 1) +#define M4U_PORT_L20_IPE_FDVT_WRA MTK_M4U_ID(20, 2) +#define M4U_PORT_L20_IPE_FDVT_WRB MTK_M4U_ID(20, 3) +#define M4U_PORT_L20_IPE_RSC_RDMA0 MTK_M4U_ID(20, 4) +#define M4U_PORT_L20_IPE_RSC_WDMA MTK_M4U_ID(20, 5) + +#endif diff --git a/include/dt-bindings/memory/mt8195-memory-port.h b/include/dt-bindings/memory/mt8195-memory-port.h new file mode 100644 index 000000000000..70ba9f498eeb --- /dev/null +++ b/include/dt-bindings/memory/mt8195-memory-port.h @@ -0,0 +1,408 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Yong Wu <yong.wu@mediatek.com> + */ +#ifndef _DT_BINDINGS_MEMORY_MT8195_LARB_PORT_H_ +#define _DT_BINDINGS_MEMORY_MT8195_LARB_PORT_H_ + +#include <dt-bindings/memory/mtk-memory-port.h> + +/* + * MM IOMMU supports 16GB dma address. We separate it to four ranges: + * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters + * locate in anyone region. BUT: + * a) Make sure all the ports inside a larb are in one range. + * b) The iova of any master can NOT cross the 4G/8G/12G boundary. + * + * This is the suggested mapping in this SoC: + * + * modules dma-address-region larbs-ports + * disp 0 ~ 4G larb0/1/2/3 + * vcodec 4G ~ 8G larb19/20/21/22/23/24 + * cam/mdp 8G ~ 12G the other larbs. + * N/A 12G ~ 16G + * CCU0 0x24000_0000 ~ 0x243ff_ffff larb18: port 0/1 + * CCU1 0x24400_0000 ~ 0x247ff_ffff larb18: port 2/3 + * + * This SoC have two IOMMU HWs, this is the detailed connected information: + * iommu-vdo: larb0/2/5/7/9/10/11/13/17/19/21/24/25/28 + * iommu-vpp: larb1/3/4/6/8/12/14/16/18/20/22/23/26/27 + */ + +/* MM IOMMU ports */ +/* larb0 */ +#define M4U_PORT_L0_DISP_RDMA0 MTK_M4U_ID(0, 0) +#define M4U_PORT_L0_DISP_WDMA0 MTK_M4U_ID(0, 1) +#define M4U_PORT_L0_DISP_OVL0_RDMA0 MTK_M4U_ID(0, 2) +#define M4U_PORT_L0_DISP_OVL0_RDMA1 MTK_M4U_ID(0, 3) +#define M4U_PORT_L0_DISP_OVL0_HDR MTK_M4U_ID(0, 4) +#define M4U_PORT_L0_DISP_FAKE0 MTK_M4U_ID(0, 5) + +/* larb1 */ +#define M4U_PORT_L1_DISP_RDMA0 MTK_M4U_ID(1, 0) +#define M4U_PORT_L1_DISP_WDMA0 MTK_M4U_ID(1, 1) +#define M4U_PORT_L1_DISP_OVL0_RDMA0 MTK_M4U_ID(1, 2) +#define M4U_PORT_L1_DISP_OVL0_RDMA1 MTK_M4U_ID(1, 3) +#define M4U_PORT_L1_DISP_OVL0_HDR MTK_M4U_ID(1, 4) +#define M4U_PORT_L1_DISP_FAKE0 MTK_M4U_ID(1, 5) + +/* larb2 */ +#define M4U_PORT_L2_MDP_RDMA0 MTK_M4U_ID(2, 0) +#define M4U_PORT_L2_MDP_RDMA2 MTK_M4U_ID(2, 1) +#define M4U_PORT_L2_MDP_RDMA4 MTK_M4U_ID(2, 2) +#define M4U_PORT_L2_MDP_RDMA6 MTK_M4U_ID(2, 3) +#define M4U_PORT_L2_DISP_FAKE1 MTK_M4U_ID(2, 4) + +/* larb3 */ +#define M4U_PORT_L3_MDP_RDMA1 MTK_M4U_ID(3, 0) +#define M4U_PORT_L3_MDP_RDMA3 MTK_M4U_ID(3, 1) +#define M4U_PORT_L3_MDP_RDMA5 MTK_M4U_ID(3, 2) +#define M4U_PORT_L3_MDP_RDMA7 MTK_M4U_ID(3, 3) +#define M4U_PORT_L3_HDR_DS MTK_M4U_ID(3, 4) +#define M4U_PORT_L3_HDR_ADL MTK_M4U_ID(3, 5) +#define M4U_PORT_L3_DISP_FAKE1 MTK_M4U_ID(3, 6) + +/* larb4 */ +#define M4U_PORT_L4_MDP_RDMA MTK_M4U_ID(4, 0) +#define M4U_PORT_L4_MDP_FG MTK_M4U_ID(4, 1) +#define M4U_PORT_L4_MDP_OVL MTK_M4U_ID(4, 2) +#define M4U_PORT_L4_MDP_WROT MTK_M4U_ID(4, 3) +#define M4U_PORT_L4_FAKE MTK_M4U_ID(4, 4) + +/* larb5 */ +#define M4U_PORT_L5_SVPP1_MDP_RDMA MTK_M4U_ID(5, 0) +#define M4U_PORT_L5_SVPP1_MDP_FG MTK_M4U_ID(5, 1) +#define M4U_PORT_L5_SVPP1_MDP_OVL MTK_M4U_ID(5, 2) +#define M4U_PORT_L5_SVPP1_MDP_WROT MTK_M4U_ID(5, 3) +#define M4U_PORT_L5_SVPP2_MDP_RDMA MTK_M4U_ID(5, 4) +#define M4U_PORT_L5_SVPP2_MDP_FG MTK_M4U_ID(5, 5) +#define M4U_PORT_L5_SVPP2_MDP_WROT MTK_M4U_ID(5, 6) +#define M4U_PORT_L5_FAKE MTK_M4U_ID(5, 7) + +/* larb6 */ +#define M4U_PORT_L6_SVPP3_MDP_RDMA MTK_M4U_ID(6, 0) +#define M4U_PORT_L6_SVPP3_MDP_FG MTK_M4U_ID(6, 1) +#define M4U_PORT_L6_SVPP3_MDP_WROT MTK_M4U_ID(6, 2) +#define M4U_PORT_L6_FAKE MTK_M4U_ID(6, 3) + +/* larb7 */ +#define M4U_PORT_L7_IMG_WPE_RDMA0 MTK_M4U_ID(7, 0) +#define M4U_PORT_L7_IMG_WPE_RDMA1 MTK_M4U_ID(7, 1) +#define M4U_PORT_L7_IMG_WPE_WDMA0 MTK_M4U_ID(7, 2) + +/* larb8 */ +#define M4U_PORT_L8_IMG_WPE_RDMA0 MTK_M4U_ID(8, 0) +#define M4U_PORT_L8_IMG_WPE_RDMA1 MTK_M4U_ID(8, 1) +#define M4U_PORT_L8_IMG_WPE_WDMA0 MTK_M4U_ID(8, 2) + +/* larb9 */ +#define M4U_PORT_L9_IMG_IMGI_T1_A MTK_M4U_ID(9, 0) +#define M4U_PORT_L9_IMG_IMGBI_T1_A MTK_M4U_ID(9, 1) +#define M4U_PORT_L9_IMG_IMGCI_T1_A MTK_M4U_ID(9, 2) +#define M4U_PORT_L9_IMG_SMTI_T1_A MTK_M4U_ID(9, 3) +#define M4U_PORT_L9_IMG_TNCSTI_T1_A MTK_M4U_ID(9, 4) +#define M4U_PORT_L9_IMG_TNCSTI_T4_A MTK_M4U_ID(9, 5) +#define M4U_PORT_L9_IMG_YUVO_T1_A MTK_M4U_ID(9, 6) +#define M4U_PORT_L9_IMG_TIMGO_T1_A MTK_M4U_ID(9, 7) +#define M4U_PORT_L9_IMG_YUVO_T2_A MTK_M4U_ID(9, 8) +#define M4U_PORT_L9_IMG_IMGI_T1_B MTK_M4U_ID(9, 9) +#define M4U_PORT_L9_IMG_IMGBI_T1_B MTK_M4U_ID(9, 10) +#define M4U_PORT_L9_IMG_IMGCI_T1_B MTK_M4U_ID(9, 11) +#define M4U_PORT_L9_IMG_YUVO_T5_A MTK_M4U_ID(9, 12) +#define M4U_PORT_L9_IMG_SMTI_T1_B MTK_M4U_ID(9, 13) +#define M4U_PORT_L9_IMG_TNCSO_T1_A MTK_M4U_ID(9, 14) +#define M4U_PORT_L9_IMG_SMTO_T1_A MTK_M4U_ID(9, 15) +#define M4U_PORT_L9_IMG_TNCSTO_T1_A MTK_M4U_ID(9, 16) +#define M4U_PORT_L9_IMG_YUVO_T2_B MTK_M4U_ID(9, 17) +#define M4U_PORT_L9_IMG_YUVO_T5_B MTK_M4U_ID(9, 18) +#define M4U_PORT_L9_IMG_SMTO_T1_B MTK_M4U_ID(9, 19) + +/* larb10 */ +#define M4U_PORT_L10_IMG_IMGI_D1_A MTK_M4U_ID(10, 0) +#define M4U_PORT_L10_IMG_IMGCI_D1_A MTK_M4U_ID(10, 1) +#define M4U_PORT_L10_IMG_DEPI_D1_A MTK_M4U_ID(10, 2) +#define M4U_PORT_L10_IMG_DMGI_D1_A MTK_M4U_ID(10, 3) +#define M4U_PORT_L10_IMG_VIPI_D1_A MTK_M4U_ID(10, 4) +#define M4U_PORT_L10_IMG_TNRWI_D1_A MTK_M4U_ID(10, 5) +#define M4U_PORT_L10_IMG_RECI_D1_A MTK_M4U_ID(10, 6) +#define M4U_PORT_L10_IMG_SMTI_D1_A MTK_M4U_ID(10, 7) +#define M4U_PORT_L10_IMG_SMTI_D6_A MTK_M4U_ID(10, 8) +#define M4U_PORT_L10_IMG_PIMGI_P1_A MTK_M4U_ID(10, 9) +#define M4U_PORT_L10_IMG_PIMGBI_P1_A MTK_M4U_ID(10, 10) +#define M4U_PORT_L10_IMG_PIMGCI_P1_A MTK_M4U_ID(10, 11) +#define M4U_PORT_L10_IMG_PIMGI_P1_B MTK_M4U_ID(10, 12) +#define M4U_PORT_L10_IMG_PIMGBI_P1_B MTK_M4U_ID(10, 13) +#define M4U_PORT_L10_IMG_PIMGCI_P1_B MTK_M4U_ID(10, 14) +#define M4U_PORT_L10_IMG_IMG3O_D1_A MTK_M4U_ID(10, 15) +#define M4U_PORT_L10_IMG_IMG4O_D1_A MTK_M4U_ID(10, 16) +#define M4U_PORT_L10_IMG_IMG3CO_D1_A MTK_M4U_ID(10, 17) +#define M4U_PORT_L10_IMG_FEO_D1_A MTK_M4U_ID(10, 18) +#define M4U_PORT_L10_IMG_IMG2O_D1_A MTK_M4U_ID(10, 19) +#define M4U_PORT_L10_IMG_TNRWO_D1_A MTK_M4U_ID(10, 20) +#define M4U_PORT_L10_IMG_SMTO_D1_A MTK_M4U_ID(10, 21) +#define M4U_PORT_L10_IMG_WROT_P1_A MTK_M4U_ID(10, 22) +#define M4U_PORT_L10_IMG_WROT_P1_B MTK_M4U_ID(10, 23) + +/* larb11 */ +#define M4U_PORT_L11_IMG_WPE_EIS_RDMA0_A MTK_M4U_ID(11, 0) +#define M4U_PORT_L11_IMG_WPE_EIS_RDMA1_A MTK_M4U_ID(11, 1) +#define M4U_PORT_L11_IMG_WPE_EIS_WDMA0_A MTK_M4U_ID(11, 2) +#define M4U_PORT_L11_IMG_WPE_TNR_RDMA0_A MTK_M4U_ID(11, 3) +#define M4U_PORT_L11_IMG_WPE_TNR_RDMA1_A MTK_M4U_ID(11, 4) +#define M4U_PORT_L11_IMG_WPE_TNR_WDMA0_A MTK_M4U_ID(11, 5) +#define M4U_PORT_L11_IMG_WPE_EIS_CQ0_A MTK_M4U_ID(11, 6) +#define M4U_PORT_L11_IMG_WPE_EIS_CQ1_A MTK_M4U_ID(11, 7) +#define M4U_PORT_L11_IMG_WPE_TNR_CQ0_A MTK_M4U_ID(11, 8) +#define M4U_PORT_L11_IMG_WPE_TNR_CQ1_A MTK_M4U_ID(11, 9) + +/* larb12 */ +#define M4U_PORT_L12_IMG_FDVT_RDA MTK_M4U_ID(12, 0) +#define M4U_PORT_L12_IMG_FDVT_RDB MTK_M4U_ID(12, 1) +#define M4U_PORT_L12_IMG_FDVT_WRA MTK_M4U_ID(12, 2) +#define M4U_PORT_L12_IMG_FDVT_WRB MTK_M4U_ID(12, 3) +#define M4U_PORT_L12_IMG_ME_RDMA MTK_M4U_ID(12, 4) +#define M4U_PORT_L12_IMG_ME_WDMA MTK_M4U_ID(12, 5) +#define M4U_PORT_L12_IMG_DVS_RDMA MTK_M4U_ID(12, 6) +#define M4U_PORT_L12_IMG_DVS_WDMA MTK_M4U_ID(12, 7) +#define M4U_PORT_L12_IMG_DVP_RDMA MTK_M4U_ID(12, 8) +#define M4U_PORT_L12_IMG_DVP_WDMA MTK_M4U_ID(12, 9) + +/* larb13 */ +#define M4U_PORT_L13_CAM_CAMSV_CQI_E1 MTK_M4U_ID(13, 0) +#define M4U_PORT_L13_CAM_CAMSV_CQI_E2 MTK_M4U_ID(13, 1) +#define M4U_PORT_L13_CAM_GCAMSV_A_IMGO_0 MTK_M4U_ID(13, 2) +#define M4U_PORT_L13_CAM_SCAMSV_A_IMGO_0 MTK_M4U_ID(13, 3) +#define M4U_PORT_L13_CAM_GCAMSV_B_IMGO_0 MTK_M4U_ID(13, 4) +#define M4U_PORT_L13_CAM_GCAMSV_B_IMGO_1 MTK_M4U_ID(13, 5) +#define M4U_PORT_L13_CAM_GCAMSV_A_UFEO_0 MTK_M4U_ID(13, 6) +#define M4U_PORT_L13_CAM_GCAMSV_B_UFEO_0 MTK_M4U_ID(13, 7) +#define M4U_PORT_L13_CAM_PDAI_0 MTK_M4U_ID(13, 8) +#define M4U_PORT_L13_CAM_FAKE MTK_M4U_ID(13, 9) + +/* larb14 */ +#define M4U_PORT_L14_CAM_GCAMSV_A_IMGO_1 MTK_M4U_ID(14, 0) +#define M4U_PORT_L14_CAM_SCAMSV_A_IMGO_1 MTK_M4U_ID(14, 1) +#define M4U_PORT_L14_CAM_GCAMSV_B_IMGO_0 MTK_M4U_ID(14, 2) +#define M4U_PORT_L14_CAM_GCAMSV_B_IMGO_1 MTK_M4U_ID(14, 3) +#define M4U_PORT_L14_CAM_SCAMSV_B_IMGO_0 MTK_M4U_ID(14, 4) +#define M4U_PORT_L14_CAM_SCAMSV_B_IMGO_1 MTK_M4U_ID(14, 5) +#define M4U_PORT_L14_CAM_IPUI MTK_M4U_ID(14, 6) +#define M4U_PORT_L14_CAM_IPU2I MTK_M4U_ID(14, 7) +#define M4U_PORT_L14_CAM_IPUO MTK_M4U_ID(14, 8) +#define M4U_PORT_L14_CAM_IPU2O MTK_M4U_ID(14, 9) +#define M4U_PORT_L14_CAM_IPU3O MTK_M4U_ID(14, 10) +#define M4U_PORT_L14_CAM_GCAMSV_A_UFEO_1 MTK_M4U_ID(14, 11) +#define M4U_PORT_L14_CAM_GCAMSV_B_UFEO_1 MTK_M4U_ID(14, 12) +#define M4U_PORT_L14_CAM_PDAI_1 MTK_M4U_ID(14, 13) +#define M4U_PORT_L14_CAM_PDAO MTK_M4U_ID(14, 14) + +/* larb15: null */ + +/* larb16 */ +#define M4U_PORT_L16_CAM_IMGO_R1 MTK_M4U_ID(16, 0) +#define M4U_PORT_L16_CAM_CQI_R1 MTK_M4U_ID(16, 1) +#define M4U_PORT_L16_CAM_CQI_R2 MTK_M4U_ID(16, 2) +#define M4U_PORT_L16_CAM_BPCI_R1 MTK_M4U_ID(16, 3) +#define M4U_PORT_L16_CAM_LSCI_R1 MTK_M4U_ID(16, 4) +#define M4U_PORT_L16_CAM_RAWI_R2 MTK_M4U_ID(16, 5) +#define M4U_PORT_L16_CAM_RAWI_R3 MTK_M4U_ID(16, 6) +#define M4U_PORT_L16_CAM_UFDI_R2 MTK_M4U_ID(16, 7) +#define M4U_PORT_L16_CAM_UFDI_R3 MTK_M4U_ID(16, 8) +#define M4U_PORT_L16_CAM_RAWI_R4 MTK_M4U_ID(16, 9) +#define M4U_PORT_L16_CAM_RAWI_R5 MTK_M4U_ID(16, 10) +#define M4U_PORT_L16_CAM_AAI_R1 MTK_M4U_ID(16, 11) +#define M4U_PORT_L16_CAM_FHO_R1 MTK_M4U_ID(16, 12) +#define M4U_PORT_L16_CAM_AAO_R1 MTK_M4U_ID(16, 13) +#define M4U_PORT_L16_CAM_TSFSO_R1 MTK_M4U_ID(16, 14) +#define M4U_PORT_L16_CAM_FLKO_R1 MTK_M4U_ID(16, 15) + +/* larb17 */ +#define M4U_PORT_L17_CAM_YUVO_R1 MTK_M4U_ID(17, 0) +#define M4U_PORT_L17_CAM_YUVO_R3 MTK_M4U_ID(17, 1) +#define M4U_PORT_L17_CAM_YUVCO_R1 MTK_M4U_ID(17, 2) +#define M4U_PORT_L17_CAM_YUVO_R2 MTK_M4U_ID(17, 3) +#define M4U_PORT_L17_CAM_RZH1N2TO_R1 MTK_M4U_ID(17, 4) +#define M4U_PORT_L17_CAM_DRZS4NO_R1 MTK_M4U_ID(17, 5) +#define M4U_PORT_L17_CAM_TNCSO_R1 MTK_M4U_ID(17, 6) + +/* larb18 */ +#define M4U_PORT_L18_CAM_CCUI MTK_M4U_ID(18, 0) +#define M4U_PORT_L18_CAM_CCUO MTK_M4U_ID(18, 1) +#define M4U_PORT_L18_CAM_CCUI2 MTK_M4U_ID(18, 2) +#define M4U_PORT_L18_CAM_CCUO2 MTK_M4U_ID(18, 3) + +/* larb19 */ +#define M4U_PORT_L19_VENC_RCPU MTK_M4U_ID(19, 0) +#define M4U_PORT_L19_VENC_REC MTK_M4U_ID(19, 1) +#define M4U_PORT_L19_VENC_BSDMA MTK_M4U_ID(19, 2) +#define M4U_PORT_L19_VENC_SV_COMV MTK_M4U_ID(19, 3) +#define M4U_PORT_L19_VENC_RD_COMV MTK_M4U_ID(19, 4) +#define M4U_PORT_L19_VENC_NBM_RDMA MTK_M4U_ID(19, 5) +#define M4U_PORT_L19_VENC_NBM_RDMA_LITE MTK_M4U_ID(19, 6) +#define M4U_PORT_L19_JPGENC_Y_RDMA MTK_M4U_ID(19, 7) +#define M4U_PORT_L19_JPGENC_C_RDMA MTK_M4U_ID(19, 8) +#define M4U_PORT_L19_JPGENC_Q_TABLE MTK_M4U_ID(19, 9) +#define M4U_PORT_L19_VENC_SUB_W_LUMA MTK_M4U_ID(19, 10) +#define M4U_PORT_L19_VENC_FCS_NBM_RDMA MTK_M4U_ID(19, 11) +#define M4U_PORT_L19_JPGENC_BSDMA MTK_M4U_ID(19, 12) +#define M4U_PORT_L19_JPGDEC_WDMA0 MTK_M4U_ID(19, 13) +#define M4U_PORT_L19_JPGDEC_BSDMA0 MTK_M4U_ID(19, 14) +#define M4U_PORT_L19_VENC_NBM_WDMA MTK_M4U_ID(19, 15) +#define M4U_PORT_L19_VENC_NBM_WDMA_LITE MTK_M4U_ID(19, 16) +#define M4U_PORT_L19_VENC_FCS_NBM_WDMA MTK_M4U_ID(19, 17) +#define M4U_PORT_L19_JPGDEC_WDMA1 MTK_M4U_ID(19, 18) +#define M4U_PORT_L19_JPGDEC_BSDMA1 MTK_M4U_ID(19, 19) +#define M4U_PORT_L19_JPGDEC_BUFF_OFFSET1 MTK_M4U_ID(19, 20) +#define M4U_PORT_L19_JPGDEC_BUFF_OFFSET0 MTK_M4U_ID(19, 21) +#define M4U_PORT_L19_VENC_CUR_LUMA MTK_M4U_ID(19, 22) +#define M4U_PORT_L19_VENC_CUR_CHROMA MTK_M4U_ID(19, 23) +#define M4U_PORT_L19_VENC_REF_LUMA MTK_M4U_ID(19, 24) +#define M4U_PORT_L19_VENC_REF_CHROMA MTK_M4U_ID(19, 25) +#define M4U_PORT_L19_VENC_SUB_R_CHROMA MTK_M4U_ID(19, 26) + +/* larb20 */ +#define M4U_PORT_L20_VENC_RCPU MTK_M4U_ID(20, 0) +#define M4U_PORT_L20_VENC_REC MTK_M4U_ID(20, 1) +#define M4U_PORT_L20_VENC_BSDMA MTK_M4U_ID(20, 2) +#define M4U_PORT_L20_VENC_SV_COMV MTK_M4U_ID(20, 3) +#define M4U_PORT_L20_VENC_RD_COMV MTK_M4U_ID(20, 4) +#define M4U_PORT_L20_VENC_NBM_RDMA MTK_M4U_ID(20, 5) +#define M4U_PORT_L20_VENC_NBM_RDMA_LITE MTK_M4U_ID(20, 6) +#define M4U_PORT_L20_JPGENC_Y_RDMA MTK_M4U_ID(20, 7) +#define M4U_PORT_L20_JPGENC_C_RDMA MTK_M4U_ID(20, 8) +#define M4U_PORT_L20_JPGENC_Q_TABLE MTK_M4U_ID(20, 9) +#define M4U_PORT_L20_VENC_SUB_W_LUMA MTK_M4U_ID(20, 10) +#define M4U_PORT_L20_VENC_FCS_NBM_RDMA MTK_M4U_ID(20, 11) +#define M4U_PORT_L20_JPGENC_BSDMA MTK_M4U_ID(20, 12) +#define M4U_PORT_L20_JPGDEC_WDMA0 MTK_M4U_ID(20, 13) +#define M4U_PORT_L20_JPGDEC_BSDMA0 MTK_M4U_ID(20, 14) +#define M4U_PORT_L20_VENC_NBM_WDMA MTK_M4U_ID(20, 15) +#define M4U_PORT_L20_VENC_NBM_WDMA_LITE MTK_M4U_ID(20, 16) +#define M4U_PORT_L20_VENC_FCS_NBM_WDMA MTK_M4U_ID(20, 17) +#define M4U_PORT_L20_JPGDEC_WDMA1 MTK_M4U_ID(20, 18) +#define M4U_PORT_L20_JPGDEC_BSDMA1 MTK_M4U_ID(20, 19) +#define M4U_PORT_L20_JPGDEC_BUFF_OFFSET1 MTK_M4U_ID(20, 20) +#define M4U_PORT_L20_JPGDEC_BUFF_OFFSET0 MTK_M4U_ID(20, 21) +#define M4U_PORT_L20_VENC_CUR_LUMA MTK_M4U_ID(20, 22) +#define M4U_PORT_L20_VENC_CUR_CHROMA MTK_M4U_ID(20, 23) +#define M4U_PORT_L20_VENC_REF_LUMA MTK_M4U_ID(20, 24) +#define M4U_PORT_L20_VENC_REF_CHROMA MTK_M4U_ID(20, 25) +#define M4U_PORT_L20_VENC_SUB_R_CHROMA MTK_M4U_ID(20, 26) + +/* larb21 */ +#define M4U_PORT_L21_VDEC_MC_EXT MTK_M4U_ID(21, 0) +#define M4U_PORT_L21_VDEC_UFO_EXT MTK_M4U_ID(21, 1) +#define M4U_PORT_L21_VDEC_PP_EXT MTK_M4U_ID(21, 2) +#define M4U_PORT_L21_VDEC_PRED_RD_EXT MTK_M4U_ID(21, 3) +#define M4U_PORT_L21_VDEC_PRED_WR_EXT MTK_M4U_ID(21, 4) +#define M4U_PORT_L21_VDEC_PPWRAP_EXT MTK_M4U_ID(21, 5) +#define M4U_PORT_L21_VDEC_TILE_EXT MTK_M4U_ID(21, 6) +#define M4U_PORT_L21_VDEC_VLD_EXT MTK_M4U_ID(21, 7) +#define M4U_PORT_L21_VDEC_VLD2_EXT MTK_M4U_ID(21, 8) +#define M4U_PORT_L21_VDEC_AVC_MV_EXT MTK_M4U_ID(21, 9) + +/* larb22 */ +#define M4U_PORT_L22_VDEC_MC_EXT MTK_M4U_ID(22, 0) +#define M4U_PORT_L22_VDEC_UFO_EXT MTK_M4U_ID(22, 1) +#define M4U_PORT_L22_VDEC_PP_EXT MTK_M4U_ID(22, 2) +#define M4U_PORT_L22_VDEC_PRED_RD_EXT MTK_M4U_ID(22, 3) +#define M4U_PORT_L22_VDEC_PRED_WR_EXT MTK_M4U_ID(22, 4) +#define M4U_PORT_L22_VDEC_PPWRAP_EXT MTK_M4U_ID(22, 5) +#define M4U_PORT_L22_VDEC_TILE_EXT MTK_M4U_ID(22, 6) +#define M4U_PORT_L22_VDEC_VLD_EXT MTK_M4U_ID(22, 7) +#define M4U_PORT_L22_VDEC_VLD2_EXT MTK_M4U_ID(22, 8) +#define M4U_PORT_L22_VDEC_AVC_MV_EXT MTK_M4U_ID(22, 9) + +/* larb23 */ +#define M4U_PORT_L23_VDEC_UFO_ENC_EXT MTK_M4U_ID(23, 0) +#define M4U_PORT_L23_VDEC_RDMA_EXT MTK_M4U_ID(23, 1) + +/* larb24 */ +#define M4U_PORT_L24_VDEC_LAT0_VLD_EXT MTK_M4U_ID(24, 0) +#define M4U_PORT_L24_VDEC_LAT0_VLD2_EXT MTK_M4U_ID(24, 1) +#define M4U_PORT_L24_VDEC_LAT0_AVC_MC_EXT MTK_M4U_ID(24, 2) +#define M4U_PORT_L24_VDEC_LAT0_PRED_RD_EXT MTK_M4U_ID(24, 3) +#define M4U_PORT_L24_VDEC_LAT0_TILE_EXT MTK_M4U_ID(24, 4) +#define M4U_PORT_L24_VDEC_LAT0_WDMA_EXT MTK_M4U_ID(24, 5) +#define M4U_PORT_L24_VDEC_LAT1_VLD_EXT MTK_M4U_ID(24, 6) +#define M4U_PORT_L24_VDEC_LAT1_VLD2_EXT MTK_M4U_ID(24, 7) +#define M4U_PORT_L24_VDEC_LAT1_AVC_MC_EXT MTK_M4U_ID(24, 8) +#define M4U_PORT_L24_VDEC_LAT1_PRED_RD_EXT MTK_M4U_ID(24, 9) +#define M4U_PORT_L24_VDEC_LAT1_TILE_EXT MTK_M4U_ID(24, 10) +#define M4U_PORT_L24_VDEC_LAT1_WDMA_EXT MTK_M4U_ID(24, 11) + +/* larb25 */ +#define M4U_PORT_L25_CAM_MRAW0_LSCI_M1 MTK_M4U_ID(25, 0) +#define M4U_PORT_L25_CAM_MRAW0_CQI_M1 MTK_M4U_ID(25, 1) +#define M4U_PORT_L25_CAM_MRAW0_CQI_M2 MTK_M4U_ID(25, 2) +#define M4U_PORT_L25_CAM_MRAW0_IMGO_M1 MTK_M4U_ID(25, 3) +#define M4U_PORT_L25_CAM_MRAW0_IMGBO_M1 MTK_M4U_ID(25, 4) +#define M4U_PORT_L25_CAM_MRAW2_LSCI_M1 MTK_M4U_ID(25, 5) +#define M4U_PORT_L25_CAM_MRAW2_CQI_M1 MTK_M4U_ID(25, 6) +#define M4U_PORT_L25_CAM_MRAW2_CQI_M2 MTK_M4U_ID(25, 7) +#define M4U_PORT_L25_CAM_MRAW2_IMGO_M1 MTK_M4U_ID(25, 8) +#define M4U_PORT_L25_CAM_MRAW2_IMGBO_M1 MTK_M4U_ID(25, 9) +#define M4U_PORT_L25_CAM_MRAW0_AFO_M1 MTK_M4U_ID(25, 10) +#define M4U_PORT_L25_CAM_MRAW2_AFO_M1 MTK_M4U_ID(25, 11) + +/* larb26 */ +#define M4U_PORT_L26_CAM_MRAW1_LSCI_M1 MTK_M4U_ID(26, 0) +#define M4U_PORT_L26_CAM_MRAW1_CQI_M1 MTK_M4U_ID(26, 1) +#define M4U_PORT_L26_CAM_MRAW1_CQI_M2 MTK_M4U_ID(26, 2) +#define M4U_PORT_L26_CAM_MRAW1_IMGO_M1 MTK_M4U_ID(26, 3) +#define M4U_PORT_L26_CAM_MRAW1_IMGBO_M1 MTK_M4U_ID(26, 4) +#define M4U_PORT_L26_CAM_MRAW3_LSCI_M1 MTK_M4U_ID(26, 5) +#define M4U_PORT_L26_CAM_MRAW3_CQI_M1 MTK_M4U_ID(26, 6) +#define M4U_PORT_L26_CAM_MRAW3_CQI_M2 MTK_M4U_ID(26, 7) +#define M4U_PORT_L26_CAM_MRAW3_IMGO_M1 MTK_M4U_ID(26, 8) +#define M4U_PORT_L26_CAM_MRAW3_IMGBO_M1 MTK_M4U_ID(26, 9) +#define M4U_PORT_L26_CAM_MRAW1_AFO_M1 MTK_M4U_ID(26, 10) +#define M4U_PORT_L26_CAM_MRAW3_AFO_M1 MTK_M4U_ID(26, 11) + +/* larb27 */ +#define M4U_PORT_L27_CAM_IMGO_R1 MTK_M4U_ID(27, 0) +#define M4U_PORT_L27_CAM_CQI_R1 MTK_M4U_ID(27, 1) +#define M4U_PORT_L27_CAM_CQI_R2 MTK_M4U_ID(27, 2) +#define M4U_PORT_L27_CAM_BPCI_R1 MTK_M4U_ID(27, 3) +#define M4U_PORT_L27_CAM_LSCI_R1 MTK_M4U_ID(27, 4) +#define M4U_PORT_L27_CAM_RAWI_R2 MTK_M4U_ID(27, 5) +#define M4U_PORT_L27_CAM_RAWI_R3 MTK_M4U_ID(27, 6) +#define M4U_PORT_L27_CAM_UFDI_R2 MTK_M4U_ID(27, 7) +#define M4U_PORT_L27_CAM_UFDI_R3 MTK_M4U_ID(27, 8) +#define M4U_PORT_L27_CAM_RAWI_R4 MTK_M4U_ID(27, 9) +#define M4U_PORT_L27_CAM_RAWI_R5 MTK_M4U_ID(27, 10) +#define M4U_PORT_L27_CAM_AAI_R1 MTK_M4U_ID(27, 11) +#define M4U_PORT_L27_CAM_FHO_R1 MTK_M4U_ID(27, 12) +#define M4U_PORT_L27_CAM_AAO_R1 MTK_M4U_ID(27, 13) +#define M4U_PORT_L27_CAM_TSFSO_R1 MTK_M4U_ID(27, 14) +#define M4U_PORT_L27_CAM_FLKO_R1 MTK_M4U_ID(27, 15) + +/* larb28 */ +#define M4U_PORT_L28_CAM_YUVO_R1 MTK_M4U_ID(28, 0) +#define M4U_PORT_L28_CAM_YUVO_R3 MTK_M4U_ID(28, 1) +#define M4U_PORT_L28_CAM_YUVCO_R1 MTK_M4U_ID(28, 2) +#define M4U_PORT_L28_CAM_YUVO_R2 MTK_M4U_ID(28, 3) +#define M4U_PORT_L28_CAM_RZH1N2TO_R1 MTK_M4U_ID(28, 4) +#define M4U_PORT_L28_CAM_DRZS4NO_R1 MTK_M4U_ID(28, 5) +#define M4U_PORT_L28_CAM_TNCSO_R1 MTK_M4U_ID(28, 6) + +/* Infra iommu ports */ +/* PCIe1: read: BIT16; write BIT17. */ +#define IOMMU_PORT_INFRA_PCIE1 MTK_IFAIOMMU_PERI_ID(16) +/* PCIe0: read: BIT18; write BIT19. */ +#define IOMMU_PORT_INFRA_PCIE0 MTK_IFAIOMMU_PERI_ID(18) +#define IOMMU_PORT_INFRA_SSUSB_P3_R MTK_IFAIOMMU_PERI_ID(20) +#define IOMMU_PORT_INFRA_SSUSB_P3_W MTK_IFAIOMMU_PERI_ID(21) +#define IOMMU_PORT_INFRA_SSUSB_P2_R MTK_IFAIOMMU_PERI_ID(22) +#define IOMMU_PORT_INFRA_SSUSB_P2_W MTK_IFAIOMMU_PERI_ID(23) +#define IOMMU_PORT_INFRA_SSUSB_P1_1_R MTK_IFAIOMMU_PERI_ID(24) +#define IOMMU_PORT_INFRA_SSUSB_P1_1_W MTK_IFAIOMMU_PERI_ID(25) +#define IOMMU_PORT_INFRA_SSUSB_P1_0_R MTK_IFAIOMMU_PERI_ID(26) +#define IOMMU_PORT_INFRA_SSUSB_P1_0_W MTK_IFAIOMMU_PERI_ID(27) +#define IOMMU_PORT_INFRA_SSUSB2_R MTK_IFAIOMMU_PERI_ID(28) +#define IOMMU_PORT_INFRA_SSUSB2_W MTK_IFAIOMMU_PERI_ID(29) +#define IOMMU_PORT_INFRA_SSUSB_R MTK_IFAIOMMU_PERI_ID(30) +#define IOMMU_PORT_INFRA_SSUSB_W MTK_IFAIOMMU_PERI_ID(31) + +#endif diff --git a/include/dt-bindings/memory/mtk-memory-port.h b/include/dt-bindings/memory/mtk-memory-port.h new file mode 100644 index 000000000000..2f68a0511a25 --- /dev/null +++ b/include/dt-bindings/memory/mtk-memory-port.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020 MediaTek Inc. + * Author: Yong Wu <yong.wu@mediatek.com> + */ +#ifndef __DT_BINDINGS_MEMORY_MTK_MEMORY_PORT_H_ +#define __DT_BINDINGS_MEMORY_MTK_MEMORY_PORT_H_ + +#define MTK_LARB_NR_MAX 32 + +#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port)) +#define MTK_M4U_TO_LARB(id) (((id) >> 5) & 0x1f) +#define MTK_M4U_TO_PORT(id) ((id) & 0x1f) + +#define MTK_IFAIOMMU_PERI_ID(port) MTK_M4U_ID(0, port) + +#endif diff --git a/include/dt-bindings/memory/tegra124-mc.h b/include/dt-bindings/memory/tegra124-mc.h index 186e6b7e9b35..7e73bb400eca 100644 --- a/include/dt-bindings/memory/tegra124-mc.h +++ b/include/dt-bindings/memory/tegra124-mc.h @@ -54,4 +54,72 @@ #define TEGRA124_MC_RESET_ISP2B 22 #define TEGRA124_MC_RESET_GPU 23 +#define TEGRA124_MC_PTCR 0 +#define TEGRA124_MC_DISPLAY0A 1 +#define TEGRA124_MC_DISPLAY0AB 2 +#define TEGRA124_MC_DISPLAY0B 3 +#define TEGRA124_MC_DISPLAY0BB 4 +#define TEGRA124_MC_DISPLAY0C 5 +#define TEGRA124_MC_DISPLAY0CB 6 +#define TEGRA124_MC_AFIR 14 +#define TEGRA124_MC_AVPCARM7R 15 +#define TEGRA124_MC_DISPLAYHC 16 +#define TEGRA124_MC_DISPLAYHCB 17 +#define TEGRA124_MC_HDAR 21 +#define TEGRA124_MC_HOST1XDMAR 22 +#define TEGRA124_MC_HOST1XR 23 +#define TEGRA124_MC_MSENCSRD 28 +#define TEGRA124_MC_PPCSAHBDMAR 29 +#define TEGRA124_MC_PPCSAHBSLVR 30 +#define TEGRA124_MC_SATAR 31 +#define TEGRA124_MC_VDEBSEVR 34 +#define TEGRA124_MC_VDEMBER 35 +#define TEGRA124_MC_VDEMCER 36 +#define TEGRA124_MC_VDETPER 37 +#define TEGRA124_MC_MPCORELPR 38 +#define TEGRA124_MC_MPCORER 39 +#define TEGRA124_MC_MSENCSWR 43 +#define TEGRA124_MC_AFIW 49 +#define TEGRA124_MC_AVPCARM7W 50 +#define TEGRA124_MC_HDAW 53 +#define TEGRA124_MC_HOST1XW 54 +#define TEGRA124_MC_MPCORELPW 56 +#define TEGRA124_MC_MPCOREW 57 +#define TEGRA124_MC_PPCSAHBDMAW 59 +#define TEGRA124_MC_PPCSAHBSLVW 60 +#define TEGRA124_MC_SATAW 61 +#define TEGRA124_MC_VDEBSEVW 62 +#define TEGRA124_MC_VDEDBGW 63 +#define TEGRA124_MC_VDEMBEW 64 +#define TEGRA124_MC_VDETPMW 65 +#define TEGRA124_MC_ISPRA 68 +#define TEGRA124_MC_ISPWA 70 +#define TEGRA124_MC_ISPWB 71 +#define TEGRA124_MC_XUSB_HOSTR 74 +#define TEGRA124_MC_XUSB_HOSTW 75 +#define TEGRA124_MC_XUSB_DEVR 76 +#define TEGRA124_MC_XUSB_DEVW 77 +#define TEGRA124_MC_ISPRAB 78 +#define TEGRA124_MC_ISPWAB 80 +#define TEGRA124_MC_ISPWBB 81 +#define TEGRA124_MC_TSECSRD 84 +#define TEGRA124_MC_TSECSWR 85 +#define TEGRA124_MC_A9AVPSCR 86 +#define TEGRA124_MC_A9AVPSCW 87 +#define TEGRA124_MC_GPUSRD 88 +#define TEGRA124_MC_GPUSWR 89 +#define TEGRA124_MC_DISPLAYT 90 +#define TEGRA124_MC_SDMMCRA 96 +#define TEGRA124_MC_SDMMCRAA 97 +#define TEGRA124_MC_SDMMCR 98 +#define TEGRA124_MC_SDMMCRAB 99 +#define TEGRA124_MC_SDMMCWA 100 +#define TEGRA124_MC_SDMMCWAA 101 +#define TEGRA124_MC_SDMMCW 102 +#define TEGRA124_MC_SDMMCWAB 103 +#define TEGRA124_MC_VICSRD 108 +#define TEGRA124_MC_VICSWR 109 +#define TEGRA124_MC_VIW 114 +#define TEGRA124_MC_DISPLAYD 115 + #endif diff --git a/include/dt-bindings/memory/tegra20-mc.h b/include/dt-bindings/memory/tegra20-mc.h index 35e131eee198..6f8829508ad0 100644 --- a/include/dt-bindings/memory/tegra20-mc.h +++ b/include/dt-bindings/memory/tegra20-mc.h @@ -18,4 +18,57 @@ #define TEGRA20_MC_RESET_VDE 13 #define TEGRA20_MC_RESET_VI 14 +#define TEGRA20_MC_DISPLAY0A 0 +#define TEGRA20_MC_DISPLAY0AB 1 +#define TEGRA20_MC_DISPLAY0B 2 +#define TEGRA20_MC_DISPLAY0BB 3 +#define TEGRA20_MC_DISPLAY0C 4 +#define TEGRA20_MC_DISPLAY0CB 5 +#define TEGRA20_MC_DISPLAY1B 6 +#define TEGRA20_MC_DISPLAY1BB 7 +#define TEGRA20_MC_EPPUP 8 +#define TEGRA20_MC_G2PR 9 +#define TEGRA20_MC_G2SR 10 +#define TEGRA20_MC_MPEUNIFBR 11 +#define TEGRA20_MC_VIRUV 12 +#define TEGRA20_MC_AVPCARM7R 13 +#define TEGRA20_MC_DISPLAYHC 14 +#define TEGRA20_MC_DISPLAYHCB 15 +#define TEGRA20_MC_FDCDRD 16 +#define TEGRA20_MC_G2DR 17 +#define TEGRA20_MC_HOST1XDMAR 18 +#define TEGRA20_MC_HOST1XR 19 +#define TEGRA20_MC_IDXSRD 20 +#define TEGRA20_MC_MPCORER 21 +#define TEGRA20_MC_MPE_IPRED 22 +#define TEGRA20_MC_MPEAMEMRD 23 +#define TEGRA20_MC_MPECSRD 24 +#define TEGRA20_MC_PPCSAHBDMAR 25 +#define TEGRA20_MC_PPCSAHBSLVR 26 +#define TEGRA20_MC_TEXSRD 27 +#define TEGRA20_MC_VDEBSEVR 28 +#define TEGRA20_MC_VDEMBER 29 +#define TEGRA20_MC_VDEMCER 30 +#define TEGRA20_MC_VDETPER 31 +#define TEGRA20_MC_EPPU 32 +#define TEGRA20_MC_EPPV 33 +#define TEGRA20_MC_EPPY 34 +#define TEGRA20_MC_MPEUNIFBW 35 +#define TEGRA20_MC_VIWSB 36 +#define TEGRA20_MC_VIWU 37 +#define TEGRA20_MC_VIWV 38 +#define TEGRA20_MC_VIWY 39 +#define TEGRA20_MC_G2DW 40 +#define TEGRA20_MC_AVPCARM7W 41 +#define TEGRA20_MC_FDCDWR 42 +#define TEGRA20_MC_HOST1XW 43 +#define TEGRA20_MC_ISPW 44 +#define TEGRA20_MC_MPCOREW 45 +#define TEGRA20_MC_MPECSWR 46 +#define TEGRA20_MC_PPCSAHBDMAW 47 +#define TEGRA20_MC_PPCSAHBSLVW 48 +#define TEGRA20_MC_VDEBSEVW 49 +#define TEGRA20_MC_VDEMBEW 50 +#define TEGRA20_MC_VDETPMW 51 + #endif diff --git a/include/dt-bindings/memory/tegra210-mc.h b/include/dt-bindings/memory/tegra210-mc.h index cacf05617e03..5e082547f179 100644 --- a/include/dt-bindings/memory/tegra210-mc.h +++ b/include/dt-bindings/memory/tegra210-mc.h @@ -33,6 +33,16 @@ #define TEGRA_SWGROUP_AXIAP 28 #define TEGRA_SWGROUP_ETR 29 #define TEGRA_SWGROUP_TSECB 30 +#define TEGRA_SWGROUP_NV 31 +#define TEGRA_SWGROUP_NV2 32 +#define TEGRA_SWGROUP_PPCS1 33 +#define TEGRA_SWGROUP_DC1 34 +#define TEGRA_SWGROUP_PPCS2 35 +#define TEGRA_SWGROUP_HC1 36 +#define TEGRA_SWGROUP_SE1 37 +#define TEGRA_SWGROUP_TSEC1 38 +#define TEGRA_SWGROUP_TSECB1 39 +#define TEGRA_SWGROUP_NVDEC1 40 #define TEGRA210_MC_RESET_AFI 0 #define TEGRA210_MC_RESET_AVPC 1 diff --git a/include/dt-bindings/memory/tegra234-mc.h b/include/dt-bindings/memory/tegra234-mc.h new file mode 100644 index 000000000000..bd71cc1d7990 --- /dev/null +++ b/include/dt-bindings/memory/tegra234-mc.h @@ -0,0 +1,143 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */ + +#ifndef DT_BINDINGS_MEMORY_TEGRA234_MC_H +#define DT_BINDINGS_MEMORY_TEGRA234_MC_H + +/* special clients */ +#define TEGRA234_SID_INVALID 0x00 +#define TEGRA234_SID_PASSTHROUGH 0x7f + +/* NISO0 stream IDs */ +#define TEGRA234_SID_APE 0x02 +#define TEGRA234_SID_HDA 0x03 +#define TEGRA234_SID_GPCDMA 0x04 +#define TEGRA234_SID_MGBE 0x06 +#define TEGRA234_SID_PCIE0 0x12 +#define TEGRA234_SID_PCIE4 0x13 +#define TEGRA234_SID_PCIE5 0x14 +#define TEGRA234_SID_PCIE6 0x15 +#define TEGRA234_SID_PCIE9 0x1f +#define TEGRA234_SID_MGBE_VF1 0x49 +#define TEGRA234_SID_MGBE_VF2 0x4a +#define TEGRA234_SID_MGBE_VF3 0x4b + +/* NISO1 stream IDs */ +#define TEGRA234_SID_SDMMC4 0x02 +#define TEGRA234_SID_PCIE1 0x05 +#define TEGRA234_SID_PCIE2 0x06 +#define TEGRA234_SID_PCIE3 0x07 +#define TEGRA234_SID_PCIE7 0x08 +#define TEGRA234_SID_PCIE8 0x09 +#define TEGRA234_SID_PCIE10 0x0b +#define TEGRA234_SID_BPMP 0x10 +#define TEGRA234_SID_HOST1X 0x27 +#define TEGRA234_SID_VIC 0x34 + +/* Shared stream IDs */ +#define TEGRA234_SID_HOST1X_CTX0 0x35 +#define TEGRA234_SID_HOST1X_CTX1 0x36 +#define TEGRA234_SID_HOST1X_CTX2 0x37 +#define TEGRA234_SID_HOST1X_CTX3 0x38 +#define TEGRA234_SID_HOST1X_CTX4 0x39 +#define TEGRA234_SID_HOST1X_CTX5 0x3a +#define TEGRA234_SID_HOST1X_CTX6 0x3b +#define TEGRA234_SID_HOST1X_CTX7 0x3c + +/* + * memory client IDs + */ + +/* High-definition audio (HDA) read clients */ +#define TEGRA234_MEMORY_CLIENT_HDAR 0x15 +#define TEGRA234_MEMORY_CLIENT_HOST1XDMAR 0x16 +/* PCIE6 read clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE6AR 0x28 +/* PCIE6 write clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE6AW 0x29 +/* PCIE7 read clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE7AR 0x2a +/* PCIE7 write clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE7AW 0x30 +/* PCIE8 read clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE8AR 0x32 +/* High-definition audio (HDA) write clients */ +#define TEGRA234_MEMORY_CLIENT_HDAW 0x35 +/* PCIE8 write clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE8AW 0x3b +/* PCIE9 read clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE9AR 0x3c +/* PCIE6r1 read clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE6AR1 0x3d +/* PCIE9 write clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE9AW 0x3e +/* PCIE10 read clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE10AR 0x3f +/* PCIE10 write clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE10AW 0x40 +/* PCIE10r1 read clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE10AR1 0x48 +/* PCIE7r1 read clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE7AR1 0x49 +/* MGBE0 read client */ +#define TEGRA234_MEMORY_CLIENT_MGBEARD 0x58 +/* MGBEB read client */ +#define TEGRA234_MEMORY_CLIENT_MGBEBRD 0x59 +/* MGBEC read client */ +#define TEGRA234_MEMORY_CLIENT_MGBECRD 0x5a +/* MGBED read client */ +#define TEGRA234_MEMORY_CLIENT_MGBEDRD 0x5b +/* MGBE0 write client */ +#define TEGRA234_MEMORY_CLIENT_MGBEAWR 0x5c +/* MGBEB write client */ +#define TEGRA234_MEMORY_CLIENT_MGBEBWR 0x5f +/* MGBEC write client */ +#define TEGRA234_MEMORY_CLIENT_MGBECWR 0x61 +/* sdmmcd memory read client */ +#define TEGRA234_MEMORY_CLIENT_SDMMCRAB 0x63 +/* MGBED write client */ +#define TEGRA234_MEMORY_CLIENT_MGBEDWR 0x65 +/* sdmmcd memory write client */ +#define TEGRA234_MEMORY_CLIENT_SDMMCWAB 0x67 +#define TEGRA234_MEMORY_CLIENT_VICSRD 0x6c +#define TEGRA234_MEMORY_CLIENT_VICSWR 0x6d +/* BPMP read client */ +#define TEGRA234_MEMORY_CLIENT_BPMPR 0x93 +/* BPMP write client */ +#define TEGRA234_MEMORY_CLIENT_BPMPW 0x94 +/* BPMPDMA read client */ +#define TEGRA234_MEMORY_CLIENT_BPMPDMAR 0x95 +/* BPMPDMA write client */ +#define TEGRA234_MEMORY_CLIENT_BPMPDMAW 0x96 +/* APEDMA read client */ +#define TEGRA234_MEMORY_CLIENT_APEDMAR 0x9f +/* APEDMA write client */ +#define TEGRA234_MEMORY_CLIENT_APEDMAW 0xa0 +/* PCIE0 read clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE0R 0xd8 +/* PCIE0 write clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE0W 0xd9 +/* PCIE1 read clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE1R 0xda +/* PCIE1 write clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE1W 0xdb +/* PCIE2 read clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE2AR 0xdc +/* PCIE2 write clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE2AW 0xdd +/* PCIE3 read clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE3R 0xde +/* PCIE3 write clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE3W 0xdf +/* PCIE4 read clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE4R 0xe0 +/* PCIE4 write clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE4W 0xe1 +/* PCIE5 read clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE5R 0xe2 +/* PCIE5 write clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE5W 0xe3 +/* PCIE5r1 read clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE5R1 0xef + +#endif diff --git a/include/dt-bindings/memory/tegra30-mc.h b/include/dt-bindings/memory/tegra30-mc.h index 169f005fbc78..930f708aca17 100644 --- a/include/dt-bindings/memory/tegra30-mc.h +++ b/include/dt-bindings/memory/tegra30-mc.h @@ -41,4 +41,71 @@ #define TEGRA30_MC_RESET_VDE 16 #define TEGRA30_MC_RESET_VI 17 +#define TEGRA30_MC_PTCR 0 +#define TEGRA30_MC_DISPLAY0A 1 +#define TEGRA30_MC_DISPLAY0AB 2 +#define TEGRA30_MC_DISPLAY0B 3 +#define TEGRA30_MC_DISPLAY0BB 4 +#define TEGRA30_MC_DISPLAY0C 5 +#define TEGRA30_MC_DISPLAY0CB 6 +#define TEGRA30_MC_DISPLAY1B 7 +#define TEGRA30_MC_DISPLAY1BB 8 +#define TEGRA30_MC_EPPUP 9 +#define TEGRA30_MC_G2PR 10 +#define TEGRA30_MC_G2SR 11 +#define TEGRA30_MC_MPEUNIFBR 12 +#define TEGRA30_MC_VIRUV 13 +#define TEGRA30_MC_AFIR 14 +#define TEGRA30_MC_AVPCARM7R 15 +#define TEGRA30_MC_DISPLAYHC 16 +#define TEGRA30_MC_DISPLAYHCB 17 +#define TEGRA30_MC_FDCDRD 18 +#define TEGRA30_MC_FDCDRD2 19 +#define TEGRA30_MC_G2DR 20 +#define TEGRA30_MC_HDAR 21 +#define TEGRA30_MC_HOST1XDMAR 22 +#define TEGRA30_MC_HOST1XR 23 +#define TEGRA30_MC_IDXSRD 24 +#define TEGRA30_MC_IDXSRD2 25 +#define TEGRA30_MC_MPE_IPRED 26 +#define TEGRA30_MC_MPEAMEMRD 27 +#define TEGRA30_MC_MPECSRD 28 +#define TEGRA30_MC_PPCSAHBDMAR 29 +#define TEGRA30_MC_PPCSAHBSLVR 30 +#define TEGRA30_MC_SATAR 31 +#define TEGRA30_MC_TEXSRD 32 +#define TEGRA30_MC_TEXSRD2 33 +#define TEGRA30_MC_VDEBSEVR 34 +#define TEGRA30_MC_VDEMBER 35 +#define TEGRA30_MC_VDEMCER 36 +#define TEGRA30_MC_VDETPER 37 +#define TEGRA30_MC_MPCORELPR 38 +#define TEGRA30_MC_MPCORER 39 +#define TEGRA30_MC_EPPU 40 +#define TEGRA30_MC_EPPV 41 +#define TEGRA30_MC_EPPY 42 +#define TEGRA30_MC_MPEUNIFBW 43 +#define TEGRA30_MC_VIWSB 44 +#define TEGRA30_MC_VIWU 45 +#define TEGRA30_MC_VIWV 46 +#define TEGRA30_MC_VIWY 47 +#define TEGRA30_MC_G2DW 48 +#define TEGRA30_MC_AFIW 49 +#define TEGRA30_MC_AVPCARM7W 50 +#define TEGRA30_MC_FDCDWR 51 +#define TEGRA30_MC_FDCDWR2 52 +#define TEGRA30_MC_HDAW 53 +#define TEGRA30_MC_HOST1XW 54 +#define TEGRA30_MC_ISPW 55 +#define TEGRA30_MC_MPCORELPW 56 +#define TEGRA30_MC_MPCOREW 57 +#define TEGRA30_MC_MPECSWR 58 +#define TEGRA30_MC_PPCSAHBDMAW 59 +#define TEGRA30_MC_PPCSAHBSLVW 60 +#define TEGRA30_MC_SATAW 61 +#define TEGRA30_MC_VDEBSEVW 62 +#define TEGRA30_MC_VDEDBGW 63 +#define TEGRA30_MC_VDEMBEW 64 +#define TEGRA30_MC_VDETPMW 65 + #endif diff --git a/include/dt-bindings/mfd/cros_ec.h b/include/dt-bindings/mfd/cros_ec.h new file mode 100644 index 000000000000..3b29cd049578 --- /dev/null +++ b/include/dt-bindings/mfd/cros_ec.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * DTS binding definitions used for the Chromium OS Embedded Controller. + * + * Copyright (c) 2022 The Chromium OS Authors. All rights reserved. + */ + +#ifndef _DT_BINDINGS_MFD_CROS_EC_H +#define _DT_BINDINGS_MFD_CROS_EC_H + +/* Typed channel for keyboard backlight. */ +#define CROS_EC_PWM_DT_KB_LIGHT 0 +/* Typed channel for display backlight. */ +#define CROS_EC_PWM_DT_DISPLAY_LIGHT 1 +/* Number of typed channels. */ +#define CROS_EC_PWM_DT_COUNT 2 + +#endif diff --git a/include/dt-bindings/mfd/qcom-pm8008.h b/include/dt-bindings/mfd/qcom-pm8008.h new file mode 100644 index 000000000000..eca9448df228 --- /dev/null +++ b/include/dt-bindings/mfd/qcom-pm8008.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021 The Linux Foundation. All rights reserved. + */ + +#ifndef __DT_BINDINGS_MFD_QCOM_PM8008_H +#define __DT_BINDINGS_MFD_QCOM_PM8008_H + +/* PM8008 IRQ numbers */ +#define PM8008_IRQ_MISC_UVLO 0 +#define PM8008_IRQ_MISC_OVLO 1 +#define PM8008_IRQ_MISC_OTST2 2 +#define PM8008_IRQ_MISC_OTST3 3 +#define PM8008_IRQ_MISC_LDO_OCP 4 +#define PM8008_IRQ_TEMP_ALARM 5 +#define PM8008_IRQ_GPIO1 6 +#define PM8008_IRQ_GPIO2 7 + +#endif diff --git a/include/dt-bindings/mux/mux.h b/include/dt-bindings/mux/mux.h index 042719218dbf..0b9d654506ef 100644 --- a/include/dt-bindings/mux/mux.h +++ b/include/dt-bindings/mux/mux.h @@ -3,7 +3,7 @@ * This header provides constants for most Multiplexer bindings. * * Most Multiplexer bindings specify an idle state. In most cases, the - * the multiplexer can be left as is when idle, and in some cases it can + * multiplexer can be left as is when idle, and in some cases it can * disconnect the input/output and leave the multiplexer in a high * impedance state. */ diff --git a/include/dt-bindings/mux/ti-serdes.h b/include/dt-bindings/mux/ti-serdes.h new file mode 100644 index 000000000000..d3116c52ab72 --- /dev/null +++ b/include/dt-bindings/mux/ti-serdes.h @@ -0,0 +1,120 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides constants for SERDES MUX for TI SoCs + */ + +#ifndef _DT_BINDINGS_MUX_TI_SERDES +#define _DT_BINDINGS_MUX_TI_SERDES + +/* J721E */ + +#define J721E_SERDES0_LANE0_QSGMII_LANE1 0x0 +#define J721E_SERDES0_LANE0_PCIE0_LANE0 0x1 +#define J721E_SERDES0_LANE0_USB3_0_SWAP 0x2 +#define J721E_SERDES0_LANE0_IP4_UNUSED 0x3 + +#define J721E_SERDES0_LANE1_QSGMII_LANE2 0x0 +#define J721E_SERDES0_LANE1_PCIE0_LANE1 0x1 +#define J721E_SERDES0_LANE1_USB3_0 0x2 +#define J721E_SERDES0_LANE1_IP4_UNUSED 0x3 + +#define J721E_SERDES1_LANE0_QSGMII_LANE3 0x0 +#define J721E_SERDES1_LANE0_PCIE1_LANE0 0x1 +#define J721E_SERDES1_LANE0_USB3_1_SWAP 0x2 +#define J721E_SERDES1_LANE0_SGMII_LANE0 0x3 + +#define J721E_SERDES1_LANE1_QSGMII_LANE4 0x0 +#define J721E_SERDES1_LANE1_PCIE1_LANE1 0x1 +#define J721E_SERDES1_LANE1_USB3_1 0x2 +#define J721E_SERDES1_LANE1_SGMII_LANE1 0x3 + +#define J721E_SERDES2_LANE0_IP1_UNUSED 0x0 +#define J721E_SERDES2_LANE0_PCIE2_LANE0 0x1 +#define J721E_SERDES2_LANE0_USB3_1_SWAP 0x2 +#define J721E_SERDES2_LANE0_SGMII_LANE0 0x3 + +#define J721E_SERDES2_LANE1_IP1_UNUSED 0x0 +#define J721E_SERDES2_LANE1_PCIE2_LANE1 0x1 +#define J721E_SERDES2_LANE1_USB3_1 0x2 +#define J721E_SERDES2_LANE1_SGMII_LANE1 0x3 + +#define J721E_SERDES3_LANE0_IP1_UNUSED 0x0 +#define J721E_SERDES3_LANE0_PCIE3_LANE0 0x1 +#define J721E_SERDES3_LANE0_USB3_0_SWAP 0x2 +#define J721E_SERDES3_LANE0_IP4_UNUSED 0x3 + +#define J721E_SERDES3_LANE1_IP1_UNUSED 0x0 +#define J721E_SERDES3_LANE1_PCIE3_LANE1 0x1 +#define J721E_SERDES3_LANE1_USB3_0 0x2 +#define J721E_SERDES3_LANE1_IP4_UNUSED 0x3 + +#define J721E_SERDES4_LANE0_EDP_LANE0 0x0 +#define J721E_SERDES4_LANE0_IP2_UNUSED 0x1 +#define J721E_SERDES4_LANE0_QSGMII_LANE5 0x2 +#define J721E_SERDES4_LANE0_IP4_UNUSED 0x3 + +#define J721E_SERDES4_LANE1_EDP_LANE1 0x0 +#define J721E_SERDES4_LANE1_IP2_UNUSED 0x1 +#define J721E_SERDES4_LANE1_QSGMII_LANE6 0x2 +#define J721E_SERDES4_LANE1_IP4_UNUSED 0x3 + +#define J721E_SERDES4_LANE2_EDP_LANE2 0x0 +#define J721E_SERDES4_LANE2_IP2_UNUSED 0x1 +#define J721E_SERDES4_LANE2_QSGMII_LANE7 0x2 +#define J721E_SERDES4_LANE2_IP4_UNUSED 0x3 + +#define J721E_SERDES4_LANE3_EDP_LANE3 0x0 +#define J721E_SERDES4_LANE3_IP2_UNUSED 0x1 +#define J721E_SERDES4_LANE3_QSGMII_LANE8 0x2 +#define J721E_SERDES4_LANE3_IP4_UNUSED 0x3 + +/* J7200 */ + +#define J7200_SERDES0_LANE0_QSGMII_LANE3 0x0 +#define J7200_SERDES0_LANE0_PCIE1_LANE0 0x1 +#define J7200_SERDES0_LANE0_IP3_UNUSED 0x2 +#define J7200_SERDES0_LANE0_IP4_UNUSED 0x3 + +#define J7200_SERDES0_LANE1_QSGMII_LANE4 0x0 +#define J7200_SERDES0_LANE1_PCIE1_LANE1 0x1 +#define J7200_SERDES0_LANE1_IP3_UNUSED 0x2 +#define J7200_SERDES0_LANE1_IP4_UNUSED 0x3 + +#define J7200_SERDES0_LANE2_QSGMII_LANE1 0x0 +#define J7200_SERDES0_LANE2_PCIE1_LANE2 0x1 +#define J7200_SERDES0_LANE2_IP3_UNUSED 0x2 +#define J7200_SERDES0_LANE2_IP4_UNUSED 0x3 + +#define J7200_SERDES0_LANE3_QSGMII_LANE2 0x0 +#define J7200_SERDES0_LANE3_PCIE1_LANE3 0x1 +#define J7200_SERDES0_LANE3_USB 0x2 +#define J7200_SERDES0_LANE3_IP4_UNUSED 0x3 + +/* AM64 */ + +#define AM64_SERDES0_LANE0_PCIE0 0x0 +#define AM64_SERDES0_LANE0_USB 0x1 + +/* J721S2 */ + +#define J721S2_SERDES0_LANE0_EDP_LANE0 0x0 +#define J721S2_SERDES0_LANE0_PCIE1_LANE0 0x1 +#define J721S2_SERDES0_LANE0_IP3_UNUSED 0x2 +#define J721S2_SERDES0_LANE0_IP4_UNUSED 0x3 + +#define J721S2_SERDES0_LANE1_EDP_LANE1 0x0 +#define J721S2_SERDES0_LANE1_PCIE1_LANE1 0x1 +#define J721S2_SERDES0_LANE1_USB 0x2 +#define J721S2_SERDES0_LANE1_IP4_UNUSED 0x3 + +#define J721S2_SERDES0_LANE2_EDP_LANE2 0x0 +#define J721S2_SERDES0_LANE2_PCIE1_LANE2 0x1 +#define J721S2_SERDES0_LANE2_IP3_UNUSED 0x2 +#define J721S2_SERDES0_LANE2_IP4_UNUSED 0x3 + +#define J721S2_SERDES0_LANE3_EDP_LANE3 0x0 +#define J721S2_SERDES0_LANE3_PCIE1_LANE3 0x1 +#define J721S2_SERDES0_LANE3_USB 0x2 +#define J721S2_SERDES0_LANE3_IP4_UNUSED 0x3 + +#endif /* _DT_BINDINGS_MUX_TI_SERDES */ diff --git a/include/dt-bindings/net/pcs-rzn1-miic.h b/include/dt-bindings/net/pcs-rzn1-miic.h new file mode 100644 index 000000000000..784782eaec9e --- /dev/null +++ b/include/dt-bindings/net/pcs-rzn1-miic.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2022 Schneider-Electric + * + * Clément Léger <clement.leger@bootlin.com> + */ + +#ifndef _DT_BINDINGS_PCS_RZN1_MIIC +#define _DT_BINDINGS_PCS_RZN1_MIIC + +/* + * Reefer to the datasheet [1] section 8.2.1, Internal Connection of Ethernet + * Ports to check the available combination + * + * [1] REN_r01uh0750ej0140-rzn1-introduction_MAT_20210228.pdf + */ + +#define MIIC_GMAC1_PORT 0 +#define MIIC_GMAC2_PORT 1 +#define MIIC_RTOS_PORT 2 +#define MIIC_SERCOS_PORTA 3 +#define MIIC_SERCOS_PORTB 4 +#define MIIC_ETHERCAT_PORTA 5 +#define MIIC_ETHERCAT_PORTB 6 +#define MIIC_ETHERCAT_PORTC 7 +#define MIIC_SWITCH_PORTA 8 +#define MIIC_SWITCH_PORTB 9 +#define MIIC_SWITCH_PORTC 10 +#define MIIC_SWITCH_PORTD 11 +#define MIIC_HSR_PORTA 12 +#define MIIC_HSR_PORTB 13 + +#endif diff --git a/include/dt-bindings/nvmem/microchip,sama7g5-otpc.h b/include/dt-bindings/nvmem/microchip,sama7g5-otpc.h new file mode 100644 index 000000000000..f570b23165a2 --- /dev/null +++ b/include/dt-bindings/nvmem/microchip,sama7g5-otpc.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ + +#ifndef _DT_BINDINGS_NVMEM_MICROCHIP_OTPC_H +#define _DT_BINDINGS_NVMEM_MICROCHIP_OTPC_H + +/* + * Need to have it as a multiple of 4 as NVMEM memory is registered with + * stride = 4. + */ +#define OTP_PKT(id) ((id) * 4) + +#endif diff --git a/include/dt-bindings/phy/phy-cadence.h b/include/dt-bindings/phy/phy-cadence.h new file mode 100644 index 000000000000..0671991208fc --- /dev/null +++ b/include/dt-bindings/phy/phy-cadence.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides constants for Cadence SERDES. + */ + +#ifndef _DT_BINDINGS_CADENCE_SERDES_H +#define _DT_BINDINGS_CADENCE_SERDES_H + +#define CDNS_SERDES_NO_SSC 0 +#define CDNS_SERDES_EXTERNAL_SSC 1 +#define CDNS_SERDES_INTERNAL_SSC 2 + +/* Torrent */ +#define CDNS_TORRENT_REFCLK_DRIVER 0 +#define CDNS_TORRENT_DERIVED_REFCLK 1 +#define CDNS_TORRENT_RECEIVED_REFCLK 2 + +/* Sierra */ +#define CDNS_SIERRA_PLL_CMNLC 0 +#define CDNS_SIERRA_PLL_CMNLC1 1 +#define CDNS_SIERRA_DERIVED_REFCLK 2 + +#endif /* _DT_BINDINGS_CADENCE_SERDES_H */ diff --git a/include/dt-bindings/phy/phy-imx8-pcie.h b/include/dt-bindings/phy/phy-imx8-pcie.h new file mode 100644 index 000000000000..8bbe2d6538d8 --- /dev/null +++ b/include/dt-bindings/phy/phy-imx8-pcie.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * This header provides constants for i.MX8 PCIe. + */ + +#ifndef _DT_BINDINGS_IMX8_PCIE_H +#define _DT_BINDINGS_IMX8_PCIE_H + +/* Reference clock PAD mode */ +#define IMX8_PCIE_REFCLK_PAD_UNUSED 0 +#define IMX8_PCIE_REFCLK_PAD_INPUT 1 +#define IMX8_PCIE_REFCLK_PAD_OUTPUT 2 + +#endif /* _DT_BINDINGS_IMX8_PCIE_H */ diff --git a/include/dt-bindings/phy/phy-lan966x-serdes.h b/include/dt-bindings/phy/phy-lan966x-serdes.h new file mode 100644 index 000000000000..4330269a901e --- /dev/null +++ b/include/dt-bindings/phy/phy-lan966x-serdes.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ + +#ifndef __PHY_LAN966X_SERDES_H__ +#define __PHY_LAN966X_SERDES_H__ + +#define CU(x) (x) +#define CU_MAX CU(2) +#define SERDES6G(x) (CU_MAX + 1 + (x)) +#define SERDES6G_MAX SERDES6G(3) +#define RGMII(x) (SERDES6G_MAX + 1 + (x)) +#define RGMII_MAX RGMII(2) +#define SERDES_MAX (RGMII_MAX + 1) + +#endif diff --git a/include/dt-bindings/phy/phy-ti.h b/include/dt-bindings/phy/phy-ti.h new file mode 100644 index 000000000000..ad955d3a56b4 --- /dev/null +++ b/include/dt-bindings/phy/phy-ti.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides constants for TI SERDES. + */ + +#ifndef _DT_BINDINGS_TI_SERDES +#define _DT_BINDINGS_TI_SERDES + +/* Clock index for output clocks from WIZ */ + +/* MUX Clocks */ +#define TI_WIZ_PLL0_REFCLK 0 +#define TI_WIZ_PLL1_REFCLK 1 +#define TI_WIZ_REFCLK_DIG 2 + +/* Reserve index here for future additions */ + +/* MISC Clocks */ +#define TI_WIZ_PHY_EN_REFCLK 16 + +#endif /* _DT_BINDINGS_TI_SERDES */ diff --git a/include/dt-bindings/phy/phy.h b/include/dt-bindings/phy/phy.h index 1f3f866fae7b..6b901b342348 100644 --- a/include/dt-bindings/phy/phy.h +++ b/include/dt-bindings/phy/phy.h @@ -17,5 +17,11 @@ #define PHY_TYPE_USB3 4 #define PHY_TYPE_UFS 5 #define PHY_TYPE_DP 6 +#define PHY_TYPE_XPCS 7 +#define PHY_TYPE_SGMII 8 +#define PHY_TYPE_QSGMII 9 +#define PHY_TYPE_DPHY 10 +#define PHY_TYPE_CPHY 11 +#define PHY_TYPE_USXGMII 12 #endif /* _DT_BINDINGS_PHY */ diff --git a/include/dt-bindings/pinctrl/apple.h b/include/dt-bindings/pinctrl/apple.h new file mode 100644 index 000000000000..ea0a6f466592 --- /dev/null +++ b/include/dt-bindings/pinctrl/apple.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ OR MIT */ +/* + * This header provides constants for Apple pinctrl bindings. + */ + +#ifndef _DT_BINDINGS_PINCTRL_APPLE_H +#define _DT_BINDINGS_PINCTRL_APPLE_H + +#define APPLE_PINMUX(pin, func) ((pin) | ((func) << 16)) +#define APPLE_PIN(pinmux) ((pinmux) & 0xffff) +#define APPLE_FUNC(pinmux) ((pinmux) >> 16) + +#endif /* _DT_BINDINGS_PINCTRL_APPLE_H */ diff --git a/include/dt-bindings/pinctrl/hisi.h b/include/dt-bindings/pinctrl/hisi.h index 0359bfdc9119..2175ec89c82f 100644 --- a/include/dt-bindings/pinctrl/hisi.h +++ b/include/dt-bindings/pinctrl/hisi.h @@ -1,17 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * This header provides constants for hisilicon pinctrl bindings. * - * Copyright (c) 2015 Hisilicon Limited. + * Copyright (c) 2015 HiSilicon Limited. * Copyright (c) 2015 Linaro Limited. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #ifndef _DT_BINDINGS_PINCTRL_HISI_H diff --git a/include/dt-bindings/pinctrl/k210-fpioa.h b/include/dt-bindings/pinctrl/k210-fpioa.h new file mode 100644 index 000000000000..314285eab3a1 --- /dev/null +++ b/include/dt-bindings/pinctrl/k210-fpioa.h @@ -0,0 +1,276 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 Sean Anderson <seanga2@gmail.com> + * Copyright (c) 2020 Western Digital Corporation or its affiliates. + */ +#ifndef PINCTRL_K210_FPIOA_H +#define PINCTRL_K210_FPIOA_H + +/* + * Full list of FPIOA functions from + * kendryte-standalone-sdk/lib/drivers/include/fpioa.h + */ +#define K210_PCF_MASK GENMASK(7, 0) +#define K210_PCF_JTAG_TCLK 0 /* JTAG Test Clock */ +#define K210_PCF_JTAG_TDI 1 /* JTAG Test Data In */ +#define K210_PCF_JTAG_TMS 2 /* JTAG Test Mode Select */ +#define K210_PCF_JTAG_TDO 3 /* JTAG Test Data Out */ +#define K210_PCF_SPI0_D0 4 /* SPI0 Data 0 */ +#define K210_PCF_SPI0_D1 5 /* SPI0 Data 1 */ +#define K210_PCF_SPI0_D2 6 /* SPI0 Data 2 */ +#define K210_PCF_SPI0_D3 7 /* SPI0 Data 3 */ +#define K210_PCF_SPI0_D4 8 /* SPI0 Data 4 */ +#define K210_PCF_SPI0_D5 9 /* SPI0 Data 5 */ +#define K210_PCF_SPI0_D6 10 /* SPI0 Data 6 */ +#define K210_PCF_SPI0_D7 11 /* SPI0 Data 7 */ +#define K210_PCF_SPI0_SS0 12 /* SPI0 Chip Select 0 */ +#define K210_PCF_SPI0_SS1 13 /* SPI0 Chip Select 1 */ +#define K210_PCF_SPI0_SS2 14 /* SPI0 Chip Select 2 */ +#define K210_PCF_SPI0_SS3 15 /* SPI0 Chip Select 3 */ +#define K210_PCF_SPI0_ARB 16 /* SPI0 Arbitration */ +#define K210_PCF_SPI0_SCLK 17 /* SPI0 Serial Clock */ +#define K210_PCF_UARTHS_RX 18 /* UART High speed Receiver */ +#define K210_PCF_UARTHS_TX 19 /* UART High speed Transmitter */ +#define K210_PCF_RESV6 20 /* Reserved function */ +#define K210_PCF_RESV7 21 /* Reserved function */ +#define K210_PCF_CLK_SPI1 22 /* Clock SPI1 */ +#define K210_PCF_CLK_I2C1 23 /* Clock I2C1 */ +#define K210_PCF_GPIOHS0 24 /* GPIO High speed 0 */ +#define K210_PCF_GPIOHS1 25 /* GPIO High speed 1 */ +#define K210_PCF_GPIOHS2 26 /* GPIO High speed 2 */ +#define K210_PCF_GPIOHS3 27 /* GPIO High speed 3 */ +#define K210_PCF_GPIOHS4 28 /* GPIO High speed 4 */ +#define K210_PCF_GPIOHS5 29 /* GPIO High speed 5 */ +#define K210_PCF_GPIOHS6 30 /* GPIO High speed 6 */ +#define K210_PCF_GPIOHS7 31 /* GPIO High speed 7 */ +#define K210_PCF_GPIOHS8 32 /* GPIO High speed 8 */ +#define K210_PCF_GPIOHS9 33 /* GPIO High speed 9 */ +#define K210_PCF_GPIOHS10 34 /* GPIO High speed 10 */ +#define K210_PCF_GPIOHS11 35 /* GPIO High speed 11 */ +#define K210_PCF_GPIOHS12 36 /* GPIO High speed 12 */ +#define K210_PCF_GPIOHS13 37 /* GPIO High speed 13 */ +#define K210_PCF_GPIOHS14 38 /* GPIO High speed 14 */ +#define K210_PCF_GPIOHS15 39 /* GPIO High speed 15 */ +#define K210_PCF_GPIOHS16 40 /* GPIO High speed 16 */ +#define K210_PCF_GPIOHS17 41 /* GPIO High speed 17 */ +#define K210_PCF_GPIOHS18 42 /* GPIO High speed 18 */ +#define K210_PCF_GPIOHS19 43 /* GPIO High speed 19 */ +#define K210_PCF_GPIOHS20 44 /* GPIO High speed 20 */ +#define K210_PCF_GPIOHS21 45 /* GPIO High speed 21 */ +#define K210_PCF_GPIOHS22 46 /* GPIO High speed 22 */ +#define K210_PCF_GPIOHS23 47 /* GPIO High speed 23 */ +#define K210_PCF_GPIOHS24 48 /* GPIO High speed 24 */ +#define K210_PCF_GPIOHS25 49 /* GPIO High speed 25 */ +#define K210_PCF_GPIOHS26 50 /* GPIO High speed 26 */ +#define K210_PCF_GPIOHS27 51 /* GPIO High speed 27 */ +#define K210_PCF_GPIOHS28 52 /* GPIO High speed 28 */ +#define K210_PCF_GPIOHS29 53 /* GPIO High speed 29 */ +#define K210_PCF_GPIOHS30 54 /* GPIO High speed 30 */ +#define K210_PCF_GPIOHS31 55 /* GPIO High speed 31 */ +#define K210_PCF_GPIO0 56 /* GPIO pin 0 */ +#define K210_PCF_GPIO1 57 /* GPIO pin 1 */ +#define K210_PCF_GPIO2 58 /* GPIO pin 2 */ +#define K210_PCF_GPIO3 59 /* GPIO pin 3 */ +#define K210_PCF_GPIO4 60 /* GPIO pin 4 */ +#define K210_PCF_GPIO5 61 /* GPIO pin 5 */ +#define K210_PCF_GPIO6 62 /* GPIO pin 6 */ +#define K210_PCF_GPIO7 63 /* GPIO pin 7 */ +#define K210_PCF_UART1_RX 64 /* UART1 Receiver */ +#define K210_PCF_UART1_TX 65 /* UART1 Transmitter */ +#define K210_PCF_UART2_RX 66 /* UART2 Receiver */ +#define K210_PCF_UART2_TX 67 /* UART2 Transmitter */ +#define K210_PCF_UART3_RX 68 /* UART3 Receiver */ +#define K210_PCF_UART3_TX 69 /* UART3 Transmitter */ +#define K210_PCF_SPI1_D0 70 /* SPI1 Data 0 */ +#define K210_PCF_SPI1_D1 71 /* SPI1 Data 1 */ +#define K210_PCF_SPI1_D2 72 /* SPI1 Data 2 */ +#define K210_PCF_SPI1_D3 73 /* SPI1 Data 3 */ +#define K210_PCF_SPI1_D4 74 /* SPI1 Data 4 */ +#define K210_PCF_SPI1_D5 75 /* SPI1 Data 5 */ +#define K210_PCF_SPI1_D6 76 /* SPI1 Data 6 */ +#define K210_PCF_SPI1_D7 77 /* SPI1 Data 7 */ +#define K210_PCF_SPI1_SS0 78 /* SPI1 Chip Select 0 */ +#define K210_PCF_SPI1_SS1 79 /* SPI1 Chip Select 1 */ +#define K210_PCF_SPI1_SS2 80 /* SPI1 Chip Select 2 */ +#define K210_PCF_SPI1_SS3 81 /* SPI1 Chip Select 3 */ +#define K210_PCF_SPI1_ARB 82 /* SPI1 Arbitration */ +#define K210_PCF_SPI1_SCLK 83 /* SPI1 Serial Clock */ +#define K210_PCF_SPI2_D0 84 /* SPI2 Data 0 */ +#define K210_PCF_SPI2_SS 85 /* SPI2 Select */ +#define K210_PCF_SPI2_SCLK 86 /* SPI2 Serial Clock */ +#define K210_PCF_I2S0_MCLK 87 /* I2S0 Master Clock */ +#define K210_PCF_I2S0_SCLK 88 /* I2S0 Serial Clock(BCLK) */ +#define K210_PCF_I2S0_WS 89 /* I2S0 Word Select(LRCLK) */ +#define K210_PCF_I2S0_IN_D0 90 /* I2S0 Serial Data Input 0 */ +#define K210_PCF_I2S0_IN_D1 91 /* I2S0 Serial Data Input 1 */ +#define K210_PCF_I2S0_IN_D2 92 /* I2S0 Serial Data Input 2 */ +#define K210_PCF_I2S0_IN_D3 93 /* I2S0 Serial Data Input 3 */ +#define K210_PCF_I2S0_OUT_D0 94 /* I2S0 Serial Data Output 0 */ +#define K210_PCF_I2S0_OUT_D1 95 /* I2S0 Serial Data Output 1 */ +#define K210_PCF_I2S0_OUT_D2 96 /* I2S0 Serial Data Output 2 */ +#define K210_PCF_I2S0_OUT_D3 97 /* I2S0 Serial Data Output 3 */ +#define K210_PCF_I2S1_MCLK 98 /* I2S1 Master Clock */ +#define K210_PCF_I2S1_SCLK 99 /* I2S1 Serial Clock(BCLK) */ +#define K210_PCF_I2S1_WS 100 /* I2S1 Word Select(LRCLK) */ +#define K210_PCF_I2S1_IN_D0 101 /* I2S1 Serial Data Input 0 */ +#define K210_PCF_I2S1_IN_D1 102 /* I2S1 Serial Data Input 1 */ +#define K210_PCF_I2S1_IN_D2 103 /* I2S1 Serial Data Input 2 */ +#define K210_PCF_I2S1_IN_D3 104 /* I2S1 Serial Data Input 3 */ +#define K210_PCF_I2S1_OUT_D0 105 /* I2S1 Serial Data Output 0 */ +#define K210_PCF_I2S1_OUT_D1 106 /* I2S1 Serial Data Output 1 */ +#define K210_PCF_I2S1_OUT_D2 107 /* I2S1 Serial Data Output 2 */ +#define K210_PCF_I2S1_OUT_D3 108 /* I2S1 Serial Data Output 3 */ +#define K210_PCF_I2S2_MCLK 109 /* I2S2 Master Clock */ +#define K210_PCF_I2S2_SCLK 110 /* I2S2 Serial Clock(BCLK) */ +#define K210_PCF_I2S2_WS 111 /* I2S2 Word Select(LRCLK) */ +#define K210_PCF_I2S2_IN_D0 112 /* I2S2 Serial Data Input 0 */ +#define K210_PCF_I2S2_IN_D1 113 /* I2S2 Serial Data Input 1 */ +#define K210_PCF_I2S2_IN_D2 114 /* I2S2 Serial Data Input 2 */ +#define K210_PCF_I2S2_IN_D3 115 /* I2S2 Serial Data Input 3 */ +#define K210_PCF_I2S2_OUT_D0 116 /* I2S2 Serial Data Output 0 */ +#define K210_PCF_I2S2_OUT_D1 117 /* I2S2 Serial Data Output 1 */ +#define K210_PCF_I2S2_OUT_D2 118 /* I2S2 Serial Data Output 2 */ +#define K210_PCF_I2S2_OUT_D3 119 /* I2S2 Serial Data Output 3 */ +#define K210_PCF_RESV0 120 /* Reserved function */ +#define K210_PCF_RESV1 121 /* Reserved function */ +#define K210_PCF_RESV2 122 /* Reserved function */ +#define K210_PCF_RESV3 123 /* Reserved function */ +#define K210_PCF_RESV4 124 /* Reserved function */ +#define K210_PCF_RESV5 125 /* Reserved function */ +#define K210_PCF_I2C0_SCLK 126 /* I2C0 Serial Clock */ +#define K210_PCF_I2C0_SDA 127 /* I2C0 Serial Data */ +#define K210_PCF_I2C1_SCLK 128 /* I2C1 Serial Clock */ +#define K210_PCF_I2C1_SDA 129 /* I2C1 Serial Data */ +#define K210_PCF_I2C2_SCLK 130 /* I2C2 Serial Clock */ +#define K210_PCF_I2C2_SDA 131 /* I2C2 Serial Data */ +#define K210_PCF_DVP_XCLK 132 /* DVP System Clock */ +#define K210_PCF_DVP_RST 133 /* DVP System Reset */ +#define K210_PCF_DVP_PWDN 134 /* DVP Power Down Mode */ +#define K210_PCF_DVP_VSYNC 135 /* DVP Vertical Sync */ +#define K210_PCF_DVP_HSYNC 136 /* DVP Horizontal Sync */ +#define K210_PCF_DVP_PCLK 137 /* Pixel Clock */ +#define K210_PCF_DVP_D0 138 /* Data Bit 0 */ +#define K210_PCF_DVP_D1 139 /* Data Bit 1 */ +#define K210_PCF_DVP_D2 140 /* Data Bit 2 */ +#define K210_PCF_DVP_D3 141 /* Data Bit 3 */ +#define K210_PCF_DVP_D4 142 /* Data Bit 4 */ +#define K210_PCF_DVP_D5 143 /* Data Bit 5 */ +#define K210_PCF_DVP_D6 144 /* Data Bit 6 */ +#define K210_PCF_DVP_D7 145 /* Data Bit 7 */ +#define K210_PCF_SCCB_SCLK 146 /* Serial Camera Control Bus Clock */ +#define K210_PCF_SCCB_SDA 147 /* Serial Camera Control Bus Data */ +#define K210_PCF_UART1_CTS 148 /* UART1 Clear To Send */ +#define K210_PCF_UART1_DSR 149 /* UART1 Data Set Ready */ +#define K210_PCF_UART1_DCD 150 /* UART1 Data Carrier Detect */ +#define K210_PCF_UART1_RI 151 /* UART1 Ring Indicator */ +#define K210_PCF_UART1_SIR_IN 152 /* UART1 Serial Infrared Input */ +#define K210_PCF_UART1_DTR 153 /* UART1 Data Terminal Ready */ +#define K210_PCF_UART1_RTS 154 /* UART1 Request To Send */ +#define K210_PCF_UART1_OUT2 155 /* UART1 User-designated Output 2 */ +#define K210_PCF_UART1_OUT1 156 /* UART1 User-designated Output 1 */ +#define K210_PCF_UART1_SIR_OUT 157 /* UART1 Serial Infrared Output */ +#define K210_PCF_UART1_BAUD 158 /* UART1 Transmit Clock Output */ +#define K210_PCF_UART1_RE 159 /* UART1 Receiver Output Enable */ +#define K210_PCF_UART1_DE 160 /* UART1 Driver Output Enable */ +#define K210_PCF_UART1_RS485_EN 161 /* UART1 RS485 Enable */ +#define K210_PCF_UART2_CTS 162 /* UART2 Clear To Send */ +#define K210_PCF_UART2_DSR 163 /* UART2 Data Set Ready */ +#define K210_PCF_UART2_DCD 164 /* UART2 Data Carrier Detect */ +#define K210_PCF_UART2_RI 165 /* UART2 Ring Indicator */ +#define K210_PCF_UART2_SIR_IN 166 /* UART2 Serial Infrared Input */ +#define K210_PCF_UART2_DTR 167 /* UART2 Data Terminal Ready */ +#define K210_PCF_UART2_RTS 168 /* UART2 Request To Send */ +#define K210_PCF_UART2_OUT2 169 /* UART2 User-designated Output 2 */ +#define K210_PCF_UART2_OUT1 170 /* UART2 User-designated Output 1 */ +#define K210_PCF_UART2_SIR_OUT 171 /* UART2 Serial Infrared Output */ +#define K210_PCF_UART2_BAUD 172 /* UART2 Transmit Clock Output */ +#define K210_PCF_UART2_RE 173 /* UART2 Receiver Output Enable */ +#define K210_PCF_UART2_DE 174 /* UART2 Driver Output Enable */ +#define K210_PCF_UART2_RS485_EN 175 /* UART2 RS485 Enable */ +#define K210_PCF_UART3_CTS 176 /* UART3 Clear To Send */ +#define K210_PCF_UART3_DSR 177 /* UART3 Data Set Ready */ +#define K210_PCF_UART3_DCD 178 /* UART3 Data Carrier Detect */ +#define K210_PCF_UART3_RI 179 /* UART3 Ring Indicator */ +#define K210_PCF_UART3_SIR_IN 180 /* UART3 Serial Infrared Input */ +#define K210_PCF_UART3_DTR 181 /* UART3 Data Terminal Ready */ +#define K210_PCF_UART3_RTS 182 /* UART3 Request To Send */ +#define K210_PCF_UART3_OUT2 183 /* UART3 User-designated Output 2 */ +#define K210_PCF_UART3_OUT1 184 /* UART3 User-designated Output 1 */ +#define K210_PCF_UART3_SIR_OUT 185 /* UART3 Serial Infrared Output */ +#define K210_PCF_UART3_BAUD 186 /* UART3 Transmit Clock Output */ +#define K210_PCF_UART3_RE 187 /* UART3 Receiver Output Enable */ +#define K210_PCF_UART3_DE 188 /* UART3 Driver Output Enable */ +#define K210_PCF_UART3_RS485_EN 189 /* UART3 RS485 Enable */ +#define K210_PCF_TIMER0_TOGGLE1 190 /* TIMER0 Toggle Output 1 */ +#define K210_PCF_TIMER0_TOGGLE2 191 /* TIMER0 Toggle Output 2 */ +#define K210_PCF_TIMER0_TOGGLE3 192 /* TIMER0 Toggle Output 3 */ +#define K210_PCF_TIMER0_TOGGLE4 193 /* TIMER0 Toggle Output 4 */ +#define K210_PCF_TIMER1_TOGGLE1 194 /* TIMER1 Toggle Output 1 */ +#define K210_PCF_TIMER1_TOGGLE2 195 /* TIMER1 Toggle Output 2 */ +#define K210_PCF_TIMER1_TOGGLE3 196 /* TIMER1 Toggle Output 3 */ +#define K210_PCF_TIMER1_TOGGLE4 197 /* TIMER1 Toggle Output 4 */ +#define K210_PCF_TIMER2_TOGGLE1 198 /* TIMER2 Toggle Output 1 */ +#define K210_PCF_TIMER2_TOGGLE2 199 /* TIMER2 Toggle Output 2 */ +#define K210_PCF_TIMER2_TOGGLE3 200 /* TIMER2 Toggle Output 3 */ +#define K210_PCF_TIMER2_TOGGLE4 201 /* TIMER2 Toggle Output 4 */ +#define K210_PCF_CLK_SPI2 202 /* Clock SPI2 */ +#define K210_PCF_CLK_I2C2 203 /* Clock I2C2 */ +#define K210_PCF_INTERNAL0 204 /* Internal function signal 0 */ +#define K210_PCF_INTERNAL1 205 /* Internal function signal 1 */ +#define K210_PCF_INTERNAL2 206 /* Internal function signal 2 */ +#define K210_PCF_INTERNAL3 207 /* Internal function signal 3 */ +#define K210_PCF_INTERNAL4 208 /* Internal function signal 4 */ +#define K210_PCF_INTERNAL5 209 /* Internal function signal 5 */ +#define K210_PCF_INTERNAL6 210 /* Internal function signal 6 */ +#define K210_PCF_INTERNAL7 211 /* Internal function signal 7 */ +#define K210_PCF_INTERNAL8 212 /* Internal function signal 8 */ +#define K210_PCF_INTERNAL9 213 /* Internal function signal 9 */ +#define K210_PCF_INTERNAL10 214 /* Internal function signal 10 */ +#define K210_PCF_INTERNAL11 215 /* Internal function signal 11 */ +#define K210_PCF_INTERNAL12 216 /* Internal function signal 12 */ +#define K210_PCF_INTERNAL13 217 /* Internal function signal 13 */ +#define K210_PCF_INTERNAL14 218 /* Internal function signal 14 */ +#define K210_PCF_INTERNAL15 219 /* Internal function signal 15 */ +#define K210_PCF_INTERNAL16 220 /* Internal function signal 16 */ +#define K210_PCF_INTERNAL17 221 /* Internal function signal 17 */ +#define K210_PCF_CONSTANT 222 /* Constant function */ +#define K210_PCF_INTERNAL18 223 /* Internal function signal 18 */ +#define K210_PCF_DEBUG0 224 /* Debug function 0 */ +#define K210_PCF_DEBUG1 225 /* Debug function 1 */ +#define K210_PCF_DEBUG2 226 /* Debug function 2 */ +#define K210_PCF_DEBUG3 227 /* Debug function 3 */ +#define K210_PCF_DEBUG4 228 /* Debug function 4 */ +#define K210_PCF_DEBUG5 229 /* Debug function 5 */ +#define K210_PCF_DEBUG6 230 /* Debug function 6 */ +#define K210_PCF_DEBUG7 231 /* Debug function 7 */ +#define K210_PCF_DEBUG8 232 /* Debug function 8 */ +#define K210_PCF_DEBUG9 233 /* Debug function 9 */ +#define K210_PCF_DEBUG10 234 /* Debug function 10 */ +#define K210_PCF_DEBUG11 235 /* Debug function 11 */ +#define K210_PCF_DEBUG12 236 /* Debug function 12 */ +#define K210_PCF_DEBUG13 237 /* Debug function 13 */ +#define K210_PCF_DEBUG14 238 /* Debug function 14 */ +#define K210_PCF_DEBUG15 239 /* Debug function 15 */ +#define K210_PCF_DEBUG16 240 /* Debug function 16 */ +#define K210_PCF_DEBUG17 241 /* Debug function 17 */ +#define K210_PCF_DEBUG18 242 /* Debug function 18 */ +#define K210_PCF_DEBUG19 243 /* Debug function 19 */ +#define K210_PCF_DEBUG20 244 /* Debug function 20 */ +#define K210_PCF_DEBUG21 245 /* Debug function 21 */ +#define K210_PCF_DEBUG22 246 /* Debug function 22 */ +#define K210_PCF_DEBUG23 247 /* Debug function 23 */ +#define K210_PCF_DEBUG24 248 /* Debug function 24 */ +#define K210_PCF_DEBUG25 249 /* Debug function 25 */ +#define K210_PCF_DEBUG26 250 /* Debug function 26 */ +#define K210_PCF_DEBUG27 251 /* Debug function 27 */ +#define K210_PCF_DEBUG28 252 /* Debug function 28 */ +#define K210_PCF_DEBUG29 253 /* Debug function 29 */ +#define K210_PCF_DEBUG30 254 /* Debug function 30 */ +#define K210_PCF_DEBUG31 255 /* Debug function 31 */ + +#define K210_FPIOA(pin, func) (((pin) << 16) | (func)) + +#define K210_PC_POWER_3V3 0 +#define K210_PC_POWER_1V8 1 + +#endif /* PINCTRL_K210_FPIOA_H */ diff --git a/include/dt-bindings/pinctrl/k3.h b/include/dt-bindings/pinctrl/k3.h index 499de6216581..54df633f9bfe 100644 --- a/include/dt-bindings/pinctrl/k3.h +++ b/include/dt-bindings/pinctrl/k3.h @@ -3,7 +3,7 @@ * This header provides constants for pinctrl bindings for TI's K3 SoC * family. * - * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef _DT_BINDINGS_PINCTRL_TI_K3_H #define _DT_BINDINGS_PINCTRL_TI_K3_H @@ -29,10 +29,22 @@ #define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) #define PIN_INPUT_PULLDOWN (INPUT_EN | PULL_DOWN) +#define AM62AX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define AM62AX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + +#define AM62X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define AM62X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + +#define AM64X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define AM64X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + #define AM65X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) #define AM65X_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) #define J721E_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) #define J721E_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define J721S2_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define J721S2_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + #endif diff --git a/include/dt-bindings/pinctrl/keystone.h b/include/dt-bindings/pinctrl/keystone.h index 7f97d776a8ff..66f8aecada53 100644 --- a/include/dt-bindings/pinctrl/keystone.h +++ b/include/dt-bindings/pinctrl/keystone.h @@ -1,16 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * This header provides constants for Keystone pinctrl bindings. * * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #ifndef _DT_BINDINGS_PINCTRL_KEYSTONE_H diff --git a/include/dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h b/include/dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h new file mode 100644 index 000000000000..2688da2f621f --- /dev/null +++ b/include/dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h @@ -0,0 +1,1280 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2022 MediaTek Inc. + * Author: Hui Liu <hui.liu@mediatek.com> + */ + +#ifndef __MEDIATEK_MT8188_PINFUNC_H +#define __MEDIATEK_MT8188_PINFUNC_H + +#include "mt65xx.h" + +#define PINMUX_GPIO0__FUNC_B_GPIO0 (MTK_PIN_NO(0) | 0) +#define PINMUX_GPIO0__FUNC_B0_TP_GPIO0_AO (MTK_PIN_NO(0) | 1) +#define PINMUX_GPIO0__FUNC_O_SPIM5_CSB (MTK_PIN_NO(0) | 2) +#define PINMUX_GPIO0__FUNC_O_UTXD1 (MTK_PIN_NO(0) | 3) +#define PINMUX_GPIO0__FUNC_O_DMIC3_CLK (MTK_PIN_NO(0) | 4) +#define PINMUX_GPIO0__FUNC_B0_I2SIN_MCK (MTK_PIN_NO(0) | 5) +#define PINMUX_GPIO0__FUNC_O_I2SO2_MCK (MTK_PIN_NO(0) | 6) +#define PINMUX_GPIO0__FUNC_B0_DBG_MON_A0 (MTK_PIN_NO(0) | 7) + +#define PINMUX_GPIO1__FUNC_B_GPIO1 (MTK_PIN_NO(1) | 0) +#define PINMUX_GPIO1__FUNC_B0_TP_GPIO1_AO (MTK_PIN_NO(1) | 1) +#define PINMUX_GPIO1__FUNC_O_SPIM5_CLK (MTK_PIN_NO(1) | 2) +#define PINMUX_GPIO1__FUNC_I1_URXD1 (MTK_PIN_NO(1) | 3) +#define PINMUX_GPIO1__FUNC_I0_DMIC3_DAT (MTK_PIN_NO(1) | 4) +#define PINMUX_GPIO1__FUNC_B0_I2SIN_BCK (MTK_PIN_NO(1) | 5) +#define PINMUX_GPIO1__FUNC_B0_I2SO2_BCK (MTK_PIN_NO(1) | 6) +#define PINMUX_GPIO1__FUNC_B0_DBG_MON_A1 (MTK_PIN_NO(1) | 7) + +#define PINMUX_GPIO2__FUNC_B_GPIO2 (MTK_PIN_NO(2) | 0) +#define PINMUX_GPIO2__FUNC_B0_TP_GPIO2_AO (MTK_PIN_NO(2) | 1) +#define PINMUX_GPIO2__FUNC_B0_SPIM5_MOSI (MTK_PIN_NO(2) | 2) +#define PINMUX_GPIO2__FUNC_O_URTS1 (MTK_PIN_NO(2) | 3) +#define PINMUX_GPIO2__FUNC_I0_DMIC3_DAT_R (MTK_PIN_NO(2) | 4) +#define PINMUX_GPIO2__FUNC_B0_I2SIN_WS (MTK_PIN_NO(2) | 5) +#define PINMUX_GPIO2__FUNC_B0_I2SO2_WS (MTK_PIN_NO(2) | 6) +#define PINMUX_GPIO2__FUNC_B0_DBG_MON_A2 (MTK_PIN_NO(2) | 7) + +#define PINMUX_GPIO3__FUNC_B_GPIO3 (MTK_PIN_NO(3) | 0) +#define PINMUX_GPIO3__FUNC_B0_TP_GPIO3_AO (MTK_PIN_NO(3) | 1) +#define PINMUX_GPIO3__FUNC_B0_SPIM5_MISO (MTK_PIN_NO(3) | 2) +#define PINMUX_GPIO3__FUNC_I1_UCTS1 (MTK_PIN_NO(3) | 3) +#define PINMUX_GPIO3__FUNC_O_DMIC4_CLK (MTK_PIN_NO(3) | 4) +#define PINMUX_GPIO3__FUNC_I0_I2SIN_D0 (MTK_PIN_NO(3) | 5) +#define PINMUX_GPIO3__FUNC_O_I2SO2_D0 (MTK_PIN_NO(3) | 6) +#define PINMUX_GPIO3__FUNC_B0_DBG_MON_A3 (MTK_PIN_NO(3) | 7) + +#define PINMUX_GPIO4__FUNC_B_GPIO4 (MTK_PIN_NO(4) | 0) +#define PINMUX_GPIO4__FUNC_B0_TP_GPIO4_AO (MTK_PIN_NO(4) | 1) +#define PINMUX_GPIO4__FUNC_I0_SPDIF_IN2 (MTK_PIN_NO(4) | 2) +#define PINMUX_GPIO4__FUNC_O_I2SO1_MCK (MTK_PIN_NO(4) | 3) +#define PINMUX_GPIO4__FUNC_I0_DMIC4_DAT (MTK_PIN_NO(4) | 4) +#define PINMUX_GPIO4__FUNC_I0_I2SIN_D1 (MTK_PIN_NO(4) | 5) +#define PINMUX_GPIO4__FUNC_O_I2SO2_D1 (MTK_PIN_NO(4) | 6) +#define PINMUX_GPIO4__FUNC_B0_DBG_MON_A4 (MTK_PIN_NO(4) | 7) + +#define PINMUX_GPIO5__FUNC_B_GPIO5 (MTK_PIN_NO(5) | 0) +#define PINMUX_GPIO5__FUNC_B0_TP_GPIO5_AO (MTK_PIN_NO(5) | 1) +#define PINMUX_GPIO5__FUNC_I0_SPDIF_IN1 (MTK_PIN_NO(5) | 2) +#define PINMUX_GPIO5__FUNC_O_I2SO1_BCK (MTK_PIN_NO(5) | 3) +#define PINMUX_GPIO5__FUNC_I0_DMIC4_DAT_R (MTK_PIN_NO(5) | 4) +#define PINMUX_GPIO5__FUNC_I0_I2SIN_D2 (MTK_PIN_NO(5) | 5) +#define PINMUX_GPIO5__FUNC_O_I2SO2_D2 (MTK_PIN_NO(5) | 6) +#define PINMUX_GPIO5__FUNC_B0_DBG_MON_A5 (MTK_PIN_NO(5) | 7) + +#define PINMUX_GPIO6__FUNC_B_GPIO6 (MTK_PIN_NO(6) | 0) +#define PINMUX_GPIO6__FUNC_B0_TP_GPIO6_AO (MTK_PIN_NO(6) | 1) +#define PINMUX_GPIO6__FUNC_I0_SPDIF_IN0 (MTK_PIN_NO(6) | 2) +#define PINMUX_GPIO6__FUNC_O_I2SO1_WS (MTK_PIN_NO(6) | 3) +#define PINMUX_GPIO6__FUNC_O_DMIC1_CLK (MTK_PIN_NO(6) | 4) +#define PINMUX_GPIO6__FUNC_I0_I2SIN_D3 (MTK_PIN_NO(6) | 5) +#define PINMUX_GPIO6__FUNC_O_I2SO2_D3 (MTK_PIN_NO(6) | 6) +#define PINMUX_GPIO6__FUNC_B0_MD32_0_GPIO0 (MTK_PIN_NO(6) | 7) + +#define PINMUX_GPIO7__FUNC_B_GPIO7 (MTK_PIN_NO(7) | 0) +#define PINMUX_GPIO7__FUNC_B0_TP_GPIO7_AO (MTK_PIN_NO(7) | 1) +#define PINMUX_GPIO7__FUNC_O_SPIM3_CSB (MTK_PIN_NO(7) | 2) +#define PINMUX_GPIO7__FUNC_B0_TDMIN_MCK (MTK_PIN_NO(7) | 3) +#define PINMUX_GPIO7__FUNC_I0_DMIC1_DAT (MTK_PIN_NO(7) | 4) +#define PINMUX_GPIO7__FUNC_O_CMVREF0 (MTK_PIN_NO(7) | 5) +#define PINMUX_GPIO7__FUNC_O_CLKM0 (MTK_PIN_NO(7) | 6) +#define PINMUX_GPIO7__FUNC_B0_DBG_MON_A6 (MTK_PIN_NO(7) | 7) + +#define PINMUX_GPIO8__FUNC_B_GPIO8 (MTK_PIN_NO(8) | 0) +#define PINMUX_GPIO8__FUNC_B0_TP_GPIO0_AO (MTK_PIN_NO(8) | 1) +#define PINMUX_GPIO8__FUNC_O_SPIM3_CLK (MTK_PIN_NO(8) | 2) +#define PINMUX_GPIO8__FUNC_B0_TDMIN_BCK (MTK_PIN_NO(8) | 3) +#define PINMUX_GPIO8__FUNC_I0_DMIC1_DAT_R (MTK_PIN_NO(8) | 4) +#define PINMUX_GPIO8__FUNC_O_CMVREF1 (MTK_PIN_NO(8) | 5) +#define PINMUX_GPIO8__FUNC_O_CLKM1 (MTK_PIN_NO(8) | 6) +#define PINMUX_GPIO8__FUNC_B0_DBG_MON_A7 (MTK_PIN_NO(8) | 7) + +#define PINMUX_GPIO9__FUNC_B_GPIO9 (MTK_PIN_NO(9) | 0) +#define PINMUX_GPIO9__FUNC_B0_TP_GPIO1_AO (MTK_PIN_NO(9) | 1) +#define PINMUX_GPIO9__FUNC_B0_SPIM3_MOSI (MTK_PIN_NO(9) | 2) +#define PINMUX_GPIO9__FUNC_B0_TDMIN_LRCK (MTK_PIN_NO(9) | 3) +#define PINMUX_GPIO9__FUNC_O_DMIC2_CLK (MTK_PIN_NO(9) | 4) +#define PINMUX_GPIO9__FUNC_O_CMFLASH0 (MTK_PIN_NO(9) | 5) +#define PINMUX_GPIO9__FUNC_O_PWM_0 (MTK_PIN_NO(9) | 6) +#define PINMUX_GPIO9__FUNC_B0_DBG_MON_A8 (MTK_PIN_NO(9) | 7) + +#define PINMUX_GPIO10__FUNC_B_GPIO10 (MTK_PIN_NO(10) | 0) +#define PINMUX_GPIO10__FUNC_B0_TP_GPIO2_AO (MTK_PIN_NO(10) | 1) +#define PINMUX_GPIO10__FUNC_B0_SPIM3_MISO (MTK_PIN_NO(10) | 2) +#define PINMUX_GPIO10__FUNC_I0_TDMIN_DI (MTK_PIN_NO(10) | 3) +#define PINMUX_GPIO10__FUNC_I0_DMIC2_DAT (MTK_PIN_NO(10) | 4) +#define PINMUX_GPIO10__FUNC_O_CMFLASH1 (MTK_PIN_NO(10) | 5) +#define PINMUX_GPIO10__FUNC_O_PWM_1 (MTK_PIN_NO(10) | 6) +#define PINMUX_GPIO10__FUNC_B0_DBG_MON_A9 (MTK_PIN_NO(10) | 7) + +#define PINMUX_GPIO11__FUNC_B_GPIO11 (MTK_PIN_NO(11) | 0) +#define PINMUX_GPIO11__FUNC_B0_TP_GPIO3_AO (MTK_PIN_NO(11) | 1) +#define PINMUX_GPIO11__FUNC_O_SPDIF_OUT (MTK_PIN_NO(11) | 2) +#define PINMUX_GPIO11__FUNC_O_I2SO1_D0 (MTK_PIN_NO(11) | 3) +#define PINMUX_GPIO11__FUNC_I0_DMIC2_DAT_R (MTK_PIN_NO(11) | 4) +#define PINMUX_GPIO11__FUNC_I0_DVFSRC_EXT_REQ (MTK_PIN_NO(11) | 5) +#define PINMUX_GPIO11__FUNC_O_CMVREF6 (MTK_PIN_NO(11) | 6) +#define PINMUX_GPIO11__FUNC_B0_DBG_MON_A10 (MTK_PIN_NO(11) | 7) + +#define PINMUX_GPIO12__FUNC_B_GPIO12 (MTK_PIN_NO(12) | 0) +#define PINMUX_GPIO12__FUNC_B0_TP_GPIO4_AO (MTK_PIN_NO(12) | 1) +#define PINMUX_GPIO12__FUNC_O_SPIM4_CSB (MTK_PIN_NO(12) | 2) +#define PINMUX_GPIO12__FUNC_B1_JTMS_SEL3 (MTK_PIN_NO(12) | 3) +#define PINMUX_GPIO12__FUNC_B1_APU_JTAG_TMS (MTK_PIN_NO(12) | 4) +#define PINMUX_GPIO12__FUNC_I0_VPU_UDI_TMS (MTK_PIN_NO(12) | 5) +#define PINMUX_GPIO12__FUNC_I0_IPU_JTAG_TMS (MTK_PIN_NO(12) | 6) +#define PINMUX_GPIO12__FUNC_I0_HDMITX20_HTPLG (MTK_PIN_NO(12) | 7) + +#define PINMUX_GPIO13__FUNC_B_GPIO13 (MTK_PIN_NO(13) | 0) +#define PINMUX_GPIO13__FUNC_B0_TP_GPIO5_AO (MTK_PIN_NO(13) | 1) +#define PINMUX_GPIO13__FUNC_O_SPIM4_CLK (MTK_PIN_NO(13) | 2) +#define PINMUX_GPIO13__FUNC_I0_JTCK_SEL3 (MTK_PIN_NO(13) | 3) +#define PINMUX_GPIO13__FUNC_I0_APU_JTAG_TCK (MTK_PIN_NO(13) | 4) +#define PINMUX_GPIO13__FUNC_I0_VPU_UDI_TCK (MTK_PIN_NO(13) | 5) +#define PINMUX_GPIO13__FUNC_I0_IPU_JTAG_TCK (MTK_PIN_NO(13) | 6) +#define PINMUX_GPIO13__FUNC_B1_HDMITX20_CEC (MTK_PIN_NO(13) | 7) + +#define PINMUX_GPIO14__FUNC_B_GPIO14 (MTK_PIN_NO(14) | 0) +#define PINMUX_GPIO14__FUNC_B0_TP_GPIO6_AO (MTK_PIN_NO(14) | 1) +#define PINMUX_GPIO14__FUNC_B0_SPIM4_MOSI (MTK_PIN_NO(14) | 2) +#define PINMUX_GPIO14__FUNC_I1_JTDI_SEL3 (MTK_PIN_NO(14) | 3) +#define PINMUX_GPIO14__FUNC_I1_APU_JTAG_TDI (MTK_PIN_NO(14) | 4) +#define PINMUX_GPIO14__FUNC_I0_VPU_UDI_TDI (MTK_PIN_NO(14) | 5) +#define PINMUX_GPIO14__FUNC_I0_IPU_JTAG_TDI (MTK_PIN_NO(14) | 6) +#define PINMUX_GPIO14__FUNC_B1_HDMITX20_SCL (MTK_PIN_NO(14) | 7) + +#define PINMUX_GPIO15__FUNC_B_GPIO15 (MTK_PIN_NO(15) | 0) +#define PINMUX_GPIO15__FUNC_B0_TP_GPIO7_AO (MTK_PIN_NO(15) | 1) +#define PINMUX_GPIO15__FUNC_B0_SPIM4_MISO (MTK_PIN_NO(15) | 2) +#define PINMUX_GPIO15__FUNC_O_JTDO_SEL3 (MTK_PIN_NO(15) | 3) +#define PINMUX_GPIO15__FUNC_O_APU_JTAG_TDO (MTK_PIN_NO(15) | 4) +#define PINMUX_GPIO15__FUNC_O_VPU_UDI_TDO (MTK_PIN_NO(15) | 5) +#define PINMUX_GPIO15__FUNC_O_IPU_JTAG_TDO (MTK_PIN_NO(15) | 6) +#define PINMUX_GPIO15__FUNC_B1_HDMITX20_SDA (MTK_PIN_NO(15) | 7) + +#define PINMUX_GPIO16__FUNC_B_GPIO16 (MTK_PIN_NO(16) | 0) +#define PINMUX_GPIO16__FUNC_B0_TP_GPIO0_AO (MTK_PIN_NO(16) | 1) +#define PINMUX_GPIO16__FUNC_O_UTXD3 (MTK_PIN_NO(16) | 2) +#define PINMUX_GPIO16__FUNC_I1_JTRSTn_SEL3 (MTK_PIN_NO(16) | 3) +#define PINMUX_GPIO16__FUNC_I0_APU_JTAG_TRST (MTK_PIN_NO(16) | 4) +#define PINMUX_GPIO16__FUNC_I0_VPU_UDI_NTRST (MTK_PIN_NO(16) | 5) +#define PINMUX_GPIO16__FUNC_I0_IPU_JTAG_TRST (MTK_PIN_NO(16) | 6) +#define PINMUX_GPIO16__FUNC_O_HDMITX20_PWR5V (MTK_PIN_NO(16) | 7) + +#define PINMUX_GPIO17__FUNC_B_GPIO17 (MTK_PIN_NO(17) | 0) +#define PINMUX_GPIO17__FUNC_B0_TP_GPIO1_AO (MTK_PIN_NO(17) | 1) +#define PINMUX_GPIO17__FUNC_I1_URXD3 (MTK_PIN_NO(17) | 2) +#define PINMUX_GPIO17__FUNC_O_CMFLASH2 (MTK_PIN_NO(17) | 3) +#define PINMUX_GPIO17__FUNC_I0_EDP_TX_HPD (MTK_PIN_NO(17) | 4) +#define PINMUX_GPIO17__FUNC_I0_DVFSRC_EXT_REQ (MTK_PIN_NO(17) | 5) +#define PINMUX_GPIO17__FUNC_O_CMVREF7 (MTK_PIN_NO(17) | 6) +#define PINMUX_GPIO17__FUNC_B0_MD32_0_GPIO1 (MTK_PIN_NO(17) | 7) + +#define PINMUX_GPIO18__FUNC_B_GPIO18 (MTK_PIN_NO(18) | 0) +#define PINMUX_GPIO18__FUNC_B0_TP_GPIO2_AO (MTK_PIN_NO(18) | 1) +#define PINMUX_GPIO18__FUNC_O_CMFLASH0 (MTK_PIN_NO(18) | 2) +#define PINMUX_GPIO18__FUNC_O_CMVREF4 (MTK_PIN_NO(18) | 3) +#define PINMUX_GPIO18__FUNC_B0_TDMIN_MCK (MTK_PIN_NO(18) | 4) +#define PINMUX_GPIO18__FUNC_O_UTXD1 (MTK_PIN_NO(18) | 5) +#define PINMUX_GPIO18__FUNC_O_TP_UTXD1_AO (MTK_PIN_NO(18) | 6) +#define PINMUX_GPIO18__FUNC_B0_DBG_MON_A11 (MTK_PIN_NO(18) | 7) + +#define PINMUX_GPIO19__FUNC_B_GPIO19 (MTK_PIN_NO(19) | 0) +#define PINMUX_GPIO19__FUNC_B0_TP_GPIO3_AO (MTK_PIN_NO(19) | 1) +#define PINMUX_GPIO19__FUNC_O_CMFLASH1 (MTK_PIN_NO(19) | 2) +#define PINMUX_GPIO19__FUNC_O_CMVREF5 (MTK_PIN_NO(19) | 3) +#define PINMUX_GPIO19__FUNC_B0_TDMIN_BCK (MTK_PIN_NO(19) | 4) +#define PINMUX_GPIO19__FUNC_I1_URXD1 (MTK_PIN_NO(19) | 5) +#define PINMUX_GPIO19__FUNC_I1_TP_URXD1_AO (MTK_PIN_NO(19) | 6) +#define PINMUX_GPIO19__FUNC_B0_DBG_MON_A12 (MTK_PIN_NO(19) | 7) + +#define PINMUX_GPIO20__FUNC_B_GPIO20 (MTK_PIN_NO(20) | 0) +#define PINMUX_GPIO20__FUNC_B0_TP_GPIO4_AO (MTK_PIN_NO(20) | 1) +#define PINMUX_GPIO20__FUNC_O_CMFLASH2 (MTK_PIN_NO(20) | 2) +#define PINMUX_GPIO20__FUNC_O_CLKM2 (MTK_PIN_NO(20) | 3) +#define PINMUX_GPIO20__FUNC_B0_TDMIN_LRCK (MTK_PIN_NO(20) | 4) +#define PINMUX_GPIO20__FUNC_O_URTS1 (MTK_PIN_NO(20) | 5) +#define PINMUX_GPIO20__FUNC_O_TP_URTS1_AO (MTK_PIN_NO(20) | 6) +#define PINMUX_GPIO20__FUNC_B0_DBG_MON_A13 (MTK_PIN_NO(20) | 7) + +#define PINMUX_GPIO21__FUNC_B_GPIO21 (MTK_PIN_NO(21) | 0) +#define PINMUX_GPIO21__FUNC_B0_TP_GPIO5_AO (MTK_PIN_NO(21) | 1) +#define PINMUX_GPIO21__FUNC_O_CMFLASH3 (MTK_PIN_NO(21) | 2) +#define PINMUX_GPIO21__FUNC_O_CLKM3 (MTK_PIN_NO(21) | 3) +#define PINMUX_GPIO21__FUNC_I0_TDMIN_DI (MTK_PIN_NO(21) | 4) +#define PINMUX_GPIO21__FUNC_I1_UCTS1 (MTK_PIN_NO(21) | 5) +#define PINMUX_GPIO21__FUNC_I1_TP_UCTS1_AO (MTK_PIN_NO(21) | 6) +#define PINMUX_GPIO21__FUNC_B0_DBG_MON_A14 (MTK_PIN_NO(21) | 7) + +#define PINMUX_GPIO22__FUNC_B_GPIO22 (MTK_PIN_NO(22) | 0) +#define PINMUX_GPIO22__FUNC_O_CMMCLK0 (MTK_PIN_NO(22) | 1) +#define PINMUX_GPIO22__FUNC_B0_TP_GPIO6_AO (MTK_PIN_NO(22) | 5) +#define PINMUX_GPIO22__FUNC_B0_DBG_MON_A15 (MTK_PIN_NO(22) | 7) + +#define PINMUX_GPIO23__FUNC_B_GPIO23 (MTK_PIN_NO(23) | 0) +#define PINMUX_GPIO23__FUNC_O_CMMCLK1 (MTK_PIN_NO(23) | 1) +#define PINMUX_GPIO23__FUNC_O_PWM_2 (MTK_PIN_NO(23) | 3) +#define PINMUX_GPIO23__FUNC_B1_PCIE_PHY_I2C_SCL (MTK_PIN_NO(23) | 4) +#define PINMUX_GPIO23__FUNC_B0_TP_GPIO7_AO (MTK_PIN_NO(23) | 5) +#define PINMUX_GPIO23__FUNC_I0_DP_TX_HPD (MTK_PIN_NO(23) | 6) +#define PINMUX_GPIO23__FUNC_B0_DBG_MON_A16 (MTK_PIN_NO(23) | 7) + +#define PINMUX_GPIO24__FUNC_B_GPIO24 (MTK_PIN_NO(24) | 0) +#define PINMUX_GPIO24__FUNC_O_CMMCLK2 (MTK_PIN_NO(24) | 1) +#define PINMUX_GPIO24__FUNC_O_PWM_3 (MTK_PIN_NO(24) | 3) +#define PINMUX_GPIO24__FUNC_B1_PCIE_PHY_I2C_SDA (MTK_PIN_NO(24) | 4) +#define PINMUX_GPIO24__FUNC_I0_DVFSRC_EXT_REQ (MTK_PIN_NO(24) | 5) +#define PINMUX_GPIO24__FUNC_I0_EDP_TX_HPD (MTK_PIN_NO(24) | 6) +#define PINMUX_GPIO24__FUNC_B0_MD32_0_GPIO2 (MTK_PIN_NO(24) | 7) + +#define PINMUX_GPIO25__FUNC_B_GPIO25 (MTK_PIN_NO(25) | 0) +#define PINMUX_GPIO25__FUNC_O_LCM_RST (MTK_PIN_NO(25) | 1) +#define PINMUX_GPIO25__FUNC_O_LCM1_RST (MTK_PIN_NO(25) | 2) +#define PINMUX_GPIO25__FUNC_I0_DP_TX_HPD (MTK_PIN_NO(25) | 3) + +#define PINMUX_GPIO26__FUNC_B_GPIO26 (MTK_PIN_NO(26) | 0) +#define PINMUX_GPIO26__FUNC_I0_DSI_TE (MTK_PIN_NO(26) | 1) +#define PINMUX_GPIO26__FUNC_I0_DSI1_TE (MTK_PIN_NO(26) | 2) +#define PINMUX_GPIO26__FUNC_I0_EDP_TX_HPD (MTK_PIN_NO(26) | 3) + +#define PINMUX_GPIO27__FUNC_B_GPIO27 (MTK_PIN_NO(27) | 0) +#define PINMUX_GPIO27__FUNC_O_LCM1_RST (MTK_PIN_NO(27) | 1) +#define PINMUX_GPIO27__FUNC_O_LCM_RST (MTK_PIN_NO(27) | 2) +#define PINMUX_GPIO27__FUNC_I0_DP_TX_HPD (MTK_PIN_NO(27) | 3) +#define PINMUX_GPIO27__FUNC_O_CMVREF2 (MTK_PIN_NO(27) | 4) +#define PINMUX_GPIO27__FUNC_O_mbistwriteen_trigger (MTK_PIN_NO(27) | 5) +#define PINMUX_GPIO27__FUNC_O_PWM_2 (MTK_PIN_NO(27) | 6) +#define PINMUX_GPIO27__FUNC_B0_DBG_MON_A17 (MTK_PIN_NO(27) | 7) + +#define PINMUX_GPIO28__FUNC_B_GPIO28 (MTK_PIN_NO(28) | 0) +#define PINMUX_GPIO28__FUNC_I0_DSI1_TE (MTK_PIN_NO(28) | 1) +#define PINMUX_GPIO28__FUNC_I0_DSI_TE (MTK_PIN_NO(28) | 2) +#define PINMUX_GPIO28__FUNC_I0_EDP_TX_HPD (MTK_PIN_NO(28) | 3) +#define PINMUX_GPIO28__FUNC_O_CMVREF3 (MTK_PIN_NO(28) | 4) +#define PINMUX_GPIO28__FUNC_O_mbistreaden_trigger (MTK_PIN_NO(28) | 5) +#define PINMUX_GPIO28__FUNC_O_PWM_3 (MTK_PIN_NO(28) | 6) +#define PINMUX_GPIO28__FUNC_B0_DBG_MON_A18 (MTK_PIN_NO(28) | 7) + +#define PINMUX_GPIO29__FUNC_B_GPIO29 (MTK_PIN_NO(29) | 0) +#define PINMUX_GPIO29__FUNC_O_DISP_PWM0 (MTK_PIN_NO(29) | 1) +#define PINMUX_GPIO29__FUNC_O_DISP_PWM1 (MTK_PIN_NO(29) | 2) + +#define PINMUX_GPIO30__FUNC_B_GPIO30 (MTK_PIN_NO(30) | 0) +#define PINMUX_GPIO30__FUNC_O_DISP_PWM1 (MTK_PIN_NO(30) | 1) +#define PINMUX_GPIO30__FUNC_O_DISP_PWM0 (MTK_PIN_NO(30) | 2) +#define PINMUX_GPIO30__FUNC_O_CMFLASH3 (MTK_PIN_NO(30) | 3) +#define PINMUX_GPIO30__FUNC_O_PWM_1 (MTK_PIN_NO(30) | 4) +#define PINMUX_GPIO30__FUNC_B0_DBG_MON_A19 (MTK_PIN_NO(30) | 7) + +#define PINMUX_GPIO31__FUNC_B_GPIO31 (MTK_PIN_NO(31) | 0) +#define PINMUX_GPIO31__FUNC_O_UTXD0 (MTK_PIN_NO(31) | 1) +#define PINMUX_GPIO31__FUNC_O_TP_UTXD1_AO (MTK_PIN_NO(31) | 2) +#define PINMUX_GPIO31__FUNC_O_ADSP_UTXD0 (MTK_PIN_NO(31) | 3) +#define PINMUX_GPIO31__FUNC_O_TP_UTXD2_AO (MTK_PIN_NO(31) | 4) +#define PINMUX_GPIO31__FUNC_O_MD32_0_TXD (MTK_PIN_NO(31) | 5) +#define PINMUX_GPIO31__FUNC_O_MD32_1_TXD (MTK_PIN_NO(31) | 6) +#define PINMUX_GPIO31__FUNC_O_SSPM_UTXD_AO (MTK_PIN_NO(31) | 7) + +#define PINMUX_GPIO32__FUNC_B_GPIO32 (MTK_PIN_NO(32) | 0) +#define PINMUX_GPIO32__FUNC_I1_URXD0 (MTK_PIN_NO(32) | 1) +#define PINMUX_GPIO32__FUNC_I1_TP_URXD1_AO (MTK_PIN_NO(32) | 2) +#define PINMUX_GPIO32__FUNC_I1_ADSP_URXD0 (MTK_PIN_NO(32) | 3) +#define PINMUX_GPIO32__FUNC_I1_TP_URXD2_AO (MTK_PIN_NO(32) | 4) +#define PINMUX_GPIO32__FUNC_I1_MD32_0_RXD (MTK_PIN_NO(32) | 5) +#define PINMUX_GPIO32__FUNC_I1_MD32_1_RXD (MTK_PIN_NO(32) | 6) +#define PINMUX_GPIO32__FUNC_I1_SSPM_URXD_AO (MTK_PIN_NO(32) | 7) + +#define PINMUX_GPIO33__FUNC_B_GPIO33 (MTK_PIN_NO(33) | 0) +#define PINMUX_GPIO33__FUNC_O_UTXD1 (MTK_PIN_NO(33) | 1) +#define PINMUX_GPIO33__FUNC_O_URTS2 (MTK_PIN_NO(33) | 2) +#define PINMUX_GPIO33__FUNC_O_ADSP_UTXD0 (MTK_PIN_NO(33) | 3) +#define PINMUX_GPIO33__FUNC_O_TP_UTXD1_AO (MTK_PIN_NO(33) | 4) +#define PINMUX_GPIO33__FUNC_O_mbistwriteen_trigger (MTK_PIN_NO(33) | 5) +#define PINMUX_GPIO33__FUNC_O_MD32_0_TXD (MTK_PIN_NO(33) | 6) +#define PINMUX_GPIO33__FUNC_O_SSPM_UTXD_AO (MTK_PIN_NO(33) | 7) + +#define PINMUX_GPIO34__FUNC_B_GPIO34 (MTK_PIN_NO(34) | 0) +#define PINMUX_GPIO34__FUNC_I1_URXD1 (MTK_PIN_NO(34) | 1) +#define PINMUX_GPIO34__FUNC_I1_UCTS2 (MTK_PIN_NO(34) | 2) +#define PINMUX_GPIO34__FUNC_I1_ADSP_URXD0 (MTK_PIN_NO(34) | 3) +#define PINMUX_GPIO34__FUNC_I1_TP_URXD1_AO (MTK_PIN_NO(34) | 4) +#define PINMUX_GPIO34__FUNC_O_mbistreaden_trigger (MTK_PIN_NO(34) | 5) +#define PINMUX_GPIO34__FUNC_I1_MD32_0_RXD (MTK_PIN_NO(34) | 6) +#define PINMUX_GPIO34__FUNC_I1_SSPM_URXD_AO (MTK_PIN_NO(34) | 7) + +#define PINMUX_GPIO35__FUNC_B_GPIO35 (MTK_PIN_NO(35) | 0) +#define PINMUX_GPIO35__FUNC_O_UTXD2 (MTK_PIN_NO(35) | 1) +#define PINMUX_GPIO35__FUNC_O_URTS1 (MTK_PIN_NO(35) | 2) +#define PINMUX_GPIO35__FUNC_O_ADSP_UTXD0 (MTK_PIN_NO(35) | 3) +#define PINMUX_GPIO35__FUNC_O_TP_URTS1_AO (MTK_PIN_NO(35) | 4) +#define PINMUX_GPIO35__FUNC_O_TP_UTXD2_AO (MTK_PIN_NO(35) | 5) +#define PINMUX_GPIO35__FUNC_O_MD32_1_TXD (MTK_PIN_NO(35) | 6) +#define PINMUX_GPIO35__FUNC_B0_DBG_MON_A20 (MTK_PIN_NO(35) | 7) + +#define PINMUX_GPIO36__FUNC_B_GPIO36 (MTK_PIN_NO(36) | 0) +#define PINMUX_GPIO36__FUNC_I1_URXD2 (MTK_PIN_NO(36) | 1) +#define PINMUX_GPIO36__FUNC_I1_UCTS1 (MTK_PIN_NO(36) | 2) +#define PINMUX_GPIO36__FUNC_I1_ADSP_URXD0 (MTK_PIN_NO(36) | 3) +#define PINMUX_GPIO36__FUNC_I1_TP_UCTS1_AO (MTK_PIN_NO(36) | 4) +#define PINMUX_GPIO36__FUNC_I1_TP_URXD2_AO (MTK_PIN_NO(36) | 5) +#define PINMUX_GPIO36__FUNC_I1_MD32_1_RXD (MTK_PIN_NO(36) | 6) +#define PINMUX_GPIO36__FUNC_B0_DBG_MON_A21 (MTK_PIN_NO(36) | 7) + +#define PINMUX_GPIO37__FUNC_B_GPIO37 (MTK_PIN_NO(37) | 0) +#define PINMUX_GPIO37__FUNC_B1_JTMS_SEL1 (MTK_PIN_NO(37) | 1) +#define PINMUX_GPIO37__FUNC_I0_UDI_TMS (MTK_PIN_NO(37) | 2) +#define PINMUX_GPIO37__FUNC_I1_SPM_JTAG_TMS (MTK_PIN_NO(37) | 3) +#define PINMUX_GPIO37__FUNC_I1_ADSP_JTAG0_TMS (MTK_PIN_NO(37) | 4) +#define PINMUX_GPIO37__FUNC_I1_SCP_JTAG0_TMS (MTK_PIN_NO(37) | 5) +#define PINMUX_GPIO37__FUNC_I1_CCU0_JTAG_TMS (MTK_PIN_NO(37) | 6) +#define PINMUX_GPIO37__FUNC_I1_MCUPM_JTAG_TMS (MTK_PIN_NO(37) | 7) + +#define PINMUX_GPIO38__FUNC_B_GPIO38 (MTK_PIN_NO(38) | 0) +#define PINMUX_GPIO38__FUNC_I0_JTCK_SEL1 (MTK_PIN_NO(38) | 1) +#define PINMUX_GPIO38__FUNC_I0_UDI_TCK (MTK_PIN_NO(38) | 2) +#define PINMUX_GPIO38__FUNC_I1_SPM_JTAG_TCK (MTK_PIN_NO(38) | 3) +#define PINMUX_GPIO38__FUNC_I0_ADSP_JTAG0_TCK (MTK_PIN_NO(38) | 4) +#define PINMUX_GPIO38__FUNC_I1_SCP_JTAG0_TCK (MTK_PIN_NO(38) | 5) +#define PINMUX_GPIO38__FUNC_I1_CCU0_JTAG_TCK (MTK_PIN_NO(38) | 6) +#define PINMUX_GPIO38__FUNC_I1_MCUPM_JTAG_TCK (MTK_PIN_NO(38) | 7) + +#define PINMUX_GPIO39__FUNC_B_GPIO39 (MTK_PIN_NO(39) | 0) +#define PINMUX_GPIO39__FUNC_I1_JTDI_SEL1 (MTK_PIN_NO(39) | 1) +#define PINMUX_GPIO39__FUNC_I0_UDI_TDI (MTK_PIN_NO(39) | 2) +#define PINMUX_GPIO39__FUNC_I1_SPM_JTAG_TDI (MTK_PIN_NO(39) | 3) +#define PINMUX_GPIO39__FUNC_I1_ADSP_JTAG0_TDI (MTK_PIN_NO(39) | 4) +#define PINMUX_GPIO39__FUNC_I1_SCP_JTAG0_TDI (MTK_PIN_NO(39) | 5) +#define PINMUX_GPIO39__FUNC_I1_CCU0_JTAG_TDI (MTK_PIN_NO(39) | 6) +#define PINMUX_GPIO39__FUNC_I1_MCUPM_JTAG_TDI (MTK_PIN_NO(39) | 7) + +#define PINMUX_GPIO40__FUNC_B_GPIO40 (MTK_PIN_NO(40) | 0) +#define PINMUX_GPIO40__FUNC_O_JTDO_SEL1 (MTK_PIN_NO(40) | 1) +#define PINMUX_GPIO40__FUNC_O_UDI_TDO (MTK_PIN_NO(40) | 2) +#define PINMUX_GPIO40__FUNC_O_SPM_JTAG_TDO (MTK_PIN_NO(40) | 3) +#define PINMUX_GPIO40__FUNC_O_ADSP_JTAG0_TDO (MTK_PIN_NO(40) | 4) +#define PINMUX_GPIO40__FUNC_O_SCP_JTAG0_TDO (MTK_PIN_NO(40) | 5) +#define PINMUX_GPIO40__FUNC_O_CCU0_JTAG_TDO (MTK_PIN_NO(40) | 6) +#define PINMUX_GPIO40__FUNC_O_MCUPM_JTAG_TDO (MTK_PIN_NO(40) | 7) + +#define PINMUX_GPIO41__FUNC_B_GPIO41 (MTK_PIN_NO(41) | 0) +#define PINMUX_GPIO41__FUNC_I1_JTRSTn_SEL1 (MTK_PIN_NO(41) | 1) +#define PINMUX_GPIO41__FUNC_I0_UDI_NTRST (MTK_PIN_NO(41) | 2) +#define PINMUX_GPIO41__FUNC_I0_SPM_JTAG_TRSTN (MTK_PIN_NO(41) | 3) +#define PINMUX_GPIO41__FUNC_I1_ADSP_JTAG0_TRSTN (MTK_PIN_NO(41) | 4) +#define PINMUX_GPIO41__FUNC_I0_SCP_JTAG0_TRSTN (MTK_PIN_NO(41) | 5) +#define PINMUX_GPIO41__FUNC_I1_CCU0_JTAG_TRST (MTK_PIN_NO(41) | 6) +#define PINMUX_GPIO41__FUNC_I0_MCUPM_JTAG_TRSTN (MTK_PIN_NO(41) | 7) + +#define PINMUX_GPIO42__FUNC_B_GPIO42 (MTK_PIN_NO(42) | 0) +#define PINMUX_GPIO42__FUNC_B1_KPCOL0 (MTK_PIN_NO(42) | 1) + +#define PINMUX_GPIO43__FUNC_B_GPIO43 (MTK_PIN_NO(43) | 0) +#define PINMUX_GPIO43__FUNC_B1_KPCOL1 (MTK_PIN_NO(43) | 1) +#define PINMUX_GPIO43__FUNC_I0_DP_TX_HPD (MTK_PIN_NO(43) | 2) +#define PINMUX_GPIO43__FUNC_O_CMFLASH2 (MTK_PIN_NO(43) | 3) +#define PINMUX_GPIO43__FUNC_I0_DVFSRC_EXT_REQ (MTK_PIN_NO(43) | 4) +#define PINMUX_GPIO43__FUNC_O_mbistwriteen_trigger (MTK_PIN_NO(43) | 7) + +#define PINMUX_GPIO44__FUNC_B_GPIO44 (MTK_PIN_NO(44) | 0) +#define PINMUX_GPIO44__FUNC_B1_KPROW0 (MTK_PIN_NO(44) | 1) + +#define PINMUX_GPIO45__FUNC_B_GPIO45 (MTK_PIN_NO(45) | 0) +#define PINMUX_GPIO45__FUNC_B1_KPROW1 (MTK_PIN_NO(45) | 1) +#define PINMUX_GPIO45__FUNC_I0_EDP_TX_HPD (MTK_PIN_NO(45) | 2) +#define PINMUX_GPIO45__FUNC_O_CMFLASH3 (MTK_PIN_NO(45) | 3) +#define PINMUX_GPIO45__FUNC_B0_I2SIN_MCK (MTK_PIN_NO(45) | 4) +#define PINMUX_GPIO45__FUNC_O_mbistreaden_trigger (MTK_PIN_NO(45) | 7) + +#define PINMUX_GPIO46__FUNC_B_GPIO46 (MTK_PIN_NO(46) | 0) +#define PINMUX_GPIO46__FUNC_I0_DP_TX_HPD (MTK_PIN_NO(46) | 1) +#define PINMUX_GPIO46__FUNC_O_PWM_0 (MTK_PIN_NO(46) | 2) +#define PINMUX_GPIO46__FUNC_I0_VBUSVALID_2P (MTK_PIN_NO(46) | 3) +#define PINMUX_GPIO46__FUNC_B0_DBG_MON_A22 (MTK_PIN_NO(46) | 7) + +#define PINMUX_GPIO47__FUNC_B_GPIO47 (MTK_PIN_NO(47) | 0) +#define PINMUX_GPIO47__FUNC_I1_WAKEN (MTK_PIN_NO(47) | 1) +#define PINMUX_GPIO47__FUNC_O_GDU_TROOPS_DET0 (MTK_PIN_NO(47) | 6) + +#define PINMUX_GPIO48__FUNC_B_GPIO48 (MTK_PIN_NO(48) | 0) +#define PINMUX_GPIO48__FUNC_O_PERSTN (MTK_PIN_NO(48) | 1) +#define PINMUX_GPIO48__FUNC_O_GDU_TROOPS_DET1 (MTK_PIN_NO(48) | 6) + +#define PINMUX_GPIO49__FUNC_B_GPIO49 (MTK_PIN_NO(49) | 0) +#define PINMUX_GPIO49__FUNC_B1_CLKREQN (MTK_PIN_NO(49) | 1) +#define PINMUX_GPIO49__FUNC_O_GDU_TROOPS_DET2 (MTK_PIN_NO(49) | 6) + +#define PINMUX_GPIO50__FUNC_B_GPIO50 (MTK_PIN_NO(50) | 0) +#define PINMUX_GPIO50__FUNC_O_HDMITX20_PWR5V (MTK_PIN_NO(50) | 1) +#define PINMUX_GPIO50__FUNC_I1_IDDIG_1P (MTK_PIN_NO(50) | 3) +#define PINMUX_GPIO50__FUNC_I1_SCP_JTAG1_TMS (MTK_PIN_NO(50) | 4) +#define PINMUX_GPIO50__FUNC_I1_SSPM_JTAG_TMS (MTK_PIN_NO(50) | 5) +#define PINMUX_GPIO50__FUNC_I1_MD32_0_JTAG_TMS (MTK_PIN_NO(50) | 6) +#define PINMUX_GPIO50__FUNC_I1_MD32_1_JTAG_TMS (MTK_PIN_NO(50) | 7) + +#define PINMUX_GPIO51__FUNC_B_GPIO51 (MTK_PIN_NO(51) | 0) +#define PINMUX_GPIO51__FUNC_I0_HDMITX20_HTPLG (MTK_PIN_NO(51) | 1) +#define PINMUX_GPIO51__FUNC_I0_EDP_TX_HPD (MTK_PIN_NO(51) | 2) +#define PINMUX_GPIO51__FUNC_O_USB_DRVVBUS_1P (MTK_PIN_NO(51) | 3) +#define PINMUX_GPIO51__FUNC_I1_SCP_JTAG1_TCK (MTK_PIN_NO(51) | 4) +#define PINMUX_GPIO51__FUNC_I1_SSPM_JTAG_TCK (MTK_PIN_NO(51) | 5) +#define PINMUX_GPIO51__FUNC_I1_MD32_0_JTAG_TCK (MTK_PIN_NO(51) | 6) +#define PINMUX_GPIO51__FUNC_I1_MD32_1_JTAG_TCK (MTK_PIN_NO(51) | 7) + +#define PINMUX_GPIO52__FUNC_B_GPIO52 (MTK_PIN_NO(52) | 0) +#define PINMUX_GPIO52__FUNC_B1_HDMITX20_CEC (MTK_PIN_NO(52) | 1) +#define PINMUX_GPIO52__FUNC_I0_VBUSVALID_1P (MTK_PIN_NO(52) | 3) +#define PINMUX_GPIO52__FUNC_I1_SCP_JTAG1_TDI (MTK_PIN_NO(52) | 4) +#define PINMUX_GPIO52__FUNC_I1_SSPM_JTAG_TDI (MTK_PIN_NO(52) | 5) +#define PINMUX_GPIO52__FUNC_I1_MD32_0_JTAG_TDI (MTK_PIN_NO(52) | 6) +#define PINMUX_GPIO52__FUNC_I1_MD32_1_JTAG_TDI (MTK_PIN_NO(52) | 7) + +#define PINMUX_GPIO53__FUNC_B_GPIO53 (MTK_PIN_NO(53) | 0) +#define PINMUX_GPIO53__FUNC_B1_HDMITX20_SCL (MTK_PIN_NO(53) | 1) +#define PINMUX_GPIO53__FUNC_I1_IDDIG_2P (MTK_PIN_NO(53) | 3) +#define PINMUX_GPIO53__FUNC_O_SCP_JTAG1_TDO (MTK_PIN_NO(53) | 4) +#define PINMUX_GPIO53__FUNC_O_SSPM_JTAG_TDO (MTK_PIN_NO(53) | 5) +#define PINMUX_GPIO53__FUNC_O_MD32_0_JTAG_TDO (MTK_PIN_NO(53) | 6) +#define PINMUX_GPIO53__FUNC_O_MD32_1_JTAG_TDO (MTK_PIN_NO(53) | 7) + +#define PINMUX_GPIO54__FUNC_B_GPIO54 (MTK_PIN_NO(54) | 0) +#define PINMUX_GPIO54__FUNC_B1_HDMITX20_SDA (MTK_PIN_NO(54) | 1) +#define PINMUX_GPIO54__FUNC_O_USB_DRVVBUS_2P (MTK_PIN_NO(54) | 3) +#define PINMUX_GPIO54__FUNC_I0_SCP_JTAG1_TRSTN (MTK_PIN_NO(54) | 4) +#define PINMUX_GPIO54__FUNC_I0_SSPM_JTAG_TRSTN (MTK_PIN_NO(54) | 5) +#define PINMUX_GPIO54__FUNC_I1_MD32_0_JTAG_TRST (MTK_PIN_NO(54) | 6) +#define PINMUX_GPIO54__FUNC_I1_MD32_1_JTAG_TRST (MTK_PIN_NO(54) | 7) + +#define PINMUX_GPIO55__FUNC_B_GPIO55 (MTK_PIN_NO(55) | 0) +#define PINMUX_GPIO55__FUNC_B1_SCL0 (MTK_PIN_NO(55) | 1) +#define PINMUX_GPIO55__FUNC_B1_SCP_SCL0 (MTK_PIN_NO(55) | 2) +#define PINMUX_GPIO55__FUNC_B1_SCP_SCL1 (MTK_PIN_NO(55) | 3) +#define PINMUX_GPIO55__FUNC_B1_PCIE_PHY_I2C_SCL (MTK_PIN_NO(55) | 4) + +#define PINMUX_GPIO56__FUNC_B_GPIO56 (MTK_PIN_NO(56) | 0) +#define PINMUX_GPIO56__FUNC_B1_SDA0 (MTK_PIN_NO(56) | 1) +#define PINMUX_GPIO56__FUNC_B1_SCP_SDA0 (MTK_PIN_NO(56) | 2) +#define PINMUX_GPIO56__FUNC_B1_SCP_SDA1 (MTK_PIN_NO(56) | 3) +#define PINMUX_GPIO56__FUNC_B1_PCIE_PHY_I2C_SDA (MTK_PIN_NO(56) | 4) + +#define PINMUX_GPIO57__FUNC_B_GPIO57 (MTK_PIN_NO(57) | 0) +#define PINMUX_GPIO57__FUNC_B1_SCL1 (MTK_PIN_NO(57) | 1) + +#define PINMUX_GPIO58__FUNC_B_GPIO58 (MTK_PIN_NO(58) | 0) +#define PINMUX_GPIO58__FUNC_B1_SDA1 (MTK_PIN_NO(58) | 1) + +#define PINMUX_GPIO59__FUNC_B_GPIO59 (MTK_PIN_NO(59) | 0) +#define PINMUX_GPIO59__FUNC_B1_SCL2 (MTK_PIN_NO(59) | 1) +#define PINMUX_GPIO59__FUNC_B1_SCP_SCL0 (MTK_PIN_NO(59) | 2) +#define PINMUX_GPIO59__FUNC_B1_SCP_SCL1 (MTK_PIN_NO(59) | 3) + +#define PINMUX_GPIO60__FUNC_B_GPIO60 (MTK_PIN_NO(60) | 0) +#define PINMUX_GPIO60__FUNC_B1_SDA2 (MTK_PIN_NO(60) | 1) +#define PINMUX_GPIO60__FUNC_B1_SCP_SDA0 (MTK_PIN_NO(60) | 2) +#define PINMUX_GPIO60__FUNC_B1_SCP_SDA1 (MTK_PIN_NO(60) | 3) + +#define PINMUX_GPIO61__FUNC_B_GPIO61 (MTK_PIN_NO(61) | 0) +#define PINMUX_GPIO61__FUNC_B1_SCL3 (MTK_PIN_NO(61) | 1) +#define PINMUX_GPIO61__FUNC_B1_SCP_SCL0 (MTK_PIN_NO(61) | 2) +#define PINMUX_GPIO61__FUNC_B1_SCP_SCL1 (MTK_PIN_NO(61) | 3) +#define PINMUX_GPIO61__FUNC_B1_PCIE_PHY_I2C_SCL (MTK_PIN_NO(61) | 4) + +#define PINMUX_GPIO62__FUNC_B_GPIO62 (MTK_PIN_NO(62) | 0) +#define PINMUX_GPIO62__FUNC_B1_SDA3 (MTK_PIN_NO(62) | 1) +#define PINMUX_GPIO62__FUNC_B1_SCP_SDA0 (MTK_PIN_NO(62) | 2) +#define PINMUX_GPIO62__FUNC_B1_SCP_SDA1 (MTK_PIN_NO(62) | 3) +#define PINMUX_GPIO62__FUNC_B1_PCIE_PHY_I2C_SDA (MTK_PIN_NO(62) | 4) + +#define PINMUX_GPIO63__FUNC_B_GPIO63 (MTK_PIN_NO(63) | 0) +#define PINMUX_GPIO63__FUNC_B1_SCL4 (MTK_PIN_NO(63) | 1) + +#define PINMUX_GPIO64__FUNC_B_GPIO64 (MTK_PIN_NO(64) | 0) +#define PINMUX_GPIO64__FUNC_B1_SDA4 (MTK_PIN_NO(64) | 1) + +#define PINMUX_GPIO65__FUNC_B_GPIO65 (MTK_PIN_NO(65) | 0) +#define PINMUX_GPIO65__FUNC_B1_SCL5 (MTK_PIN_NO(65) | 1) +#define PINMUX_GPIO65__FUNC_B1_SCP_SCL0 (MTK_PIN_NO(65) | 2) +#define PINMUX_GPIO65__FUNC_B1_SCP_SCL1 (MTK_PIN_NO(65) | 3) + +#define PINMUX_GPIO66__FUNC_B_GPIO66 (MTK_PIN_NO(66) | 0) +#define PINMUX_GPIO66__FUNC_B1_SDA5 (MTK_PIN_NO(66) | 1) +#define PINMUX_GPIO66__FUNC_B1_SCP_SDA0 (MTK_PIN_NO(66) | 2) +#define PINMUX_GPIO66__FUNC_B1_SCP_SDA1 (MTK_PIN_NO(66) | 3) + +#define PINMUX_GPIO67__FUNC_B_GPIO67 (MTK_PIN_NO(67) | 0) +#define PINMUX_GPIO67__FUNC_B1_SCL6 (MTK_PIN_NO(67) | 1) +#define PINMUX_GPIO67__FUNC_B1_SCP_SCL0 (MTK_PIN_NO(67) | 2) +#define PINMUX_GPIO67__FUNC_B1_SCP_SCL1 (MTK_PIN_NO(67) | 3) +#define PINMUX_GPIO67__FUNC_B1_PCIE_PHY_I2C_SCL (MTK_PIN_NO(67) | 4) + +#define PINMUX_GPIO68__FUNC_B_GPIO68 (MTK_PIN_NO(68) | 0) +#define PINMUX_GPIO68__FUNC_B1_SDA6 (MTK_PIN_NO(68) | 1) +#define PINMUX_GPIO68__FUNC_B1_SCP_SDA0 (MTK_PIN_NO(68) | 2) +#define PINMUX_GPIO68__FUNC_B1_SCP_SDA1 (MTK_PIN_NO(68) | 3) +#define PINMUX_GPIO68__FUNC_B1_PCIE_PHY_I2C_SDA (MTK_PIN_NO(68) | 4) + +#define PINMUX_GPIO69__FUNC_B_GPIO69 (MTK_PIN_NO(69) | 0) +#define PINMUX_GPIO69__FUNC_O_SPIM0_CSB (MTK_PIN_NO(69) | 1) +#define PINMUX_GPIO69__FUNC_O_SCP_SPI0_CS (MTK_PIN_NO(69) | 2) +#define PINMUX_GPIO69__FUNC_O_DMIC3_CLK (MTK_PIN_NO(69) | 3) +#define PINMUX_GPIO69__FUNC_B0_MD32_1_GPIO0 (MTK_PIN_NO(69) | 4) +#define PINMUX_GPIO69__FUNC_O_CMVREF0 (MTK_PIN_NO(69) | 5) +#define PINMUX_GPIO69__FUNC_O_GDU_SUM_TROOP0_0 (MTK_PIN_NO(69) | 6) +#define PINMUX_GPIO69__FUNC_B0_DBG_MON_A23 (MTK_PIN_NO(69) | 7) + +#define PINMUX_GPIO70__FUNC_B_GPIO70 (MTK_PIN_NO(70) | 0) +#define PINMUX_GPIO70__FUNC_O_SPIM0_CLK (MTK_PIN_NO(70) | 1) +#define PINMUX_GPIO70__FUNC_O_SCP_SPI0_CK (MTK_PIN_NO(70) | 2) +#define PINMUX_GPIO70__FUNC_I0_DMIC3_DAT (MTK_PIN_NO(70) | 3) +#define PINMUX_GPIO70__FUNC_B0_MD32_1_GPIO1 (MTK_PIN_NO(70) | 4) +#define PINMUX_GPIO70__FUNC_O_CMVREF1 (MTK_PIN_NO(70) | 5) +#define PINMUX_GPIO70__FUNC_O_GDU_SUM_TROOP0_1 (MTK_PIN_NO(70) | 6) +#define PINMUX_GPIO70__FUNC_B0_DBG_MON_A24 (MTK_PIN_NO(70) | 7) + +#define PINMUX_GPIO71__FUNC_B_GPIO71 (MTK_PIN_NO(71) | 0) +#define PINMUX_GPIO71__FUNC_B0_SPIM0_MOSI (MTK_PIN_NO(71) | 1) +#define PINMUX_GPIO71__FUNC_O_SCP_SPI0_MO (MTK_PIN_NO(71) | 2) +#define PINMUX_GPIO71__FUNC_I0_DMIC3_DAT_R (MTK_PIN_NO(71) | 3) +#define PINMUX_GPIO71__FUNC_B0_MD32_1_GPIO2 (MTK_PIN_NO(71) | 4) +#define PINMUX_GPIO71__FUNC_O_CMVREF2 (MTK_PIN_NO(71) | 5) +#define PINMUX_GPIO71__FUNC_O_GDU_SUM_TROOP0_2 (MTK_PIN_NO(71) | 6) +#define PINMUX_GPIO71__FUNC_B0_DBG_MON_A25 (MTK_PIN_NO(71) | 7) + +#define PINMUX_GPIO72__FUNC_B_GPIO72 (MTK_PIN_NO(72) | 0) +#define PINMUX_GPIO72__FUNC_B0_SPIM0_MISO (MTK_PIN_NO(72) | 1) +#define PINMUX_GPIO72__FUNC_I0_SCP_SPI0_MI (MTK_PIN_NO(72) | 2) +#define PINMUX_GPIO72__FUNC_O_DMIC4_CLK (MTK_PIN_NO(72) | 3) +#define PINMUX_GPIO72__FUNC_O_CMVREF3 (MTK_PIN_NO(72) | 5) +#define PINMUX_GPIO72__FUNC_O_GDU_SUM_TROOP1_0 (MTK_PIN_NO(72) | 6) +#define PINMUX_GPIO72__FUNC_B0_DBG_MON_A26 (MTK_PIN_NO(72) | 7) + +#define PINMUX_GPIO73__FUNC_B_GPIO73 (MTK_PIN_NO(73) | 0) +#define PINMUX_GPIO73__FUNC_B0_SPIM0_MIO2 (MTK_PIN_NO(73) | 1) +#define PINMUX_GPIO73__FUNC_O_UTXD3 (MTK_PIN_NO(73) | 2) +#define PINMUX_GPIO73__FUNC_I0_DMIC4_DAT (MTK_PIN_NO(73) | 3) +#define PINMUX_GPIO73__FUNC_O_CLKM0 (MTK_PIN_NO(73) | 4) +#define PINMUX_GPIO73__FUNC_O_CMVREF4 (MTK_PIN_NO(73) | 5) +#define PINMUX_GPIO73__FUNC_O_GDU_SUM_TROOP1_1 (MTK_PIN_NO(73) | 6) +#define PINMUX_GPIO73__FUNC_B0_DBG_MON_A27 (MTK_PIN_NO(73) | 7) + +#define PINMUX_GPIO74__FUNC_B_GPIO74 (MTK_PIN_NO(74) | 0) +#define PINMUX_GPIO74__FUNC_B0_SPIM0_MIO3 (MTK_PIN_NO(74) | 1) +#define PINMUX_GPIO74__FUNC_I1_URXD3 (MTK_PIN_NO(74) | 2) +#define PINMUX_GPIO74__FUNC_I0_DMIC4_DAT_R (MTK_PIN_NO(74) | 3) +#define PINMUX_GPIO74__FUNC_O_CLKM1 (MTK_PIN_NO(74) | 4) +#define PINMUX_GPIO74__FUNC_O_CMVREF5 (MTK_PIN_NO(74) | 5) +#define PINMUX_GPIO74__FUNC_O_GDU_SUM_TROOP1_2 (MTK_PIN_NO(74) | 6) +#define PINMUX_GPIO74__FUNC_B0_DBG_MON_A28 (MTK_PIN_NO(74) | 7) + +#define PINMUX_GPIO75__FUNC_B_GPIO75 (MTK_PIN_NO(75) | 0) +#define PINMUX_GPIO75__FUNC_O_SPIM1_CSB (MTK_PIN_NO(75) | 1) +#define PINMUX_GPIO75__FUNC_O_SCP_SPI1_A_CS (MTK_PIN_NO(75) | 2) +#define PINMUX_GPIO75__FUNC_B0_TDMIN_MCK (MTK_PIN_NO(75) | 3) +#define PINMUX_GPIO75__FUNC_B1_SCP_SCL0 (MTK_PIN_NO(75) | 4) +#define PINMUX_GPIO75__FUNC_O_CMVREF6 (MTK_PIN_NO(75) | 5) +#define PINMUX_GPIO75__FUNC_O_GDU_SUM_TROOP2_0 (MTK_PIN_NO(75) | 6) +#define PINMUX_GPIO75__FUNC_B0_DBG_MON_A29 (MTK_PIN_NO(75) | 7) + +#define PINMUX_GPIO76__FUNC_B_GPIO76 (MTK_PIN_NO(76) | 0) +#define PINMUX_GPIO76__FUNC_O_SPIM1_CLK (MTK_PIN_NO(76) | 1) +#define PINMUX_GPIO76__FUNC_O_SCP_SPI1_A_CK (MTK_PIN_NO(76) | 2) +#define PINMUX_GPIO76__FUNC_B0_TDMIN_BCK (MTK_PIN_NO(76) | 3) +#define PINMUX_GPIO76__FUNC_B1_SCP_SDA0 (MTK_PIN_NO(76) | 4) +#define PINMUX_GPIO76__FUNC_O_CMVREF7 (MTK_PIN_NO(76) | 5) +#define PINMUX_GPIO76__FUNC_O_GDU_SUM_TROOP2_1 (MTK_PIN_NO(76) | 6) +#define PINMUX_GPIO76__FUNC_B0_DBG_MON_A30 (MTK_PIN_NO(76) | 7) + +#define PINMUX_GPIO77__FUNC_B_GPIO77 (MTK_PIN_NO(77) | 0) +#define PINMUX_GPIO77__FUNC_B0_SPIM1_MOSI (MTK_PIN_NO(77) | 1) +#define PINMUX_GPIO77__FUNC_O_SCP_SPI1_A_MO (MTK_PIN_NO(77) | 2) +#define PINMUX_GPIO77__FUNC_B0_TDMIN_LRCK (MTK_PIN_NO(77) | 3) +#define PINMUX_GPIO77__FUNC_B1_SCP_SCL1 (MTK_PIN_NO(77) | 4) +#define PINMUX_GPIO77__FUNC_O_GDU_SUM_TROOP2_2 (MTK_PIN_NO(77) | 6) +#define PINMUX_GPIO77__FUNC_B0_DBG_MON_A31 (MTK_PIN_NO(77) | 7) + +#define PINMUX_GPIO78__FUNC_B_GPIO78 (MTK_PIN_NO(78) | 0) +#define PINMUX_GPIO78__FUNC_B0_SPIM1_MISO (MTK_PIN_NO(78) | 1) +#define PINMUX_GPIO78__FUNC_I0_SCP_SPI1_A_MI (MTK_PIN_NO(78) | 2) +#define PINMUX_GPIO78__FUNC_I0_TDMIN_DI (MTK_PIN_NO(78) | 3) +#define PINMUX_GPIO78__FUNC_B1_SCP_SDA1 (MTK_PIN_NO(78) | 4) +#define PINMUX_GPIO78__FUNC_B0_DBG_MON_A32 (MTK_PIN_NO(78) | 7) + +#define PINMUX_GPIO79__FUNC_B_GPIO79 (MTK_PIN_NO(79) | 0) +#define PINMUX_GPIO79__FUNC_O_SPIM2_CSB (MTK_PIN_NO(79) | 1) +#define PINMUX_GPIO79__FUNC_O_SCP_SPI2_CS (MTK_PIN_NO(79) | 2) +#define PINMUX_GPIO79__FUNC_O_I2SO1_MCK (MTK_PIN_NO(79) | 3) +#define PINMUX_GPIO79__FUNC_O_UTXD2 (MTK_PIN_NO(79) | 4) +#define PINMUX_GPIO79__FUNC_O_TP_UTXD2_AO (MTK_PIN_NO(79) | 5) +#define PINMUX_GPIO79__FUNC_B0_PCM_SYNC (MTK_PIN_NO(79) | 6) +#define PINMUX_GPIO79__FUNC_B0_DBG_MON_B0 (MTK_PIN_NO(79) | 7) + +#define PINMUX_GPIO80__FUNC_B_GPIO80 (MTK_PIN_NO(80) | 0) +#define PINMUX_GPIO80__FUNC_O_SPIM2_CLK (MTK_PIN_NO(80) | 1) +#define PINMUX_GPIO80__FUNC_O_SCP_SPI2_CK (MTK_PIN_NO(80) | 2) +#define PINMUX_GPIO80__FUNC_O_I2SO1_BCK (MTK_PIN_NO(80) | 3) +#define PINMUX_GPIO80__FUNC_I1_URXD2 (MTK_PIN_NO(80) | 4) +#define PINMUX_GPIO80__FUNC_I1_TP_URXD2_AO (MTK_PIN_NO(80) | 5) +#define PINMUX_GPIO80__FUNC_B0_PCM_CLK (MTK_PIN_NO(80) | 6) +#define PINMUX_GPIO80__FUNC_B0_DBG_MON_B1 (MTK_PIN_NO(80) | 7) + +#define PINMUX_GPIO81__FUNC_B_GPIO81 (MTK_PIN_NO(81) | 0) +#define PINMUX_GPIO81__FUNC_B0_SPIM2_MOSI (MTK_PIN_NO(81) | 1) +#define PINMUX_GPIO81__FUNC_O_SCP_SPI2_MO (MTK_PIN_NO(81) | 2) +#define PINMUX_GPIO81__FUNC_O_I2SO1_WS (MTK_PIN_NO(81) | 3) +#define PINMUX_GPIO81__FUNC_O_URTS2 (MTK_PIN_NO(81) | 4) +#define PINMUX_GPIO81__FUNC_O_TP_URTS2_AO (MTK_PIN_NO(81) | 5) +#define PINMUX_GPIO81__FUNC_O_PCM_DO (MTK_PIN_NO(81) | 6) +#define PINMUX_GPIO81__FUNC_B0_DBG_MON_B2 (MTK_PIN_NO(81) | 7) + +#define PINMUX_GPIO82__FUNC_B_GPIO82 (MTK_PIN_NO(82) | 0) +#define PINMUX_GPIO82__FUNC_B0_SPIM2_MISO (MTK_PIN_NO(82) | 1) +#define PINMUX_GPIO82__FUNC_I0_SCP_SPI2_MI (MTK_PIN_NO(82) | 2) +#define PINMUX_GPIO82__FUNC_O_I2SO1_D0 (MTK_PIN_NO(82) | 3) +#define PINMUX_GPIO82__FUNC_I1_UCTS2 (MTK_PIN_NO(82) | 4) +#define PINMUX_GPIO82__FUNC_I1_TP_UCTS2_AO (MTK_PIN_NO(82) | 5) +#define PINMUX_GPIO82__FUNC_I0_PCM_DI (MTK_PIN_NO(82) | 6) +#define PINMUX_GPIO82__FUNC_B0_DBG_MON_B3 (MTK_PIN_NO(82) | 7) + +#define PINMUX_GPIO83__FUNC_B_GPIO83 (MTK_PIN_NO(83) | 0) +#define PINMUX_GPIO83__FUNC_I1_IDDIG (MTK_PIN_NO(83) | 1) + +#define PINMUX_GPIO84__FUNC_B_GPIO84 (MTK_PIN_NO(84) | 0) +#define PINMUX_GPIO84__FUNC_O_USB_DRVVBUS (MTK_PIN_NO(84) | 1) + +#define PINMUX_GPIO85__FUNC_B_GPIO85 (MTK_PIN_NO(85) | 0) +#define PINMUX_GPIO85__FUNC_I0_VBUSVALID (MTK_PIN_NO(85) | 1) + +#define PINMUX_GPIO86__FUNC_B_GPIO86 (MTK_PIN_NO(86) | 0) +#define PINMUX_GPIO86__FUNC_I1_IDDIG_1P (MTK_PIN_NO(86) | 1) +#define PINMUX_GPIO86__FUNC_O_UTXD1 (MTK_PIN_NO(86) | 2) +#define PINMUX_GPIO86__FUNC_O_URTS2 (MTK_PIN_NO(86) | 3) +#define PINMUX_GPIO86__FUNC_O_PWM_2 (MTK_PIN_NO(86) | 4) +#define PINMUX_GPIO86__FUNC_B0_TP_GPIO4_AO (MTK_PIN_NO(86) | 5) +#define PINMUX_GPIO86__FUNC_O_AUXIF_ST0 (MTK_PIN_NO(86) | 6) +#define PINMUX_GPIO86__FUNC_B0_DBG_MON_B4 (MTK_PIN_NO(86) | 7) + +#define PINMUX_GPIO87__FUNC_B_GPIO87 (MTK_PIN_NO(87) | 0) +#define PINMUX_GPIO87__FUNC_O_USB_DRVVBUS_1P (MTK_PIN_NO(87) | 1) +#define PINMUX_GPIO87__FUNC_I1_URXD1 (MTK_PIN_NO(87) | 2) +#define PINMUX_GPIO87__FUNC_I1_UCTS2 (MTK_PIN_NO(87) | 3) +#define PINMUX_GPIO87__FUNC_O_PWM_3 (MTK_PIN_NO(87) | 4) +#define PINMUX_GPIO87__FUNC_B0_TP_GPIO5_AO (MTK_PIN_NO(87) | 5) +#define PINMUX_GPIO87__FUNC_O_AUXIF_CLK0 (MTK_PIN_NO(87) | 6) +#define PINMUX_GPIO87__FUNC_B0_DBG_MON_B5 (MTK_PIN_NO(87) | 7) + +#define PINMUX_GPIO88__FUNC_B_GPIO88 (MTK_PIN_NO(88) | 0) +#define PINMUX_GPIO88__FUNC_I0_VBUSVALID_1P (MTK_PIN_NO(88) | 1) +#define PINMUX_GPIO88__FUNC_O_UTXD2 (MTK_PIN_NO(88) | 2) +#define PINMUX_GPIO88__FUNC_O_URTS1 (MTK_PIN_NO(88) | 3) +#define PINMUX_GPIO88__FUNC_O_CLKM2 (MTK_PIN_NO(88) | 4) +#define PINMUX_GPIO88__FUNC_B0_TP_GPIO6_AO (MTK_PIN_NO(88) | 5) +#define PINMUX_GPIO88__FUNC_O_AUXIF_ST1 (MTK_PIN_NO(88) | 6) +#define PINMUX_GPIO88__FUNC_B0_DBG_MON_B6 (MTK_PIN_NO(88) | 7) + +#define PINMUX_GPIO89__FUNC_B_GPIO89 (MTK_PIN_NO(89) | 0) +#define PINMUX_GPIO89__FUNC_I1_IDDIG_2P (MTK_PIN_NO(89) | 1) +#define PINMUX_GPIO89__FUNC_I1_URXD2 (MTK_PIN_NO(89) | 2) +#define PINMUX_GPIO89__FUNC_I1_UCTS1 (MTK_PIN_NO(89) | 3) +#define PINMUX_GPIO89__FUNC_O_CLKM3 (MTK_PIN_NO(89) | 4) +#define PINMUX_GPIO89__FUNC_B0_TP_GPIO7_AO (MTK_PIN_NO(89) | 5) +#define PINMUX_GPIO89__FUNC_O_AUXIF_CLK1 (MTK_PIN_NO(89) | 6) +#define PINMUX_GPIO89__FUNC_B0_DBG_MON_B7 (MTK_PIN_NO(89) | 7) + +#define PINMUX_GPIO90__FUNC_B_GPIO90 (MTK_PIN_NO(90) | 0) +#define PINMUX_GPIO90__FUNC_O_USB_DRVVBUS_2P (MTK_PIN_NO(90) | 1) +#define PINMUX_GPIO90__FUNC_O_UTXD3 (MTK_PIN_NO(90) | 2) +#define PINMUX_GPIO90__FUNC_O_ADSP_UTXD0 (MTK_PIN_NO(90) | 3) +#define PINMUX_GPIO90__FUNC_O_SSPM_UTXD_AO (MTK_PIN_NO(90) | 4) +#define PINMUX_GPIO90__FUNC_O_MD32_0_TXD (MTK_PIN_NO(90) | 5) +#define PINMUX_GPIO90__FUNC_O_MD32_1_TXD (MTK_PIN_NO(90) | 6) +#define PINMUX_GPIO90__FUNC_B0_DBG_MON_B8 (MTK_PIN_NO(90) | 7) + +#define PINMUX_GPIO91__FUNC_B_GPIO91 (MTK_PIN_NO(91) | 0) +#define PINMUX_GPIO91__FUNC_I0_VBUSVALID_2P (MTK_PIN_NO(91) | 1) +#define PINMUX_GPIO91__FUNC_I1_URXD3 (MTK_PIN_NO(91) | 2) +#define PINMUX_GPIO91__FUNC_I1_ADSP_URXD0 (MTK_PIN_NO(91) | 3) +#define PINMUX_GPIO91__FUNC_I1_SSPM_URXD_AO (MTK_PIN_NO(91) | 4) +#define PINMUX_GPIO91__FUNC_I1_MD32_0_RXD (MTK_PIN_NO(91) | 5) +#define PINMUX_GPIO91__FUNC_I1_MD32_1_RXD (MTK_PIN_NO(91) | 6) +#define PINMUX_GPIO91__FUNC_B0_DBG_MON_B9 (MTK_PIN_NO(91) | 7) + +#define PINMUX_GPIO92__FUNC_B_GPIO92 (MTK_PIN_NO(92) | 0) +#define PINMUX_GPIO92__FUNC_O_PWRAP_SPI0_CSN (MTK_PIN_NO(92) | 1) + +#define PINMUX_GPIO93__FUNC_B_GPIO93 (MTK_PIN_NO(93) | 0) +#define PINMUX_GPIO93__FUNC_O_PWRAP_SPI0_CK (MTK_PIN_NO(93) | 1) + +#define PINMUX_GPIO94__FUNC_B_GPIO94 (MTK_PIN_NO(94) | 0) +#define PINMUX_GPIO94__FUNC_B0_PWRAP_SPI0_MO (MTK_PIN_NO(94) | 1) +#define PINMUX_GPIO94__FUNC_B0_PWRAP_SPI0_MI (MTK_PIN_NO(94) | 2) + +#define PINMUX_GPIO95__FUNC_B_GPIO95 (MTK_PIN_NO(95) | 0) +#define PINMUX_GPIO95__FUNC_B0_PWRAP_SPI0_MI (MTK_PIN_NO(95) | 1) +#define PINMUX_GPIO95__FUNC_B0_PWRAP_SPI0_MO (MTK_PIN_NO(95) | 2) + +#define PINMUX_GPIO96__FUNC_B_GPIO96 (MTK_PIN_NO(96) | 0) +#define PINMUX_GPIO96__FUNC_O_SRCLKENA0 (MTK_PIN_NO(96) | 1) + +#define PINMUX_GPIO97__FUNC_B_GPIO97 (MTK_PIN_NO(97) | 0) +#define PINMUX_GPIO97__FUNC_O_SRCLKENA1 (MTK_PIN_NO(97) | 1) + +#define PINMUX_GPIO98__FUNC_B_GPIO98 (MTK_PIN_NO(98) | 0) +#define PINMUX_GPIO98__FUNC_O_SCP_VREQ_VAO (MTK_PIN_NO(98) | 1) +#define PINMUX_GPIO98__FUNC_I0_DVFSRC_EXT_REQ (MTK_PIN_NO(98) | 2) + +#define PINMUX_GPIO99__FUNC_B_GPIO99 (MTK_PIN_NO(99) | 0) +#define PINMUX_GPIO99__FUNC_I0_RTC32K_CK (MTK_PIN_NO(99) | 1) + +#define PINMUX_GPIO100__FUNC_B_GPIO100 (MTK_PIN_NO(100) | 0) +#define PINMUX_GPIO100__FUNC_O_WATCHDOG (MTK_PIN_NO(100) | 1) + +#define PINMUX_GPIO101__FUNC_B_GPIO101 (MTK_PIN_NO(101) | 0) +#define PINMUX_GPIO101__FUNC_O_AUD_CLK_MOSI (MTK_PIN_NO(101) | 1) +#define PINMUX_GPIO101__FUNC_O_I2SO1_MCK (MTK_PIN_NO(101) | 2) +#define PINMUX_GPIO101__FUNC_B0_I2SIN_BCK (MTK_PIN_NO(101) | 3) + +#define PINMUX_GPIO102__FUNC_B_GPIO102 (MTK_PIN_NO(102) | 0) +#define PINMUX_GPIO102__FUNC_O_AUD_SYNC_MOSI (MTK_PIN_NO(102) | 1) +#define PINMUX_GPIO102__FUNC_O_I2SO1_BCK (MTK_PIN_NO(102) | 2) +#define PINMUX_GPIO102__FUNC_B0_I2SIN_WS (MTK_PIN_NO(102) | 3) + +#define PINMUX_GPIO103__FUNC_B_GPIO103 (MTK_PIN_NO(103) | 0) +#define PINMUX_GPIO103__FUNC_O_AUD_DAT_MOSI0 (MTK_PIN_NO(103) | 1) +#define PINMUX_GPIO103__FUNC_O_I2SO1_WS (MTK_PIN_NO(103) | 2) +#define PINMUX_GPIO103__FUNC_I0_I2SIN_D0 (MTK_PIN_NO(103) | 3) + +#define PINMUX_GPIO104__FUNC_B_GPIO104 (MTK_PIN_NO(104) | 0) +#define PINMUX_GPIO104__FUNC_O_AUD_DAT_MOSI1 (MTK_PIN_NO(104) | 1) +#define PINMUX_GPIO104__FUNC_O_I2SO1_D0 (MTK_PIN_NO(104) | 2) +#define PINMUX_GPIO104__FUNC_I0_I2SIN_D1 (MTK_PIN_NO(104) | 3) + +#define PINMUX_GPIO105__FUNC_B_GPIO105 (MTK_PIN_NO(105) | 0) +#define PINMUX_GPIO105__FUNC_I0_AUD_DAT_MISO0 (MTK_PIN_NO(105) | 1) +#define PINMUX_GPIO105__FUNC_I0_VOW_DAT_MISO (MTK_PIN_NO(105) | 2) +#define PINMUX_GPIO105__FUNC_I0_I2SIN_D2 (MTK_PIN_NO(105) | 3) + +#define PINMUX_GPIO106__FUNC_B_GPIO106 (MTK_PIN_NO(106) | 0) +#define PINMUX_GPIO106__FUNC_I0_AUD_DAT_MISO1 (MTK_PIN_NO(106) | 1) +#define PINMUX_GPIO106__FUNC_I0_VOW_CLK_MISO (MTK_PIN_NO(106) | 2) +#define PINMUX_GPIO106__FUNC_I0_I2SIN_D3 (MTK_PIN_NO(106) | 3) + +#define PINMUX_GPIO107__FUNC_B_GPIO107 (MTK_PIN_NO(107) | 0) +#define PINMUX_GPIO107__FUNC_B0_I2SIN_MCK (MTK_PIN_NO(107) | 1) +#define PINMUX_GPIO107__FUNC_I0_SPLIN_MCK (MTK_PIN_NO(107) | 2) +#define PINMUX_GPIO107__FUNC_I0_SPDIF_IN0 (MTK_PIN_NO(107) | 3) +#define PINMUX_GPIO107__FUNC_O_CMVREF4 (MTK_PIN_NO(107) | 4) +#define PINMUX_GPIO107__FUNC_O_AUXIF_ST0 (MTK_PIN_NO(107) | 5) +#define PINMUX_GPIO107__FUNC_O_PGD_LV_LSC_PWR0 (MTK_PIN_NO(107) | 6) + +#define PINMUX_GPIO108__FUNC_B_GPIO108 (MTK_PIN_NO(108) | 0) +#define PINMUX_GPIO108__FUNC_B0_I2SIN_BCK (MTK_PIN_NO(108) | 1) +#define PINMUX_GPIO108__FUNC_I0_SPLIN_LRCK (MTK_PIN_NO(108) | 2) +#define PINMUX_GPIO108__FUNC_O_DMIC4_CLK (MTK_PIN_NO(108) | 3) +#define PINMUX_GPIO108__FUNC_O_CMVREF5 (MTK_PIN_NO(108) | 4) +#define PINMUX_GPIO108__FUNC_O_AUXIF_CLK0 (MTK_PIN_NO(108) | 5) +#define PINMUX_GPIO108__FUNC_O_PGD_LV_LSC_PWR1 (MTK_PIN_NO(108) | 6) +#define PINMUX_GPIO108__FUNC_B0_DBG_MON_B10 (MTK_PIN_NO(108) | 7) + +#define PINMUX_GPIO109__FUNC_B_GPIO109 (MTK_PIN_NO(109) | 0) +#define PINMUX_GPIO109__FUNC_B0_I2SIN_WS (MTK_PIN_NO(109) | 1) +#define PINMUX_GPIO109__FUNC_I0_SPLIN_BCK (MTK_PIN_NO(109) | 2) +#define PINMUX_GPIO109__FUNC_I0_DMIC4_DAT (MTK_PIN_NO(109) | 3) +#define PINMUX_GPIO109__FUNC_O_CMVREF6 (MTK_PIN_NO(109) | 4) +#define PINMUX_GPIO109__FUNC_O_AUXIF_ST1 (MTK_PIN_NO(109) | 5) +#define PINMUX_GPIO109__FUNC_O_PGD_LV_LSC_PWR2 (MTK_PIN_NO(109) | 6) +#define PINMUX_GPIO109__FUNC_B0_DBG_MON_B11 (MTK_PIN_NO(109) | 7) + +#define PINMUX_GPIO110__FUNC_B_GPIO110 (MTK_PIN_NO(110) | 0) +#define PINMUX_GPIO110__FUNC_I0_I2SIN_D0 (MTK_PIN_NO(110) | 1) +#define PINMUX_GPIO110__FUNC_I0_SPLIN_D0 (MTK_PIN_NO(110) | 2) +#define PINMUX_GPIO110__FUNC_I0_DMIC4_DAT_R (MTK_PIN_NO(110) | 3) +#define PINMUX_GPIO110__FUNC_O_CMVREF7 (MTK_PIN_NO(110) | 4) +#define PINMUX_GPIO110__FUNC_O_AUXIF_CLK1 (MTK_PIN_NO(110) | 5) +#define PINMUX_GPIO110__FUNC_O_PGD_LV_LSC_PWR3 (MTK_PIN_NO(110) | 6) +#define PINMUX_GPIO110__FUNC_B0_DBG_MON_B12 (MTK_PIN_NO(110) | 7) + +#define PINMUX_GPIO111__FUNC_B_GPIO111 (MTK_PIN_NO(111) | 0) +#define PINMUX_GPIO111__FUNC_I0_I2SIN_D1 (MTK_PIN_NO(111) | 1) +#define PINMUX_GPIO111__FUNC_I0_SPLIN_D1 (MTK_PIN_NO(111) | 2) +#define PINMUX_GPIO111__FUNC_O_DMIC3_CLK (MTK_PIN_NO(111) | 3) +#define PINMUX_GPIO111__FUNC_O_SPDIF_OUT (MTK_PIN_NO(111) | 4) +#define PINMUX_GPIO111__FUNC_O_PGD_LV_LSC_PWR4 (MTK_PIN_NO(111) | 6) +#define PINMUX_GPIO111__FUNC_B0_DBG_MON_B13 (MTK_PIN_NO(111) | 7) + +#define PINMUX_GPIO112__FUNC_B_GPIO112 (MTK_PIN_NO(112) | 0) +#define PINMUX_GPIO112__FUNC_I0_I2SIN_D2 (MTK_PIN_NO(112) | 1) +#define PINMUX_GPIO112__FUNC_I0_SPLIN_D2 (MTK_PIN_NO(112) | 2) +#define PINMUX_GPIO112__FUNC_I0_DMIC3_DAT (MTK_PIN_NO(112) | 3) +#define PINMUX_GPIO112__FUNC_B0_TDMIN_MCK (MTK_PIN_NO(112) | 4) +#define PINMUX_GPIO112__FUNC_O_I2SO1_WS (MTK_PIN_NO(112) | 5) +#define PINMUX_GPIO112__FUNC_O_PGD_LV_LSC_PWR5 (MTK_PIN_NO(112) | 6) +#define PINMUX_GPIO112__FUNC_B0_DBG_MON_B14 (MTK_PIN_NO(112) | 7) + +#define PINMUX_GPIO113__FUNC_B_GPIO113 (MTK_PIN_NO(113) | 0) +#define PINMUX_GPIO113__FUNC_I0_I2SIN_D3 (MTK_PIN_NO(113) | 1) +#define PINMUX_GPIO113__FUNC_I0_SPLIN_D3 (MTK_PIN_NO(113) | 2) +#define PINMUX_GPIO113__FUNC_I0_DMIC3_DAT_R (MTK_PIN_NO(113) | 3) +#define PINMUX_GPIO113__FUNC_B0_TDMIN_BCK (MTK_PIN_NO(113) | 4) +#define PINMUX_GPIO113__FUNC_O_I2SO1_D0 (MTK_PIN_NO(113) | 5) +#define PINMUX_GPIO113__FUNC_B0_DBG_MON_B15 (MTK_PIN_NO(113) | 7) + +#define PINMUX_GPIO114__FUNC_B_GPIO114 (MTK_PIN_NO(114) | 0) +#define PINMUX_GPIO114__FUNC_O_I2SO2_MCK (MTK_PIN_NO(114) | 1) +#define PINMUX_GPIO114__FUNC_B0_I2SIN_MCK (MTK_PIN_NO(114) | 2) +#define PINMUX_GPIO114__FUNC_I1_MCUPM_JTAG_TMS (MTK_PIN_NO(114) | 3) +#define PINMUX_GPIO114__FUNC_B1_APU_JTAG_TMS (MTK_PIN_NO(114) | 4) +#define PINMUX_GPIO114__FUNC_I1_SCP_JTAG1_TMS (MTK_PIN_NO(114) | 5) +#define PINMUX_GPIO114__FUNC_I1_SPM_JTAG_TMS (MTK_PIN_NO(114) | 6) +#define PINMUX_GPIO114__FUNC_B0_DBG_MON_B16 (MTK_PIN_NO(114) | 7) + +#define PINMUX_GPIO115__FUNC_B_GPIO115 (MTK_PIN_NO(115) | 0) +#define PINMUX_GPIO115__FUNC_B0_I2SO2_BCK (MTK_PIN_NO(115) | 1) +#define PINMUX_GPIO115__FUNC_B0_I2SIN_BCK (MTK_PIN_NO(115) | 2) +#define PINMUX_GPIO115__FUNC_I1_MCUPM_JTAG_TCK (MTK_PIN_NO(115) | 3) +#define PINMUX_GPIO115__FUNC_I0_APU_JTAG_TCK (MTK_PIN_NO(115) | 4) +#define PINMUX_GPIO115__FUNC_I1_SCP_JTAG1_TCK (MTK_PIN_NO(115) | 5) +#define PINMUX_GPIO115__FUNC_I1_SPM_JTAG_TCK (MTK_PIN_NO(115) | 6) +#define PINMUX_GPIO115__FUNC_B0_DBG_MON_B17 (MTK_PIN_NO(115) | 7) + +#define PINMUX_GPIO116__FUNC_B_GPIO116 (MTK_PIN_NO(116) | 0) +#define PINMUX_GPIO116__FUNC_B0_I2SO2_WS (MTK_PIN_NO(116) | 1) +#define PINMUX_GPIO116__FUNC_B0_I2SIN_WS (MTK_PIN_NO(116) | 2) +#define PINMUX_GPIO116__FUNC_I1_MCUPM_JTAG_TDI (MTK_PIN_NO(116) | 3) +#define PINMUX_GPIO116__FUNC_I1_APU_JTAG_TDI (MTK_PIN_NO(116) | 4) +#define PINMUX_GPIO116__FUNC_I1_SCP_JTAG1_TDI (MTK_PIN_NO(116) | 5) +#define PINMUX_GPIO116__FUNC_I1_SPM_JTAG_TDI (MTK_PIN_NO(116) | 6) +#define PINMUX_GPIO116__FUNC_B0_DBG_MON_B18 (MTK_PIN_NO(116) | 7) + +#define PINMUX_GPIO117__FUNC_B_GPIO117 (MTK_PIN_NO(117) | 0) +#define PINMUX_GPIO117__FUNC_O_I2SO2_D0 (MTK_PIN_NO(117) | 1) +#define PINMUX_GPIO117__FUNC_I0_I2SIN_D0 (MTK_PIN_NO(117) | 2) +#define PINMUX_GPIO117__FUNC_O_MCUPM_JTAG_TDO (MTK_PIN_NO(117) | 3) +#define PINMUX_GPIO117__FUNC_O_APU_JTAG_TDO (MTK_PIN_NO(117) | 4) +#define PINMUX_GPIO117__FUNC_O_SCP_JTAG1_TDO (MTK_PIN_NO(117) | 5) +#define PINMUX_GPIO117__FUNC_O_SPM_JTAG_TDO (MTK_PIN_NO(117) | 6) +#define PINMUX_GPIO117__FUNC_B0_DBG_MON_B19 (MTK_PIN_NO(117) | 7) + +#define PINMUX_GPIO118__FUNC_B_GPIO118 (MTK_PIN_NO(118) | 0) +#define PINMUX_GPIO118__FUNC_O_I2SO2_D1 (MTK_PIN_NO(118) | 1) +#define PINMUX_GPIO118__FUNC_I0_I2SIN_D1 (MTK_PIN_NO(118) | 2) +#define PINMUX_GPIO118__FUNC_I0_MCUPM_JTAG_TRSTN (MTK_PIN_NO(118) | 3) +#define PINMUX_GPIO118__FUNC_I0_APU_JTAG_TRST (MTK_PIN_NO(118) | 4) +#define PINMUX_GPIO118__FUNC_I0_SCP_JTAG1_TRSTN (MTK_PIN_NO(118) | 5) +#define PINMUX_GPIO118__FUNC_I0_SPM_JTAG_TRSTN (MTK_PIN_NO(118) | 6) +#define PINMUX_GPIO118__FUNC_B0_DBG_MON_B20 (MTK_PIN_NO(118) | 7) + +#define PINMUX_GPIO119__FUNC_B_GPIO119 (MTK_PIN_NO(119) | 0) +#define PINMUX_GPIO119__FUNC_O_I2SO2_D2 (MTK_PIN_NO(119) | 1) +#define PINMUX_GPIO119__FUNC_I0_I2SIN_D2 (MTK_PIN_NO(119) | 2) +#define PINMUX_GPIO119__FUNC_O_UTXD3 (MTK_PIN_NO(119) | 3) +#define PINMUX_GPIO119__FUNC_B0_TDMIN_LRCK (MTK_PIN_NO(119) | 4) +#define PINMUX_GPIO119__FUNC_O_I2SO1_MCK (MTK_PIN_NO(119) | 5) +#define PINMUX_GPIO119__FUNC_O_SSPM_UTXD_AO (MTK_PIN_NO(119) | 6) +#define PINMUX_GPIO119__FUNC_B0_DBG_MON_B21 (MTK_PIN_NO(119) | 7) + +#define PINMUX_GPIO120__FUNC_B_GPIO120 (MTK_PIN_NO(120) | 0) +#define PINMUX_GPIO120__FUNC_O_I2SO2_D3 (MTK_PIN_NO(120) | 1) +#define PINMUX_GPIO120__FUNC_I0_I2SIN_D3 (MTK_PIN_NO(120) | 2) +#define PINMUX_GPIO120__FUNC_I1_URXD3 (MTK_PIN_NO(120) | 3) +#define PINMUX_GPIO120__FUNC_I0_TDMIN_DI (MTK_PIN_NO(120) | 4) +#define PINMUX_GPIO120__FUNC_O_I2SO1_BCK (MTK_PIN_NO(120) | 5) +#define PINMUX_GPIO120__FUNC_I1_SSPM_URXD_AO (MTK_PIN_NO(120) | 6) +#define PINMUX_GPIO120__FUNC_B0_DBG_MON_B22 (MTK_PIN_NO(120) | 7) + +#define PINMUX_GPIO121__FUNC_B_GPIO121 (MTK_PIN_NO(121) | 0) +#define PINMUX_GPIO121__FUNC_B0_PCM_CLK (MTK_PIN_NO(121) | 1) +#define PINMUX_GPIO121__FUNC_O_SPIM4_CSB (MTK_PIN_NO(121) | 2) +#define PINMUX_GPIO121__FUNC_O_SCP_SPI1_B_CS (MTK_PIN_NO(121) | 3) +#define PINMUX_GPIO121__FUNC_O_TP_UTXD2_AO (MTK_PIN_NO(121) | 4) +#define PINMUX_GPIO121__FUNC_O_AUXIF_ST0 (MTK_PIN_NO(121) | 5) +#define PINMUX_GPIO121__FUNC_O_PGD_DA_EFUSE_RDY (MTK_PIN_NO(121) | 6) +#define PINMUX_GPIO121__FUNC_B0_DBG_MON_B23 (MTK_PIN_NO(121) | 7) + +#define PINMUX_GPIO122__FUNC_B_GPIO122 (MTK_PIN_NO(122) | 0) +#define PINMUX_GPIO122__FUNC_B0_PCM_SYNC (MTK_PIN_NO(122) | 1) +#define PINMUX_GPIO122__FUNC_O_SPIM4_CLK (MTK_PIN_NO(122) | 2) +#define PINMUX_GPIO122__FUNC_O_SCP_SPI1_B_CK (MTK_PIN_NO(122) | 3) +#define PINMUX_GPIO122__FUNC_I1_TP_URXD2_AO (MTK_PIN_NO(122) | 4) +#define PINMUX_GPIO122__FUNC_O_AUXIF_CLK0 (MTK_PIN_NO(122) | 5) +#define PINMUX_GPIO122__FUNC_O_PGD_DA_EFUSE_RDY_PRE (MTK_PIN_NO(122) | 6) +#define PINMUX_GPIO122__FUNC_B0_DBG_MON_B24 (MTK_PIN_NO(122) | 7) + +#define PINMUX_GPIO123__FUNC_B_GPIO123 (MTK_PIN_NO(123) | 0) +#define PINMUX_GPIO123__FUNC_O_PCM_DO (MTK_PIN_NO(123) | 1) +#define PINMUX_GPIO123__FUNC_B0_SPIM4_MOSI (MTK_PIN_NO(123) | 2) +#define PINMUX_GPIO123__FUNC_O_SCP_SPI1_B_MO (MTK_PIN_NO(123) | 3) +#define PINMUX_GPIO123__FUNC_O_TP_URTS2_AO (MTK_PIN_NO(123) | 4) +#define PINMUX_GPIO123__FUNC_O_AUXIF_ST1 (MTK_PIN_NO(123) | 5) +#define PINMUX_GPIO123__FUNC_O_PGD_DA_PWRGD_RESET (MTK_PIN_NO(123) | 6) +#define PINMUX_GPIO123__FUNC_B0_DBG_MON_B25 (MTK_PIN_NO(123) | 7) + +#define PINMUX_GPIO124__FUNC_B_GPIO124 (MTK_PIN_NO(124) | 0) +#define PINMUX_GPIO124__FUNC_I0_PCM_DI (MTK_PIN_NO(124) | 1) +#define PINMUX_GPIO124__FUNC_B0_SPIM4_MISO (MTK_PIN_NO(124) | 2) +#define PINMUX_GPIO124__FUNC_I0_SCP_SPI1_B_MI (MTK_PIN_NO(124) | 3) +#define PINMUX_GPIO124__FUNC_I1_TP_UCTS2_AO (MTK_PIN_NO(124) | 4) +#define PINMUX_GPIO124__FUNC_O_AUXIF_CLK1 (MTK_PIN_NO(124) | 5) +#define PINMUX_GPIO124__FUNC_O_PGD_DA_PWRGD_ENB (MTK_PIN_NO(124) | 6) +#define PINMUX_GPIO124__FUNC_B0_DBG_MON_B26 (MTK_PIN_NO(124) | 7) + +#define PINMUX_GPIO125__FUNC_B_GPIO125 (MTK_PIN_NO(125) | 0) +#define PINMUX_GPIO125__FUNC_O_DMIC1_CLK (MTK_PIN_NO(125) | 1) +#define PINMUX_GPIO125__FUNC_O_SPINOR_CK (MTK_PIN_NO(125) | 2) +#define PINMUX_GPIO125__FUNC_B0_TDMIN_MCK (MTK_PIN_NO(125) | 3) +#define PINMUX_GPIO125__FUNC_O_LVTS_FOUT (MTK_PIN_NO(125) | 6) +#define PINMUX_GPIO125__FUNC_B0_DBG_MON_B27 (MTK_PIN_NO(125) | 7) + +#define PINMUX_GPIO126__FUNC_B_GPIO126 (MTK_PIN_NO(126) | 0) +#define PINMUX_GPIO126__FUNC_I0_DMIC1_DAT (MTK_PIN_NO(126) | 1) +#define PINMUX_GPIO126__FUNC_O_SPINOR_CS (MTK_PIN_NO(126) | 2) +#define PINMUX_GPIO126__FUNC_B0_TDMIN_BCK (MTK_PIN_NO(126) | 3) +#define PINMUX_GPIO126__FUNC_O_LVTS_SDO (MTK_PIN_NO(126) | 6) +#define PINMUX_GPIO126__FUNC_B0_DBG_MON_B28 (MTK_PIN_NO(126) | 7) + +#define PINMUX_GPIO127__FUNC_B_GPIO127 (MTK_PIN_NO(127) | 0) +#define PINMUX_GPIO127__FUNC_I0_DMIC1_DAT_R (MTK_PIN_NO(127) | 1) +#define PINMUX_GPIO127__FUNC_B0_SPINOR_IO0 (MTK_PIN_NO(127) | 2) +#define PINMUX_GPIO127__FUNC_B0_TDMIN_LRCK (MTK_PIN_NO(127) | 3) +#define PINMUX_GPIO127__FUNC_I0_LVTS_26M (MTK_PIN_NO(127) | 6) +#define PINMUX_GPIO127__FUNC_B0_DBG_MON_B29 (MTK_PIN_NO(127) | 7) + +#define PINMUX_GPIO128__FUNC_B_GPIO128 (MTK_PIN_NO(128) | 0) +#define PINMUX_GPIO128__FUNC_O_DMIC2_CLK (MTK_PIN_NO(128) | 1) +#define PINMUX_GPIO128__FUNC_B0_SPINOR_IO1 (MTK_PIN_NO(128) | 2) +#define PINMUX_GPIO128__FUNC_I0_TDMIN_DI (MTK_PIN_NO(128) | 3) +#define PINMUX_GPIO128__FUNC_I0_LVTS_SCF (MTK_PIN_NO(128) | 6) +#define PINMUX_GPIO128__FUNC_B0_DBG_MON_B30 (MTK_PIN_NO(128) | 7) + +#define PINMUX_GPIO129__FUNC_B_GPIO129 (MTK_PIN_NO(129) | 0) +#define PINMUX_GPIO129__FUNC_I0_DMIC2_DAT (MTK_PIN_NO(129) | 1) +#define PINMUX_GPIO129__FUNC_B0_SPINOR_IO2 (MTK_PIN_NO(129) | 2) +#define PINMUX_GPIO129__FUNC_I0_SPDIF_IN1 (MTK_PIN_NO(129) | 3) +#define PINMUX_GPIO129__FUNC_I0_LVTS_SCK (MTK_PIN_NO(129) | 6) +#define PINMUX_GPIO129__FUNC_B0_DBG_MON_B31 (MTK_PIN_NO(129) | 7) + +#define PINMUX_GPIO130__FUNC_B_GPIO130 (MTK_PIN_NO(130) | 0) +#define PINMUX_GPIO130__FUNC_I0_DMIC2_DAT_R (MTK_PIN_NO(130) | 1) +#define PINMUX_GPIO130__FUNC_B0_SPINOR_IO3 (MTK_PIN_NO(130) | 2) +#define PINMUX_GPIO130__FUNC_I0_SPDIF_IN2 (MTK_PIN_NO(130) | 3) +#define PINMUX_GPIO130__FUNC_I0_LVTS_SDI (MTK_PIN_NO(130) | 6) +#define PINMUX_GPIO130__FUNC_B0_DBG_MON_B32 (MTK_PIN_NO(130) | 7) + +#define PINMUX_GPIO131__FUNC_B_GPIO131 (MTK_PIN_NO(131) | 0) +#define PINMUX_GPIO131__FUNC_O_DPI_D0 (MTK_PIN_NO(131) | 1) +#define PINMUX_GPIO131__FUNC_O_GBE_TXD3 (MTK_PIN_NO(131) | 2) +#define PINMUX_GPIO131__FUNC_O_DMIC1_CLK (MTK_PIN_NO(131) | 3) +#define PINMUX_GPIO131__FUNC_O_I2SO2_MCK (MTK_PIN_NO(131) | 4) +#define PINMUX_GPIO131__FUNC_B0_TP_GPIO0_AO (MTK_PIN_NO(131) | 5) +#define PINMUX_GPIO131__FUNC_O_SPIM5_CSB (MTK_PIN_NO(131) | 6) +#define PINMUX_GPIO131__FUNC_O_PGD_LV_HSC_PWR0 (MTK_PIN_NO(131) | 7) + +#define PINMUX_GPIO132__FUNC_B_GPIO132 (MTK_PIN_NO(132) | 0) +#define PINMUX_GPIO132__FUNC_O_DPI_D1 (MTK_PIN_NO(132) | 1) +#define PINMUX_GPIO132__FUNC_O_GBE_TXD2 (MTK_PIN_NO(132) | 2) +#define PINMUX_GPIO132__FUNC_I0_DMIC1_DAT (MTK_PIN_NO(132) | 3) +#define PINMUX_GPIO132__FUNC_B0_I2SO2_BCK (MTK_PIN_NO(132) | 4) +#define PINMUX_GPIO132__FUNC_B0_TP_GPIO1_AO (MTK_PIN_NO(132) | 5) +#define PINMUX_GPIO132__FUNC_O_SPIM5_CLK (MTK_PIN_NO(132) | 6) +#define PINMUX_GPIO132__FUNC_O_PGD_LV_HSC_PWR1 (MTK_PIN_NO(132) | 7) + +#define PINMUX_GPIO133__FUNC_B_GPIO133 (MTK_PIN_NO(133) | 0) +#define PINMUX_GPIO133__FUNC_O_DPI_D2 (MTK_PIN_NO(133) | 1) +#define PINMUX_GPIO133__FUNC_O_GBE_TXD1 (MTK_PIN_NO(133) | 2) +#define PINMUX_GPIO133__FUNC_I0_DMIC1_DAT_R (MTK_PIN_NO(133) | 3) +#define PINMUX_GPIO133__FUNC_B0_I2SO2_WS (MTK_PIN_NO(133) | 4) +#define PINMUX_GPIO133__FUNC_B0_TP_GPIO2_AO (MTK_PIN_NO(133) | 5) +#define PINMUX_GPIO133__FUNC_B0_SPIM5_MOSI (MTK_PIN_NO(133) | 6) +#define PINMUX_GPIO133__FUNC_O_PGD_LV_HSC_PWR2 (MTK_PIN_NO(133) | 7) + +#define PINMUX_GPIO134__FUNC_B_GPIO134 (MTK_PIN_NO(134) | 0) +#define PINMUX_GPIO134__FUNC_O_DPI_D3 (MTK_PIN_NO(134) | 1) +#define PINMUX_GPIO134__FUNC_O_GBE_TXD0 (MTK_PIN_NO(134) | 2) +#define PINMUX_GPIO134__FUNC_O_DMIC2_CLK (MTK_PIN_NO(134) | 3) +#define PINMUX_GPIO134__FUNC_O_I2SO2_D0 (MTK_PIN_NO(134) | 4) +#define PINMUX_GPIO134__FUNC_B0_TP_GPIO3_AO (MTK_PIN_NO(134) | 5) +#define PINMUX_GPIO134__FUNC_B0_SPIM5_MISO (MTK_PIN_NO(134) | 6) +#define PINMUX_GPIO134__FUNC_O_PGD_LV_HSC_PWR3 (MTK_PIN_NO(134) | 7) + +#define PINMUX_GPIO135__FUNC_B_GPIO135 (MTK_PIN_NO(135) | 0) +#define PINMUX_GPIO135__FUNC_O_DPI_D4 (MTK_PIN_NO(135) | 1) +#define PINMUX_GPIO135__FUNC_I0_GBE_RXD3 (MTK_PIN_NO(135) | 2) +#define PINMUX_GPIO135__FUNC_I0_DMIC2_DAT (MTK_PIN_NO(135) | 3) +#define PINMUX_GPIO135__FUNC_O_I2SO2_D1 (MTK_PIN_NO(135) | 4) +#define PINMUX_GPIO135__FUNC_B0_TP_GPIO4_AO (MTK_PIN_NO(135) | 5) +#define PINMUX_GPIO135__FUNC_I1_WAKEN (MTK_PIN_NO(135) | 6) +#define PINMUX_GPIO135__FUNC_O_PGD_LV_HSC_PWR4 (MTK_PIN_NO(135) | 7) + +#define PINMUX_GPIO136__FUNC_B_GPIO136 (MTK_PIN_NO(136) | 0) +#define PINMUX_GPIO136__FUNC_O_DPI_D5 (MTK_PIN_NO(136) | 1) +#define PINMUX_GPIO136__FUNC_I0_GBE_RXD2 (MTK_PIN_NO(136) | 2) +#define PINMUX_GPIO136__FUNC_I0_DMIC2_DAT_R (MTK_PIN_NO(136) | 3) +#define PINMUX_GPIO136__FUNC_O_I2SO2_D2 (MTK_PIN_NO(136) | 4) +#define PINMUX_GPIO136__FUNC_B0_TP_GPIO5_AO (MTK_PIN_NO(136) | 5) +#define PINMUX_GPIO136__FUNC_O_PERSTN (MTK_PIN_NO(136) | 6) +#define PINMUX_GPIO136__FUNC_O_PGD_LV_HSC_PWR5 (MTK_PIN_NO(136) | 7) + +#define PINMUX_GPIO137__FUNC_B_GPIO137 (MTK_PIN_NO(137) | 0) +#define PINMUX_GPIO137__FUNC_O_DPI_D6 (MTK_PIN_NO(137) | 1) +#define PINMUX_GPIO137__FUNC_I0_GBE_RXD1 (MTK_PIN_NO(137) | 2) +#define PINMUX_GPIO137__FUNC_O_DMIC3_CLK (MTK_PIN_NO(137) | 3) +#define PINMUX_GPIO137__FUNC_O_I2SO2_D3 (MTK_PIN_NO(137) | 4) +#define PINMUX_GPIO137__FUNC_B0_TP_GPIO6_AO (MTK_PIN_NO(137) | 5) +#define PINMUX_GPIO137__FUNC_B1_CLKREQN (MTK_PIN_NO(137) | 6) +#define PINMUX_GPIO137__FUNC_O_PWM_0 (MTK_PIN_NO(137) | 7) + +#define PINMUX_GPIO138__FUNC_B_GPIO138 (MTK_PIN_NO(138) | 0) +#define PINMUX_GPIO138__FUNC_O_DPI_D7 (MTK_PIN_NO(138) | 1) +#define PINMUX_GPIO138__FUNC_I0_GBE_RXD0 (MTK_PIN_NO(138) | 2) +#define PINMUX_GPIO138__FUNC_I0_DMIC3_DAT (MTK_PIN_NO(138) | 3) +#define PINMUX_GPIO138__FUNC_O_CLKM2 (MTK_PIN_NO(138) | 4) +#define PINMUX_GPIO138__FUNC_B0_TP_GPIO7_AO (MTK_PIN_NO(138) | 5) +#define PINMUX_GPIO138__FUNC_B0_MD32_0_GPIO0 (MTK_PIN_NO(138) | 7) + +#define PINMUX_GPIO139__FUNC_B_GPIO139 (MTK_PIN_NO(139) | 0) +#define PINMUX_GPIO139__FUNC_O_DPI_D8 (MTK_PIN_NO(139) | 1) +#define PINMUX_GPIO139__FUNC_B0_GBE_TXC (MTK_PIN_NO(139) | 2) +#define PINMUX_GPIO139__FUNC_I0_DMIC3_DAT_R (MTK_PIN_NO(139) | 3) +#define PINMUX_GPIO139__FUNC_O_CLKM3 (MTK_PIN_NO(139) | 4) +#define PINMUX_GPIO139__FUNC_O_TP_UTXD2_AO (MTK_PIN_NO(139) | 5) +#define PINMUX_GPIO139__FUNC_O_UTXD2 (MTK_PIN_NO(139) | 6) +#define PINMUX_GPIO139__FUNC_B0_MD32_0_GPIO1 (MTK_PIN_NO(139) | 7) + +#define PINMUX_GPIO140__FUNC_B_GPIO140 (MTK_PIN_NO(140) | 0) +#define PINMUX_GPIO140__FUNC_O_DPI_D9 (MTK_PIN_NO(140) | 1) +#define PINMUX_GPIO140__FUNC_I0_GBE_RXC (MTK_PIN_NO(140) | 2) +#define PINMUX_GPIO140__FUNC_O_DMIC4_CLK (MTK_PIN_NO(140) | 3) +#define PINMUX_GPIO140__FUNC_O_PWM_2 (MTK_PIN_NO(140) | 4) +#define PINMUX_GPIO140__FUNC_I1_TP_URXD2_AO (MTK_PIN_NO(140) | 5) +#define PINMUX_GPIO140__FUNC_I1_URXD2 (MTK_PIN_NO(140) | 6) +#define PINMUX_GPIO140__FUNC_B0_MD32_0_GPIO2 (MTK_PIN_NO(140) | 7) + +#define PINMUX_GPIO141__FUNC_B_GPIO141 (MTK_PIN_NO(141) | 0) +#define PINMUX_GPIO141__FUNC_O_DPI_D10 (MTK_PIN_NO(141) | 1) +#define PINMUX_GPIO141__FUNC_I0_GBE_RXDV (MTK_PIN_NO(141) | 2) +#define PINMUX_GPIO141__FUNC_I0_DMIC4_DAT (MTK_PIN_NO(141) | 3) +#define PINMUX_GPIO141__FUNC_O_PWM_3 (MTK_PIN_NO(141) | 4) +#define PINMUX_GPIO141__FUNC_O_TP_URTS2_AO (MTK_PIN_NO(141) | 5) +#define PINMUX_GPIO141__FUNC_O_URTS2 (MTK_PIN_NO(141) | 6) +#define PINMUX_GPIO141__FUNC_B0_MD32_1_GPIO0 (MTK_PIN_NO(141) | 7) + +#define PINMUX_GPIO142__FUNC_B_GPIO142 (MTK_PIN_NO(142) | 0) +#define PINMUX_GPIO142__FUNC_O_DPI_D11 (MTK_PIN_NO(142) | 1) +#define PINMUX_GPIO142__FUNC_O_GBE_TXEN (MTK_PIN_NO(142) | 2) +#define PINMUX_GPIO142__FUNC_I0_DMIC4_DAT_R (MTK_PIN_NO(142) | 3) +#define PINMUX_GPIO142__FUNC_O_PWM_1 (MTK_PIN_NO(142) | 4) +#define PINMUX_GPIO142__FUNC_I1_TP_UCTS2_AO (MTK_PIN_NO(142) | 5) +#define PINMUX_GPIO142__FUNC_I1_UCTS2 (MTK_PIN_NO(142) | 6) +#define PINMUX_GPIO142__FUNC_B0_MD32_1_GPIO1 (MTK_PIN_NO(142) | 7) + +#define PINMUX_GPIO143__FUNC_B_GPIO143 (MTK_PIN_NO(143) | 0) +#define PINMUX_GPIO143__FUNC_O_DPI_D12 (MTK_PIN_NO(143) | 1) +#define PINMUX_GPIO143__FUNC_O_GBE_MDC (MTK_PIN_NO(143) | 2) +#define PINMUX_GPIO143__FUNC_B0_MD32_0_GPIO0 (MTK_PIN_NO(143) | 3) +#define PINMUX_GPIO143__FUNC_O_CLKM0 (MTK_PIN_NO(143) | 4) +#define PINMUX_GPIO143__FUNC_O_SPIM3_CSB (MTK_PIN_NO(143) | 5) +#define PINMUX_GPIO143__FUNC_O_UTXD1 (MTK_PIN_NO(143) | 6) +#define PINMUX_GPIO143__FUNC_B0_MD32_1_GPIO2 (MTK_PIN_NO(143) | 7) + +#define PINMUX_GPIO144__FUNC_B_GPIO144 (MTK_PIN_NO(144) | 0) +#define PINMUX_GPIO144__FUNC_O_DPI_D13 (MTK_PIN_NO(144) | 1) +#define PINMUX_GPIO144__FUNC_B1_GBE_MDIO (MTK_PIN_NO(144) | 2) +#define PINMUX_GPIO144__FUNC_B0_MD32_0_GPIO1 (MTK_PIN_NO(144) | 3) +#define PINMUX_GPIO144__FUNC_O_CLKM1 (MTK_PIN_NO(144) | 4) +#define PINMUX_GPIO144__FUNC_O_SPIM3_CLK (MTK_PIN_NO(144) | 5) +#define PINMUX_GPIO144__FUNC_I1_URXD1 (MTK_PIN_NO(144) | 6) +#define PINMUX_GPIO144__FUNC_O_PGD_HV_HSC_PWR0 (MTK_PIN_NO(144) | 7) + +#define PINMUX_GPIO145__FUNC_B_GPIO145 (MTK_PIN_NO(145) | 0) +#define PINMUX_GPIO145__FUNC_O_DPI_D14 (MTK_PIN_NO(145) | 1) +#define PINMUX_GPIO145__FUNC_O_GBE_TXER (MTK_PIN_NO(145) | 2) +#define PINMUX_GPIO145__FUNC_B0_MD32_1_GPIO0 (MTK_PIN_NO(145) | 3) +#define PINMUX_GPIO145__FUNC_O_CMFLASH0 (MTK_PIN_NO(145) | 4) +#define PINMUX_GPIO145__FUNC_B0_SPIM3_MOSI (MTK_PIN_NO(145) | 5) +#define PINMUX_GPIO145__FUNC_B0_GBE_AUX_PPS2 (MTK_PIN_NO(145) | 6) +#define PINMUX_GPIO145__FUNC_O_PGD_HV_HSC_PWR1 (MTK_PIN_NO(145) | 7) + +#define PINMUX_GPIO146__FUNC_B_GPIO146 (MTK_PIN_NO(146) | 0) +#define PINMUX_GPIO146__FUNC_O_DPI_D15 (MTK_PIN_NO(146) | 1) +#define PINMUX_GPIO146__FUNC_I0_GBE_RXER (MTK_PIN_NO(146) | 2) +#define PINMUX_GPIO146__FUNC_B0_MD32_1_GPIO1 (MTK_PIN_NO(146) | 3) +#define PINMUX_GPIO146__FUNC_O_CMFLASH1 (MTK_PIN_NO(146) | 4) +#define PINMUX_GPIO146__FUNC_B0_SPIM3_MISO (MTK_PIN_NO(146) | 5) +#define PINMUX_GPIO146__FUNC_B0_GBE_AUX_PPS3 (MTK_PIN_NO(146) | 6) +#define PINMUX_GPIO146__FUNC_O_PGD_HV_HSC_PWR2 (MTK_PIN_NO(146) | 7) + +#define PINMUX_GPIO147__FUNC_B_GPIO147 (MTK_PIN_NO(147) | 0) +#define PINMUX_GPIO147__FUNC_O_DPI_HSYNC (MTK_PIN_NO(147) | 1) +#define PINMUX_GPIO147__FUNC_I0_GBE_COL (MTK_PIN_NO(147) | 2) +#define PINMUX_GPIO147__FUNC_O_I2SO1_MCK (MTK_PIN_NO(147) | 3) +#define PINMUX_GPIO147__FUNC_O_CMVREF0 (MTK_PIN_NO(147) | 4) +#define PINMUX_GPIO147__FUNC_O_SPDIF_OUT (MTK_PIN_NO(147) | 5) +#define PINMUX_GPIO147__FUNC_O_URTS1 (MTK_PIN_NO(147) | 6) +#define PINMUX_GPIO147__FUNC_O_PGD_HV_HSC_PWR3 (MTK_PIN_NO(147) | 7) + +#define PINMUX_GPIO148__FUNC_B_GPIO148 (MTK_PIN_NO(148) | 0) +#define PINMUX_GPIO148__FUNC_O_DPI_VSYNC (MTK_PIN_NO(148) | 1) +#define PINMUX_GPIO148__FUNC_I0_GBE_INTR (MTK_PIN_NO(148) | 2) +#define PINMUX_GPIO148__FUNC_O_I2SO1_BCK (MTK_PIN_NO(148) | 3) +#define PINMUX_GPIO148__FUNC_O_CMVREF1 (MTK_PIN_NO(148) | 4) +#define PINMUX_GPIO148__FUNC_I0_SPDIF_IN0 (MTK_PIN_NO(148) | 5) +#define PINMUX_GPIO148__FUNC_I1_UCTS1 (MTK_PIN_NO(148) | 6) +#define PINMUX_GPIO148__FUNC_O_PGD_HV_HSC_PWR4 (MTK_PIN_NO(148) | 7) + +#define PINMUX_GPIO149__FUNC_B_GPIO149 (MTK_PIN_NO(149) | 0) +#define PINMUX_GPIO149__FUNC_O_DPI_DE (MTK_PIN_NO(149) | 1) +#define PINMUX_GPIO149__FUNC_B0_GBE_AUX_PPS0 (MTK_PIN_NO(149) | 2) +#define PINMUX_GPIO149__FUNC_O_I2SO1_WS (MTK_PIN_NO(149) | 3) +#define PINMUX_GPIO149__FUNC_O_CMVREF2 (MTK_PIN_NO(149) | 4) +#define PINMUX_GPIO149__FUNC_I0_SPDIF_IN1 (MTK_PIN_NO(149) | 5) +#define PINMUX_GPIO149__FUNC_O_UTXD3 (MTK_PIN_NO(149) | 6) +#define PINMUX_GPIO149__FUNC_O_PGD_HV_HSC_PWR5 (MTK_PIN_NO(149) | 7) + +#define PINMUX_GPIO150__FUNC_B_GPIO150 (MTK_PIN_NO(150) | 0) +#define PINMUX_GPIO150__FUNC_O_DPI_CK (MTK_PIN_NO(150) | 1) +#define PINMUX_GPIO150__FUNC_B0_GBE_AUX_PPS1 (MTK_PIN_NO(150) | 2) +#define PINMUX_GPIO150__FUNC_O_I2SO1_D0 (MTK_PIN_NO(150) | 3) +#define PINMUX_GPIO150__FUNC_O_CMVREF3 (MTK_PIN_NO(150) | 4) +#define PINMUX_GPIO150__FUNC_I0_SPDIF_IN2 (MTK_PIN_NO(150) | 5) +#define PINMUX_GPIO150__FUNC_I1_URXD3 (MTK_PIN_NO(150) | 6) + +#define PINMUX_GPIO151__FUNC_B_GPIO151 (MTK_PIN_NO(151) | 0) +#define PINMUX_GPIO151__FUNC_B1_MSDC0_DAT7 (MTK_PIN_NO(151) | 1) + +#define PINMUX_GPIO152__FUNC_B_GPIO152 (MTK_PIN_NO(152) | 0) +#define PINMUX_GPIO152__FUNC_B1_MSDC0_DAT6 (MTK_PIN_NO(152) | 1) + +#define PINMUX_GPIO153__FUNC_B_GPIO153 (MTK_PIN_NO(153) | 0) +#define PINMUX_GPIO153__FUNC_B1_MSDC0_DAT5 (MTK_PIN_NO(153) | 1) + +#define PINMUX_GPIO154__FUNC_B_GPIO154 (MTK_PIN_NO(154) | 0) +#define PINMUX_GPIO154__FUNC_B1_MSDC0_DAT4 (MTK_PIN_NO(154) | 1) + +#define PINMUX_GPIO155__FUNC_B_GPIO155 (MTK_PIN_NO(155) | 0) +#define PINMUX_GPIO155__FUNC_O_MSDC0_RSTB (MTK_PIN_NO(155) | 1) + +#define PINMUX_GPIO156__FUNC_B_GPIO156 (MTK_PIN_NO(156) | 0) +#define PINMUX_GPIO156__FUNC_B1_MSDC0_CMD (MTK_PIN_NO(156) | 1) + +#define PINMUX_GPIO157__FUNC_B_GPIO157 (MTK_PIN_NO(157) | 0) +#define PINMUX_GPIO157__FUNC_B1_MSDC0_CLK (MTK_PIN_NO(157) | 1) + +#define PINMUX_GPIO158__FUNC_B_GPIO158 (MTK_PIN_NO(158) | 0) +#define PINMUX_GPIO158__FUNC_B1_MSDC0_DAT3 (MTK_PIN_NO(158) | 1) + +#define PINMUX_GPIO159__FUNC_B_GPIO159 (MTK_PIN_NO(159) | 0) +#define PINMUX_GPIO159__FUNC_B1_MSDC0_DAT2 (MTK_PIN_NO(159) | 1) + +#define PINMUX_GPIO160__FUNC_B_GPIO160 (MTK_PIN_NO(160) | 0) +#define PINMUX_GPIO160__FUNC_B1_MSDC0_DAT1 (MTK_PIN_NO(160) | 1) + +#define PINMUX_GPIO161__FUNC_B_GPIO161 (MTK_PIN_NO(161) | 0) +#define PINMUX_GPIO161__FUNC_B1_MSDC0_DAT0 (MTK_PIN_NO(161) | 1) + +#define PINMUX_GPIO162__FUNC_B_GPIO162 (MTK_PIN_NO(162) | 0) +#define PINMUX_GPIO162__FUNC_B0_MSDC0_DSL (MTK_PIN_NO(162) | 1) + +#define PINMUX_GPIO163__FUNC_B_GPIO163 (MTK_PIN_NO(163) | 0) +#define PINMUX_GPIO163__FUNC_B1_MSDC1_CMD (MTK_PIN_NO(163) | 1) +#define PINMUX_GPIO163__FUNC_O_SPDIF_OUT (MTK_PIN_NO(163) | 2) +#define PINMUX_GPIO163__FUNC_I1_MD32_0_JTAG_TMS (MTK_PIN_NO(163) | 3) +#define PINMUX_GPIO163__FUNC_I1_ADSP_JTAG0_TMS (MTK_PIN_NO(163) | 4) +#define PINMUX_GPIO163__FUNC_I1_SCP_JTAG0_TMS (MTK_PIN_NO(163) | 5) +#define PINMUX_GPIO163__FUNC_I1_CCU0_JTAG_TMS (MTK_PIN_NO(163) | 6) +#define PINMUX_GPIO163__FUNC_I0_IPU_JTAG_TMS (MTK_PIN_NO(163) | 7) + +#define PINMUX_GPIO164__FUNC_B_GPIO164 (MTK_PIN_NO(164) | 0) +#define PINMUX_GPIO164__FUNC_B1_MSDC1_CLK (MTK_PIN_NO(164) | 1) +#define PINMUX_GPIO164__FUNC_I0_SPDIF_IN0 (MTK_PIN_NO(164) | 2) +#define PINMUX_GPIO164__FUNC_I1_MD32_0_JTAG_TCK (MTK_PIN_NO(164) | 3) +#define PINMUX_GPIO164__FUNC_I0_ADSP_JTAG0_TCK (MTK_PIN_NO(164) | 4) +#define PINMUX_GPIO164__FUNC_I1_SCP_JTAG0_TCK (MTK_PIN_NO(164) | 5) +#define PINMUX_GPIO164__FUNC_I1_CCU0_JTAG_TCK (MTK_PIN_NO(164) | 6) +#define PINMUX_GPIO164__FUNC_I0_IPU_JTAG_TCK (MTK_PIN_NO(164) | 7) + +#define PINMUX_GPIO165__FUNC_B_GPIO165 (MTK_PIN_NO(165) | 0) +#define PINMUX_GPIO165__FUNC_B1_MSDC1_DAT0 (MTK_PIN_NO(165) | 1) +#define PINMUX_GPIO165__FUNC_I0_SPDIF_IN1 (MTK_PIN_NO(165) | 2) +#define PINMUX_GPIO165__FUNC_I1_MD32_0_JTAG_TDI (MTK_PIN_NO(165) | 3) +#define PINMUX_GPIO165__FUNC_I1_ADSP_JTAG0_TDI (MTK_PIN_NO(165) | 4) +#define PINMUX_GPIO165__FUNC_I1_SCP_JTAG0_TDI (MTK_PIN_NO(165) | 5) +#define PINMUX_GPIO165__FUNC_I1_CCU0_JTAG_TDI (MTK_PIN_NO(165) | 6) +#define PINMUX_GPIO165__FUNC_I0_IPU_JTAG_TDI (MTK_PIN_NO(165) | 7) + +#define PINMUX_GPIO166__FUNC_B_GPIO166 (MTK_PIN_NO(166) | 0) +#define PINMUX_GPIO166__FUNC_B1_MSDC1_DAT1 (MTK_PIN_NO(166) | 1) +#define PINMUX_GPIO166__FUNC_I0_SPDIF_IN2 (MTK_PIN_NO(166) | 2) +#define PINMUX_GPIO166__FUNC_O_MD32_0_JTAG_TDO (MTK_PIN_NO(166) | 3) +#define PINMUX_GPIO166__FUNC_O_ADSP_JTAG0_TDO (MTK_PIN_NO(166) | 4) +#define PINMUX_GPIO166__FUNC_O_SCP_JTAG0_TDO (MTK_PIN_NO(166) | 5) +#define PINMUX_GPIO166__FUNC_O_CCU0_JTAG_TDO (MTK_PIN_NO(166) | 6) +#define PINMUX_GPIO166__FUNC_O_IPU_JTAG_TDO (MTK_PIN_NO(166) | 7) + +#define PINMUX_GPIO167__FUNC_B_GPIO167 (MTK_PIN_NO(167) | 0) +#define PINMUX_GPIO167__FUNC_B1_MSDC1_DAT2 (MTK_PIN_NO(167) | 1) +#define PINMUX_GPIO167__FUNC_O_PWM_0 (MTK_PIN_NO(167) | 2) +#define PINMUX_GPIO167__FUNC_I1_MD32_0_JTAG_TRST (MTK_PIN_NO(167) | 3) +#define PINMUX_GPIO167__FUNC_I1_ADSP_JTAG0_TRSTN (MTK_PIN_NO(167) | 4) +#define PINMUX_GPIO167__FUNC_I0_SCP_JTAG0_TRSTN (MTK_PIN_NO(167) | 5) +#define PINMUX_GPIO167__FUNC_I1_CCU0_JTAG_TRST (MTK_PIN_NO(167) | 6) +#define PINMUX_GPIO167__FUNC_I0_IPU_JTAG_TRST (MTK_PIN_NO(167) | 7) + +#define PINMUX_GPIO168__FUNC_B_GPIO168 (MTK_PIN_NO(168) | 0) +#define PINMUX_GPIO168__FUNC_B1_MSDC1_DAT3 (MTK_PIN_NO(168) | 1) +#define PINMUX_GPIO168__FUNC_O_PWM_1 (MTK_PIN_NO(168) | 2) +#define PINMUX_GPIO168__FUNC_O_CLKM0 (MTK_PIN_NO(168) | 3) + +#define PINMUX_GPIO169__FUNC_B_GPIO169 (MTK_PIN_NO(169) | 0) +#define PINMUX_GPIO169__FUNC_B1_MSDC2_CMD (MTK_PIN_NO(169) | 1) +#define PINMUX_GPIO169__FUNC_O_LVTS_FOUT (MTK_PIN_NO(169) | 2) +#define PINMUX_GPIO169__FUNC_I1_MD32_1_JTAG_TMS (MTK_PIN_NO(169) | 3) +#define PINMUX_GPIO169__FUNC_I0_UDI_TMS (MTK_PIN_NO(169) | 4) +#define PINMUX_GPIO169__FUNC_I0_VPU_UDI_TMS (MTK_PIN_NO(169) | 5) +#define PINMUX_GPIO169__FUNC_B0_TDMIN_MCK (MTK_PIN_NO(169) | 6) +#define PINMUX_GPIO169__FUNC_I1_SSPM_JTAG_TMS (MTK_PIN_NO(169) | 7) + +#define PINMUX_GPIO170__FUNC_B_GPIO170 (MTK_PIN_NO(170) | 0) +#define PINMUX_GPIO170__FUNC_B1_MSDC2_CLK (MTK_PIN_NO(170) | 1) +#define PINMUX_GPIO170__FUNC_O_LVTS_SDO (MTK_PIN_NO(170) | 2) +#define PINMUX_GPIO170__FUNC_I1_MD32_1_JTAG_TCK (MTK_PIN_NO(170) | 3) +#define PINMUX_GPIO170__FUNC_I0_UDI_TCK (MTK_PIN_NO(170) | 4) +#define PINMUX_GPIO170__FUNC_I0_VPU_UDI_TCK (MTK_PIN_NO(170) | 5) +#define PINMUX_GPIO170__FUNC_B0_TDMIN_BCK (MTK_PIN_NO(170) | 6) +#define PINMUX_GPIO170__FUNC_I1_SSPM_JTAG_TCK (MTK_PIN_NO(170) | 7) + +#define PINMUX_GPIO171__FUNC_B_GPIO171 (MTK_PIN_NO(171) | 0) +#define PINMUX_GPIO171__FUNC_B1_MSDC2_DAT0 (MTK_PIN_NO(171) | 1) +#define PINMUX_GPIO171__FUNC_I0_LVTS_26M (MTK_PIN_NO(171) | 2) +#define PINMUX_GPIO171__FUNC_I1_MD32_1_JTAG_TDI (MTK_PIN_NO(171) | 3) +#define PINMUX_GPIO171__FUNC_I0_UDI_TDI (MTK_PIN_NO(171) | 4) +#define PINMUX_GPIO171__FUNC_I0_VPU_UDI_TDI (MTK_PIN_NO(171) | 5) +#define PINMUX_GPIO171__FUNC_B0_TDMIN_LRCK (MTK_PIN_NO(171) | 6) +#define PINMUX_GPIO171__FUNC_I1_SSPM_JTAG_TDI (MTK_PIN_NO(171) | 7) + +#define PINMUX_GPIO172__FUNC_B_GPIO172 (MTK_PIN_NO(172) | 0) +#define PINMUX_GPIO172__FUNC_B1_MSDC2_DAT1 (MTK_PIN_NO(172) | 1) +#define PINMUX_GPIO172__FUNC_I0_LVTS_SCF (MTK_PIN_NO(172) | 2) +#define PINMUX_GPIO172__FUNC_O_MD32_1_JTAG_TDO (MTK_PIN_NO(172) | 3) +#define PINMUX_GPIO172__FUNC_O_UDI_TDO (MTK_PIN_NO(172) | 4) +#define PINMUX_GPIO172__FUNC_O_VPU_UDI_TDO (MTK_PIN_NO(172) | 5) +#define PINMUX_GPIO172__FUNC_I0_TDMIN_DI (MTK_PIN_NO(172) | 6) +#define PINMUX_GPIO172__FUNC_O_SSPM_JTAG_TDO (MTK_PIN_NO(172) | 7) + +#define PINMUX_GPIO173__FUNC_B_GPIO173 (MTK_PIN_NO(173) | 0) +#define PINMUX_GPIO173__FUNC_B1_MSDC2_DAT2 (MTK_PIN_NO(173) | 1) +#define PINMUX_GPIO173__FUNC_I0_LVTS_SCK (MTK_PIN_NO(173) | 2) +#define PINMUX_GPIO173__FUNC_I1_MD32_1_JTAG_TRST (MTK_PIN_NO(173) | 3) +#define PINMUX_GPIO173__FUNC_I0_UDI_NTRST (MTK_PIN_NO(173) | 4) +#define PINMUX_GPIO173__FUNC_I0_VPU_UDI_NTRST (MTK_PIN_NO(173) | 5) +#define PINMUX_GPIO173__FUNC_I0_SSPM_JTAG_TRSTN (MTK_PIN_NO(173) | 7) + +#define PINMUX_GPIO174__FUNC_B_GPIO174 (MTK_PIN_NO(174) | 0) +#define PINMUX_GPIO174__FUNC_B1_MSDC2_DAT3 (MTK_PIN_NO(174) | 1) +#define PINMUX_GPIO174__FUNC_I0_LVTS_SDI (MTK_PIN_NO(174) | 2) + +#define PINMUX_GPIO175__FUNC_B_GPIO175 (MTK_PIN_NO(175) | 0) +#define PINMUX_GPIO175__FUNC_B0_SPMI_M_SCL (MTK_PIN_NO(175) | 1) + +#define PINMUX_GPIO176__FUNC_B_GPIO176 (MTK_PIN_NO(176) | 0) +#define PINMUX_GPIO176__FUNC_B0_SPMI_M_SDA (MTK_PIN_NO(176) | 1) + +#endif /* __MEDIATEK_MT8188-PINFUNC_H */ diff --git a/include/dt-bindings/pinctrl/mt65xx.h b/include/dt-bindings/pinctrl/mt65xx.h index 7e16e58fe1f7..f5934abcd1bd 100644 --- a/include/dt-bindings/pinctrl/mt65xx.h +++ b/include/dt-bindings/pinctrl/mt65xx.h @@ -16,6 +16,15 @@ #define MTK_PUPD_SET_R1R0_10 102 #define MTK_PUPD_SET_R1R0_11 103 +#define MTK_PULL_SET_RSEL_000 200 +#define MTK_PULL_SET_RSEL_001 201 +#define MTK_PULL_SET_RSEL_010 202 +#define MTK_PULL_SET_RSEL_011 203 +#define MTK_PULL_SET_RSEL_100 204 +#define MTK_PULL_SET_RSEL_101 205 +#define MTK_PULL_SET_RSEL_110 206 +#define MTK_PULL_SET_RSEL_111 207 + #define MTK_DRIVE_2mA 2 #define MTK_DRIVE_4mA 4 #define MTK_DRIVE_6mA 6 diff --git a/include/dt-bindings/pinctrl/mt6779-pinfunc.h b/include/dt-bindings/pinctrl/mt6779-pinfunc.h new file mode 100644 index 000000000000..87fdc4310936 --- /dev/null +++ b/include/dt-bindings/pinctrl/mt6779-pinfunc.h @@ -0,0 +1,1242 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 MediaTek Inc. + * Author: Andy Teng <andy.teng@mediatek.com> + * + */ + +#ifndef __MT6779_PINFUNC_H +#define __MT6779_PINFUNC_H + +#include <dt-bindings/pinctrl/mt65xx.h> + +#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define PINMUX_GPIO0__FUNC_SPI6_MI (MTK_PIN_NO(0) | 1) +#define PINMUX_GPIO0__FUNC_I2S5_LRCK (MTK_PIN_NO(0) | 2) +#define PINMUX_GPIO0__FUNC_TDM_LRCK_2ND (MTK_PIN_NO(0) | 3) +#define PINMUX_GPIO0__FUNC_PCM1_SYNC (MTK_PIN_NO(0) | 4) +#define PINMUX_GPIO0__FUNC_SCL_6306 (MTK_PIN_NO(0) | 5) +#define PINMUX_GPIO0__FUNC_TP_GPIO0_AO (MTK_PIN_NO(0) | 6) +#define PINMUX_GPIO0__FUNC_PTA_RXD (MTK_PIN_NO(0) | 7) + +#define PINMUX_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define PINMUX_GPIO1__FUNC_SPI6_CSB (MTK_PIN_NO(1) | 1) +#define PINMUX_GPIO1__FUNC_I2S5_DO (MTK_PIN_NO(1) | 2) +#define PINMUX_GPIO1__FUNC_TDM_DATA0_2ND (MTK_PIN_NO(1) | 3) +#define PINMUX_GPIO1__FUNC_PCM1_DO0 (MTK_PIN_NO(1) | 4) +#define PINMUX_GPIO1__FUNC_SDA_6306 (MTK_PIN_NO(1) | 5) +#define PINMUX_GPIO1__FUNC_TP_GPIO1_AO (MTK_PIN_NO(1) | 6) +#define PINMUX_GPIO1__FUNC_PTA_TXD (MTK_PIN_NO(1) | 7) + +#define PINMUX_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define PINMUX_GPIO2__FUNC_SPI6_MO (MTK_PIN_NO(2) | 1) +#define PINMUX_GPIO2__FUNC_I2S5_BCK (MTK_PIN_NO(2) | 2) +#define PINMUX_GPIO2__FUNC_TDM_BCK_2ND (MTK_PIN_NO(2) | 3) +#define PINMUX_GPIO2__FUNC_PCM1_CLK (MTK_PIN_NO(2) | 4) +#define PINMUX_GPIO2__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(2) | 5) +#define PINMUX_GPIO2__FUNC_TP_GPIO2_AO (MTK_PIN_NO(2) | 6) + +#define PINMUX_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define PINMUX_GPIO3__FUNC_SPI6_CLK (MTK_PIN_NO(3) | 1) +#define PINMUX_GPIO3__FUNC_I2S5_MCK (MTK_PIN_NO(3) | 2) +#define PINMUX_GPIO3__FUNC_TDM_MCK_2ND (MTK_PIN_NO(3) | 3) +#define PINMUX_GPIO3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(3) | 4) +#define PINMUX_GPIO3__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(3) | 5) +#define PINMUX_GPIO3__FUNC_TP_GPIO3_AO (MTK_PIN_NO(3) | 6) + +#define PINMUX_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define PINMUX_GPIO4__FUNC_SPI7_MI (MTK_PIN_NO(4) | 1) +#define PINMUX_GPIO4__FUNC_I2S0_MCK (MTK_PIN_NO(4) | 2) +#define PINMUX_GPIO4__FUNC_TDM_DATA1_2ND (MTK_PIN_NO(4) | 3) +#define PINMUX_GPIO4__FUNC_PCM1_DO1 (MTK_PIN_NO(4) | 4) +#define PINMUX_GPIO4__FUNC_DMIC1_CLK (MTK_PIN_NO(4) | 5) +#define PINMUX_GPIO4__FUNC_TP_GPIO4_AO (MTK_PIN_NO(4) | 6) +#define PINMUX_GPIO4__FUNC_SCL8 (MTK_PIN_NO(4) | 7) + +#define PINMUX_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define PINMUX_GPIO5__FUNC_SPI7_CSB (MTK_PIN_NO(5) | 1) +#define PINMUX_GPIO5__FUNC_I2S0_BCK (MTK_PIN_NO(5) | 2) +#define PINMUX_GPIO5__FUNC_TDM_DATA2_2ND (MTK_PIN_NO(5) | 3) +#define PINMUX_GPIO5__FUNC_PCM1_DO2 (MTK_PIN_NO(5) | 4) +#define PINMUX_GPIO5__FUNC_DMIC1_DAT (MTK_PIN_NO(5) | 5) +#define PINMUX_GPIO5__FUNC_TP_GPIO5_AO (MTK_PIN_NO(5) | 6) +#define PINMUX_GPIO5__FUNC_SDA8 (MTK_PIN_NO(5) | 7) + +#define PINMUX_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define PINMUX_GPIO6__FUNC_SPI7_MO (MTK_PIN_NO(6) | 1) +#define PINMUX_GPIO6__FUNC_I2S0_LRCK (MTK_PIN_NO(6) | 2) +#define PINMUX_GPIO6__FUNC_TDM_DATA3_2ND (MTK_PIN_NO(6) | 3) +#define PINMUX_GPIO6__FUNC_PCM1_DI (MTK_PIN_NO(6) | 4) +#define PINMUX_GPIO6__FUNC_DMIC_CLK (MTK_PIN_NO(6) | 5) +#define PINMUX_GPIO6__FUNC_TP_GPIO6_AO (MTK_PIN_NO(6) | 6) +#define PINMUX_GPIO6__FUNC_SCL9 (MTK_PIN_NO(6) | 7) + +#define PINMUX_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +#define PINMUX_GPIO7__FUNC_SPI7_CLK (MTK_PIN_NO(7) | 1) +#define PINMUX_GPIO7__FUNC_I2S0_DI (MTK_PIN_NO(7) | 2) +#define PINMUX_GPIO7__FUNC_SRCLKENAI1 (MTK_PIN_NO(7) | 3) +#define PINMUX_GPIO7__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(7) | 4) +#define PINMUX_GPIO7__FUNC_DMIC_DAT (MTK_PIN_NO(7) | 5) +#define PINMUX_GPIO7__FUNC_TP_GPIO7_AO (MTK_PIN_NO(7) | 6) +#define PINMUX_GPIO7__FUNC_SDA9 (MTK_PIN_NO(7) | 7) + +#define PINMUX_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +#define PINMUX_GPIO8__FUNC_PWM_0 (MTK_PIN_NO(8) | 1) +#define PINMUX_GPIO8__FUNC_I2S2_DI2 (MTK_PIN_NO(8) | 2) +#define PINMUX_GPIO8__FUNC_SRCLKENAI0 (MTK_PIN_NO(8) | 3) +#define PINMUX_GPIO8__FUNC_URXD1 (MTK_PIN_NO(8) | 4) +#define PINMUX_GPIO8__FUNC_I2S0_MCK (MTK_PIN_NO(8) | 5) +#define PINMUX_GPIO8__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(8) | 6) +#define PINMUX_GPIO8__FUNC_IDDIG (MTK_PIN_NO(8) | 7) + +#define PINMUX_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +#define PINMUX_GPIO9__FUNC_PWM_3 (MTK_PIN_NO(9) | 1) +#define PINMUX_GPIO9__FUNC_MD_INT0 (MTK_PIN_NO(9) | 2) +#define PINMUX_GPIO9__FUNC_SRCLKENAI1 (MTK_PIN_NO(9) | 3) +#define PINMUX_GPIO9__FUNC_UTXD1 (MTK_PIN_NO(9) | 4) +#define PINMUX_GPIO9__FUNC_I2S0_BCK (MTK_PIN_NO(9) | 5) +#define PINMUX_GPIO9__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(9) | 6) +#define PINMUX_GPIO9__FUNC_USB_DRVVBUS (MTK_PIN_NO(9) | 7) + +#define PINMUX_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +#define PINMUX_GPIO10__FUNC_MSDC1_CLK_A (MTK_PIN_NO(10) | 1) +#define PINMUX_GPIO10__FUNC_TP_URXD1_AO (MTK_PIN_NO(10) | 2) +#define PINMUX_GPIO10__FUNC_I2S1_LRCK (MTK_PIN_NO(10) | 3) +#define PINMUX_GPIO10__FUNC_UCTS0 (MTK_PIN_NO(10) | 4) +#define PINMUX_GPIO10__FUNC_DMIC1_CLK (MTK_PIN_NO(10) | 5) +#define PINMUX_GPIO10__FUNC_KPCOL2 (MTK_PIN_NO(10) | 6) +#define PINMUX_GPIO10__FUNC_SCL8 (MTK_PIN_NO(10) | 7) + +#define PINMUX_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +#define PINMUX_GPIO11__FUNC_MSDC1_CMD_A (MTK_PIN_NO(11) | 1) +#define PINMUX_GPIO11__FUNC_TP_UTXD1_AO (MTK_PIN_NO(11) | 2) +#define PINMUX_GPIO11__FUNC_I2S1_DO (MTK_PIN_NO(11) | 3) +#define PINMUX_GPIO11__FUNC_URTS0 (MTK_PIN_NO(11) | 4) +#define PINMUX_GPIO11__FUNC_DMIC1_DAT (MTK_PIN_NO(11) | 5) +#define PINMUX_GPIO11__FUNC_KPROW2 (MTK_PIN_NO(11) | 6) +#define PINMUX_GPIO11__FUNC_SDA8 (MTK_PIN_NO(11) | 7) + +#define PINMUX_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +#define PINMUX_GPIO12__FUNC_MSDC1_DAT3_A (MTK_PIN_NO(12) | 1) +#define PINMUX_GPIO12__FUNC_TP_URXD2_AO (MTK_PIN_NO(12) | 2) +#define PINMUX_GPIO12__FUNC_I2S1_MCK (MTK_PIN_NO(12) | 3) +#define PINMUX_GPIO12__FUNC_UCTS1 (MTK_PIN_NO(12) | 4) +#define PINMUX_GPIO12__FUNC_DMIC_CLK (MTK_PIN_NO(12) | 5) +#define PINMUX_GPIO12__FUNC_ANT_SEL9 (MTK_PIN_NO(12) | 6) +#define PINMUX_GPIO12__FUNC_SCL9 (MTK_PIN_NO(12) | 7) + +#define PINMUX_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) +#define PINMUX_GPIO13__FUNC_MSDC1_DAT0_A (MTK_PIN_NO(13) | 1) +#define PINMUX_GPIO13__FUNC_TP_UTXD2_AO (MTK_PIN_NO(13) | 2) +#define PINMUX_GPIO13__FUNC_I2S1_BCK (MTK_PIN_NO(13) | 3) +#define PINMUX_GPIO13__FUNC_URTS1 (MTK_PIN_NO(13) | 4) +#define PINMUX_GPIO13__FUNC_DMIC_DAT (MTK_PIN_NO(13) | 5) +#define PINMUX_GPIO13__FUNC_ANT_SEL10 (MTK_PIN_NO(13) | 6) +#define PINMUX_GPIO13__FUNC_SDA9 (MTK_PIN_NO(13) | 7) + +#define PINMUX_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) +#define PINMUX_GPIO14__FUNC_MSDC1_DAT2_A (MTK_PIN_NO(14) | 1) +#define PINMUX_GPIO14__FUNC_PWM_3 (MTK_PIN_NO(14) | 2) +#define PINMUX_GPIO14__FUNC_IDDIG (MTK_PIN_NO(14) | 3) +#define PINMUX_GPIO14__FUNC_MD_INT0 (MTK_PIN_NO(14) | 4) +#define PINMUX_GPIO14__FUNC_PTA_RXD (MTK_PIN_NO(14) | 5) +#define PINMUX_GPIO14__FUNC_ANT_SEL11 (MTK_PIN_NO(14) | 6) + +#define PINMUX_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) +#define PINMUX_GPIO15__FUNC_MSDC1_DAT1_A (MTK_PIN_NO(15) | 1) +#define PINMUX_GPIO15__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(15) | 2) +#define PINMUX_GPIO15__FUNC_USB_DRVVBUS (MTK_PIN_NO(15) | 3) +#define PINMUX_GPIO15__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(15) | 4) +#define PINMUX_GPIO15__FUNC_PTA_TXD (MTK_PIN_NO(15) | 5) +#define PINMUX_GPIO15__FUNC_ANT_SEL12 (MTK_PIN_NO(15) | 6) + +#define PINMUX_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) +#define PINMUX_GPIO16__FUNC_SRCLKENAI0 (MTK_PIN_NO(16) | 1) +#define PINMUX_GPIO16__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(16) | 2) +#define PINMUX_GPIO16__FUNC_MFG_EJTAG_TRSTN (MTK_PIN_NO(16) | 3) +#define PINMUX_GPIO16__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(16) | 4) +#define PINMUX_GPIO16__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(16) | 5) +#define PINMUX_GPIO16__FUNC_PWM_2 (MTK_PIN_NO(16) | 6) +#define PINMUX_GPIO16__FUNC_JTRSTN_SEL1 (MTK_PIN_NO(16) | 7) + +#define PINMUX_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) +#define PINMUX_GPIO17__FUNC_SPI0_A_MI (MTK_PIN_NO(17) | 1) +#define PINMUX_GPIO17__FUNC_SCP_SPI0_MI (MTK_PIN_NO(17) | 2) +#define PINMUX_GPIO17__FUNC_MFG_EJTAG_TDO (MTK_PIN_NO(17) | 3) +#define PINMUX_GPIO17__FUNC_DPI_HSYNC (MTK_PIN_NO(17) | 4) +#define PINMUX_GPIO17__FUNC_MFG_DFD_JTAG_TDO (MTK_PIN_NO(17) | 5) +#define PINMUX_GPIO17__FUNC_DFD_TDO (MTK_PIN_NO(17) | 6) +#define PINMUX_GPIO17__FUNC_JTDO_SEL1 (MTK_PIN_NO(17) | 7) + +#define PINMUX_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) +#define PINMUX_GPIO18__FUNC_SPI0_A_MO (MTK_PIN_NO(18) | 1) +#define PINMUX_GPIO18__FUNC_SCP_SPI0_MO (MTK_PIN_NO(18) | 2) +#define PINMUX_GPIO18__FUNC_MFG_EJTAG_TDI (MTK_PIN_NO(18) | 3) +#define PINMUX_GPIO18__FUNC_DPI_VSYNC (MTK_PIN_NO(18) | 4) +#define PINMUX_GPIO18__FUNC_MFG_DFD_JTAG_TDI (MTK_PIN_NO(18) | 5) +#define PINMUX_GPIO18__FUNC_DFD_TDI (MTK_PIN_NO(18) | 6) +#define PINMUX_GPIO18__FUNC_JTDI_SEL1 (MTK_PIN_NO(18) | 7) + +#define PINMUX_GPIO19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) +#define PINMUX_GPIO19__FUNC_SPI0_A_CSB (MTK_PIN_NO(19) | 1) +#define PINMUX_GPIO19__FUNC_SCP_SPI0_CS (MTK_PIN_NO(19) | 2) +#define PINMUX_GPIO19__FUNC_MFG_EJTAG_TMS (MTK_PIN_NO(19) | 3) +#define PINMUX_GPIO19__FUNC_DPI_DE (MTK_PIN_NO(19) | 4) +#define PINMUX_GPIO19__FUNC_MFG_DFD_JTAG_TMS (MTK_PIN_NO(19) | 5) +#define PINMUX_GPIO19__FUNC_DFD_TMS (MTK_PIN_NO(19) | 6) +#define PINMUX_GPIO19__FUNC_JTMS_SEL1 (MTK_PIN_NO(19) | 7) + +#define PINMUX_GPIO20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) +#define PINMUX_GPIO20__FUNC_SPI0_A_CLK (MTK_PIN_NO(20) | 1) +#define PINMUX_GPIO20__FUNC_SCP_SPI0_CK (MTK_PIN_NO(20) | 2) +#define PINMUX_GPIO20__FUNC_MFG_EJTAG_TCK (MTK_PIN_NO(20) | 3) +#define PINMUX_GPIO20__FUNC_DPI_CK (MTK_PIN_NO(20) | 4) +#define PINMUX_GPIO20__FUNC_MFG_DFD_JTAG_TCK (MTK_PIN_NO(20) | 5) +#define PINMUX_GPIO20__FUNC_DFD_TCK_XI (MTK_PIN_NO(20) | 6) +#define PINMUX_GPIO20__FUNC_JTCK_SEL1 (MTK_PIN_NO(20) | 7) + +#define PINMUX_GPIO21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) +#define PINMUX_GPIO21__FUNC_PWM_0 (MTK_PIN_NO(21) | 1) +#define PINMUX_GPIO21__FUNC_CMFLASH0 (MTK_PIN_NO(21) | 2) +#define PINMUX_GPIO21__FUNC_CMVREF2 (MTK_PIN_NO(21) | 3) +#define PINMUX_GPIO21__FUNC_CLKM0 (MTK_PIN_NO(21) | 4) +#define PINMUX_GPIO21__FUNC_ANT_SEL9 (MTK_PIN_NO(21) | 5) +#define PINMUX_GPIO21__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(21) | 6) +#define PINMUX_GPIO21__FUNC_DBG_MON_A27 (MTK_PIN_NO(21) | 7) + +#define PINMUX_GPIO22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) +#define PINMUX_GPIO22__FUNC_PWM_1 (MTK_PIN_NO(22) | 1) +#define PINMUX_GPIO22__FUNC_CMFLASH1 (MTK_PIN_NO(22) | 2) +#define PINMUX_GPIO22__FUNC_CMVREF3 (MTK_PIN_NO(22) | 3) +#define PINMUX_GPIO22__FUNC_CLKM1 (MTK_PIN_NO(22) | 4) +#define PINMUX_GPIO22__FUNC_ANT_SEL10 (MTK_PIN_NO(22) | 5) +#define PINMUX_GPIO22__FUNC_DBG_MON_A28 (MTK_PIN_NO(22) | 7) + +#define PINMUX_GPIO23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) +#define PINMUX_GPIO23__FUNC_PWM_2 (MTK_PIN_NO(23) | 1) +#define PINMUX_GPIO23__FUNC_CMFLASH2 (MTK_PIN_NO(23) | 2) +#define PINMUX_GPIO23__FUNC_CMVREF0 (MTK_PIN_NO(23) | 3) +#define PINMUX_GPIO23__FUNC_CLKM2 (MTK_PIN_NO(23) | 4) +#define PINMUX_GPIO23__FUNC_ANT_SEL11 (MTK_PIN_NO(23) | 5) +#define PINMUX_GPIO23__FUNC_DBG_MON_A29 (MTK_PIN_NO(23) | 7) + +#define PINMUX_GPIO24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) +#define PINMUX_GPIO24__FUNC_PWM_0 (MTK_PIN_NO(24) | 1) +#define PINMUX_GPIO24__FUNC_CMFLASH3 (MTK_PIN_NO(24) | 2) +#define PINMUX_GPIO24__FUNC_CMVREF1 (MTK_PIN_NO(24) | 3) +#define PINMUX_GPIO24__FUNC_CLKM3 (MTK_PIN_NO(24) | 4) +#define PINMUX_GPIO24__FUNC_ANT_SEL12 (MTK_PIN_NO(24) | 5) +#define PINMUX_GPIO24__FUNC_DBG_MON_A30 (MTK_PIN_NO(24) | 7) + +#define PINMUX_GPIO25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) +#define PINMUX_GPIO25__FUNC_SRCLKENAI0 (MTK_PIN_NO(25) | 1) +#define PINMUX_GPIO25__FUNC_UCTS0 (MTK_PIN_NO(25) | 2) +#define PINMUX_GPIO25__FUNC_SCL8 (MTK_PIN_NO(25) | 3) +#define PINMUX_GPIO25__FUNC_CMVREF4 (MTK_PIN_NO(25) | 4) +#define PINMUX_GPIO25__FUNC_I2S0_LRCK (MTK_PIN_NO(25) | 5) +#define PINMUX_GPIO25__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(25) | 6) +#define PINMUX_GPIO25__FUNC_DBG_MON_A31 (MTK_PIN_NO(25) | 7) + +#define PINMUX_GPIO26__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) +#define PINMUX_GPIO26__FUNC_PWM_0 (MTK_PIN_NO(26) | 1) +#define PINMUX_GPIO26__FUNC_URTS0 (MTK_PIN_NO(26) | 2) +#define PINMUX_GPIO26__FUNC_SDA8 (MTK_PIN_NO(26) | 3) +#define PINMUX_GPIO26__FUNC_CLKM0 (MTK_PIN_NO(26) | 4) +#define PINMUX_GPIO26__FUNC_I2S0_DI (MTK_PIN_NO(26) | 5) +#define PINMUX_GPIO26__FUNC_AGPS_SYNC (MTK_PIN_NO(26) | 6) +#define PINMUX_GPIO26__FUNC_DBG_MON_A32 (MTK_PIN_NO(26) | 7) + +#define PINMUX_GPIO27__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) +#define PINMUX_GPIO27__FUNC_AP_GOOD (MTK_PIN_NO(27) | 1) + +#define PINMUX_GPIO28__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) +#define PINMUX_GPIO28__FUNC_SCL5 (MTK_PIN_NO(28) | 1) + +#define PINMUX_GPIO29__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) +#define PINMUX_GPIO29__FUNC_SDA5 (MTK_PIN_NO(29) | 1) + +#define PINMUX_GPIO30__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) +#define PINMUX_GPIO30__FUNC_I2S1_MCK (MTK_PIN_NO(30) | 1) +#define PINMUX_GPIO30__FUNC_I2S3_MCK (MTK_PIN_NO(30) | 2) +#define PINMUX_GPIO30__FUNC_I2S2_MCK (MTK_PIN_NO(30) | 3) +#define PINMUX_GPIO30__FUNC_DPI_D0 (MTK_PIN_NO(30) | 4) +#define PINMUX_GPIO30__FUNC_SPI4_MI (MTK_PIN_NO(30) | 5) +#define PINMUX_GPIO30__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(30) | 6) + +#define PINMUX_GPIO31__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) +#define PINMUX_GPIO31__FUNC_I2S1_BCK (MTK_PIN_NO(31) | 1) +#define PINMUX_GPIO31__FUNC_I2S3_BCK (MTK_PIN_NO(31) | 2) +#define PINMUX_GPIO31__FUNC_I2S2_BCK (MTK_PIN_NO(31) | 3) +#define PINMUX_GPIO31__FUNC_DPI_D1 (MTK_PIN_NO(31) | 4) +#define PINMUX_GPIO31__FUNC_SPI4_CSB (MTK_PIN_NO(31) | 5) +#define PINMUX_GPIO31__FUNC_CONN_MCU_TDO (MTK_PIN_NO(31) | 6) + +#define PINMUX_GPIO32__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) +#define PINMUX_GPIO32__FUNC_I2S1_LRCK (MTK_PIN_NO(32) | 1) +#define PINMUX_GPIO32__FUNC_I2S3_LRCK (MTK_PIN_NO(32) | 2) +#define PINMUX_GPIO32__FUNC_I2S2_LRCK (MTK_PIN_NO(32) | 3) +#define PINMUX_GPIO32__FUNC_DPI_D2 (MTK_PIN_NO(32) | 4) +#define PINMUX_GPIO32__FUNC_SPI4_MO (MTK_PIN_NO(32) | 5) +#define PINMUX_GPIO32__FUNC_CONN_MCU_TDI (MTK_PIN_NO(32) | 6) + +#define PINMUX_GPIO33__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) +#define PINMUX_GPIO33__FUNC_I2S2_DI (MTK_PIN_NO(33) | 1) +#define PINMUX_GPIO33__FUNC_I2S0_DI (MTK_PIN_NO(33) | 2) +#define PINMUX_GPIO33__FUNC_I2S5_DO (MTK_PIN_NO(33) | 3) +#define PINMUX_GPIO33__FUNC_DPI_D3 (MTK_PIN_NO(33) | 4) +#define PINMUX_GPIO33__FUNC_SPI4_CLK (MTK_PIN_NO(33) | 5) +#define PINMUX_GPIO33__FUNC_CONN_MCU_TMS (MTK_PIN_NO(33) | 6) + +#define PINMUX_GPIO34__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) +#define PINMUX_GPIO34__FUNC_I2S1_DO (MTK_PIN_NO(34) | 1) +#define PINMUX_GPIO34__FUNC_I2S3_DO (MTK_PIN_NO(34) | 2) +#define PINMUX_GPIO34__FUNC_I2S2_DI2 (MTK_PIN_NO(34) | 3) +#define PINMUX_GPIO34__FUNC_DPI_D4 (MTK_PIN_NO(34) | 4) +#define PINMUX_GPIO34__FUNC_AGPS_SYNC (MTK_PIN_NO(34) | 5) +#define PINMUX_GPIO34__FUNC_CONN_MCU_TCK (MTK_PIN_NO(34) | 6) + +#define PINMUX_GPIO35__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) +#define PINMUX_GPIO35__FUNC_TDM_LRCK (MTK_PIN_NO(35) | 1) +#define PINMUX_GPIO35__FUNC_I2S1_LRCK (MTK_PIN_NO(35) | 2) +#define PINMUX_GPIO35__FUNC_I2S5_LRCK (MTK_PIN_NO(35) | 3) +#define PINMUX_GPIO35__FUNC_DPI_D5 (MTK_PIN_NO(35) | 4) +#define PINMUX_GPIO35__FUNC_SPI5_A_MO (MTK_PIN_NO(35) | 5) +#define PINMUX_GPIO35__FUNC_IO_JTAG_TDI (MTK_PIN_NO(35) | 6) +#define PINMUX_GPIO35__FUNC_PWM_2 (MTK_PIN_NO(35) | 7) + +#define PINMUX_GPIO36__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) +#define PINMUX_GPIO36__FUNC_TDM_BCK (MTK_PIN_NO(36) | 1) +#define PINMUX_GPIO36__FUNC_I2S1_BCK (MTK_PIN_NO(36) | 2) +#define PINMUX_GPIO36__FUNC_I2S5_BCK (MTK_PIN_NO(36) | 3) +#define PINMUX_GPIO36__FUNC_DPI_D6 (MTK_PIN_NO(36) | 4) +#define PINMUX_GPIO36__FUNC_SPI5_A_CSB (MTK_PIN_NO(36) | 5) +#define PINMUX_GPIO36__FUNC_IO_JTAG_TRSTN (MTK_PIN_NO(36) | 6) +#define PINMUX_GPIO36__FUNC_SRCLKENAI1 (MTK_PIN_NO(36) | 7) + +#define PINMUX_GPIO37__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) +#define PINMUX_GPIO37__FUNC_TDM_MCK (MTK_PIN_NO(37) | 1) +#define PINMUX_GPIO37__FUNC_I2S1_MCK (MTK_PIN_NO(37) | 2) +#define PINMUX_GPIO37__FUNC_I2S5_MCK (MTK_PIN_NO(37) | 3) +#define PINMUX_GPIO37__FUNC_DPI_D7 (MTK_PIN_NO(37) | 4) +#define PINMUX_GPIO37__FUNC_SPI5_A_MI (MTK_PIN_NO(37) | 5) +#define PINMUX_GPIO37__FUNC_IO_JTAG_TCK (MTK_PIN_NO(37) | 6) +#define PINMUX_GPIO37__FUNC_SRCLKENAI0 (MTK_PIN_NO(37) | 7) + +#define PINMUX_GPIO38__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) +#define PINMUX_GPIO38__FUNC_TDM_DATA0 (MTK_PIN_NO(38) | 1) +#define PINMUX_GPIO38__FUNC_I2S2_DI (MTK_PIN_NO(38) | 2) +#define PINMUX_GPIO38__FUNC_I2S5_DO (MTK_PIN_NO(38) | 3) +#define PINMUX_GPIO38__FUNC_DPI_D8 (MTK_PIN_NO(38) | 4) +#define PINMUX_GPIO38__FUNC_SPI5_A_CLK (MTK_PIN_NO(38) | 5) +#define PINMUX_GPIO38__FUNC_IO_JTAG_TDO (MTK_PIN_NO(38) | 6) +#define PINMUX_GPIO38__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(38) | 7) + +#define PINMUX_GPIO39__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) +#define PINMUX_GPIO39__FUNC_TDM_DATA1 (MTK_PIN_NO(39) | 1) +#define PINMUX_GPIO39__FUNC_I2S1_DO (MTK_PIN_NO(39) | 2) +#define PINMUX_GPIO39__FUNC_I2S2_DI2 (MTK_PIN_NO(39) | 3) +#define PINMUX_GPIO39__FUNC_DPI_D9 (MTK_PIN_NO(39) | 4) +#define PINMUX_GPIO39__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(39) | 5) +#define PINMUX_GPIO39__FUNC_IO_JTAG_TMS (MTK_PIN_NO(39) | 6) +#define PINMUX_GPIO39__FUNC_IDDIG (MTK_PIN_NO(39) | 7) + +#define PINMUX_GPIO40__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) +#define PINMUX_GPIO40__FUNC_TDM_DATA2 (MTK_PIN_NO(40) | 1) +#define PINMUX_GPIO40__FUNC_SCL9 (MTK_PIN_NO(40) | 2) +#define PINMUX_GPIO40__FUNC_PWM_3 (MTK_PIN_NO(40) | 3) +#define PINMUX_GPIO40__FUNC_DPI_D10 (MTK_PIN_NO(40) | 4) +#define PINMUX_GPIO40__FUNC_SRCLKENAI0 (MTK_PIN_NO(40) | 5) +#define PINMUX_GPIO40__FUNC_DAP_MD32_SWD (MTK_PIN_NO(40) | 6) +#define PINMUX_GPIO40__FUNC_USB_DRVVBUS (MTK_PIN_NO(40) | 7) + +#define PINMUX_GPIO41__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) +#define PINMUX_GPIO41__FUNC_TDM_DATA3 (MTK_PIN_NO(41) | 1) +#define PINMUX_GPIO41__FUNC_SDA9 (MTK_PIN_NO(41) | 2) +#define PINMUX_GPIO41__FUNC_PWM_1 (MTK_PIN_NO(41) | 3) +#define PINMUX_GPIO41__FUNC_DPI_D11 (MTK_PIN_NO(41) | 4) +#define PINMUX_GPIO41__FUNC_CLKM1 (MTK_PIN_NO(41) | 5) +#define PINMUX_GPIO41__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(41) | 6) + +#define PINMUX_GPIO42__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) +#define PINMUX_GPIO42__FUNC_DISP_PWM (MTK_PIN_NO(42) | 1) + +#define PINMUX_GPIO43__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) +#define PINMUX_GPIO43__FUNC_DSI_TE (MTK_PIN_NO(43) | 1) + +#define PINMUX_GPIO44__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) +#define PINMUX_GPIO44__FUNC_LCM_RST (MTK_PIN_NO(44) | 1) + +#define PINMUX_GPIO45__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) +#define PINMUX_GPIO45__FUNC_SCL6 (MTK_PIN_NO(45) | 1) +#define PINMUX_GPIO45__FUNC_SCP_SCL0 (MTK_PIN_NO(45) | 2) +#define PINMUX_GPIO45__FUNC_SCP_SCL1 (MTK_PIN_NO(45) | 3) +#define PINMUX_GPIO45__FUNC_SCL_6306 (MTK_PIN_NO(45) | 4) + +#define PINMUX_GPIO46__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) +#define PINMUX_GPIO46__FUNC_SDA6 (MTK_PIN_NO(46) | 1) +#define PINMUX_GPIO46__FUNC_SCP_SDA0 (MTK_PIN_NO(46) | 2) +#define PINMUX_GPIO46__FUNC_SCP_SDA1 (MTK_PIN_NO(46) | 3) +#define PINMUX_GPIO46__FUNC_SDA_6306 (MTK_PIN_NO(46) | 4) + +#define PINMUX_GPIO47__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) +#define PINMUX_GPIO47__FUNC_SPI1_A_MI (MTK_PIN_NO(47) | 1) +#define PINMUX_GPIO47__FUNC_SCP_SPI1_A_MI (MTK_PIN_NO(47) | 2) +#define PINMUX_GPIO47__FUNC_KPCOL2 (MTK_PIN_NO(47) | 3) +#define PINMUX_GPIO47__FUNC_MD_URXD0 (MTK_PIN_NO(47) | 4) +#define PINMUX_GPIO47__FUNC_CONN_UART0_RXD (MTK_PIN_NO(47) | 5) +#define PINMUX_GPIO47__FUNC_SSPM_URXD_AO (MTK_PIN_NO(47) | 6) +#define PINMUX_GPIO47__FUNC_DBG_MON_B32 (MTK_PIN_NO(47) | 7) + +#define PINMUX_GPIO48__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) +#define PINMUX_GPIO48__FUNC_SPI1_A_CSB (MTK_PIN_NO(48) | 1) +#define PINMUX_GPIO48__FUNC_SCP_SPI1_A_CS (MTK_PIN_NO(48) | 2) +#define PINMUX_GPIO48__FUNC_KPROW2 (MTK_PIN_NO(48) | 3) +#define PINMUX_GPIO48__FUNC_MD_UTXD0 (MTK_PIN_NO(48) | 4) +#define PINMUX_GPIO48__FUNC_CONN_UART0_TXD (MTK_PIN_NO(48) | 5) +#define PINMUX_GPIO48__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(48) | 6) +#define PINMUX_GPIO48__FUNC_DBG_MON_B31 (MTK_PIN_NO(48) | 7) + +#define PINMUX_GPIO49__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) +#define PINMUX_GPIO49__FUNC_SPI1_A_MO (MTK_PIN_NO(49) | 1) +#define PINMUX_GPIO49__FUNC_SCP_SPI1_A_MO (MTK_PIN_NO(49) | 2) +#define PINMUX_GPIO49__FUNC_UCTS0 (MTK_PIN_NO(49) | 3) +#define PINMUX_GPIO49__FUNC_MD_URXD1 (MTK_PIN_NO(49) | 4) +#define PINMUX_GPIO49__FUNC_PWM_1 (MTK_PIN_NO(49) | 5) +#define PINMUX_GPIO49__FUNC_TP_URXD2_AO (MTK_PIN_NO(49) | 6) +#define PINMUX_GPIO49__FUNC_DBG_MON_B30 (MTK_PIN_NO(49) | 7) + +#define PINMUX_GPIO50__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) +#define PINMUX_GPIO50__FUNC_SPI1_A_CLK (MTK_PIN_NO(50) | 1) +#define PINMUX_GPIO50__FUNC_SCP_SPI1_A_CK (MTK_PIN_NO(50) | 2) +#define PINMUX_GPIO50__FUNC_URTS0 (MTK_PIN_NO(50) | 3) +#define PINMUX_GPIO50__FUNC_MD_UTXD1 (MTK_PIN_NO(50) | 4) +#define PINMUX_GPIO50__FUNC_WIFI_TXD (MTK_PIN_NO(50) | 5) +#define PINMUX_GPIO50__FUNC_TP_UTXD2_AO (MTK_PIN_NO(50) | 6) +#define PINMUX_GPIO50__FUNC_DBG_MON_B29 (MTK_PIN_NO(50) | 7) + +#define PINMUX_GPIO51__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) +#define PINMUX_GPIO51__FUNC_SCL0 (MTK_PIN_NO(51) | 1) + +#define PINMUX_GPIO52__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) +#define PINMUX_GPIO52__FUNC_SDA0 (MTK_PIN_NO(52) | 1) + +#define PINMUX_GPIO53__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) +#define PINMUX_GPIO53__FUNC_URXD0 (MTK_PIN_NO(53) | 1) +#define PINMUX_GPIO53__FUNC_UTXD0 (MTK_PIN_NO(53) | 2) +#define PINMUX_GPIO53__FUNC_MD_URXD0 (MTK_PIN_NO(53) | 3) +#define PINMUX_GPIO53__FUNC_MD_URXD1 (MTK_PIN_NO(53) | 4) +#define PINMUX_GPIO53__FUNC_SSPM_URXD_AO (MTK_PIN_NO(53) | 5) +#define PINMUX_GPIO53__FUNC_CONN_UART0_RXD (MTK_PIN_NO(53) | 7) + +#define PINMUX_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) +#define PINMUX_GPIO54__FUNC_UTXD0 (MTK_PIN_NO(54) | 1) +#define PINMUX_GPIO54__FUNC_URXD0 (MTK_PIN_NO(54) | 2) +#define PINMUX_GPIO54__FUNC_MD_UTXD0 (MTK_PIN_NO(54) | 3) +#define PINMUX_GPIO54__FUNC_MD_UTXD1 (MTK_PIN_NO(54) | 4) +#define PINMUX_GPIO54__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(54) | 5) +#define PINMUX_GPIO54__FUNC_WIFI_TXD (MTK_PIN_NO(54) | 6) +#define PINMUX_GPIO54__FUNC_CONN_UART0_TXD (MTK_PIN_NO(54) | 7) + +#define PINMUX_GPIO55__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) +#define PINMUX_GPIO55__FUNC_SCL3 (MTK_PIN_NO(55) | 1) +#define PINMUX_GPIO55__FUNC_SCP_SCL0 (MTK_PIN_NO(55) | 2) +#define PINMUX_GPIO55__FUNC_SCP_SCL1 (MTK_PIN_NO(55) | 3) +#define PINMUX_GPIO55__FUNC_SCL_6306 (MTK_PIN_NO(55) | 4) + +#define PINMUX_GPIO56__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) +#define PINMUX_GPIO56__FUNC_SDA3 (MTK_PIN_NO(56) | 1) +#define PINMUX_GPIO56__FUNC_SCP_SDA0 (MTK_PIN_NO(56) | 2) +#define PINMUX_GPIO56__FUNC_SCP_SDA1 (MTK_PIN_NO(56) | 3) +#define PINMUX_GPIO56__FUNC_SDA_6306 (MTK_PIN_NO(56) | 4) + +#define PINMUX_GPIO57__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) +#define PINMUX_GPIO57__FUNC_KPROW1 (MTK_PIN_NO(57) | 1) +#define PINMUX_GPIO57__FUNC_PWM_1 (MTK_PIN_NO(57) | 2) +#define PINMUX_GPIO57__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(57) | 3) +#define PINMUX_GPIO57__FUNC_CLKM1 (MTK_PIN_NO(57) | 4) +#define PINMUX_GPIO57__FUNC_IDDIG (MTK_PIN_NO(57) | 5) +#define PINMUX_GPIO57__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(57) | 6) +#define PINMUX_GPIO57__FUNC_MBISTREADEN_TRIGGER (MTK_PIN_NO(57) | 7) + +#define PINMUX_GPIO58__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) +#define PINMUX_GPIO58__FUNC_KPROW0 (MTK_PIN_NO(58) | 1) +#define PINMUX_GPIO58__FUNC_DBG_MON_B28 (MTK_PIN_NO(58) | 7) + +#define PINMUX_GPIO59__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) +#define PINMUX_GPIO59__FUNC_KPCOL0 (MTK_PIN_NO(59) | 1) +#define PINMUX_GPIO59__FUNC_DBG_MON_B27 (MTK_PIN_NO(59) | 7) + +#define PINMUX_GPIO60__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) +#define PINMUX_GPIO60__FUNC_KPCOL1 (MTK_PIN_NO(60) | 1) +#define PINMUX_GPIO60__FUNC_PWM_2 (MTK_PIN_NO(60) | 2) +#define PINMUX_GPIO60__FUNC_UCTS1 (MTK_PIN_NO(60) | 3) +#define PINMUX_GPIO60__FUNC_CLKM2 (MTK_PIN_NO(60) | 4) +#define PINMUX_GPIO60__FUNC_USB_DRVVBUS (MTK_PIN_NO(60) | 5) +#define PINMUX_GPIO60__FUNC_MBISTWRITEEN_TRIGGER (MTK_PIN_NO(60) | 7) + +#define PINMUX_GPIO61__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) +#define PINMUX_GPIO61__FUNC_SCL1 (MTK_PIN_NO(61) | 1) +#define PINMUX_GPIO61__FUNC_SCP_SCL0 (MTK_PIN_NO(61) | 2) +#define PINMUX_GPIO61__FUNC_SCP_SCL1 (MTK_PIN_NO(61) | 3) + +#define PINMUX_GPIO62__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) +#define PINMUX_GPIO62__FUNC_SDA1 (MTK_PIN_NO(62) | 1) +#define PINMUX_GPIO62__FUNC_SCP_SDA0 (MTK_PIN_NO(62) | 2) +#define PINMUX_GPIO62__FUNC_SCP_SDA1 (MTK_PIN_NO(62) | 3) + +#define PINMUX_GPIO63__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) +#define PINMUX_GPIO63__FUNC_SPI2_MI (MTK_PIN_NO(63) | 1) +#define PINMUX_GPIO63__FUNC_SCP_SPI2_MI (MTK_PIN_NO(63) | 2) +#define PINMUX_GPIO63__FUNC_KPCOL2 (MTK_PIN_NO(63) | 3) +#define PINMUX_GPIO63__FUNC_MRG_DI (MTK_PIN_NO(63) | 4) +#define PINMUX_GPIO63__FUNC_MD_URXD0 (MTK_PIN_NO(63) | 5) +#define PINMUX_GPIO63__FUNC_CONN_UART0_RXD (MTK_PIN_NO(63) | 6) +#define PINMUX_GPIO63__FUNC_DBG_MON_B26 (MTK_PIN_NO(63) | 7) + +#define PINMUX_GPIO64__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) +#define PINMUX_GPIO64__FUNC_SPI2_CSB (MTK_PIN_NO(64) | 1) +#define PINMUX_GPIO64__FUNC_SCP_SPI2_CS (MTK_PIN_NO(64) | 2) +#define PINMUX_GPIO64__FUNC_KPROW2 (MTK_PIN_NO(64) | 3) +#define PINMUX_GPIO64__FUNC_MRG_SYNC (MTK_PIN_NO(64) | 4) +#define PINMUX_GPIO64__FUNC_MD_UTXD0 (MTK_PIN_NO(64) | 5) +#define PINMUX_GPIO64__FUNC_CONN_UART0_TXD (MTK_PIN_NO(64) | 6) +#define PINMUX_GPIO64__FUNC_DBG_MON_B25 (MTK_PIN_NO(64) | 7) + +#define PINMUX_GPIO65__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) +#define PINMUX_GPIO65__FUNC_SPI2_MO (MTK_PIN_NO(65) | 1) +#define PINMUX_GPIO65__FUNC_SCP_SPI2_MO (MTK_PIN_NO(65) | 2) +#define PINMUX_GPIO65__FUNC_SCP_SDA1 (MTK_PIN_NO(65) | 3) +#define PINMUX_GPIO65__FUNC_MRG_DO (MTK_PIN_NO(65) | 4) +#define PINMUX_GPIO65__FUNC_MD_URXD1 (MTK_PIN_NO(65) | 5) +#define PINMUX_GPIO65__FUNC_PWM_3 (MTK_PIN_NO(65) | 6) + +#define PINMUX_GPIO66__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) +#define PINMUX_GPIO66__FUNC_SPI2_CLK (MTK_PIN_NO(66) | 1) +#define PINMUX_GPIO66__FUNC_SCP_SPI2_CK (MTK_PIN_NO(66) | 2) +#define PINMUX_GPIO66__FUNC_SCP_SCL1 (MTK_PIN_NO(66) | 3) +#define PINMUX_GPIO66__FUNC_MRG_CLK (MTK_PIN_NO(66) | 4) +#define PINMUX_GPIO66__FUNC_MD_UTXD1 (MTK_PIN_NO(66) | 5) +#define PINMUX_GPIO66__FUNC_WIFI_TXD (MTK_PIN_NO(66) | 6) + +#define PINMUX_GPIO67__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) +#define PINMUX_GPIO67__FUNC_I2S3_LRCK (MTK_PIN_NO(67) | 1) +#define PINMUX_GPIO67__FUNC_I2S1_LRCK (MTK_PIN_NO(67) | 2) +#define PINMUX_GPIO67__FUNC_URXD1 (MTK_PIN_NO(67) | 3) +#define PINMUX_GPIO67__FUNC_PCM0_SYNC (MTK_PIN_NO(67) | 4) +#define PINMUX_GPIO67__FUNC_I2S5_LRCK (MTK_PIN_NO(67) | 5) +#define PINMUX_GPIO67__FUNC_ANT_SEL9 (MTK_PIN_NO(67) | 6) +#define PINMUX_GPIO67__FUNC_DBG_MON_B10 (MTK_PIN_NO(67) | 7) + +#define PINMUX_GPIO68__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) +#define PINMUX_GPIO68__FUNC_I2S3_DO (MTK_PIN_NO(68) | 1) +#define PINMUX_GPIO68__FUNC_I2S1_DO (MTK_PIN_NO(68) | 2) +#define PINMUX_GPIO68__FUNC_UTXD1 (MTK_PIN_NO(68) | 3) +#define PINMUX_GPIO68__FUNC_PCM0_DO (MTK_PIN_NO(68) | 4) +#define PINMUX_GPIO68__FUNC_I2S5_DO (MTK_PIN_NO(68) | 5) +#define PINMUX_GPIO68__FUNC_ANT_SEL10 (MTK_PIN_NO(68) | 6) +#define PINMUX_GPIO68__FUNC_DBG_MON_B9 (MTK_PIN_NO(68) | 7) + +#define PINMUX_GPIO69__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) +#define PINMUX_GPIO69__FUNC_I2S3_MCK (MTK_PIN_NO(69) | 1) +#define PINMUX_GPIO69__FUNC_I2S1_MCK (MTK_PIN_NO(69) | 2) +#define PINMUX_GPIO69__FUNC_URTS1 (MTK_PIN_NO(69) | 3) +#define PINMUX_GPIO69__FUNC_AGPS_SYNC (MTK_PIN_NO(69) | 4) +#define PINMUX_GPIO69__FUNC_I2S5_MCK (MTK_PIN_NO(69) | 5) +#define PINMUX_GPIO69__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(69) | 6) +#define PINMUX_GPIO69__FUNC_DBG_MON_B8 (MTK_PIN_NO(69) | 7) + +#define PINMUX_GPIO70__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) +#define PINMUX_GPIO70__FUNC_I2S0_DI (MTK_PIN_NO(70) | 1) +#define PINMUX_GPIO70__FUNC_I2S2_DI (MTK_PIN_NO(70) | 2) +#define PINMUX_GPIO70__FUNC_KPCOL2 (MTK_PIN_NO(70) | 3) +#define PINMUX_GPIO70__FUNC_PCM0_DI (MTK_PIN_NO(70) | 4) +#define PINMUX_GPIO70__FUNC_I2S2_DI2 (MTK_PIN_NO(70) | 5) +#define PINMUX_GPIO70__FUNC_ANT_SEL11 (MTK_PIN_NO(70) | 6) +#define PINMUX_GPIO70__FUNC_DBG_MON_B7 (MTK_PIN_NO(70) | 7) + +#define PINMUX_GPIO71__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) +#define PINMUX_GPIO71__FUNC_I2S3_BCK (MTK_PIN_NO(71) | 1) +#define PINMUX_GPIO71__FUNC_I2S1_BCK (MTK_PIN_NO(71) | 2) +#define PINMUX_GPIO71__FUNC_KPROW2 (MTK_PIN_NO(71) | 3) +#define PINMUX_GPIO71__FUNC_PCM0_CLK (MTK_PIN_NO(71) | 4) +#define PINMUX_GPIO71__FUNC_I2S5_BCK (MTK_PIN_NO(71) | 5) +#define PINMUX_GPIO71__FUNC_ANT_SEL12 (MTK_PIN_NO(71) | 6) +#define PINMUX_GPIO71__FUNC_DBG_MON_B6 (MTK_PIN_NO(71) | 7) + +#define PINMUX_GPIO72__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) +#define PINMUX_GPIO72__FUNC_BPI_BUS19_OLAT0 (MTK_PIN_NO(72) | 1) +#define PINMUX_GPIO72__FUNC_CONN_BPI_BUS19_OLAT0 (MTK_PIN_NO(72) | 2) + +#define PINMUX_GPIO73__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) +#define PINMUX_GPIO73__FUNC_BPI_BUS18_PA_VM1 (MTK_PIN_NO(73) | 1) +#define PINMUX_GPIO73__FUNC_CONN_MIPI5_SCLK (MTK_PIN_NO(73) | 2) +#define PINMUX_GPIO73__FUNC_MIPI5_SCLK (MTK_PIN_NO(73) | 3) + +#define PINMUX_GPIO74__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) +#define PINMUX_GPIO74__FUNC_BPI_BUS17_PA_VM0 (MTK_PIN_NO(74) | 1) +#define PINMUX_GPIO74__FUNC_CONN_MIPI5_SDATA (MTK_PIN_NO(74) | 2) +#define PINMUX_GPIO74__FUNC_MIPI5_SDATA (MTK_PIN_NO(74) | 3) + +#define PINMUX_GPIO75__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) +#define PINMUX_GPIO75__FUNC_BPI_BUS20_OLAT1 (MTK_PIN_NO(75) | 1) +#define PINMUX_GPIO75__FUNC_CONN_BPI_BUS20_OLAT1 (MTK_PIN_NO(75) | 2) +#define PINMUX_GPIO75__FUNC_RFIC0_BSI_D2 (MTK_PIN_NO(75) | 3) + +#define PINMUX_GPIO76__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) +#define PINMUX_GPIO76__FUNC_RFIC0_BSI_D1 (MTK_PIN_NO(76) | 1) + +#define PINMUX_GPIO77__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) +#define PINMUX_GPIO77__FUNC_RFIC0_BSI_D0 (MTK_PIN_NO(77) | 1) + +#define PINMUX_GPIO78__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) +#define PINMUX_GPIO78__FUNC_BPI_BUS7 (MTK_PIN_NO(78) | 1) +#define PINMUX_GPIO78__FUNC_DBG_MON_B24 (MTK_PIN_NO(78) | 7) + +#define PINMUX_GPIO79__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) +#define PINMUX_GPIO79__FUNC_BPI_BUS6 (MTK_PIN_NO(79) | 1) +#define PINMUX_GPIO79__FUNC_DBG_MON_B23 (MTK_PIN_NO(79) | 7) + +#define PINMUX_GPIO80__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) +#define PINMUX_GPIO80__FUNC_BPI_BUS8 (MTK_PIN_NO(80) | 1) +#define PINMUX_GPIO80__FUNC_DBG_MON_B22 (MTK_PIN_NO(80) | 7) + +#define PINMUX_GPIO81__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) +#define PINMUX_GPIO81__FUNC_BPI_BUS9 (MTK_PIN_NO(81) | 1) +#define PINMUX_GPIO81__FUNC_DBG_MON_B21 (MTK_PIN_NO(81) | 7) + +#define PINMUX_GPIO82__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) +#define PINMUX_GPIO82__FUNC_BPI_BUS10 (MTK_PIN_NO(82) | 1) +#define PINMUX_GPIO82__FUNC_DBG_MON_B20 (MTK_PIN_NO(82) | 7) + +#define PINMUX_GPIO83__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) +#define PINMUX_GPIO83__FUNC_BPI_BUS11 (MTK_PIN_NO(83) | 1) +#define PINMUX_GPIO83__FUNC_DBG_MON_B19 (MTK_PIN_NO(83) | 7) + +#define PINMUX_GPIO84__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) +#define PINMUX_GPIO84__FUNC_BPI_BUS12 (MTK_PIN_NO(84) | 1) +#define PINMUX_GPIO84__FUNC_CONN_BPI_BUS12 (MTK_PIN_NO(84) | 2) + +#define PINMUX_GPIO85__FUNC_GPIO85 (MTK_PIN_NO(85) | 0) +#define PINMUX_GPIO85__FUNC_BPI_BUS13 (MTK_PIN_NO(85) | 1) +#define PINMUX_GPIO85__FUNC_CONN_BPI_BUS13 (MTK_PIN_NO(85) | 2) + +#define PINMUX_GPIO86__FUNC_GPIO86 (MTK_PIN_NO(86) | 0) +#define PINMUX_GPIO86__FUNC_BPI_BUS14 (MTK_PIN_NO(86) | 1) +#define PINMUX_GPIO86__FUNC_CONN_BPI_BUS14 (MTK_PIN_NO(86) | 2) + +#define PINMUX_GPIO87__FUNC_GPIO87 (MTK_PIN_NO(87) | 0) +#define PINMUX_GPIO87__FUNC_BPI_BUS15 (MTK_PIN_NO(87) | 1) +#define PINMUX_GPIO87__FUNC_CONN_BPI_BUS15 (MTK_PIN_NO(87) | 2) + +#define PINMUX_GPIO88__FUNC_GPIO88 (MTK_PIN_NO(88) | 0) +#define PINMUX_GPIO88__FUNC_BPI_BUS16 (MTK_PIN_NO(88) | 1) +#define PINMUX_GPIO88__FUNC_CONN_BPI_BUS16 (MTK_PIN_NO(88) | 2) + +#define PINMUX_GPIO89__FUNC_GPIO89 (MTK_PIN_NO(89) | 0) +#define PINMUX_GPIO89__FUNC_BPI_BUS5 (MTK_PIN_NO(89) | 1) +#define PINMUX_GPIO89__FUNC_DBG_MON_B18 (MTK_PIN_NO(89) | 7) + +#define PINMUX_GPIO90__FUNC_GPIO90 (MTK_PIN_NO(90) | 0) +#define PINMUX_GPIO90__FUNC_BPI_BUS4 (MTK_PIN_NO(90) | 1) +#define PINMUX_GPIO90__FUNC_DBG_MON_B17 (MTK_PIN_NO(90) | 7) + +#define PINMUX_GPIO91__FUNC_GPIO91 (MTK_PIN_NO(91) | 0) +#define PINMUX_GPIO91__FUNC_BPI_BUS3 (MTK_PIN_NO(91) | 1) + +#define PINMUX_GPIO92__FUNC_GPIO92 (MTK_PIN_NO(92) | 0) +#define PINMUX_GPIO92__FUNC_BPI_BUS2 (MTK_PIN_NO(92) | 1) +#define PINMUX_GPIO92__FUNC_DBG_MON_B16 (MTK_PIN_NO(92) | 7) + +#define PINMUX_GPIO93__FUNC_GPIO93 (MTK_PIN_NO(93) | 0) +#define PINMUX_GPIO93__FUNC_BPI_BUS1 (MTK_PIN_NO(93) | 1) + +#define PINMUX_GPIO94__FUNC_GPIO94 (MTK_PIN_NO(94) | 0) +#define PINMUX_GPIO94__FUNC_BPI_BUS0 (MTK_PIN_NO(94) | 1) +#define PINMUX_GPIO94__FUNC_DBG_MON_B15 (MTK_PIN_NO(94) | 7) + +#define PINMUX_GPIO95__FUNC_GPIO95 (MTK_PIN_NO(95) | 0) +#define PINMUX_GPIO95__FUNC_MIPI0_SDATA (MTK_PIN_NO(95) | 1) + +#define PINMUX_GPIO96__FUNC_GPIO96 (MTK_PIN_NO(96) | 0) +#define PINMUX_GPIO96__FUNC_MIPI0_SCLK (MTK_PIN_NO(96) | 1) + +#define PINMUX_GPIO97__FUNC_GPIO97 (MTK_PIN_NO(97) | 0) +#define PINMUX_GPIO97__FUNC_MIPI1_SDATA (MTK_PIN_NO(97) | 1) + +#define PINMUX_GPIO98__FUNC_GPIO98 (MTK_PIN_NO(98) | 0) +#define PINMUX_GPIO98__FUNC_MIPI1_SCLK (MTK_PIN_NO(98) | 1) + +#define PINMUX_GPIO99__FUNC_GPIO99 (MTK_PIN_NO(99) | 0) +#define PINMUX_GPIO99__FUNC_MIPI2_SCLK (MTK_PIN_NO(99) | 1) +#define PINMUX_GPIO99__FUNC_DBG_MON_B14 (MTK_PIN_NO(99) | 7) + +#define PINMUX_GPIO100__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) +#define PINMUX_GPIO100__FUNC_MIPI2_SDATA (MTK_PIN_NO(100) | 1) +#define PINMUX_GPIO100__FUNC_DBG_MON_B13 (MTK_PIN_NO(100) | 7) + +#define PINMUX_GPIO101__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) +#define PINMUX_GPIO101__FUNC_MIPI3_SCLK (MTK_PIN_NO(101) | 1) +#define PINMUX_GPIO101__FUNC_DBG_MON_B12 (MTK_PIN_NO(101) | 7) + +#define PINMUX_GPIO102__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) +#define PINMUX_GPIO102__FUNC_MIPI3_SDATA (MTK_PIN_NO(102) | 1) +#define PINMUX_GPIO102__FUNC_DBG_MON_B11 (MTK_PIN_NO(102) | 7) + +#define PINMUX_GPIO103__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) +#define PINMUX_GPIO103__FUNC_MIPI4_SCLK (MTK_PIN_NO(103) | 1) +#define PINMUX_GPIO103__FUNC_CONN_MIPI4_SCLK (MTK_PIN_NO(103) | 2) + +#define PINMUX_GPIO104__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) +#define PINMUX_GPIO104__FUNC_MIPI4_SDATA (MTK_PIN_NO(104) | 1) +#define PINMUX_GPIO104__FUNC_CONN_MIPI4_SDATA (MTK_PIN_NO(104) | 2) + +#define PINMUX_GPIO105__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) +#define PINMUX_GPIO105__FUNC_BPI_BUS22_OLAT3 (MTK_PIN_NO(105) | 1) +#define PINMUX_GPIO105__FUNC_CONN_BPI_BUS22_OLAT3 (MTK_PIN_NO(105) | 2) + +#define PINMUX_GPIO106__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) +#define PINMUX_GPIO106__FUNC_BPI_BUS21_OLAT2 (MTK_PIN_NO(106) | 1) +#define PINMUX_GPIO106__FUNC_CONN_BPI_BUS21_OLAT2 (MTK_PIN_NO(106) | 2) + +#define PINMUX_GPIO107__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) +#define PINMUX_GPIO107__FUNC_BPI_BUS24_ANT1 (MTK_PIN_NO(107) | 1) +#define PINMUX_GPIO107__FUNC_CONN_BPI_BUS24_ANT1 (MTK_PIN_NO(107) | 2) + +#define PINMUX_GPIO108__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) +#define PINMUX_GPIO108__FUNC_BPI_BUS25_ANT2 (MTK_PIN_NO(108) | 1) +#define PINMUX_GPIO108__FUNC_CONN_BPI_BUS25_ANT2 (MTK_PIN_NO(108) | 2) + +#define PINMUX_GPIO109__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) +#define PINMUX_GPIO109__FUNC_BPI_BUS23_ANT0 (MTK_PIN_NO(109) | 1) +#define PINMUX_GPIO109__FUNC_CONN_BPI_BUS23_ANT0 (MTK_PIN_NO(109) | 2) + +#define PINMUX_GPIO110__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) +#define PINMUX_GPIO110__FUNC_SCL4 (MTK_PIN_NO(110) | 1) + +#define PINMUX_GPIO111__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) +#define PINMUX_GPIO111__FUNC_SDA4 (MTK_PIN_NO(111) | 1) + +#define PINMUX_GPIO112__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) +#define PINMUX_GPIO112__FUNC_SCL2 (MTK_PIN_NO(112) | 1) + +#define PINMUX_GPIO113__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) +#define PINMUX_GPIO113__FUNC_SDA2 (MTK_PIN_NO(113) | 1) + +#define PINMUX_GPIO114__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) +#define PINMUX_GPIO114__FUNC_CLKM0 (MTK_PIN_NO(114) | 1) +#define PINMUX_GPIO114__FUNC_SPI3_MI (MTK_PIN_NO(114) | 2) +#define PINMUX_GPIO114__FUNC_DBG_MON_B5 (MTK_PIN_NO(114) | 7) + +#define PINMUX_GPIO115__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) +#define PINMUX_GPIO115__FUNC_CLKM1 (MTK_PIN_NO(115) | 1) +#define PINMUX_GPIO115__FUNC_SPI3_CSB (MTK_PIN_NO(115) | 2) +#define PINMUX_GPIO115__FUNC_DBG_MON_B4 (MTK_PIN_NO(115) | 7) + +#define PINMUX_GPIO116__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) +#define PINMUX_GPIO116__FUNC_CMMCLK0 (MTK_PIN_NO(116) | 1) +#define PINMUX_GPIO116__FUNC_DBG_MON_B3 (MTK_PIN_NO(116) | 7) + +#define PINMUX_GPIO117__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) +#define PINMUX_GPIO117__FUNC_CMMCLK1 (MTK_PIN_NO(117) | 1) +#define PINMUX_GPIO117__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(117) | 2) +#define PINMUX_GPIO117__FUNC_DBG_MON_B2 (MTK_PIN_NO(117) | 7) + +#define PINMUX_GPIO118__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) +#define PINMUX_GPIO118__FUNC_CLKM2 (MTK_PIN_NO(118) | 1) +#define PINMUX_GPIO118__FUNC_SPI3_MO (MTK_PIN_NO(118) | 2) +#define PINMUX_GPIO118__FUNC_DBG_MON_B1 (MTK_PIN_NO(118) | 7) + +#define PINMUX_GPIO119__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) +#define PINMUX_GPIO119__FUNC_CLKM3 (MTK_PIN_NO(119) | 1) +#define PINMUX_GPIO119__FUNC_SPI3_CLK (MTK_PIN_NO(119) | 2) +#define PINMUX_GPIO119__FUNC_DBG_MON_B0 (MTK_PIN_NO(119) | 7) + +#define PINMUX_GPIO120__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) +#define PINMUX_GPIO120__FUNC_CMMCLK2 (MTK_PIN_NO(120) | 1) +#define PINMUX_GPIO120__FUNC_CLKM2 (MTK_PIN_NO(120) | 2) +#define PINMUX_GPIO120__FUNC_ANT_SEL12 (MTK_PIN_NO(120) | 6) +#define PINMUX_GPIO120__FUNC_TP_UCTS2_AO (MTK_PIN_NO(120) | 7) + +#define PINMUX_GPIO121__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) +#define PINMUX_GPIO121__FUNC_CMMCLK3 (MTK_PIN_NO(121) | 1) +#define PINMUX_GPIO121__FUNC_CLKM3 (MTK_PIN_NO(121) | 2) +#define PINMUX_GPIO121__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(121) | 3) +#define PINMUX_GPIO121__FUNC_ANT_SEL11 (MTK_PIN_NO(121) | 6) +#define PINMUX_GPIO121__FUNC_TP_URTS2_AO (MTK_PIN_NO(121) | 7) + +#define PINMUX_GPIO122__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) +#define PINMUX_GPIO122__FUNC_CMVREF1 (MTK_PIN_NO(122) | 1) +#define PINMUX_GPIO122__FUNC_PCM0_SYNC (MTK_PIN_NO(122) | 2) +#define PINMUX_GPIO122__FUNC_SRCLKENAI1 (MTK_PIN_NO(122) | 3) +#define PINMUX_GPIO122__FUNC_AGPS_SYNC (MTK_PIN_NO(122) | 4) +#define PINMUX_GPIO122__FUNC_PWM_1 (MTK_PIN_NO(122) | 5) +#define PINMUX_GPIO122__FUNC_ANT_SEL9 (MTK_PIN_NO(122) | 6) +#define PINMUX_GPIO122__FUNC_TP_UCTS1_AO (MTK_PIN_NO(122) | 7) + +#define PINMUX_GPIO123__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) +#define PINMUX_GPIO123__FUNC_PCM0_DI (MTK_PIN_NO(123) | 2) +#define PINMUX_GPIO123__FUNC_ADSP_JTAG_TRSTN (MTK_PIN_NO(123) | 3) +#define PINMUX_GPIO123__FUNC_VPU_UDI_NTRST (MTK_PIN_NO(123) | 4) +#define PINMUX_GPIO123__FUNC_SPM_JTAG_TRSTN (MTK_PIN_NO(123) | 5) +#define PINMUX_GPIO123__FUNC_SSPM_JTAG_TRSTN (MTK_PIN_NO(123) | 6) + +#define PINMUX_GPIO124__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) +#define PINMUX_GPIO124__FUNC_CMVREF2 (MTK_PIN_NO(124) | 1) +#define PINMUX_GPIO124__FUNC_PCM0_CLK (MTK_PIN_NO(124) | 2) +#define PINMUX_GPIO124__FUNC_MD_INT0 (MTK_PIN_NO(124) | 3) +#define PINMUX_GPIO124__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(124) | 4) +#define PINMUX_GPIO124__FUNC_PWM_2 (MTK_PIN_NO(124) | 5) +#define PINMUX_GPIO124__FUNC_ANT_SEL10 (MTK_PIN_NO(124) | 6) +#define PINMUX_GPIO124__FUNC_TP_URTS1_AO (MTK_PIN_NO(124) | 7) + +#define PINMUX_GPIO125__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) +#define PINMUX_GPIO125__FUNC_CMVREF3 (MTK_PIN_NO(125) | 1) +#define PINMUX_GPIO125__FUNC_PCM0_DO (MTK_PIN_NO(125) | 2) +#define PINMUX_GPIO125__FUNC_ADSP_JTAG_TMS (MTK_PIN_NO(125) | 3) +#define PINMUX_GPIO125__FUNC_VPU_UDI_TMS (MTK_PIN_NO(125) | 4) +#define PINMUX_GPIO125__FUNC_SPM_JTAG_TMS (MTK_PIN_NO(125) | 5) +#define PINMUX_GPIO125__FUNC_SSPM_JTAG_TMS (MTK_PIN_NO(125) | 6) + +#define PINMUX_GPIO126__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) +#define PINMUX_GPIO126__FUNC_CMVREF4 (MTK_PIN_NO(126) | 1) +#define PINMUX_GPIO126__FUNC_CMFLASH0 (MTK_PIN_NO(126) | 2) +#define PINMUX_GPIO126__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(126) | 6) + +#define PINMUX_GPIO127__FUNC_GPIO127 (MTK_PIN_NO(127) | 0) +#define PINMUX_GPIO127__FUNC_CMVREF0 (MTK_PIN_NO(127) | 1) +#define PINMUX_GPIO127__FUNC_CMFLASH1 (MTK_PIN_NO(127) | 2) +#define PINMUX_GPIO127__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(127) | 6) + +#define PINMUX_GPIO128__FUNC_GPIO128 (MTK_PIN_NO(128) | 0) +#define PINMUX_GPIO128__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(128) | 1) +#define PINMUX_GPIO128__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(128) | 2) +#define PINMUX_GPIO128__FUNC_CCU_JTAG_TRST (MTK_PIN_NO(128) | 3) +#define PINMUX_GPIO128__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(128) | 4) +#define PINMUX_GPIO128__FUNC_SCP_JTAG_TRSTN (MTK_PIN_NO(128) | 5) +#define PINMUX_GPIO128__FUNC_LVTS_FOUT (MTK_PIN_NO(128) | 6) +#define PINMUX_GPIO128__FUNC_DBG_MON_A3 (MTK_PIN_NO(128) | 7) + +#define PINMUX_GPIO129__FUNC_GPIO129 (MTK_PIN_NO(129) | 0) +#define PINMUX_GPIO129__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(129) | 1) +#define PINMUX_GPIO129__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(129) | 2) +#define PINMUX_GPIO129__FUNC_CCU_JTAG_TCK (MTK_PIN_NO(129) | 3) +#define PINMUX_GPIO129__FUNC_CONN_DSP_JCK (MTK_PIN_NO(129) | 4) +#define PINMUX_GPIO129__FUNC_SCP_JTAG_TCK (MTK_PIN_NO(129) | 5) +#define PINMUX_GPIO129__FUNC_LVTS_SDO (MTK_PIN_NO(129) | 6) +#define PINMUX_GPIO129__FUNC_DBG_MON_A4 (MTK_PIN_NO(129) | 7) + +#define PINMUX_GPIO130__FUNC_GPIO130 (MTK_PIN_NO(130) | 0) +#define PINMUX_GPIO130__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(130) | 1) +#define PINMUX_GPIO130__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(130) | 2) +#define PINMUX_GPIO130__FUNC_LVTS_26M (MTK_PIN_NO(130) | 6) +#define PINMUX_GPIO130__FUNC_DBG_MON_A5 (MTK_PIN_NO(130) | 7) + +#define PINMUX_GPIO131__FUNC_GPIO131 (MTK_PIN_NO(131) | 0) +#define PINMUX_GPIO131__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(131) | 1) +#define PINMUX_GPIO131__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(131) | 2) +#define PINMUX_GPIO131__FUNC_CCU_JTAG_TDI (MTK_PIN_NO(131) | 3) +#define PINMUX_GPIO131__FUNC_CONN_DSP_JDI (MTK_PIN_NO(131) | 4) +#define PINMUX_GPIO131__FUNC_SCP_JTAG_TDI (MTK_PIN_NO(131) | 5) +#define PINMUX_GPIO131__FUNC_LVTS_SCK (MTK_PIN_NO(131) | 6) +#define PINMUX_GPIO131__FUNC_DBG_MON_A0 (MTK_PIN_NO(131) | 7) + +#define PINMUX_GPIO132__FUNC_GPIO132 (MTK_PIN_NO(132) | 0) +#define PINMUX_GPIO132__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(132) | 1) +#define PINMUX_GPIO132__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(132) | 2) +#define PINMUX_GPIO132__FUNC_CCU_JTAG_TMS (MTK_PIN_NO(132) | 3) +#define PINMUX_GPIO132__FUNC_CONN_DSP_JMS (MTK_PIN_NO(132) | 4) +#define PINMUX_GPIO132__FUNC_SCP_JTAG_TMS (MTK_PIN_NO(132) | 5) +#define PINMUX_GPIO132__FUNC_LVTS_SDI (MTK_PIN_NO(132) | 6) +#define PINMUX_GPIO132__FUNC_DBG_MON_A1 (MTK_PIN_NO(132) | 7) + +#define PINMUX_GPIO133__FUNC_GPIO133 (MTK_PIN_NO(133) | 0) +#define PINMUX_GPIO133__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(133) | 1) +#define PINMUX_GPIO133__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(133) | 2) +#define PINMUX_GPIO133__FUNC_CCU_JTAG_TDO (MTK_PIN_NO(133) | 3) +#define PINMUX_GPIO133__FUNC_CONN_DSP_JDO (MTK_PIN_NO(133) | 4) +#define PINMUX_GPIO133__FUNC_SCP_JTAG_TDO (MTK_PIN_NO(133) | 5) +#define PINMUX_GPIO133__FUNC_LVTS_SCF (MTK_PIN_NO(133) | 6) +#define PINMUX_GPIO133__FUNC_DBG_MON_A2 (MTK_PIN_NO(133) | 7) + +#define PINMUX_GPIO134__FUNC_GPIO134 (MTK_PIN_NO(134) | 0) +#define PINMUX_GPIO134__FUNC_MSDC1_CLK (MTK_PIN_NO(134) | 1) +#define PINMUX_GPIO134__FUNC_PCM1_CLK (MTK_PIN_NO(134) | 2) +#define PINMUX_GPIO134__FUNC_SPI5_B_MI (MTK_PIN_NO(134) | 3) +#define PINMUX_GPIO134__FUNC_UDI_TCK (MTK_PIN_NO(134) | 4) +#define PINMUX_GPIO134__FUNC_CONN_DSP_JCK (MTK_PIN_NO(134) | 5) +#define PINMUX_GPIO134__FUNC_IPU_JTAG_TCK (MTK_PIN_NO(134) | 6) +#define PINMUX_GPIO134__FUNC_JTCK_SEL3 (MTK_PIN_NO(134) | 7) + +#define PINMUX_GPIO135__FUNC_GPIO135 (MTK_PIN_NO(135) | 0) +#define PINMUX_GPIO135__FUNC_MSDC1_CMD (MTK_PIN_NO(135) | 1) +#define PINMUX_GPIO135__FUNC_PCM1_SYNC (MTK_PIN_NO(135) | 2) +#define PINMUX_GPIO135__FUNC_SPI5_B_CSB (MTK_PIN_NO(135) | 3) +#define PINMUX_GPIO135__FUNC_UDI_TMS (MTK_PIN_NO(135) | 4) +#define PINMUX_GPIO135__FUNC_CONN_DSP_JMS (MTK_PIN_NO(135) | 5) +#define PINMUX_GPIO135__FUNC_IPU_JTAG_TMS (MTK_PIN_NO(135) | 6) +#define PINMUX_GPIO135__FUNC_JTMS_SEL3 (MTK_PIN_NO(135) | 7) + +#define PINMUX_GPIO136__FUNC_GPIO136 (MTK_PIN_NO(136) | 0) +#define PINMUX_GPIO136__FUNC_MSDC1_DAT3 (MTK_PIN_NO(136) | 1) +#define PINMUX_GPIO136__FUNC_PCM1_DI (MTK_PIN_NO(136) | 2) +#define PINMUX_GPIO136__FUNC_SPI5_B_MO (MTK_PIN_NO(136) | 3) +#define PINMUX_GPIO136__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(136) | 4) +#define PINMUX_GPIO136__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(136) | 5) +#define PINMUX_GPIO136__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(136) | 6) + +#define PINMUX_GPIO137__FUNC_GPIO137 (MTK_PIN_NO(137) | 0) +#define PINMUX_GPIO137__FUNC_MSDC1_DAT0 (MTK_PIN_NO(137) | 1) +#define PINMUX_GPIO137__FUNC_PCM1_DO0 (MTK_PIN_NO(137) | 2) +#define PINMUX_GPIO137__FUNC_SPI5_B_CLK (MTK_PIN_NO(137) | 3) +#define PINMUX_GPIO137__FUNC_UDI_TDI (MTK_PIN_NO(137) | 4) +#define PINMUX_GPIO137__FUNC_CONN_DSP_JDI (MTK_PIN_NO(137) | 5) +#define PINMUX_GPIO137__FUNC_IPU_JTAG_TDI (MTK_PIN_NO(137) | 6) +#define PINMUX_GPIO137__FUNC_JTDI_SEL3 (MTK_PIN_NO(137) | 7) + +#define PINMUX_GPIO138__FUNC_GPIO138 (MTK_PIN_NO(138) | 0) +#define PINMUX_GPIO138__FUNC_MSDC1_DAT2 (MTK_PIN_NO(138) | 1) +#define PINMUX_GPIO138__FUNC_PCM1_DO2 (MTK_PIN_NO(138) | 2) +#define PINMUX_GPIO138__FUNC_ANT_SEL11 (MTK_PIN_NO(138) | 3) +#define PINMUX_GPIO138__FUNC_UDI_NTRST (MTK_PIN_NO(138) | 4) +#define PINMUX_GPIO138__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(138) | 5) +#define PINMUX_GPIO138__FUNC_IPU_JTAG_TRST (MTK_PIN_NO(138) | 6) +#define PINMUX_GPIO138__FUNC_JTRSTN_SEL3 (MTK_PIN_NO(138) | 7) + +#define PINMUX_GPIO139__FUNC_GPIO139 (MTK_PIN_NO(139) | 0) +#define PINMUX_GPIO139__FUNC_MSDC1_DAT1 (MTK_PIN_NO(139) | 1) +#define PINMUX_GPIO139__FUNC_PCM1_DO1 (MTK_PIN_NO(139) | 2) +#define PINMUX_GPIO139__FUNC_ANT_SEL12 (MTK_PIN_NO(139) | 3) +#define PINMUX_GPIO139__FUNC_UDI_TDO (MTK_PIN_NO(139) | 4) +#define PINMUX_GPIO139__FUNC_CONN_DSP_JDO (MTK_PIN_NO(139) | 5) +#define PINMUX_GPIO139__FUNC_IPU_JTAG_TDO (MTK_PIN_NO(139) | 6) +#define PINMUX_GPIO139__FUNC_JTDO_SEL3 (MTK_PIN_NO(139) | 7) + +#define PINMUX_GPIO140__FUNC_GPIO140 (MTK_PIN_NO(140) | 0) +#define PINMUX_GPIO140__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(140) | 1) +#define PINMUX_GPIO140__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(140) | 2) +#define PINMUX_GPIO140__FUNC_ADSP_URXD0 (MTK_PIN_NO(140) | 3) +#define PINMUX_GPIO140__FUNC_SCL_6306 (MTK_PIN_NO(140) | 4) +#define PINMUX_GPIO140__FUNC_PTA_RXD (MTK_PIN_NO(140) | 5) +#define PINMUX_GPIO140__FUNC_SSPM_URXD_AO (MTK_PIN_NO(140) | 6) + +#define PINMUX_GPIO141__FUNC_GPIO141 (MTK_PIN_NO(141) | 0) +#define PINMUX_GPIO141__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(141) | 1) +#define PINMUX_GPIO141__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(141) | 2) +#define PINMUX_GPIO141__FUNC_ADSP_UTXD0 (MTK_PIN_NO(141) | 3) +#define PINMUX_GPIO141__FUNC_SDA_6306 (MTK_PIN_NO(141) | 4) +#define PINMUX_GPIO141__FUNC_PTA_TXD (MTK_PIN_NO(141) | 5) +#define PINMUX_GPIO141__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(141) | 6) + +#define PINMUX_GPIO142__FUNC_GPIO142 (MTK_PIN_NO(142) | 0) +#define PINMUX_GPIO142__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(142) | 1) +#define PINMUX_GPIO142__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(142) | 2) + +#define PINMUX_GPIO143__FUNC_GPIO143 (MTK_PIN_NO(143) | 0) +#define PINMUX_GPIO143__FUNC_AUD_DAT_MOSI2 (MTK_PIN_NO(143) | 1) +#define PINMUX_GPIO143__FUNC_DBG_MON_A9 (MTK_PIN_NO(143) | 7) + +#define PINMUX_GPIO144__FUNC_GPIO144 (MTK_PIN_NO(144) | 0) +#define PINMUX_GPIO144__FUNC_AUD_NLE_MOSI1 (MTK_PIN_NO(144) | 1) +#define PINMUX_GPIO144__FUNC_AUD_CLK_MISO (MTK_PIN_NO(144) | 2) +#define PINMUX_GPIO144__FUNC_I2S2_MCK (MTK_PIN_NO(144) | 3) +#define PINMUX_GPIO144__FUNC_UDI_TCK (MTK_PIN_NO(144) | 5) +#define PINMUX_GPIO144__FUNC_UFS_UNIPRO_SDA (MTK_PIN_NO(144) | 6) +#define PINMUX_GPIO144__FUNC_DBG_MON_A10 (MTK_PIN_NO(144) | 7) + +#define PINMUX_GPIO145__FUNC_GPIO145 (MTK_PIN_NO(145) | 0) +#define PINMUX_GPIO145__FUNC_AUD_NLE_MOSI0 (MTK_PIN_NO(145) | 1) +#define PINMUX_GPIO145__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(145) | 2) +#define PINMUX_GPIO145__FUNC_I2S2_BCK (MTK_PIN_NO(145) | 3) +#define PINMUX_GPIO145__FUNC_UDI_TMS (MTK_PIN_NO(145) | 5) +#define PINMUX_GPIO145__FUNC_DBG_MON_A11 (MTK_PIN_NO(145) | 7) + +#define PINMUX_GPIO146__FUNC_GPIO146 (MTK_PIN_NO(146) | 0) +#define PINMUX_GPIO146__FUNC_AUD_DAT_MISO2 (MTK_PIN_NO(146) | 1) +#define PINMUX_GPIO146__FUNC_I2S2_DI2 (MTK_PIN_NO(146) | 3) +#define PINMUX_GPIO146__FUNC_UDI_TDO (MTK_PIN_NO(146) | 5) +#define PINMUX_GPIO146__FUNC_DBG_MON_A14 (MTK_PIN_NO(146) | 7) + +#define PINMUX_GPIO147__FUNC_GPIO147 (MTK_PIN_NO(147) | 0) +#define PINMUX_GPIO147__FUNC_ANT_SEL0 (MTK_PIN_NO(147) | 1) +#define PINMUX_GPIO147__FUNC_PWM_3 (MTK_PIN_NO(147) | 2) + +#define PINMUX_GPIO148__FUNC_GPIO148 (MTK_PIN_NO(148) | 0) +#define PINMUX_GPIO148__FUNC_ANT_SEL1 (MTK_PIN_NO(148) | 1) +#define PINMUX_GPIO148__FUNC_SPI0_B_MI (MTK_PIN_NO(148) | 2) +#define PINMUX_GPIO148__FUNC_SSPM_URXD_AO (MTK_PIN_NO(148) | 3) +#define PINMUX_GPIO148__FUNC_TP_UCTS2_AO (MTK_PIN_NO(148) | 5) +#define PINMUX_GPIO148__FUNC_CLKM0 (MTK_PIN_NO(148) | 6) + +#define PINMUX_GPIO149__FUNC_GPIO149 (MTK_PIN_NO(149) | 0) +#define PINMUX_GPIO149__FUNC_ANT_SEL2 (MTK_PIN_NO(149) | 1) +#define PINMUX_GPIO149__FUNC_SPI0_B_CSB (MTK_PIN_NO(149) | 2) +#define PINMUX_GPIO149__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(149) | 3) +#define PINMUX_GPIO149__FUNC_TP_URTS2_AO (MTK_PIN_NO(149) | 5) +#define PINMUX_GPIO149__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(149) | 6) + +#define PINMUX_GPIO150__FUNC_GPIO150 (MTK_PIN_NO(150) | 0) +#define PINMUX_GPIO150__FUNC_ANT_SEL3 (MTK_PIN_NO(150) | 1) +#define PINMUX_GPIO150__FUNC_SPI0_B_MO (MTK_PIN_NO(150) | 2) +#define PINMUX_GPIO150__FUNC_UCTS1 (MTK_PIN_NO(150) | 3) +#define PINMUX_GPIO150__FUNC_TP_UCTS1_AO (MTK_PIN_NO(150) | 5) +#define PINMUX_GPIO150__FUNC_IDDIG (MTK_PIN_NO(150) | 6) +#define PINMUX_GPIO150__FUNC_SCL9 (MTK_PIN_NO(150) | 7) + +#define PINMUX_GPIO151__FUNC_GPIO151 (MTK_PIN_NO(151) | 0) +#define PINMUX_GPIO151__FUNC_ANT_SEL4 (MTK_PIN_NO(151) | 1) +#define PINMUX_GPIO151__FUNC_SPI0_B_CLK (MTK_PIN_NO(151) | 2) +#define PINMUX_GPIO151__FUNC_URTS1 (MTK_PIN_NO(151) | 3) +#define PINMUX_GPIO151__FUNC_TP_URTS1_AO (MTK_PIN_NO(151) | 5) +#define PINMUX_GPIO151__FUNC_USB_DRVVBUS (MTK_PIN_NO(151) | 6) +#define PINMUX_GPIO151__FUNC_SDA9 (MTK_PIN_NO(151) | 7) + +#define PINMUX_GPIO152__FUNC_GPIO152 (MTK_PIN_NO(152) | 0) +#define PINMUX_GPIO152__FUNC_ANT_SEL5 (MTK_PIN_NO(152) | 1) +#define PINMUX_GPIO152__FUNC_SPI1_B_MI (MTK_PIN_NO(152) | 2) +#define PINMUX_GPIO152__FUNC_CLKM3 (MTK_PIN_NO(152) | 3) +#define PINMUX_GPIO152__FUNC_TP_URXD1_AO (MTK_PIN_NO(152) | 5) +#define PINMUX_GPIO152__FUNC_SCP_SPI1_B_MI (MTK_PIN_NO(152) | 6) +#define PINMUX_GPIO152__FUNC_SCL8 (MTK_PIN_NO(152) | 7) + +#define PINMUX_GPIO153__FUNC_GPIO153 (MTK_PIN_NO(153) | 0) +#define PINMUX_GPIO153__FUNC_ANT_SEL6 (MTK_PIN_NO(153) | 1) +#define PINMUX_GPIO153__FUNC_SPI1_B_CSB (MTK_PIN_NO(153) | 2) +#define PINMUX_GPIO153__FUNC_SRCLKENAI0 (MTK_PIN_NO(153) | 3) +#define PINMUX_GPIO153__FUNC_PWM_0 (MTK_PIN_NO(153) | 4) +#define PINMUX_GPIO153__FUNC_TP_UTXD1_AO (MTK_PIN_NO(153) | 5) +#define PINMUX_GPIO153__FUNC_SCP_SPI1_B_CS (MTK_PIN_NO(153) | 6) +#define PINMUX_GPIO153__FUNC_SDA8 (MTK_PIN_NO(153) | 7) + +#define PINMUX_GPIO154__FUNC_GPIO154 (MTK_PIN_NO(154) | 0) +#define PINMUX_GPIO154__FUNC_ANT_SEL7 (MTK_PIN_NO(154) | 1) +#define PINMUX_GPIO154__FUNC_SPI1_B_MO (MTK_PIN_NO(154) | 2) +#define PINMUX_GPIO154__FUNC_SRCLKENAI1 (MTK_PIN_NO(154) | 3) +#define PINMUX_GPIO154__FUNC_TP_URXD2_AO (MTK_PIN_NO(154) | 5) +#define PINMUX_GPIO154__FUNC_SCP_SPI1_B_MO (MTK_PIN_NO(154) | 6) + +#define PINMUX_GPIO155__FUNC_GPIO155 (MTK_PIN_NO(155) | 0) +#define PINMUX_GPIO155__FUNC_ANT_SEL8 (MTK_PIN_NO(155) | 1) +#define PINMUX_GPIO155__FUNC_SPI1_B_CLK (MTK_PIN_NO(155) | 2) +#define PINMUX_GPIO155__FUNC_MD_INT0 (MTK_PIN_NO(155) | 3) +#define PINMUX_GPIO155__FUNC_TP_UTXD2_AO (MTK_PIN_NO(155) | 5) +#define PINMUX_GPIO155__FUNC_SCP_SPI1_B_CK (MTK_PIN_NO(155) | 6) +#define PINMUX_GPIO155__FUNC_DBG_MON_A15 (MTK_PIN_NO(155) | 7) + +#define PINMUX_GPIO156__FUNC_GPIO156 (MTK_PIN_NO(156) | 0) +#define PINMUX_GPIO156__FUNC_CONN_TOP_CLK (MTK_PIN_NO(156) | 1) +#define PINMUX_GPIO156__FUNC_AUXIF_CLK0 (MTK_PIN_NO(156) | 2) +#define PINMUX_GPIO156__FUNC_DBG_MON_A16 (MTK_PIN_NO(156) | 7) + +#define PINMUX_GPIO157__FUNC_GPIO157 (MTK_PIN_NO(157) | 0) +#define PINMUX_GPIO157__FUNC_CONN_TOP_DATA (MTK_PIN_NO(157) | 1) +#define PINMUX_GPIO157__FUNC_AUXIF_ST0 (MTK_PIN_NO(157) | 2) +#define PINMUX_GPIO157__FUNC_DBG_MON_A17 (MTK_PIN_NO(157) | 7) + +#define PINMUX_GPIO158__FUNC_GPIO158 (MTK_PIN_NO(158) | 0) +#define PINMUX_GPIO158__FUNC_CONN_HRST_B (MTK_PIN_NO(158) | 1) +#define PINMUX_GPIO158__FUNC_DBG_MON_A18 (MTK_PIN_NO(158) | 7) + +#define PINMUX_GPIO159__FUNC_GPIO159 (MTK_PIN_NO(159) | 0) +#define PINMUX_GPIO159__FUNC_CONN_WB_PTA (MTK_PIN_NO(159) | 1) +#define PINMUX_GPIO159__FUNC_DBG_MON_A19 (MTK_PIN_NO(159) | 7) + +#define PINMUX_GPIO160__FUNC_GPIO160 (MTK_PIN_NO(160) | 0) +#define PINMUX_GPIO160__FUNC_CONN_BT_CLK (MTK_PIN_NO(160) | 1) +#define PINMUX_GPIO160__FUNC_AUXIF_CLK1 (MTK_PIN_NO(160) | 2) +#define PINMUX_GPIO160__FUNC_DBG_MON_A20 (MTK_PIN_NO(160) | 7) + +#define PINMUX_GPIO161__FUNC_GPIO161 (MTK_PIN_NO(161) | 0) +#define PINMUX_GPIO161__FUNC_CONN_BT_DATA (MTK_PIN_NO(161) | 1) +#define PINMUX_GPIO161__FUNC_AUXIF_ST1 (MTK_PIN_NO(161) | 2) +#define PINMUX_GPIO161__FUNC_DBG_MON_A21 (MTK_PIN_NO(161) | 7) + +#define PINMUX_GPIO162__FUNC_GPIO162 (MTK_PIN_NO(162) | 0) +#define PINMUX_GPIO162__FUNC_CONN_WF_CTRL0 (MTK_PIN_NO(162) | 1) +#define PINMUX_GPIO162__FUNC_DBG_MON_A22 (MTK_PIN_NO(162) | 7) + +#define PINMUX_GPIO163__FUNC_GPIO163 (MTK_PIN_NO(163) | 0) +#define PINMUX_GPIO163__FUNC_CONN_WF_CTRL1 (MTK_PIN_NO(163) | 1) +#define PINMUX_GPIO163__FUNC_UFS_MPHY_SCL (MTK_PIN_NO(163) | 2) +#define PINMUX_GPIO163__FUNC_DBG_MON_A23 (MTK_PIN_NO(163) | 7) + +#define PINMUX_GPIO164__FUNC_GPIO164 (MTK_PIN_NO(164) | 0) +#define PINMUX_GPIO164__FUNC_CONN_WF_CTRL2 (MTK_PIN_NO(164) | 1) +#define PINMUX_GPIO164__FUNC_UFS_MPHY_SDA (MTK_PIN_NO(164) | 2) +#define PINMUX_GPIO164__FUNC_DBG_MON_A24 (MTK_PIN_NO(164) | 7) + +#define PINMUX_GPIO165__FUNC_GPIO165 (MTK_PIN_NO(165) | 0) +#define PINMUX_GPIO165__FUNC_CONN_WF_CTRL3 (MTK_PIN_NO(165) | 1) +#define PINMUX_GPIO165__FUNC_UFS_UNIPRO_SDA (MTK_PIN_NO(165) | 2) +#define PINMUX_GPIO165__FUNC_DBG_MON_A25 (MTK_PIN_NO(165) | 7) + +#define PINMUX_GPIO166__FUNC_GPIO166 (MTK_PIN_NO(166) | 0) +#define PINMUX_GPIO166__FUNC_CONN_WF_CTRL4 (MTK_PIN_NO(166) | 1) +#define PINMUX_GPIO166__FUNC_UFS_UNIPRO_SCL (MTK_PIN_NO(166) | 2) +#define PINMUX_GPIO166__FUNC_DBG_MON_A26 (MTK_PIN_NO(166) | 7) + +#define PINMUX_GPIO167__FUNC_GPIO167 (MTK_PIN_NO(167) | 0) +#define PINMUX_GPIO167__FUNC_MSDC0_CMD (MTK_PIN_NO(167) | 1) + +#define PINMUX_GPIO168__FUNC_GPIO168 (MTK_PIN_NO(168) | 0) +#define PINMUX_GPIO168__FUNC_MSDC0_DAT0 (MTK_PIN_NO(168) | 1) + +#define PINMUX_GPIO169__FUNC_GPIO169 (MTK_PIN_NO(169) | 0) +#define PINMUX_GPIO169__FUNC_MSDC0_DAT2 (MTK_PIN_NO(169) | 1) + +#define PINMUX_GPIO170__FUNC_GPIO170 (MTK_PIN_NO(170) | 0) +#define PINMUX_GPIO170__FUNC_MSDC0_DAT4 (MTK_PIN_NO(170) | 1) + +#define PINMUX_GPIO171__FUNC_GPIO171 (MTK_PIN_NO(171) | 0) +#define PINMUX_GPIO171__FUNC_MSDC0_DAT6 (MTK_PIN_NO(171) | 1) + +#define PINMUX_GPIO172__FUNC_GPIO172 (MTK_PIN_NO(172) | 0) +#define PINMUX_GPIO172__FUNC_MSDC0_DAT1 (MTK_PIN_NO(172) | 1) + +#define PINMUX_GPIO173__FUNC_GPIO173 (MTK_PIN_NO(173) | 0) +#define PINMUX_GPIO173__FUNC_MSDC0_DAT5 (MTK_PIN_NO(173) | 1) + +#define PINMUX_GPIO174__FUNC_GPIO174 (MTK_PIN_NO(174) | 0) +#define PINMUX_GPIO174__FUNC_MSDC0_DAT7 (MTK_PIN_NO(174) | 1) + +#define PINMUX_GPIO175__FUNC_GPIO175 (MTK_PIN_NO(175) | 0) +#define PINMUX_GPIO175__FUNC_MSDC0_DSL (MTK_PIN_NO(175) | 1) +#define PINMUX_GPIO175__FUNC_ANT_SEL9 (MTK_PIN_NO(175) | 2) + +#define PINMUX_GPIO176__FUNC_GPIO176 (MTK_PIN_NO(176) | 0) +#define PINMUX_GPIO176__FUNC_MSDC0_CLK (MTK_PIN_NO(176) | 1) +#define PINMUX_GPIO176__FUNC_ANT_SEL10 (MTK_PIN_NO(176) | 2) + +#define PINMUX_GPIO177__FUNC_GPIO177 (MTK_PIN_NO(177) | 0) +#define PINMUX_GPIO177__FUNC_MSDC0_DAT3 (MTK_PIN_NO(177) | 1) + +#define PINMUX_GPIO178__FUNC_GPIO178 (MTK_PIN_NO(178) | 0) +#define PINMUX_GPIO178__FUNC_MSDC0_RSTB (MTK_PIN_NO(178) | 1) + +#define PINMUX_GPIO179__FUNC_GPIO179 (MTK_PIN_NO(179) | 0) +#define PINMUX_GPIO179__FUNC_RFIC0_BSI_EN (MTK_PIN_NO(179) | 1) + +#define PINMUX_GPIO180__FUNC_GPIO180 (MTK_PIN_NO(180) | 0) +#define PINMUX_GPIO180__FUNC_RFIC0_BSI_CK (MTK_PIN_NO(180) | 1) + +#define PINMUX_GPIO181__FUNC_GPIO181 (MTK_PIN_NO(181) | 0) +#define PINMUX_GPIO181__FUNC_SRCLKENA0 (MTK_PIN_NO(181) | 1) + +#define PINMUX_GPIO182__FUNC_GPIO182 (MTK_PIN_NO(182) | 0) +#define PINMUX_GPIO182__FUNC_SRCLKENA1 (MTK_PIN_NO(182) | 1) + +#define PINMUX_GPIO183__FUNC_GPIO183 (MTK_PIN_NO(183) | 0) +#define PINMUX_GPIO183__FUNC_WATCHDOG (MTK_PIN_NO(183) | 1) + +#define PINMUX_GPIO184__FUNC_GPIO184 (MTK_PIN_NO(184) | 0) +#define PINMUX_GPIO184__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(184) | 1) +#define PINMUX_GPIO184__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(184) | 2) + +#define PINMUX_GPIO185__FUNC_GPIO185 (MTK_PIN_NO(185) | 0) +#define PINMUX_GPIO185__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(185) | 1) + +#define PINMUX_GPIO186__FUNC_GPIO186 (MTK_PIN_NO(186) | 0) +#define PINMUX_GPIO186__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(186) | 1) +#define PINMUX_GPIO186__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(186) | 2) + +#define PINMUX_GPIO187__FUNC_GPIO187 (MTK_PIN_NO(187) | 0) +#define PINMUX_GPIO187__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(187) | 1) + +#define PINMUX_GPIO188__FUNC_GPIO188 (MTK_PIN_NO(188) | 0) +#define PINMUX_GPIO188__FUNC_RTC32K_CK (MTK_PIN_NO(188) | 1) + +#define PINMUX_GPIO189__FUNC_GPIO189 (MTK_PIN_NO(189) | 0) +#define PINMUX_GPIO189__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(189) | 1) +#define PINMUX_GPIO189__FUNC_I2S1_MCK (MTK_PIN_NO(189) | 3) +#define PINMUX_GPIO189__FUNC_UFS_UNIPRO_SCL (MTK_PIN_NO(189) | 6) + +#define PINMUX_GPIO190__FUNC_GPIO190 (MTK_PIN_NO(190) | 0) +#define PINMUX_GPIO190__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(190) | 1) +#define PINMUX_GPIO190__FUNC_I2S1_BCK (MTK_PIN_NO(190) | 3) +#define PINMUX_GPIO190__FUNC_DBG_MON_A6 (MTK_PIN_NO(190) | 7) + +#define PINMUX_GPIO191__FUNC_GPIO191 (MTK_PIN_NO(191) | 0) +#define PINMUX_GPIO191__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(191) | 1) +#define PINMUX_GPIO191__FUNC_I2S1_LRCK (MTK_PIN_NO(191) | 3) +#define PINMUX_GPIO191__FUNC_DBG_MON_A7 (MTK_PIN_NO(191) | 7) + +#define PINMUX_GPIO192__FUNC_GPIO192 (MTK_PIN_NO(192) | 0) +#define PINMUX_GPIO192__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(192) | 1) +#define PINMUX_GPIO192__FUNC_I2S1_DO (MTK_PIN_NO(192) | 3) +#define PINMUX_GPIO192__FUNC_UFS_MPHY_SDA (MTK_PIN_NO(192) | 6) +#define PINMUX_GPIO192__FUNC_DBG_MON_A8 (MTK_PIN_NO(192) | 7) + +#define PINMUX_GPIO193__FUNC_GPIO193 (MTK_PIN_NO(193) | 0) +#define PINMUX_GPIO193__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(193) | 1) +#define PINMUX_GPIO193__FUNC_VOW_DAT_MISO (MTK_PIN_NO(193) | 2) +#define PINMUX_GPIO193__FUNC_I2S2_LRCK (MTK_PIN_NO(193) | 3) +#define PINMUX_GPIO193__FUNC_UDI_TDI (MTK_PIN_NO(193) | 5) +#define PINMUX_GPIO193__FUNC_DBG_MON_A12 (MTK_PIN_NO(193) | 7) + +#define PINMUX_GPIO194__FUNC_GPIO194 (MTK_PIN_NO(194) | 0) +#define PINMUX_GPIO194__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(194) | 1) +#define PINMUX_GPIO194__FUNC_VOW_CLK_MISO (MTK_PIN_NO(194) | 2) +#define PINMUX_GPIO194__FUNC_I2S2_DI (MTK_PIN_NO(194) | 3) +#define PINMUX_GPIO194__FUNC_UDI_NTRST (MTK_PIN_NO(194) | 5) +#define PINMUX_GPIO194__FUNC_UFS_MPHY_SCL (MTK_PIN_NO(194) | 6) +#define PINMUX_GPIO194__FUNC_DBG_MON_A13 (MTK_PIN_NO(194) | 7) + +#define PINMUX_GPIO195__FUNC_GPIO195 (MTK_PIN_NO(195) | 0) +#define PINMUX_GPIO195__FUNC_ADSP_JTAG_TCK (MTK_PIN_NO(195) | 3) +#define PINMUX_GPIO195__FUNC_VPU_UDI_TCK (MTK_PIN_NO(195) | 4) +#define PINMUX_GPIO195__FUNC_SPM_JTAG_TCK (MTK_PIN_NO(195) | 5) +#define PINMUX_GPIO195__FUNC_SSPM_JTAG_TCK (MTK_PIN_NO(195) | 6) + +#define PINMUX_GPIO196__FUNC_GPIO196 (MTK_PIN_NO(196) | 0) +#define PINMUX_GPIO196__FUNC_CMMCLK4 (MTK_PIN_NO(196) | 1) +#define PINMUX_GPIO196__FUNC_ADSP_JTAG_TDI (MTK_PIN_NO(196) | 3) +#define PINMUX_GPIO196__FUNC_VPU_UDI_TDI (MTK_PIN_NO(196) | 4) +#define PINMUX_GPIO196__FUNC_SPM_JTAG_TDI (MTK_PIN_NO(196) | 5) +#define PINMUX_GPIO196__FUNC_SSPM_JTAG_TDI (MTK_PIN_NO(196) | 6) + +#define PINMUX_GPIO197__FUNC_GPIO197 (MTK_PIN_NO(197) | 0) +#define PINMUX_GPIO197__FUNC_ADSP_JTAG_TDO (MTK_PIN_NO(197) | 3) +#define PINMUX_GPIO197__FUNC_VPU_UDI_TDO (MTK_PIN_NO(197) | 4) +#define PINMUX_GPIO197__FUNC_SPM_JTAG_TDO (MTK_PIN_NO(197) | 5) +#define PINMUX_GPIO197__FUNC_SSPM_JTAG_TDO (MTK_PIN_NO(197) | 6) + +#define PINMUX_GPIO198__FUNC_GPIO198 (MTK_PIN_NO(198) | 0) +#define PINMUX_GPIO198__FUNC_SCL7 (MTK_PIN_NO(198) | 1) + +#define PINMUX_GPIO199__FUNC_GPIO199 (MTK_PIN_NO(199) | 0) +#define PINMUX_GPIO199__FUNC_SDA7 (MTK_PIN_NO(199) | 1) + +#define PINMUX_GPIO200__FUNC_GPIO200 (MTK_PIN_NO(200) | 0) +#define PINMUX_GPIO200__FUNC_URXD1 (MTK_PIN_NO(200) | 1) +#define PINMUX_GPIO200__FUNC_ADSP_URXD0 (MTK_PIN_NO(200) | 2) +#define PINMUX_GPIO200__FUNC_TP_URXD1_AO (MTK_PIN_NO(200) | 3) +#define PINMUX_GPIO200__FUNC_SSPM_URXD_AO (MTK_PIN_NO(200) | 4) +#define PINMUX_GPIO200__FUNC_TP_URXD2_AO (MTK_PIN_NO(200) | 5) +#define PINMUX_GPIO200__FUNC_MBISTREADEN_TRIGGER (MTK_PIN_NO(200) | 6) + +#define PINMUX_GPIO201__FUNC_GPIO201 (MTK_PIN_NO(201) | 0) +#define PINMUX_GPIO201__FUNC_UTXD1 (MTK_PIN_NO(201) | 1) +#define PINMUX_GPIO201__FUNC_ADSP_UTXD0 (MTK_PIN_NO(201) | 2) +#define PINMUX_GPIO201__FUNC_TP_UTXD1_AO (MTK_PIN_NO(201) | 3) +#define PINMUX_GPIO201__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(201) | 4) +#define PINMUX_GPIO201__FUNC_TP_UTXD2_AO (MTK_PIN_NO(201) | 5) +#define PINMUX_GPIO201__FUNC_MBISTWRITEEN_TRIGGER (MTK_PIN_NO(201) | 6) + +#define PINMUX_GPIO202__FUNC_GPIO202 (MTK_PIN_NO(202) | 0) +#define PINMUX_GPIO202__FUNC_PWM_3 (MTK_PIN_NO(202) | 1) +#define PINMUX_GPIO202__FUNC_CLKM3 (MTK_PIN_NO(202) | 2) + +#define PINMUX_GPIO203__FUNC_GPIO203 (MTK_PIN_NO(203) | 0) + +#define PINMUX_GPIO204__FUNC_GPIO204 (MTK_PIN_NO(204) | 0) + +#define PINMUX_GPIO205__FUNC_GPIO205 (MTK_PIN_NO(205) | 0) + +#define PINMUX_GPIO206__FUNC_GPIO206 (MTK_PIN_NO(206) | 0) + +#define PINMUX_GPIO207__FUNC_GPIO207 (MTK_PIN_NO(207) | 0) + +#define PINMUX_GPIO208__FUNC_GPIO208 (MTK_PIN_NO(208) | 0) + +#define PINMUX_GPIO209__FUNC_GPIO209 (MTK_PIN_NO(209) | 0) + +#endif /* __MT6779-PINFUNC_H */ diff --git a/include/dt-bindings/pinctrl/mt6795-pinfunc.h b/include/dt-bindings/pinctrl/mt6795-pinfunc.h new file mode 100644 index 000000000000..bd1c5a9fad06 --- /dev/null +++ b/include/dt-bindings/pinctrl/mt6795-pinfunc.h @@ -0,0 +1,908 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022 Collabora Ltd. + * Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> + */ + +#ifndef __DTS_MT8173_PINFUNC_H +#define __DTS_MT8173_PINFUNC_H + +#include <dt-bindings/pinctrl/mt65xx.h> + +#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define PINMUX_GPIO0__FUNC_IRDA_PDN (MTK_PIN_NO(0) | 1) +#define PINMUX_GPIO0__FUNC_I2S1_WS (MTK_PIN_NO(0) | 2) +#define PINMUX_GPIO0__FUNC_TDD_TMS (MTK_PIN_NO(0) | 4) +#define PINMUX_GPIO0__FUNC_UTXD0 (MTK_PIN_NO(0) | 5) + +#define PINMUX_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define PINMUX_GPIO1__FUNC_IRDA_RXD (MTK_PIN_NO(1) | 1) +#define PINMUX_GPIO1__FUNC_I2S1_BCK (MTK_PIN_NO(1) | 2) +#define PINMUX_GPIO1__FUNC_SDA4 (MTK_PIN_NO(1) | 3) +#define PINMUX_GPIO1__FUNC_TDD_TCK (MTK_PIN_NO(1) | 4) +#define PINMUX_GPIO1__FUNC_URXD0 (MTK_PIN_NO(1) | 5) + +#define PINMUX_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define PINMUX_GPIO2__FUNC_IRDA_TXD (MTK_PIN_NO(2) | 1) +#define PINMUX_GPIO2__FUNC_I2S1_MCK (MTK_PIN_NO(2) | 2) +#define PINMUX_GPIO2__FUNC_SCL4 (MTK_PIN_NO(2) | 3) +#define PINMUX_GPIO2__FUNC_TDD_TDI (MTK_PIN_NO(2) | 4) +#define PINMUX_GPIO2__FUNC_UTXD3 (MTK_PIN_NO(2) | 5) + +#define PINMUX_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define PINMUX_GPIO3__FUNC_DSI1_TE (MTK_PIN_NO(3) | 1) +#define PINMUX_GPIO3__FUNC_I2S1_DO_1 (MTK_PIN_NO(3) | 2) +#define PINMUX_GPIO3__FUNC_SDA3 (MTK_PIN_NO(3) | 3) +#define PINMUX_GPIO3__FUNC_TDD_TDO (MTK_PIN_NO(3) | 4) +#define PINMUX_GPIO3__FUNC_URXD3 (MTK_PIN_NO(3) | 5) + +#define PINMUX_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define PINMUX_GPIO4__FUNC_DISP_PWM1 (MTK_PIN_NO(4) | 1) +#define PINMUX_GPIO4__FUNC_I2S1_DO_2 (MTK_PIN_NO(4) | 2) +#define PINMUX_GPIO4__FUNC_SCL3 (MTK_PIN_NO(4) | 3) +#define PINMUX_GPIO4__FUNC_TDD_TRSTN (MTK_PIN_NO(4) | 4) + +#define PINMUX_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define PINMUX_GPIO5__FUNC_PCM1_CLK (MTK_PIN_NO(5) | 1) +#define PINMUX_GPIO5__FUNC_I2S2_WS (MTK_PIN_NO(5) | 2) +#define PINMUX_GPIO5__FUNC_SPI_CK_3 (MTK_PIN_NO(5) | 3) +#define PINMUX_GPIO5__FUNC_LTE_MD32_JTAG_TMS (MTK_PIN_NO(5) | 4) +#define PINMUX_GPIO5__FUNC_AP_MD32_JTAG_TMS (MTK_PIN_NO(5) | 5) + +#define PINMUX_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define PINMUX_GPIO6__FUNC_PCM1_SYNC (MTK_PIN_NO(6) | 1) +#define PINMUX_GPIO6__FUNC_I2S2_BCK (MTK_PIN_NO(6) | 2) +#define PINMUX_GPIO6__FUNC_SPI_MI_3 (MTK_PIN_NO(6) | 3) +#define PINMUX_GPIO6__FUNC_LTE_MD32_JTAG_TCK (MTK_PIN_NO(6) | 4) +#define PINMUX_GPIO6__FUNC_AP_MD32_JTAG_TCK (MTK_PIN_NO(6) | 5) + +#define PINMUX_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +#define PINMUX_GPIO7__FUNC_PCM1_DI (MTK_PIN_NO(7) | 1) +#define PINMUX_GPIO7__FUNC_I2S2_DI_1 (MTK_PIN_NO(7) | 2) +#define PINMUX_GPIO7__FUNC_SPI_MO_3 (MTK_PIN_NO(7) | 3) +#define PINMUX_GPIO7__FUNC_LTE_MD32_JTAG_TDI (MTK_PIN_NO(7) | 4) +#define PINMUX_GPIO7__FUNC_AP_MD32_JTAG_TDI (MTK_PIN_NO(7) | 5) + +#define PINMUX_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +#define PINMUX_GPIO8__FUNC_PCM1_DO (MTK_PIN_NO(8) | 1) +#define PINMUX_GPIO8__FUNC_I2S2_DI_2 (MTK_PIN_NO(8) | 2) +#define PINMUX_GPIO8__FUNC_SPI_CS_3 (MTK_PIN_NO(8) | 3) +#define PINMUX_GPIO8__FUNC_LTE_MD32_JTAG_TDO (MTK_PIN_NO(8) | 4) +#define PINMUX_GPIO8__FUNC_AP_MD32_JTAG_TDO (MTK_PIN_NO(8) | 5) + +#define PINMUX_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +#define PINMUX_GPIO9__FUNC_USB_DRVVBUS (MTK_PIN_NO(9) | 1) +#define PINMUX_GPIO9__FUNC_I2S2_MCK (MTK_PIN_NO(9) | 2) +#define PINMUX_GPIO9__FUNC_LTE_MD32_JTAG_TRST (MTK_PIN_NO(9) | 4) +#define PINMUX_GPIO9__FUNC_AP_MD32_JTAG_TRST (MTK_PIN_NO(9) | 5) + +#define PINMUX_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +#define PINMUX_GPIO10__FUNC_I2S0_WS (MTK_PIN_NO(10) | 2) + +#define PINMUX_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +#define PINMUX_GPIO11__FUNC_I2S0_BCK (MTK_PIN_NO(11) | 2) + +#define PINMUX_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +#define PINMUX_GPIO12__FUNC_I2S0_MCK (MTK_PIN_NO(12) | 2) + +#define PINMUX_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) +#define PINMUX_GPIO13__FUNC_I2S0_DO (MTK_PIN_NO(13) | 2) + +#define PINMUX_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) +#define PINMUX_GPIO14__FUNC_I2S0_DI (MTK_PIN_NO(14) | 2) +#define PINMUX_GPIO14__FUNC_DISP_PWM1 (MTK_PIN_NO(14) | 3) +#define PINMUX_GPIO14__FUNC_PWM4 (MTK_PIN_NO(14) | 4) +#define PINMUX_GPIO14__FUNC_IRDA_RXD (MTK_PIN_NO(14) | 5) +#define PINMUX_GPIO14__FUNC_I2S1_BCK (MTK_PIN_NO(14) | 6) + +#define PINMUX_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) +#define PINMUX_GPIO15__FUNC_DSI1_TE (MTK_PIN_NO(15) | 2) +#define PINMUX_GPIO15__FUNC_USB_DRVVBUS (MTK_PIN_NO(15) | 3) +#define PINMUX_GPIO15__FUNC_PWM5 (MTK_PIN_NO(15) | 4) +#define PINMUX_GPIO15__FUNC_IRDA_TXD (MTK_PIN_NO(15) | 5) +#define PINMUX_GPIO15__FUNC_I2S1_MCK (MTK_PIN_NO(15) | 6) + +#define PINMUX_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) +#define PINMUX_GPIO16__FUNC_IDDIG (MTK_PIN_NO(16) | 1) +#define PINMUX_GPIO16__FUNC_FLASH (MTK_PIN_NO(16) | 2) +#define PINMUX_GPIO16__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(16) | 3) +#define PINMUX_GPIO16__FUNC_PWM5 (MTK_PIN_NO(16) | 4) + +#define PINMUX_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) +#define PINMUX_GPIO17__FUNC_SIM1_SCLK (MTK_PIN_NO(17) | 1) +#define PINMUX_GPIO17__FUNC_SIM2_SCLK (MTK_PIN_NO(17) | 2) + +#define PINMUX_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) +#define PINMUX_GPIO18__FUNC_SIM1_SRST (MTK_PIN_NO(18) | 1) +#define PINMUX_GPIO18__FUNC_SIM2_SRST (MTK_PIN_NO(18) | 2) + +#define PINMUX_GPIO19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) +#define PINMUX_GPIO19__FUNC_SIM1_SDAT (MTK_PIN_NO(19) | 1) +#define PINMUX_GPIO19__FUNC_SIM2_SDAT (MTK_PIN_NO(19) | 2) + +#define PINMUX_GPIO20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) +#define PINMUX_GPIO20__FUNC_SIM2_SCLK (MTK_PIN_NO(20) | 1) +#define PINMUX_GPIO20__FUNC_SIM1_SCLK (MTK_PIN_NO(20) | 2) + +#define PINMUX_GPIO21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) +#define PINMUX_GPIO21__FUNC_SIM2_SRST (MTK_PIN_NO(21) | 1) +#define PINMUX_GPIO21__FUNC_SIM1_SRST (MTK_PIN_NO(21) | 2) + +#define PINMUX_GPIO22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) +#define PINMUX_GPIO22__FUNC_SIM2_SDAT (MTK_PIN_NO(22) | 1) +#define PINMUX_GPIO22__FUNC_SIM1_SDAT (MTK_PIN_NO(22) | 2) + +#define PINMUX_GPIO23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) +#define PINMUX_GPIO23__FUNC_MSDC3_DAT0 (MTK_PIN_NO(23) | 1) + +#define PINMUX_GPIO24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) +#define PINMUX_GPIO24__FUNC_MSDC3_DAT1 (MTK_PIN_NO(24) | 1) + +#define PINMUX_GPIO25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) +#define PINMUX_GPIO25__FUNC_MSDC3_DAT2 (MTK_PIN_NO(25) | 1) + +#define PINMUX_GPIO26__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) +#define PINMUX_GPIO26__FUNC_MSDC3_DAT3 (MTK_PIN_NO(26) | 1) + +#define PINMUX_GPIO27__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) +#define PINMUX_GPIO27__FUNC_MSDC3_CLK (MTK_PIN_NO(27) | 1) + +#define PINMUX_GPIO28__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) +#define PINMUX_GPIO28__FUNC_MSDC3_CMD (MTK_PIN_NO(28) | 1) + +#define PINMUX_GPIO29__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) +#define PINMUX_GPIO29__FUNC_PTA_RXD (MTK_PIN_NO(29) | 1) +#define PINMUX_GPIO29__FUNC_UCTS2 (MTK_PIN_NO(29) | 2) + +#define PINMUX_GPIO30__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) +#define PINMUX_GPIO30__FUNC_PTA_TXD (MTK_PIN_NO(30) | 1) +#define PINMUX_GPIO30__FUNC_URTS2 (MTK_PIN_NO(30) | 2) + +#define PINMUX_GPIO31__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) +#define PINMUX_GPIO31__FUNC_URXD2 (MTK_PIN_NO(31) | 1) +#define PINMUX_GPIO31__FUNC_UTXD2 (MTK_PIN_NO(31) | 2) + +#define PINMUX_GPIO32__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) +#define PINMUX_GPIO32__FUNC_UTXD2 (MTK_PIN_NO(32) | 1) +#define PINMUX_GPIO32__FUNC_URXD2 (MTK_PIN_NO(32) | 2) + +#define PINMUX_GPIO33__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) +#define PINMUX_GPIO33__FUNC_MRG_CLK (MTK_PIN_NO(33) | 1) +#define PINMUX_GPIO33__FUNC_PCM0_CLK (MTK_PIN_NO(33) | 2) + +#define PINMUX_GPIO34__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) +#define PINMUX_GPIO34__FUNC_MRG_DI (MTK_PIN_NO(34) | 1) +#define PINMUX_GPIO34__FUNC_PCM0_DI (MTK_PIN_NO(34) | 2) + +#define PINMUX_GPIO35__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) +#define PINMUX_GPIO35__FUNC_MRG_DO (MTK_PIN_NO(35) | 1) +#define PINMUX_GPIO35__FUNC_PCM0_DO (MTK_PIN_NO(35) | 2) + +#define PINMUX_GPIO36__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) +#define PINMUX_GPIO36__FUNC_MRG_SYNC (MTK_PIN_NO(36) | 1) +#define PINMUX_GPIO36__FUNC_PCM0_SYNC (MTK_PIN_NO(36) | 2) + +#define PINMUX_GPIO37__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) +#define PINMUX_GPIO37__FUNC_GPS_SYNC (MTK_PIN_NO(37) | 1) + +#define PINMUX_GPIO38__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) +#define PINMUX_GPIO38__FUNC_DAIRSTB (MTK_PIN_NO(38) | 1) + +#define PINMUX_GPIO39__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) +#define PINMUX_GPIO39__FUNC_CM2MCLK (MTK_PIN_NO(39) | 1) + +#define PINMUX_GPIO40__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) +#define PINMUX_GPIO40__FUNC_CM3MCLK (MTK_PIN_NO(40) | 1) +#define PINMUX_GPIO40__FUNC_IRDA_PDN (MTK_PIN_NO(40) | 2) +#define PINMUX_GPIO40__FUNC_PWM6 (MTK_PIN_NO(40) | 3) +#define PINMUX_GPIO40__FUNC_I2S1_WS (MTK_PIN_NO(40) | 4) + +#define PINMUX_GPIO41__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) +#define PINMUX_GPIO41__FUNC_CMPCLK (MTK_PIN_NO(41) | 1) +#define PINMUX_GPIO41__FUNC_CMCSK (MTK_PIN_NO(41) | 2) +#define PINMUX_GPIO41__FUNC_FLASH (MTK_PIN_NO(41) | 3) + +#define PINMUX_GPIO42__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) +#define PINMUX_GPIO42__FUNC_CMMCLK (MTK_PIN_NO(42) | 1) + +#define PINMUX_GPIO43__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) +#define PINMUX_GPIO43__FUNC_SDA2 (MTK_PIN_NO(43) | 1) + +#define PINMUX_GPIO44__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) +#define PINMUX_GPIO44__FUNC_SCL2 (MTK_PIN_NO(44) | 1) + +#define PINMUX_GPIO45__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) +#define PINMUX_GPIO45__FUNC_SDA0 (MTK_PIN_NO(45) | 1) + +#define PINMUX_GPIO46__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) +#define PINMUX_GPIO46__FUNC_SCL0 (MTK_PIN_NO(46) | 1) + +#define PINMUX_GPIO47__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) +#define PINMUX_GPIO47__FUNC_BPI_BUS0 (MTK_PIN_NO(47) | 1) + +#define PINMUX_GPIO48__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) +#define PINMUX_GPIO48__FUNC_BPI_BUS1 (MTK_PIN_NO(48) | 1) + +#define PINMUX_GPIO49__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) +#define PINMUX_GPIO49__FUNC_BPI_BUS2 (MTK_PIN_NO(49) | 1) + +#define PINMUX_GPIO50__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) +#define PINMUX_GPIO50__FUNC_BPI_BUS3 (MTK_PIN_NO(50) | 1) + +#define PINMUX_GPIO51__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) +#define PINMUX_GPIO51__FUNC_BPI_BUS4 (MTK_PIN_NO(51) | 1) + +#define PINMUX_GPIO52__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) +#define PINMUX_GPIO52__FUNC_BPI_BUS5 (MTK_PIN_NO(52) | 1) + +#define PINMUX_GPIO53__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) +#define PINMUX_GPIO53__FUNC_BPI_BUS6 (MTK_PIN_NO(53) | 1) + +#define PINMUX_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) +#define PINMUX_GPIO54__FUNC_BPI_BUS7 (MTK_PIN_NO(54) | 1) + +#define PINMUX_GPIO55__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) +#define PINMUX_GPIO55__FUNC_BPI_BUS8 (MTK_PIN_NO(55) | 1) + +#define PINMUX_GPIO56__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) +#define PINMUX_GPIO56__FUNC_BPI_BUS9 (MTK_PIN_NO(56) | 1) + +#define PINMUX_GPIO57__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) +#define PINMUX_GPIO57__FUNC_BPI_BUS10 (MTK_PIN_NO(57) | 1) + +#define PINMUX_GPIO58__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) +#define PINMUX_GPIO58__FUNC_BPI_BUS11 (MTK_PIN_NO(58) | 1) + +#define PINMUX_GPIO59__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) +#define PINMUX_GPIO59__FUNC_BPI_BUS12 (MTK_PIN_NO(59) | 1) + +#define PINMUX_GPIO60__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) +#define PINMUX_GPIO60__FUNC_BPI_BUS13 (MTK_PIN_NO(60) | 1) + +#define PINMUX_GPIO61__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) +#define PINMUX_GPIO61__FUNC_BPI_BUS14 (MTK_PIN_NO(61) | 1) + +#define PINMUX_GPIO62__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) +#define PINMUX_GPIO62__FUNC_RFIC1_BSI_CK (MTK_PIN_NO(62) | 1) + +#define PINMUX_GPIO63__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) +#define PINMUX_GPIO63__FUNC_RFIC1_BSI_D0 (MTK_PIN_NO(63) | 1) + +#define PINMUX_GPIO64__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) +#define PINMUX_GPIO64__FUNC_RFIC1_BSI_D1 (MTK_PIN_NO(64) | 1) + +#define PINMUX_GPIO65__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) +#define PINMUX_GPIO65__FUNC_RFIC1_BSI_D2 (MTK_PIN_NO(65) | 1) + +#define PINMUX_GPIO66__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) +#define PINMUX_GPIO66__FUNC_RFIC1_BSI_CS (MTK_PIN_NO(66) | 1) + +#define PINMUX_GPIO67__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) +#define PINMUX_GPIO67__FUNC_TD_TXBPI (MTK_PIN_NO(67) | 1) + +#define PINMUX_GPIO68__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) +#define PINMUX_GPIO68__FUNC_RFIC0_BSI_CK (MTK_PIN_NO(68) | 1) + +#define PINMUX_GPIO69__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) +#define PINMUX_GPIO69__FUNC_RFIC0_BSI_D0 (MTK_PIN_NO(69) | 1) + +#define PINMUX_GPIO70__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) +#define PINMUX_GPIO70__FUNC_RFIC0_BSI_D1 (MTK_PIN_NO(70) | 1) + +#define PINMUX_GPIO71__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) +#define PINMUX_GPIO71__FUNC_RFIC0_BSI_D2 (MTK_PIN_NO(71) | 1) + +#define PINMUX_GPIO72__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) +#define PINMUX_GPIO72__FUNC_RFIC0_BSI_CS (MTK_PIN_NO(72) | 1) + +#define PINMUX_GPIO73__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) +#define PINMUX_GPIO73__FUNC_MISC_BSI_DO (MTK_PIN_NO(73) | 1) + +#define PINMUX_GPIO74__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) +#define PINMUX_GPIO74__FUNC_MISC_BSI_CK (MTK_PIN_NO(74) | 1) + +#define PINMUX_GPIO75__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) +#define PINMUX_GPIO75__FUNC_MISC_BSI_CS0B (MTK_PIN_NO(75) | 1) +#define PINMUX_GPIO75__FUNC_MIPI1_SCLK (MTK_PIN_NO(75) | 2) + +#define PINMUX_GPIO76__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) +#define PINMUX_GPIO76__FUNC_MISC_BSI_CS1B (MTK_PIN_NO(76) | 1) + +#define PINMUX_GPIO77__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) +#define PINMUX_GPIO77__FUNC_MISC_BSI_DI (MTK_PIN_NO(77) | 1) +#define PINMUX_GPIO77__FUNC_MIPI1_SDATA (MTK_PIN_NO(77) | 2) + +#define PINMUX_GPIO78__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) +#define PINMUX_GPIO78__FUNC_LTE_TXBPI (MTK_PIN_NO(78) | 1) + +#define PINMUX_GPIO79__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) +#define PINMUX_GPIO79__FUNC_BPI_BUS15 (MTK_PIN_NO(79) | 1) + +#define PINMUX_GPIO80__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) +#define PINMUX_GPIO80__FUNC_BPI_BUS16 (MTK_PIN_NO(80) | 1) + +#define PINMUX_GPIO81__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) +#define PINMUX_GPIO81__FUNC_BPI_BUS17 (MTK_PIN_NO(81) | 1) + +#define PINMUX_GPIO82__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) +#define PINMUX_GPIO82__FUNC_BPI_BUS18 (MTK_PIN_NO(82) | 1) + +#define PINMUX_GPIO83__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) +#define PINMUX_GPIO83__FUNC_BPI_BUS19 (MTK_PIN_NO(83) | 1) + +#define PINMUX_GPIO84__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) +#define PINMUX_GPIO84__FUNC_BPI_BUS20 (MTK_PIN_NO(84) | 1) + +#define PINMUX_GPIO85__FUNC_GPIO85 (MTK_PIN_NO(85) | 0) +#define PINMUX_GPIO85__FUNC_BPI_BUS21 (MTK_PIN_NO(85) | 1) + +#define PINMUX_GPIO86__FUNC_GPIO86 (MTK_PIN_NO(86) | 0) +#define PINMUX_GPIO86__FUNC_BPI_BUS22 (MTK_PIN_NO(86) | 1) + +#define PINMUX_GPIO87__FUNC_GPIO87 (MTK_PIN_NO(87) | 0) +#define PINMUX_GPIO87__FUNC_BPI_BUS23 (MTK_PIN_NO(87) | 1) + +#define PINMUX_GPIO88__FUNC_GPIO88 (MTK_PIN_NO(88) | 0) +#define PINMUX_GPIO88__FUNC_BPI_BUS24 (MTK_PIN_NO(88) | 1) + +#define PINMUX_GPIO89__FUNC_GPIO89 (MTK_PIN_NO(89) | 0) +#define PINMUX_GPIO89__FUNC_BPI_BUS25 (MTK_PIN_NO(89) | 1) + +#define PINMUX_GPIO90__FUNC_GPIO90 (MTK_PIN_NO(90) | 0) +#define PINMUX_GPIO90__FUNC_BPI_BUS26 (MTK_PIN_NO(90) | 1) + +#define PINMUX_GPIO91__FUNC_GPIO91 (MTK_PIN_NO(91) | 0) +#define PINMUX_GPIO91__FUNC_BPI_BUS27 (MTK_PIN_NO(91) | 1) + +#define PINMUX_GPIO92__FUNC_GPIO92 (MTK_PIN_NO(92) | 0) +#define PINMUX_GPIO92__FUNC_PCM1_CLK (MTK_PIN_NO(92) | 1) +#define PINMUX_GPIO92__FUNC_I2S0_BCK (MTK_PIN_NO(92) | 2) +#define PINMUX_GPIO92__FUNC_NLD6 (MTK_PIN_NO(92) | 3) + +#define PINMUX_GPIO93__FUNC_GPIO93 (MTK_PIN_NO(93) | 0) +#define PINMUX_GPIO93__FUNC_PCM1_SYNC (MTK_PIN_NO(93) | 1) +#define PINMUX_GPIO93__FUNC_I2S0_WS (MTK_PIN_NO(93) | 2) +#define PINMUX_GPIO93__FUNC_NLD7 (MTK_PIN_NO(93) | 3) + +#define PINMUX_GPIO94__FUNC_GPIO94 (MTK_PIN_NO(94) | 0) +#define PINMUX_GPIO94__FUNC_PCM1_DI (MTK_PIN_NO(94) | 1) +#define PINMUX_GPIO94__FUNC_I2S0_DI (MTK_PIN_NO(94) | 2) +#define PINMUX_GPIO94__FUNC_NREB (MTK_PIN_NO(94) | 3) + +#define PINMUX_GPIO95__FUNC_GPIO95 (MTK_PIN_NO(95) | 0) +#define PINMUX_GPIO95__FUNC_PCM1_DO (MTK_PIN_NO(95) | 1) +#define PINMUX_GPIO95__FUNC_I2S0_DO (MTK_PIN_NO(95) | 2) +#define PINMUX_GPIO95__FUNC_NRNB0 (MTK_PIN_NO(95) | 3) + +#define PINMUX_GPIO96__FUNC_GPIO96 (MTK_PIN_NO(96) | 0) +#define PINMUX_GPIO96__FUNC_URXD1 (MTK_PIN_NO(96) | 1) +#define PINMUX_GPIO96__FUNC_UTXD1 (MTK_PIN_NO(96) | 2) +#define PINMUX_GPIO96__FUNC_NWEB (MTK_PIN_NO(96) | 3) + +#define PINMUX_GPIO97__FUNC_GPIO97 (MTK_PIN_NO(97) | 0) +#define PINMUX_GPIO97__FUNC_UTXD1 (MTK_PIN_NO(97) | 1) +#define PINMUX_GPIO97__FUNC_URXD1 (MTK_PIN_NO(97) | 2) +#define PINMUX_GPIO97__FUNC_NCEB0 (MTK_PIN_NO(97) | 3) + +#define PINMUX_GPIO98__FUNC_GPIO98 (MTK_PIN_NO(98) | 0) +#define PINMUX_GPIO98__FUNC_URTS1 (MTK_PIN_NO(98) | 1) +#define PINMUX_GPIO98__FUNC_UCTS1 (MTK_PIN_NO(98) | 2) +#define PINMUX_GPIO98__FUNC_NALE (MTK_PIN_NO(98) | 3) + +#define PINMUX_GPIO99__FUNC_GPIO99 (MTK_PIN_NO(99) | 0) +#define PINMUX_GPIO99__FUNC_UCTS1 (MTK_PIN_NO(99) | 1) +#define PINMUX_GPIO99__FUNC_URTS1 (MTK_PIN_NO(99) | 2) +#define PINMUX_GPIO99__FUNC_NCLE (MTK_PIN_NO(99) | 3) + +#define PINMUX_GPIO100__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) +#define PINMUX_GPIO100__FUNC_MSDC2_DAT0 (MTK_PIN_NO(100) | 1) +#define PINMUX_GPIO100__FUNC_URXD1 (MTK_PIN_NO(100) | 2) +#define PINMUX_GPIO100__FUNC_USB_DRVVBUS (MTK_PIN_NO(100) | 3) +#define PINMUX_GPIO100__FUNC_SDA4 (MTK_PIN_NO(100) | 4) + +#define PINMUX_GPIO101__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) +#define PINMUX_GPIO101__FUNC_MSDC2_DAT1 (MTK_PIN_NO(101) | 1) +#define PINMUX_GPIO101__FUNC_UTXD1 (MTK_PIN_NO(101) | 2) +#define PINMUX_GPIO101__FUNC_SCL4 (MTK_PIN_NO(101) | 4) + +#define PINMUX_GPIO102__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) +#define PINMUX_GPIO102__FUNC_MSDC2_DAT2 (MTK_PIN_NO(102) | 1) +#define PINMUX_GPIO102__FUNC_URTS1 (MTK_PIN_NO(102) | 2) +#define PINMUX_GPIO102__FUNC_UTXD0 (MTK_PIN_NO(102) | 3) +#define PINMUX_GPIO102__FUNC_PWM0 (MTK_PIN_NO(102) | 5) +#define PINMUX_GPIO102__FUNC_SPI_CK_1 (MTK_PIN_NO(102) | 6) + +#define PINMUX_GPIO103__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) +#define PINMUX_GPIO103__FUNC_MSDC2_DAT3 (MTK_PIN_NO(103) | 1) +#define PINMUX_GPIO103__FUNC_UCTS1 (MTK_PIN_NO(103) | 2) +#define PINMUX_GPIO103__FUNC_URXD0 (MTK_PIN_NO(103) | 3) +#define PINMUX_GPIO103__FUNC_PWM1 (MTK_PIN_NO(103) | 5) +#define PINMUX_GPIO103__FUNC_SPI_MI_1 (MTK_PIN_NO(103) | 6) + +#define PINMUX_GPIO104__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) +#define PINMUX_GPIO104__FUNC_MSDC2_CLK (MTK_PIN_NO(104) | 1) +#define PINMUX_GPIO104__FUNC_NLD4 (MTK_PIN_NO(104) | 2) +#define PINMUX_GPIO104__FUNC_UTXD3 (MTK_PIN_NO(104) | 3) +#define PINMUX_GPIO104__FUNC_SDA3 (MTK_PIN_NO(104) | 4) +#define PINMUX_GPIO104__FUNC_PWM2 (MTK_PIN_NO(104) | 5) +#define PINMUX_GPIO104__FUNC_SPI_MO_1 (MTK_PIN_NO(104) | 6) + +#define PINMUX_GPIO105__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) +#define PINMUX_GPIO105__FUNC_MSDC2_CMD (MTK_PIN_NO(105) | 1) +#define PINMUX_GPIO105__FUNC_NLD5 (MTK_PIN_NO(105) | 2) +#define PINMUX_GPIO105__FUNC_URXD3 (MTK_PIN_NO(105) | 3) +#define PINMUX_GPIO105__FUNC_SCL3 (MTK_PIN_NO(105) | 4) +#define PINMUX_GPIO105__FUNC_PWM3 (MTK_PIN_NO(105) | 5) +#define PINMUX_GPIO105__FUNC_SPI_CS_1 (MTK_PIN_NO(105) | 6) + +#define PINMUX_GPIO106__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) +#define PINMUX_GPIO106__FUNC_LCM_RST (MTK_PIN_NO(106) | 1) + +#define PINMUX_GPIO107__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) +#define PINMUX_GPIO107__FUNC_DSI_TE (MTK_PIN_NO(107) | 1) + +#define PINMUX_GPIO108__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) +#define PINMUX_GPIO108__FUNC_JTMS (MTK_PIN_NO(108) | 1) +#define PINMUX_GPIO108__FUNC_MFG_JTAG_TMS (MTK_PIN_NO(108) | 2) +#define PINMUX_GPIO108__FUNC_TDD_TMS (MTK_PIN_NO(108) | 3) +#define PINMUX_GPIO108__FUNC_LTE_MD32_JTAG_TMS (MTK_PIN_NO(108) | 4) +#define PINMUX_GPIO108__FUNC_AP_MD32_JTAG_TMS (MTK_PIN_NO(108) | 5) +#define PINMUX_GPIO108__FUNC_DFD_TMS (MTK_PIN_NO(108) | 6) + +#define PINMUX_GPIO109__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) +#define PINMUX_GPIO109__FUNC_JTCK (MTK_PIN_NO(109) | 1) +#define PINMUX_GPIO109__FUNC_MFG_JTAG_TCK (MTK_PIN_NO(109) | 2) +#define PINMUX_GPIO109__FUNC_TDD_TCK (MTK_PIN_NO(109) | 3) +#define PINMUX_GPIO109__FUNC_LTE_MD32_JTAG_TCK (MTK_PIN_NO(109) | 4) +#define PINMUX_GPIO109__FUNC_AP_MD32_JTAG_TCK (MTK_PIN_NO(109) | 5) +#define PINMUX_GPIO109__FUNC_DFD_TCK (MTK_PIN_NO(109) | 6) + +#define PINMUX_GPIO110__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) +#define PINMUX_GPIO110__FUNC_JTDI (MTK_PIN_NO(110) | 1) +#define PINMUX_GPIO110__FUNC_MFG_JTAG_TDI (MTK_PIN_NO(110) | 2) +#define PINMUX_GPIO110__FUNC_TDD_TDI (MTK_PIN_NO(110) | 3) +#define PINMUX_GPIO110__FUNC_LTE_MD32_JTAG_TDI (MTK_PIN_NO(110) | 4) +#define PINMUX_GPIO110__FUNC_AP_MD32_JTAG_TDI (MTK_PIN_NO(110) | 5) +#define PINMUX_GPIO110__FUNC_DFD_TDI (MTK_PIN_NO(110) | 6) + +#define PINMUX_GPIO111__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) +#define PINMUX_GPIO111__FUNC_JTDO (MTK_PIN_NO(111) | 1) +#define PINMUX_GPIO111__FUNC_MFG_JTAG_TDO (MTK_PIN_NO(111) | 2) +#define PINMUX_GPIO111__FUNC_TDD_TDO (MTK_PIN_NO(111) | 3) +#define PINMUX_GPIO111__FUNC_LTE_MD32_JTAG_TDO (MTK_PIN_NO(111) | 4) +#define PINMUX_GPIO111__FUNC_AP_MD32_JTAG_TDO (MTK_PIN_NO(111) | 5) +#define PINMUX_GPIO111__FUNC_DFD_TDO (MTK_PIN_NO(111) | 6) + +#define PINMUX_GPIO112__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) +#define PINMUX_GPIO112__FUNC_JTRST_B (MTK_PIN_NO(112) | 1) +#define PINMUX_GPIO112__FUNC_MFG_JTAG_TRSTN (MTK_PIN_NO(112) | 2) +#define PINMUX_GPIO112__FUNC_TDD_TRSTN (MTK_PIN_NO(112) | 3) +#define PINMUX_GPIO112__FUNC_LTE_MD32_JTAG_TRST (MTK_PIN_NO(112) | 4) +#define PINMUX_GPIO112__FUNC_AP_MD32_JTAG_TRST (MTK_PIN_NO(112) | 5) +#define PINMUX_GPIO112__FUNC_DFD_NTRST (MTK_PIN_NO(112) | 6) + +#define PINMUX_GPIO113__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) +#define PINMUX_GPIO113__FUNC_URXD0 (MTK_PIN_NO(113) | 1) +#define PINMUX_GPIO113__FUNC_UTXD0 (MTK_PIN_NO(113) | 2) +#define PINMUX_GPIO113__FUNC_MD_URXD (MTK_PIN_NO(113) | 3) +#define PINMUX_GPIO113__FUNC_LTE_URXD (MTK_PIN_NO(113) | 4) +#define PINMUX_GPIO113__FUNC_TDD_TXD (MTK_PIN_NO(113) | 5) +#define PINMUX_GPIO113__FUNC_I2S2_WS (MTK_PIN_NO(113) | 6) + +#define PINMUX_GPIO114__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) +#define PINMUX_GPIO114__FUNC_UTXD0 (MTK_PIN_NO(114) | 1) +#define PINMUX_GPIO114__FUNC_URXD0 (MTK_PIN_NO(114) | 2) +#define PINMUX_GPIO114__FUNC_MD_UTXD (MTK_PIN_NO(114) | 3) +#define PINMUX_GPIO114__FUNC_LTE_UTXD (MTK_PIN_NO(114) | 4) +#define PINMUX_GPIO114__FUNC_TDD_TXD (MTK_PIN_NO(114) | 5) +#define PINMUX_GPIO114__FUNC_I2S2_BCK (MTK_PIN_NO(114) | 6) + +#define PINMUX_GPIO115__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) +#define PINMUX_GPIO115__FUNC_URTS0 (MTK_PIN_NO(115) | 1) +#define PINMUX_GPIO115__FUNC_UCTS0 (MTK_PIN_NO(115) | 2) +#define PINMUX_GPIO115__FUNC_MD_URXD (MTK_PIN_NO(115) | 3) +#define PINMUX_GPIO115__FUNC_LTE_URXD (MTK_PIN_NO(115) | 4) +#define PINMUX_GPIO115__FUNC_TDD_TXD (MTK_PIN_NO(115) | 5) +#define PINMUX_GPIO115__FUNC_I2S2_MCK (MTK_PIN_NO(115) | 6) + +#define PINMUX_GPIO116__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) +#define PINMUX_GPIO116__FUNC_UCTS0 (MTK_PIN_NO(116) | 1) +#define PINMUX_GPIO116__FUNC_URTS0 (MTK_PIN_NO(116) | 2) +#define PINMUX_GPIO116__FUNC_MD_UTXD (MTK_PIN_NO(116) | 3) +#define PINMUX_GPIO116__FUNC_LTE_UTXD (MTK_PIN_NO(116) | 4) +#define PINMUX_GPIO116__FUNC_TDD_TXD (MTK_PIN_NO(116) | 5) +#define PINMUX_GPIO116__FUNC_I2S2_DI_1 (MTK_PIN_NO(116) | 6) + +#define PINMUX_GPIO117__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) +#define PINMUX_GPIO117__FUNC_URXD3 (MTK_PIN_NO(117) | 1) +#define PINMUX_GPIO117__FUNC_UTXD3 (MTK_PIN_NO(117) | 2) +#define PINMUX_GPIO117__FUNC_MD_URXD (MTK_PIN_NO(117) | 3) +#define PINMUX_GPIO117__FUNC_LTE_URXD (MTK_PIN_NO(117) | 4) +#define PINMUX_GPIO117__FUNC_TDD_TXD (MTK_PIN_NO(117) | 5) + +#define PINMUX_GPIO118__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) +#define PINMUX_GPIO118__FUNC_UTXD3 (MTK_PIN_NO(118) | 1) +#define PINMUX_GPIO118__FUNC_URXD3 (MTK_PIN_NO(118) | 2) +#define PINMUX_GPIO118__FUNC_MD_UTXD (MTK_PIN_NO(118) | 3) +#define PINMUX_GPIO118__FUNC_LTE_UTXD (MTK_PIN_NO(118) | 4) +#define PINMUX_GPIO118__FUNC_TDD_TXD (MTK_PIN_NO(118) | 5) + +#define PINMUX_GPIO119__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) +#define PINMUX_GPIO119__FUNC_KROW0 (MTK_PIN_NO(119) | 1) + +#define PINMUX_GPIO120__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) +#define PINMUX_GPIO120__FUNC_KROW1 (MTK_PIN_NO(120) | 1) +#define PINMUX_GPIO120__FUNC_PWM6 (MTK_PIN_NO(120) | 3) + +#define PINMUX_GPIO121__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) +#define PINMUX_GPIO121__FUNC_KROW2 (MTK_PIN_NO(121) | 1) +#define PINMUX_GPIO121__FUNC_IRDA_PDN (MTK_PIN_NO(121) | 2) +#define PINMUX_GPIO121__FUNC_I2S1_DO_1 (MTK_PIN_NO(121) | 3) +#define PINMUX_GPIO121__FUNC_USB_DRVVBUS (MTK_PIN_NO(121) | 4) +#define PINMUX_GPIO121__FUNC_SPI_CK_2 (MTK_PIN_NO(121) | 5) +#define PINMUX_GPIO121__FUNC_PWM4 (MTK_PIN_NO(121) | 6) + +#define PINMUX_GPIO122__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) +#define PINMUX_GPIO122__FUNC_KCOL0 (MTK_PIN_NO(122) | 1) + +#define PINMUX_GPIO123__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) +#define PINMUX_GPIO123__FUNC_KCOL1 (MTK_PIN_NO(123) | 1) +#define PINMUX_GPIO123__FUNC_IRDA_RXD (MTK_PIN_NO(123) | 2) +#define PINMUX_GPIO123__FUNC_I2S2_DI_2 (MTK_PIN_NO(123) | 3) +#define PINMUX_GPIO123__FUNC_PWM5 (MTK_PIN_NO(123) | 4) + +#define PINMUX_GPIO124__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) +#define PINMUX_GPIO124__FUNC_KCOL2 (MTK_PIN_NO(124) | 1) +#define PINMUX_GPIO124__FUNC_IRDA_TXD (MTK_PIN_NO(124) | 2) +#define PINMUX_GPIO124__FUNC_I2S1_DO_2 (MTK_PIN_NO(124) | 3) +#define PINMUX_GPIO124__FUNC_USB_DRVVBUS (MTK_PIN_NO(124) | 4) +#define PINMUX_GPIO124__FUNC_SPI_MI_2 (MTK_PIN_NO(124) | 5) +#define PINMUX_GPIO124__FUNC_PWM3 (MTK_PIN_NO(124) | 6) + +#define PINMUX_GPIO125__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) +#define PINMUX_GPIO125__FUNC_SDA1 (MTK_PIN_NO(125) | 1) + +#define PINMUX_GPIO126__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) +#define PINMUX_GPIO126__FUNC_SCL1 (MTK_PIN_NO(126) | 1) + +#define PINMUX_GPIO127__FUNC_GPIO127 (MTK_PIN_NO(127) | 0) +#define PINMUX_GPIO127__FUNC_MD_EINT1 (MTK_PIN_NO(127) | 1) +#define PINMUX_GPIO127__FUNC_DISP_PWM1 (MTK_PIN_NO(127) | 2) +#define PINMUX_GPIO127__FUNC_SPI_MO_2 (MTK_PIN_NO(127) | 3) + +#define PINMUX_GPIO128__FUNC_GPIO128 (MTK_PIN_NO(128) | 0) +#define PINMUX_GPIO128__FUNC_MD_EINT2 (MTK_PIN_NO(128) | 1) +#define PINMUX_GPIO128__FUNC_DSI1_TE (MTK_PIN_NO(128) | 2) +#define PINMUX_GPIO128__FUNC_SPI_CS_2 (MTK_PIN_NO(128) | 3) + +#define PINMUX_GPIO129__FUNC_GPIO129 (MTK_PIN_NO(129) | 0) +#define PINMUX_GPIO129__FUNC_I2S3_WS (MTK_PIN_NO(129) | 1) +#define PINMUX_GPIO129__FUNC_I2S2_WS (MTK_PIN_NO(129) | 2) +#define PINMUX_GPIO129__FUNC_PWM0 (MTK_PIN_NO(129) | 3) + +#define PINMUX_GPIO130__FUNC_GPIO130 (MTK_PIN_NO(130) | 0) +#define PINMUX_GPIO130__FUNC_I2S3_BCK (MTK_PIN_NO(130) | 1) +#define PINMUX_GPIO130__FUNC_I2S2_BCK (MTK_PIN_NO(130) | 2) +#define PINMUX_GPIO130__FUNC_PWM1 (MTK_PIN_NO(130) | 3) + +#define PINMUX_GPIO131__FUNC_GPIO131 (MTK_PIN_NO(131) | 0) +#define PINMUX_GPIO131__FUNC_I2S3_MCK (MTK_PIN_NO(131) | 1) +#define PINMUX_GPIO131__FUNC_I2S2_MCK (MTK_PIN_NO(131) | 2) +#define PINMUX_GPIO131__FUNC_PWM2 (MTK_PIN_NO(131) | 3) + +#define PINMUX_GPIO132__FUNC_GPIO132 (MTK_PIN_NO(132) | 0) +#define PINMUX_GPIO132__FUNC_I2S3_DO_1 (MTK_PIN_NO(132) | 1) +#define PINMUX_GPIO132__FUNC_I2S2_DI_1 (MTK_PIN_NO(132) | 2) +#define PINMUX_GPIO132__FUNC_PWM3 (MTK_PIN_NO(132) | 3) + +#define PINMUX_GPIO133__FUNC_GPIO133 (MTK_PIN_NO(133) | 0) +#define PINMUX_GPIO133__FUNC_I2S3_DO_2 (MTK_PIN_NO(133) | 1) +#define PINMUX_GPIO133__FUNC_I2S2_DI_2 (MTK_PIN_NO(133) | 2) +#define PINMUX_GPIO133__FUNC_PWM4 (MTK_PIN_NO(133) | 3) + +#define PINMUX_GPIO134__FUNC_GPIO134 (MTK_PIN_NO(134) | 0) +#define PINMUX_GPIO134__FUNC_I2S3_DO_3 (MTK_PIN_NO(134) | 1) +#define PINMUX_GPIO134__FUNC_DISP_PWM1 (MTK_PIN_NO(134) | 2) +#define PINMUX_GPIO134__FUNC_I2S1_DO_1 (MTK_PIN_NO(134) | 3) +#define PINMUX_GPIO134__FUNC_PWM5 (MTK_PIN_NO(134) | 4) + +#define PINMUX_GPIO135__FUNC_GPIO135 (MTK_PIN_NO(135) | 0) +#define PINMUX_GPIO135__FUNC_I2S3_DO_4 (MTK_PIN_NO(135) | 1) +#define PINMUX_GPIO135__FUNC_DSI1_TE (MTK_PIN_NO(135) | 2) +#define PINMUX_GPIO135__FUNC_I2S1_DO_2 (MTK_PIN_NO(135) | 3) +#define PINMUX_GPIO135__FUNC_PWM6 (MTK_PIN_NO(135) | 4) + +#define PINMUX_GPIO136__FUNC_GPIO136 (MTK_PIN_NO(136) | 0) +#define PINMUX_GPIO136__FUNC_SDA3 (MTK_PIN_NO(136) | 1) + +#define PINMUX_GPIO137__FUNC_GPIO137 (MTK_PIN_NO(137) | 0) +#define PINMUX_GPIO137__FUNC_SCL3 (MTK_PIN_NO(137) | 1) + +#define PINMUX_GPIO138__FUNC_GPIO138 (MTK_PIN_NO(138) | 0) +#define PINMUX_GPIO138__FUNC_DPI_CK (MTK_PIN_NO(138) | 1) +#define PINMUX_GPIO138__FUNC_NLD6 (MTK_PIN_NO(138) | 2) +#define PINMUX_GPIO138__FUNC_UTXD0 (MTK_PIN_NO(138) | 3) +#define PINMUX_GPIO138__FUNC_USB_DRVVBUS (MTK_PIN_NO(138) | 4) +#define PINMUX_GPIO138__FUNC_IRDA_PDN (MTK_PIN_NO(138) | 5) + +#define PINMUX_GPIO139__FUNC_GPIO139 (MTK_PIN_NO(139) | 0) +#define PINMUX_GPIO139__FUNC_DPI_DE (MTK_PIN_NO(139) | 1) +#define PINMUX_GPIO139__FUNC_NLD7 (MTK_PIN_NO(139) | 2) +#define PINMUX_GPIO139__FUNC_URXD0 (MTK_PIN_NO(139) | 3) +#define PINMUX_GPIO139__FUNC_MD_UTXD (MTK_PIN_NO(139) | 4) +#define PINMUX_GPIO139__FUNC_IRDA_RXD (MTK_PIN_NO(139) | 5) + +#define PINMUX_GPIO140__FUNC_GPIO140 (MTK_PIN_NO(140) | 0) +#define PINMUX_GPIO140__FUNC_DPI_D0 (MTK_PIN_NO(140) | 1) +#define PINMUX_GPIO140__FUNC_NREB (MTK_PIN_NO(140) | 2) +#define PINMUX_GPIO140__FUNC_UCTS0 (MTK_PIN_NO(140) | 3) +#define PINMUX_GPIO140__FUNC_MD_URXD (MTK_PIN_NO(140) | 4) +#define PINMUX_GPIO140__FUNC_IRDA_TXD (MTK_PIN_NO(140) | 5) + +#define PINMUX_GPIO141__FUNC_GPIO141 (MTK_PIN_NO(141) | 0) +#define PINMUX_GPIO141__FUNC_DPI_D1 (MTK_PIN_NO(141) | 1) +#define PINMUX_GPIO141__FUNC_NRNB0 (MTK_PIN_NO(141) | 2) +#define PINMUX_GPIO141__FUNC_URTS0 (MTK_PIN_NO(141) | 3) +#define PINMUX_GPIO141__FUNC_LTE_UTXD (MTK_PIN_NO(141) | 4) +#define PINMUX_GPIO141__FUNC_I2S2_WS (MTK_PIN_NO(141) | 5) + +#define PINMUX_GPIO142__FUNC_GPIO142 (MTK_PIN_NO(142) | 0) +#define PINMUX_GPIO142__FUNC_DPI_D2 (MTK_PIN_NO(142) | 1) +#define PINMUX_GPIO142__FUNC_NWEB (MTK_PIN_NO(142) | 2) +#define PINMUX_GPIO142__FUNC_UTXD1 (MTK_PIN_NO(142) | 3) +#define PINMUX_GPIO142__FUNC_LTE_URXD (MTK_PIN_NO(142) | 4) +#define PINMUX_GPIO142__FUNC_I2S2_BCK (MTK_PIN_NO(142) | 5) + +#define PINMUX_GPIO143__FUNC_GPIO143 (MTK_PIN_NO(143) | 0) +#define PINMUX_GPIO143__FUNC_DPI_D3 (MTK_PIN_NO(143) | 1) +#define PINMUX_GPIO143__FUNC_NCEB0 (MTK_PIN_NO(143) | 2) +#define PINMUX_GPIO143__FUNC_URXD1 (MTK_PIN_NO(143) | 3) +#define PINMUX_GPIO143__FUNC_TDD_TXD (MTK_PIN_NO(143) | 4) +#define PINMUX_GPIO143__FUNC_I2S2_MCK (MTK_PIN_NO(143) | 5) + +#define PINMUX_GPIO144__FUNC_GPIO144 (MTK_PIN_NO(144) | 0) +#define PINMUX_GPIO144__FUNC_DPI_D4 (MTK_PIN_NO(144) | 1) +#define PINMUX_GPIO144__FUNC_NALE (MTK_PIN_NO(144) | 2) +#define PINMUX_GPIO144__FUNC_UCTS1 (MTK_PIN_NO(144) | 3) +#define PINMUX_GPIO144__FUNC_TDD_TMS (MTK_PIN_NO(144) | 4) +#define PINMUX_GPIO144__FUNC_I2S2_DI_1 (MTK_PIN_NO(144) | 5) + +#define PINMUX_GPIO145__FUNC_GPIO145 (MTK_PIN_NO(145) | 0) +#define PINMUX_GPIO145__FUNC_DPI_D5 (MTK_PIN_NO(145) | 1) +#define PINMUX_GPIO145__FUNC_NCLE (MTK_PIN_NO(145) | 2) +#define PINMUX_GPIO145__FUNC_URTS1 (MTK_PIN_NO(145) | 3) +#define PINMUX_GPIO145__FUNC_TDD_TCK (MTK_PIN_NO(145) | 4) +#define PINMUX_GPIO145__FUNC_I2S2_DI_2 (MTK_PIN_NO(145) | 5) + +#define PINMUX_GPIO146__FUNC_GPIO146 (MTK_PIN_NO(146) | 0) +#define PINMUX_GPIO146__FUNC_DPI_D6 (MTK_PIN_NO(146) | 1) +#define PINMUX_GPIO146__FUNC_NLD8 (MTK_PIN_NO(146) | 2) +#define PINMUX_GPIO146__FUNC_UTXD2 (MTK_PIN_NO(146) | 3) +#define PINMUX_GPIO146__FUNC_TDD_TDI (MTK_PIN_NO(146) | 4) + +#define PINMUX_GPIO147__FUNC_GPIO147 (MTK_PIN_NO(147) | 0) +#define PINMUX_GPIO147__FUNC_DPI_D7 (MTK_PIN_NO(147) | 1) +#define PINMUX_GPIO147__FUNC_NLD9 (MTK_PIN_NO(147) | 2) +#define PINMUX_GPIO147__FUNC_URXD2 (MTK_PIN_NO(147) | 3) +#define PINMUX_GPIO147__FUNC_TDD_TDO (MTK_PIN_NO(147) | 4) +#define PINMUX_GPIO147__FUNC_I2S1_WS (MTK_PIN_NO(147) | 5) + +#define PINMUX_GPIO148__FUNC_GPIO148 (MTK_PIN_NO(148) | 0) +#define PINMUX_GPIO148__FUNC_DPI_D8 (MTK_PIN_NO(148) | 1) +#define PINMUX_GPIO148__FUNC_NLD10 (MTK_PIN_NO(148) | 2) +#define PINMUX_GPIO148__FUNC_UCTS2 (MTK_PIN_NO(148) | 3) +#define PINMUX_GPIO148__FUNC_TDD_TRSTN (MTK_PIN_NO(148) | 4) +#define PINMUX_GPIO148__FUNC_I2S1_BCK (MTK_PIN_NO(148) | 5) + +#define PINMUX_GPIO149__FUNC_GPIO149 (MTK_PIN_NO(149) | 0) +#define PINMUX_GPIO149__FUNC_DPI_D9 (MTK_PIN_NO(149) | 1) +#define PINMUX_GPIO149__FUNC_NLD11 (MTK_PIN_NO(149) | 2) +#define PINMUX_GPIO149__FUNC_URTS2 (MTK_PIN_NO(149) | 3) +#define PINMUX_GPIO149__FUNC_LTE_MD32_JTAG_TMS (MTK_PIN_NO(149) | 4) +#define PINMUX_GPIO149__FUNC_I2S1_MCK (MTK_PIN_NO(149) | 5) + +#define PINMUX_GPIO150__FUNC_GPIO150 (MTK_PIN_NO(150) | 0) +#define PINMUX_GPIO150__FUNC_DPI_D10 (MTK_PIN_NO(150) | 1) +#define PINMUX_GPIO150__FUNC_NLD12 (MTK_PIN_NO(150) | 2) +#define PINMUX_GPIO150__FUNC_UTXD3 (MTK_PIN_NO(150) | 3) +#define PINMUX_GPIO150__FUNC_LTE_MD32_JTAG_TCK (MTK_PIN_NO(150) | 4) +#define PINMUX_GPIO150__FUNC_I2S1_DO_1 (MTK_PIN_NO(150) | 5) + +#define PINMUX_GPIO151__FUNC_GPIO151 (MTK_PIN_NO(151) | 0) +#define PINMUX_GPIO151__FUNC_DPI_D11 (MTK_PIN_NO(151) | 1) +#define PINMUX_GPIO151__FUNC_NLD13 (MTK_PIN_NO(151) | 2) +#define PINMUX_GPIO151__FUNC_URXD3 (MTK_PIN_NO(151) | 3) +#define PINMUX_GPIO151__FUNC_LTE_MD32_JTAG_TDI (MTK_PIN_NO(151) | 4) +#define PINMUX_GPIO151__FUNC_I2S1_DO_2 (MTK_PIN_NO(151) | 5) + +#define PINMUX_GPIO152__FUNC_GPIO152 (MTK_PIN_NO(152) | 0) +#define PINMUX_GPIO152__FUNC_DPI_HSYNC (MTK_PIN_NO(152) | 1) +#define PINMUX_GPIO152__FUNC_NLD14 (MTK_PIN_NO(152) | 2) +#define PINMUX_GPIO152__FUNC_UCTS3 (MTK_PIN_NO(152) | 3) +#define PINMUX_GPIO152__FUNC_LTE_MD32_JTAG_TDO (MTK_PIN_NO(152) | 4) +#define PINMUX_GPIO152__FUNC_DSI1_TE (MTK_PIN_NO(152) | 5) + +#define PINMUX_GPIO153__FUNC_GPIO153 (MTK_PIN_NO(153) | 0) +#define PINMUX_GPIO153__FUNC_DPI_VSYNC (MTK_PIN_NO(153) | 1) +#define PINMUX_GPIO153__FUNC_NLD15 (MTK_PIN_NO(153) | 2) +#define PINMUX_GPIO153__FUNC_URTS3 (MTK_PIN_NO(153) | 3) +#define PINMUX_GPIO153__FUNC_LTE_MD32_JTAG_TRST (MTK_PIN_NO(153) | 4) +#define PINMUX_GPIO153__FUNC_DISP_PWM1 (MTK_PIN_NO(153) | 5) + +#define PINMUX_GPIO154__FUNC_GPIO154 (MTK_PIN_NO(154) | 0) +#define PINMUX_GPIO154__FUNC_MSDC0_DAT0 (MTK_PIN_NO(154) | 1) +#define PINMUX_GPIO154__FUNC_NLD8 (MTK_PIN_NO(154) | 2) + +#define PINMUX_GPIO155__FUNC_GPIO155 (MTK_PIN_NO(155) | 0) +#define PINMUX_GPIO155__FUNC_MSDC0_DAT1 (MTK_PIN_NO(155) | 1) +#define PINMUX_GPIO155__FUNC_NLD9 (MTK_PIN_NO(155) | 2) + +#define PINMUX_GPIO156__FUNC_GPIO156 (MTK_PIN_NO(156) | 0) +#define PINMUX_GPIO156__FUNC_MSDC0_DAT2 (MTK_PIN_NO(156) | 1) +#define PINMUX_GPIO156__FUNC_NLD10 (MTK_PIN_NO(156) | 2) + +#define PINMUX_GPIO157__FUNC_GPIO157 (MTK_PIN_NO(157) | 0) +#define PINMUX_GPIO157__FUNC_MSDC0_DAT3 (MTK_PIN_NO(157) | 1) +#define PINMUX_GPIO157__FUNC_NLD11 (MTK_PIN_NO(157) | 2) + +#define PINMUX_GPIO158__FUNC_GPIO158 (MTK_PIN_NO(158) | 0) +#define PINMUX_GPIO158__FUNC_MSDC0_DAT4 (MTK_PIN_NO(158) | 1) +#define PINMUX_GPIO158__FUNC_NLD12 (MTK_PIN_NO(158) | 2) + +#define PINMUX_GPIO159__FUNC_GPIO159 (MTK_PIN_NO(159) | 0) +#define PINMUX_GPIO159__FUNC_MSDC0_DAT5 (MTK_PIN_NO(159) | 1) +#define PINMUX_GPIO159__FUNC_NLD13 (MTK_PIN_NO(159) | 2) + +#define PINMUX_GPIO160__FUNC_GPIO160 (MTK_PIN_NO(160) | 0) +#define PINMUX_GPIO160__FUNC_MSDC0_DAT6 (MTK_PIN_NO(160) | 1) +#define PINMUX_GPIO160__FUNC_NLD14 (MTK_PIN_NO(160) | 2) + +#define PINMUX_GPIO161__FUNC_GPIO161 (MTK_PIN_NO(161) | 0) +#define PINMUX_GPIO161__FUNC_MSDC0_DAT7 (MTK_PIN_NO(161) | 1) +#define PINMUX_GPIO161__FUNC_NLD15 (MTK_PIN_NO(161) | 2) + +#define PINMUX_GPIO162__FUNC_GPIO162 (MTK_PIN_NO(162) | 0) +#define PINMUX_GPIO162__FUNC_MSDC0_CMD (MTK_PIN_NO(162) | 1) + +#define PINMUX_GPIO163__FUNC_GPIO163 (MTK_PIN_NO(163) | 0) +#define PINMUX_GPIO163__FUNC_MSDC0_CLK (MTK_PIN_NO(163) | 1) + +#define PINMUX_GPIO164__FUNC_GPIO164 (MTK_PIN_NO(164) | 0) +#define PINMUX_GPIO164__FUNC_MSDC0_DSL (MTK_PIN_NO(164) | 1) + +#define PINMUX_GPIO165__FUNC_GPIO165 (MTK_PIN_NO(165) | 0) +#define PINMUX_GPIO165__FUNC_MSDC0_RSTB (MTK_PIN_NO(165) | 1) + +#define PINMUX_GPIO166__FUNC_GPIO166 (MTK_PIN_NO(166) | 0) +#define PINMUX_GPIO166__FUNC_SPI_CK_0 (MTK_PIN_NO(166) | 1) +#define PINMUX_GPIO166__FUNC_PWM0 (MTK_PIN_NO(166) | 3) + +#define PINMUX_GPIO167__FUNC_GPIO167 (MTK_PIN_NO(167) | 0) +#define PINMUX_GPIO167__FUNC_SPI_MI_0 (MTK_PIN_NO(167) | 1) +#define PINMUX_GPIO167__FUNC_PWM1 (MTK_PIN_NO(167) | 3) +#define PINMUX_GPIO167__FUNC_SPI_MO_0 (MTK_PIN_NO(167) | 4) + +#define PINMUX_GPIO168__FUNC_GPIO168 (MTK_PIN_NO(168) | 0) +#define PINMUX_GPIO168__FUNC_SPI_MO_0 (MTK_PIN_NO(168) | 1) +#define PINMUX_GPIO168__FUNC_MD_EINT3 (MTK_PIN_NO(168) | 2) +#define PINMUX_GPIO168__FUNC_PWM2 (MTK_PIN_NO(168) | 3) +#define PINMUX_GPIO168__FUNC_SPI_MI_0 (MTK_PIN_NO(168) | 4) + +#define PINMUX_GPIO169__FUNC_GPIO169 (MTK_PIN_NO(169) | 0) +#define PINMUX_GPIO169__FUNC_SPI_CS_0 (MTK_PIN_NO(169) | 1) +#define PINMUX_GPIO169__FUNC_MD_EINT4 (MTK_PIN_NO(169) | 2) +#define PINMUX_GPIO169__FUNC_PWM3 (MTK_PIN_NO(169) | 3) + +#define PINMUX_GPIO170__FUNC_GPIO170 (MTK_PIN_NO(170) | 0) +#define PINMUX_GPIO170__FUNC_MSDC1_CMD (MTK_PIN_NO(170) | 1) + +#define PINMUX_GPIO171__FUNC_GPIO171 (MTK_PIN_NO(171) | 0) +#define PINMUX_GPIO171__FUNC_MSDC1_DAT0 (MTK_PIN_NO(171) | 1) + +#define PINMUX_GPIO172__FUNC_GPIO172 (MTK_PIN_NO(172) | 0) +#define PINMUX_GPIO172__FUNC_MSDC1_DAT1 (MTK_PIN_NO(172) | 1) + +#define PINMUX_GPIO173__FUNC_GPIO173 (MTK_PIN_NO(173) | 0) +#define PINMUX_GPIO173__FUNC_MSDC1_DAT2 (MTK_PIN_NO(173) | 1) + +#define PINMUX_GPIO174__FUNC_GPIO174 (MTK_PIN_NO(174) | 0) +#define PINMUX_GPIO174__FUNC_MSDC1_DAT3 (MTK_PIN_NO(174) | 1) + +#define PINMUX_GPIO175__FUNC_GPIO175 (MTK_PIN_NO(175) | 0) +#define PINMUX_GPIO175__FUNC_MSDC1_CLK (MTK_PIN_NO(175) | 1) + +#define PINMUX_GPIO176__FUNC_GPIO176 (MTK_PIN_NO(176) | 0) +#define PINMUX_GPIO176__FUNC_PWRAP_SPIMI (MTK_PIN_NO(176) | 1) +#define PINMUX_GPIO176__FUNC_PWRAP_SPIMO (MTK_PIN_NO(176) | 2) + +#define PINMUX_GPIO177__FUNC_GPIO177 (MTK_PIN_NO(177) | 0) +#define PINMUX_GPIO177__FUNC_PWRAP_SPIMO (MTK_PIN_NO(177) | 1) +#define PINMUX_GPIO177__FUNC_PWRAP_SPIMI (MTK_PIN_NO(177) | 2) + +#define PINMUX_GPIO178__FUNC_GPIO178 (MTK_PIN_NO(178) | 0) +#define PINMUX_GPIO178__FUNC_PWRAP_SPICK (MTK_PIN_NO(178) | 1) + +#define PINMUX_GPIO179__FUNC_GPIO179 (MTK_PIN_NO(179) | 0) +#define PINMUX_GPIO179__FUNC_PWRAP_SPICS (MTK_PIN_NO(179) | 1) + +#define PINMUX_GPIO180__FUNC_GPIO180 (MTK_PIN_NO(180) | 0) +#define PINMUX_GPIO180__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(180) | 1) +#define PINMUX_GPIO180__FUNC_I2S1_WS (MTK_PIN_NO(180) | 2) +#define PINMUX_GPIO180__FUNC_I2S2_WS (MTK_PIN_NO(180) | 3) +#define PINMUX_GPIO180__FUNC_I2S0_WS (MTK_PIN_NO(180) | 4) + +#define PINMUX_GPIO181__FUNC_GPIO181 (MTK_PIN_NO(181) | 0) +#define PINMUX_GPIO181__FUNC_AUD_DAT_MISO_1 (MTK_PIN_NO(181) | 1) +#define PINMUX_GPIO181__FUNC_I2S1_BCK (MTK_PIN_NO(181) | 2) +#define PINMUX_GPIO181__FUNC_I2S2_BCK (MTK_PIN_NO(181) | 3) +#define PINMUX_GPIO181__FUNC_I2S0_BCK (MTK_PIN_NO(181) | 4) + +#define PINMUX_GPIO182__FUNC_GPIO182 (MTK_PIN_NO(182) | 0) +#define PINMUX_GPIO182__FUNC_AUD_DAT_MOSI_1 (MTK_PIN_NO(182) | 1) +#define PINMUX_GPIO182__FUNC_I2S1_MCK (MTK_PIN_NO(182) | 2) +#define PINMUX_GPIO182__FUNC_I2S2_MCK (MTK_PIN_NO(182) | 3) +#define PINMUX_GPIO182__FUNC_I2S0_MCK (MTK_PIN_NO(182) | 4) + +#define PINMUX_GPIO183__FUNC_GPIO183 (MTK_PIN_NO(183) | 0) +#define PINMUX_GPIO183__FUNC_AUD_DAT_MISO_2 (MTK_PIN_NO(183) | 1) +#define PINMUX_GPIO183__FUNC_I2S1_DO_1 (MTK_PIN_NO(183) | 2) +#define PINMUX_GPIO183__FUNC_I2S2_DI_1 (MTK_PIN_NO(183) | 3) +#define PINMUX_GPIO183__FUNC_I2S0_DO (MTK_PIN_NO(183) | 4) + +#define PINMUX_GPIO184__FUNC_GPIO184 (MTK_PIN_NO(184) | 0) +#define PINMUX_GPIO184__FUNC_AUD_DAT_MOSI_2 (MTK_PIN_NO(184) | 1) +#define PINMUX_GPIO184__FUNC_I2S1_DO_2 (MTK_PIN_NO(184) | 2) +#define PINMUX_GPIO184__FUNC_I2S2_DI_2 (MTK_PIN_NO(184) | 3) +#define PINMUX_GPIO184__FUNC_I2S0_DI (MTK_PIN_NO(184) | 4) + +#define PINMUX_GPIO185__FUNC_GPIO185 (MTK_PIN_NO(185) | 0) +#define PINMUX_GPIO185__FUNC_RTC32K_CK (MTK_PIN_NO(185) | 1) + +#define PINMUX_GPIO186__FUNC_GPIO186 (MTK_PIN_NO(186) | 0) +#define PINMUX_GPIO186__FUNC_DISP_PWM0 (MTK_PIN_NO(186) | 1) +#define PINMUX_GPIO186__FUNC_DISP_PWM1 (MTK_PIN_NO(186) | 2) + +#define PINMUX_GPIO187__FUNC_GPIO187 (MTK_PIN_NO(187) | 0) +#define PINMUX_GPIO187__FUNC_SRCLKENAI (MTK_PIN_NO(187) | 1) + +#define PINMUX_GPIO188__FUNC_GPIO188 (MTK_PIN_NO(188) | 0) +#define PINMUX_GPIO188__FUNC_SRCLKENAI2 (MTK_PIN_NO(188) | 1) + +#define PINMUX_GPIO189__FUNC_GPIO189 (MTK_PIN_NO(189) | 0) +#define PINMUX_GPIO189__FUNC_SRCLKENA0 (MTK_PIN_NO(189) | 1) + +#define PINMUX_GPIO190__FUNC_GPIO190 (MTK_PIN_NO(190) | 0) +#define PINMUX_GPIO190__FUNC_SRCLKENA1 (MTK_PIN_NO(190) | 1) + +#define PINMUX_GPIO191__FUNC_GPIO191 (MTK_PIN_NO(191) | 0) +#define PINMUX_GPIO191__FUNC_WATCHDOG_AO (MTK_PIN_NO(191) | 1) + +#define PINMUX_GPIO192__FUNC_GPIO192 (MTK_PIN_NO(192) | 0) +#define PINMUX_GPIO192__FUNC_I2S0_WS (MTK_PIN_NO(192) | 1) +#define PINMUX_GPIO192__FUNC_I2S1_WS (MTK_PIN_NO(192) | 2) +#define PINMUX_GPIO192__FUNC_I2S2_WS (MTK_PIN_NO(192) | 3) +#define PINMUX_GPIO192__FUNC_NCEB1 (MTK_PIN_NO(192) | 4) + +#define PINMUX_GPIO193__FUNC_GPIO193 (MTK_PIN_NO(193) | 0) +#define PINMUX_GPIO193__FUNC_I2S0_BCK (MTK_PIN_NO(193) | 1) +#define PINMUX_GPIO193__FUNC_I2S1_BCK (MTK_PIN_NO(193) | 2) +#define PINMUX_GPIO193__FUNC_I2S2_BCK (MTK_PIN_NO(193) | 3) +#define PINMUX_GPIO193__FUNC_NRNB1 (MTK_PIN_NO(193) | 4) + +#define PINMUX_GPIO194__FUNC_GPIO194 (MTK_PIN_NO(194) | 0) +#define PINMUX_GPIO194__FUNC_I2S0_MCK (MTK_PIN_NO(194) | 1) +#define PINMUX_GPIO194__FUNC_I2S1_MCK (MTK_PIN_NO(194) | 2) +#define PINMUX_GPIO194__FUNC_I2S2_MCK (MTK_PIN_NO(194) | 3) + +#define PINMUX_GPIO195__FUNC_GPIO195 (MTK_PIN_NO(195) | 0) +#define PINMUX_GPIO195__FUNC_I2S0_DO (MTK_PIN_NO(195) | 1) +#define PINMUX_GPIO195__FUNC_I2S1_DO_1 (MTK_PIN_NO(195) | 2) +#define PINMUX_GPIO195__FUNC_I2S2_DI_1 (MTK_PIN_NO(195) | 3) + +#define PINMUX_GPIO196__FUNC_GPIO196 (MTK_PIN_NO(196) | 0) +#define PINMUX_GPIO196__FUNC_I2S0_DI (MTK_PIN_NO(196) | 1) +#define PINMUX_GPIO196__FUNC_I2S1_DO_2 (MTK_PIN_NO(196) | 2) +#define PINMUX_GPIO196__FUNC_I2S2_DI_2 (MTK_PIN_NO(196) | 3) + + +#endif diff --git a/include/dt-bindings/pinctrl/mt8135-pinfunc.h b/include/dt-bindings/pinctrl/mt8135-pinfunc.h new file mode 100644 index 000000000000..ce0cb5a440eb --- /dev/null +++ b/include/dt-bindings/pinctrl/mt8135-pinfunc.h @@ -0,0 +1,1294 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com> + */ + +#ifndef __DTS_MT8135_PINFUNC_H +#define __DTS_MT8135_PINFUNC_H + +#include <dt-bindings/pinctrl/mt65xx.h> + +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(0) | 1) +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_EINT49 (MTK_PIN_NO(0) | 2) +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_I2SOUT_DAT (MTK_PIN_NO(0) | 3) +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_DAC_DAT_OUT (MTK_PIN_NO(0) | 4) +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_PCM1_DO (MTK_PIN_NO(0) | 5) +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_SPI1_MO (MTK_PIN_NO(0) | 6) +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_NALE (MTK_PIN_NO(0) | 7) + +#define MT8135_PIN_1_MSDC0_DAT6__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define MT8135_PIN_1_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(1) | 1) +#define MT8135_PIN_1_MSDC0_DAT6__FUNC_EINT48 (MTK_PIN_NO(1) | 2) +#define MT8135_PIN_1_MSDC0_DAT6__FUNC_I2SIN_WS (MTK_PIN_NO(1) | 3) +#define MT8135_PIN_1_MSDC0_DAT6__FUNC_DAC_WS (MTK_PIN_NO(1) | 4) +#define MT8135_PIN_1_MSDC0_DAT6__FUNC_PCM1_WS (MTK_PIN_NO(1) | 5) +#define MT8135_PIN_1_MSDC0_DAT6__FUNC_SPI1_CSN (MTK_PIN_NO(1) | 6) +#define MT8135_PIN_1_MSDC0_DAT6__FUNC_NCLE (MTK_PIN_NO(1) | 7) + +#define MT8135_PIN_2_MSDC0_DAT5__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define MT8135_PIN_2_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(2) | 1) +#define MT8135_PIN_2_MSDC0_DAT5__FUNC_EINT47 (MTK_PIN_NO(2) | 2) +#define MT8135_PIN_2_MSDC0_DAT5__FUNC_I2SIN_CK (MTK_PIN_NO(2) | 3) +#define MT8135_PIN_2_MSDC0_DAT5__FUNC_DAC_CK (MTK_PIN_NO(2) | 4) +#define MT8135_PIN_2_MSDC0_DAT5__FUNC_PCM1_CK (MTK_PIN_NO(2) | 5) +#define MT8135_PIN_2_MSDC0_DAT5__FUNC_SPI1_CLK (MTK_PIN_NO(2) | 6) +#define MT8135_PIN_2_MSDC0_DAT5__FUNC_NLD4 (MTK_PIN_NO(2) | 7) + +#define MT8135_PIN_3_MSDC0_DAT4__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define MT8135_PIN_3_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(3) | 1) +#define MT8135_PIN_3_MSDC0_DAT4__FUNC_EINT46 (MTK_PIN_NO(3) | 2) +#define MT8135_PIN_3_MSDC0_DAT4__FUNC_A_FUNC_CK (MTK_PIN_NO(3) | 3) +#define MT8135_PIN_3_MSDC0_DAT4__FUNC_LSCE1B_2X (MTK_PIN_NO(3) | 6) +#define MT8135_PIN_3_MSDC0_DAT4__FUNC_NLD5 (MTK_PIN_NO(3) | 7) + +#define MT8135_PIN_4_MSDC0_CMD__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define MT8135_PIN_4_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(4) | 1) +#define MT8135_PIN_4_MSDC0_CMD__FUNC_EINT41 (MTK_PIN_NO(4) | 2) +#define MT8135_PIN_4_MSDC0_CMD__FUNC_A_FUNC_DOUT_0 (MTK_PIN_NO(4) | 3) +#define MT8135_PIN_4_MSDC0_CMD__FUNC_USB_TEST_IO_0 (MTK_PIN_NO(4) | 5) +#define MT8135_PIN_4_MSDC0_CMD__FUNC_LRSTB_2X (MTK_PIN_NO(4) | 6) +#define MT8135_PIN_4_MSDC0_CMD__FUNC_NRNB (MTK_PIN_NO(4) | 7) + +#define MT8135_PIN_5_MSDC0_CLK__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define MT8135_PIN_5_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(5) | 1) +#define MT8135_PIN_5_MSDC0_CLK__FUNC_EINT40 (MTK_PIN_NO(5) | 2) +#define MT8135_PIN_5_MSDC0_CLK__FUNC_A_FUNC_DOUT_1 (MTK_PIN_NO(5) | 3) +#define MT8135_PIN_5_MSDC0_CLK__FUNC_USB_TEST_IO_1 (MTK_PIN_NO(5) | 5) +#define MT8135_PIN_5_MSDC0_CLK__FUNC_LPTE (MTK_PIN_NO(5) | 6) +#define MT8135_PIN_5_MSDC0_CLK__FUNC_NREB (MTK_PIN_NO(5) | 7) + +#define MT8135_PIN_6_MSDC0_DAT3__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define MT8135_PIN_6_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(6) | 1) +#define MT8135_PIN_6_MSDC0_DAT3__FUNC_EINT45 (MTK_PIN_NO(6) | 2) +#define MT8135_PIN_6_MSDC0_DAT3__FUNC_A_FUNC_DOUT_2 (MTK_PIN_NO(6) | 3) +#define MT8135_PIN_6_MSDC0_DAT3__FUNC_USB_TEST_IO_2 (MTK_PIN_NO(6) | 5) +#define MT8135_PIN_6_MSDC0_DAT3__FUNC_LSCE0B_2X (MTK_PIN_NO(6) | 6) +#define MT8135_PIN_6_MSDC0_DAT3__FUNC_NLD7 (MTK_PIN_NO(6) | 7) + +#define MT8135_PIN_7_MSDC0_DAT2__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +#define MT8135_PIN_7_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(7) | 1) +#define MT8135_PIN_7_MSDC0_DAT2__FUNC_EINT44 (MTK_PIN_NO(7) | 2) +#define MT8135_PIN_7_MSDC0_DAT2__FUNC_A_FUNC_DOUT_3 (MTK_PIN_NO(7) | 3) +#define MT8135_PIN_7_MSDC0_DAT2__FUNC_USB_TEST_IO_3 (MTK_PIN_NO(7) | 5) +#define MT8135_PIN_7_MSDC0_DAT2__FUNC_LSA0_2X (MTK_PIN_NO(7) | 6) +#define MT8135_PIN_7_MSDC0_DAT2__FUNC_NLD14 (MTK_PIN_NO(7) | 7) + +#define MT8135_PIN_8_MSDC0_DAT1__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +#define MT8135_PIN_8_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(8) | 1) +#define MT8135_PIN_8_MSDC0_DAT1__FUNC_EINT43 (MTK_PIN_NO(8) | 2) +#define MT8135_PIN_8_MSDC0_DAT1__FUNC_USB_TEST_IO_4 (MTK_PIN_NO(8) | 5) +#define MT8135_PIN_8_MSDC0_DAT1__FUNC_LSCK_2X (MTK_PIN_NO(8) | 6) +#define MT8135_PIN_8_MSDC0_DAT1__FUNC_NLD11 (MTK_PIN_NO(8) | 7) + +#define MT8135_PIN_9_MSDC0_DAT0__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +#define MT8135_PIN_9_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(9) | 1) +#define MT8135_PIN_9_MSDC0_DAT0__FUNC_EINT42 (MTK_PIN_NO(9) | 2) +#define MT8135_PIN_9_MSDC0_DAT0__FUNC_USB_TEST_IO_5 (MTK_PIN_NO(9) | 5) +#define MT8135_PIN_9_MSDC0_DAT0__FUNC_LSDA_2X (MTK_PIN_NO(9) | 6) + +#define MT8135_PIN_10_NCEB0__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +#define MT8135_PIN_10_NCEB0__FUNC_NCEB0 (MTK_PIN_NO(10) | 1) +#define MT8135_PIN_10_NCEB0__FUNC_EINT139 (MTK_PIN_NO(10) | 2) +#define MT8135_PIN_10_NCEB0__FUNC_TESTA_OUT4 (MTK_PIN_NO(10) | 7) + +#define MT8135_PIN_11_NCEB1__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +#define MT8135_PIN_11_NCEB1__FUNC_NCEB1 (MTK_PIN_NO(11) | 1) +#define MT8135_PIN_11_NCEB1__FUNC_EINT140 (MTK_PIN_NO(11) | 2) +#define MT8135_PIN_11_NCEB1__FUNC_USB_DRVVBUS (MTK_PIN_NO(11) | 6) +#define MT8135_PIN_11_NCEB1__FUNC_TESTA_OUT5 (MTK_PIN_NO(11) | 7) + +#define MT8135_PIN_12_NRNB__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +#define MT8135_PIN_12_NRNB__FUNC_NRNB (MTK_PIN_NO(12) | 1) +#define MT8135_PIN_12_NRNB__FUNC_EINT141 (MTK_PIN_NO(12) | 2) +#define MT8135_PIN_12_NRNB__FUNC_A_FUNC_DOUT_4 (MTK_PIN_NO(12) | 3) +#define MT8135_PIN_12_NRNB__FUNC_TESTA_OUT6 (MTK_PIN_NO(12) | 7) + +#define MT8135_PIN_13_NCLE__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) +#define MT8135_PIN_13_NCLE__FUNC_NCLE (MTK_PIN_NO(13) | 1) +#define MT8135_PIN_13_NCLE__FUNC_EINT142 (MTK_PIN_NO(13) | 2) +#define MT8135_PIN_13_NCLE__FUNC_A_FUNC_DOUT_5 (MTK_PIN_NO(13) | 3) +#define MT8135_PIN_13_NCLE__FUNC_CM2PDN_1X (MTK_PIN_NO(13) | 4) +#define MT8135_PIN_13_NCLE__FUNC_NALE (MTK_PIN_NO(13) | 6) +#define MT8135_PIN_13_NCLE__FUNC_TESTA_OUT7 (MTK_PIN_NO(13) | 7) + +#define MT8135_PIN_14_NALE__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) +#define MT8135_PIN_14_NALE__FUNC_NALE (MTK_PIN_NO(14) | 1) +#define MT8135_PIN_14_NALE__FUNC_EINT143 (MTK_PIN_NO(14) | 2) +#define MT8135_PIN_14_NALE__FUNC_A_FUNC_DOUT_6 (MTK_PIN_NO(14) | 3) +#define MT8135_PIN_14_NALE__FUNC_CM2MCLK_1X (MTK_PIN_NO(14) | 4) +#define MT8135_PIN_14_NALE__FUNC_IRDA_RXD (MTK_PIN_NO(14) | 5) +#define MT8135_PIN_14_NALE__FUNC_NCLE (MTK_PIN_NO(14) | 6) +#define MT8135_PIN_14_NALE__FUNC_TESTA_OUT8 (MTK_PIN_NO(14) | 7) + +#define MT8135_PIN_15_NREB__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) +#define MT8135_PIN_15_NREB__FUNC_NREB (MTK_PIN_NO(15) | 1) +#define MT8135_PIN_15_NREB__FUNC_EINT144 (MTK_PIN_NO(15) | 2) +#define MT8135_PIN_15_NREB__FUNC_A_FUNC_DOUT_7 (MTK_PIN_NO(15) | 3) +#define MT8135_PIN_15_NREB__FUNC_CM2RST_1X (MTK_PIN_NO(15) | 4) +#define MT8135_PIN_15_NREB__FUNC_IRDA_TXD (MTK_PIN_NO(15) | 5) +#define MT8135_PIN_15_NREB__FUNC_TESTA_OUT9 (MTK_PIN_NO(15) | 7) + +#define MT8135_PIN_16_NWEB__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) +#define MT8135_PIN_16_NWEB__FUNC_NWEB (MTK_PIN_NO(16) | 1) +#define MT8135_PIN_16_NWEB__FUNC_EINT145 (MTK_PIN_NO(16) | 2) +#define MT8135_PIN_16_NWEB__FUNC_A_FUNC_DIN_0 (MTK_PIN_NO(16) | 3) +#define MT8135_PIN_16_NWEB__FUNC_CM2PCLK_1X (MTK_PIN_NO(16) | 4) +#define MT8135_PIN_16_NWEB__FUNC_IRDA_PDN (MTK_PIN_NO(16) | 5) +#define MT8135_PIN_16_NWEB__FUNC_TESTA_OUT10 (MTK_PIN_NO(16) | 7) + +#define MT8135_PIN_17_NLD0__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) +#define MT8135_PIN_17_NLD0__FUNC_NLD0 (MTK_PIN_NO(17) | 1) +#define MT8135_PIN_17_NLD0__FUNC_EINT146 (MTK_PIN_NO(17) | 2) +#define MT8135_PIN_17_NLD0__FUNC_A_FUNC_DIN_1 (MTK_PIN_NO(17) | 3) +#define MT8135_PIN_17_NLD0__FUNC_CM2DAT_1X_0 (MTK_PIN_NO(17) | 4) +#define MT8135_PIN_17_NLD0__FUNC_I2SIN_CK (MTK_PIN_NO(17) | 5) +#define MT8135_PIN_17_NLD0__FUNC_DAC_CK (MTK_PIN_NO(17) | 6) +#define MT8135_PIN_17_NLD0__FUNC_TESTA_OUT11 (MTK_PIN_NO(17) | 7) + +#define MT8135_PIN_18_NLD1__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) +#define MT8135_PIN_18_NLD1__FUNC_NLD1 (MTK_PIN_NO(18) | 1) +#define MT8135_PIN_18_NLD1__FUNC_EINT147 (MTK_PIN_NO(18) | 2) +#define MT8135_PIN_18_NLD1__FUNC_A_FUNC_DIN_2 (MTK_PIN_NO(18) | 3) +#define MT8135_PIN_18_NLD1__FUNC_CM2DAT_1X_1 (MTK_PIN_NO(18) | 4) +#define MT8135_PIN_18_NLD1__FUNC_I2SIN_WS (MTK_PIN_NO(18) | 5) +#define MT8135_PIN_18_NLD1__FUNC_DAC_WS (MTK_PIN_NO(18) | 6) +#define MT8135_PIN_18_NLD1__FUNC_TESTA_OUT12 (MTK_PIN_NO(18) | 7) + +#define MT8135_PIN_19_NLD2__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) +#define MT8135_PIN_19_NLD2__FUNC_NLD2 (MTK_PIN_NO(19) | 1) +#define MT8135_PIN_19_NLD2__FUNC_EINT148 (MTK_PIN_NO(19) | 2) +#define MT8135_PIN_19_NLD2__FUNC_A_FUNC_DIN_3 (MTK_PIN_NO(19) | 3) +#define MT8135_PIN_19_NLD2__FUNC_CM2DAT_1X_2 (MTK_PIN_NO(19) | 4) +#define MT8135_PIN_19_NLD2__FUNC_I2SOUT_DAT (MTK_PIN_NO(19) | 5) +#define MT8135_PIN_19_NLD2__FUNC_DAC_DAT_OUT (MTK_PIN_NO(19) | 6) +#define MT8135_PIN_19_NLD2__FUNC_TESTA_OUT13 (MTK_PIN_NO(19) | 7) + +#define MT8135_PIN_20_NLD3__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) +#define MT8135_PIN_20_NLD3__FUNC_NLD3 (MTK_PIN_NO(20) | 1) +#define MT8135_PIN_20_NLD3__FUNC_EINT149 (MTK_PIN_NO(20) | 2) +#define MT8135_PIN_20_NLD3__FUNC_A_FUNC_DIN_4 (MTK_PIN_NO(20) | 3) +#define MT8135_PIN_20_NLD3__FUNC_CM2DAT_1X_3 (MTK_PIN_NO(20) | 4) +#define MT8135_PIN_20_NLD3__FUNC_TESTA_OUT14 (MTK_PIN_NO(20) | 7) + +#define MT8135_PIN_21_NLD4__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) +#define MT8135_PIN_21_NLD4__FUNC_NLD4 (MTK_PIN_NO(21) | 1) +#define MT8135_PIN_21_NLD4__FUNC_EINT150 (MTK_PIN_NO(21) | 2) +#define MT8135_PIN_21_NLD4__FUNC_A_FUNC_DIN_5 (MTK_PIN_NO(21) | 3) +#define MT8135_PIN_21_NLD4__FUNC_CM2DAT_1X_4 (MTK_PIN_NO(21) | 4) +#define MT8135_PIN_21_NLD4__FUNC_TESTA_OUT15 (MTK_PIN_NO(21) | 7) + +#define MT8135_PIN_22_NLD5__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) +#define MT8135_PIN_22_NLD5__FUNC_NLD5 (MTK_PIN_NO(22) | 1) +#define MT8135_PIN_22_NLD5__FUNC_EINT151 (MTK_PIN_NO(22) | 2) +#define MT8135_PIN_22_NLD5__FUNC_A_FUNC_DIN_6 (MTK_PIN_NO(22) | 3) +#define MT8135_PIN_22_NLD5__FUNC_CM2DAT_1X_5 (MTK_PIN_NO(22) | 4) +#define MT8135_PIN_22_NLD5__FUNC_TESTA_OUT16 (MTK_PIN_NO(22) | 7) + +#define MT8135_PIN_23_NLD6__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) +#define MT8135_PIN_23_NLD6__FUNC_NLD6 (MTK_PIN_NO(23) | 1) +#define MT8135_PIN_23_NLD6__FUNC_EINT152 (MTK_PIN_NO(23) | 2) +#define MT8135_PIN_23_NLD6__FUNC_A_FUNC_DIN_7 (MTK_PIN_NO(23) | 3) +#define MT8135_PIN_23_NLD6__FUNC_CM2DAT_1X_6 (MTK_PIN_NO(23) | 4) +#define MT8135_PIN_23_NLD6__FUNC_TESTA_OUT17 (MTK_PIN_NO(23) | 7) + +#define MT8135_PIN_24_NLD7__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) +#define MT8135_PIN_24_NLD7__FUNC_NLD7 (MTK_PIN_NO(24) | 1) +#define MT8135_PIN_24_NLD7__FUNC_EINT153 (MTK_PIN_NO(24) | 2) +#define MT8135_PIN_24_NLD7__FUNC_A_FUNC_DIN_8 (MTK_PIN_NO(24) | 3) +#define MT8135_PIN_24_NLD7__FUNC_CM2DAT_1X_7 (MTK_PIN_NO(24) | 4) +#define MT8135_PIN_24_NLD7__FUNC_TESTA_OUT18 (MTK_PIN_NO(24) | 7) + +#define MT8135_PIN_25_NLD8__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) +#define MT8135_PIN_25_NLD8__FUNC_NLD8 (MTK_PIN_NO(25) | 1) +#define MT8135_PIN_25_NLD8__FUNC_EINT154 (MTK_PIN_NO(25) | 2) +#define MT8135_PIN_25_NLD8__FUNC_CM2DAT_1X_8 (MTK_PIN_NO(25) | 4) + +#define MT8135_PIN_26_NLD9__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) +#define MT8135_PIN_26_NLD9__FUNC_NLD9 (MTK_PIN_NO(26) | 1) +#define MT8135_PIN_26_NLD9__FUNC_EINT155 (MTK_PIN_NO(26) | 2) +#define MT8135_PIN_26_NLD9__FUNC_CM2DAT_1X_9 (MTK_PIN_NO(26) | 4) +#define MT8135_PIN_26_NLD9__FUNC_PWM1 (MTK_PIN_NO(26) | 5) + +#define MT8135_PIN_27_NLD10__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) +#define MT8135_PIN_27_NLD10__FUNC_NLD10 (MTK_PIN_NO(27) | 1) +#define MT8135_PIN_27_NLD10__FUNC_EINT156 (MTK_PIN_NO(27) | 2) +#define MT8135_PIN_27_NLD10__FUNC_CM2VSYNC_1X (MTK_PIN_NO(27) | 4) +#define MT8135_PIN_27_NLD10__FUNC_PWM2 (MTK_PIN_NO(27) | 5) + +#define MT8135_PIN_28_NLD11__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) +#define MT8135_PIN_28_NLD11__FUNC_NLD11 (MTK_PIN_NO(28) | 1) +#define MT8135_PIN_28_NLD11__FUNC_EINT157 (MTK_PIN_NO(28) | 2) +#define MT8135_PIN_28_NLD11__FUNC_CM2HSYNC_1X (MTK_PIN_NO(28) | 4) +#define MT8135_PIN_28_NLD11__FUNC_PWM3 (MTK_PIN_NO(28) | 5) + +#define MT8135_PIN_29_NLD12__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) +#define MT8135_PIN_29_NLD12__FUNC_NLD12 (MTK_PIN_NO(29) | 1) +#define MT8135_PIN_29_NLD12__FUNC_EINT158 (MTK_PIN_NO(29) | 2) +#define MT8135_PIN_29_NLD12__FUNC_I2SIN_CK (MTK_PIN_NO(29) | 3) +#define MT8135_PIN_29_NLD12__FUNC_DAC_CK (MTK_PIN_NO(29) | 4) +#define MT8135_PIN_29_NLD12__FUNC_PCM1_CK (MTK_PIN_NO(29) | 5) + +#define MT8135_PIN_30_NLD13__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) +#define MT8135_PIN_30_NLD13__FUNC_NLD13 (MTK_PIN_NO(30) | 1) +#define MT8135_PIN_30_NLD13__FUNC_EINT159 (MTK_PIN_NO(30) | 2) +#define MT8135_PIN_30_NLD13__FUNC_I2SIN_WS (MTK_PIN_NO(30) | 3) +#define MT8135_PIN_30_NLD13__FUNC_DAC_WS (MTK_PIN_NO(30) | 4) +#define MT8135_PIN_30_NLD13__FUNC_PCM1_WS (MTK_PIN_NO(30) | 5) + +#define MT8135_PIN_31_NLD14__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) +#define MT8135_PIN_31_NLD14__FUNC_NLD14 (MTK_PIN_NO(31) | 1) +#define MT8135_PIN_31_NLD14__FUNC_EINT160 (MTK_PIN_NO(31) | 2) +#define MT8135_PIN_31_NLD14__FUNC_I2SOUT_DAT (MTK_PIN_NO(31) | 3) +#define MT8135_PIN_31_NLD14__FUNC_DAC_DAT_OUT (MTK_PIN_NO(31) | 4) +#define MT8135_PIN_31_NLD14__FUNC_PCM1_DO (MTK_PIN_NO(31) | 5) + +#define MT8135_PIN_32_NLD15__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) +#define MT8135_PIN_32_NLD15__FUNC_NLD15 (MTK_PIN_NO(32) | 1) +#define MT8135_PIN_32_NLD15__FUNC_EINT161 (MTK_PIN_NO(32) | 2) +#define MT8135_PIN_32_NLD15__FUNC_DISP_PWM (MTK_PIN_NO(32) | 3) +#define MT8135_PIN_32_NLD15__FUNC_PWM4 (MTK_PIN_NO(32) | 4) +#define MT8135_PIN_32_NLD15__FUNC_PCM1_DI (MTK_PIN_NO(32) | 5) + +#define MT8135_PIN_33_MSDC0_RSTB__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) +#define MT8135_PIN_33_MSDC0_RSTB__FUNC_MSDC0_RSTB (MTK_PIN_NO(33) | 1) +#define MT8135_PIN_33_MSDC0_RSTB__FUNC_EINT50 (MTK_PIN_NO(33) | 2) +#define MT8135_PIN_33_MSDC0_RSTB__FUNC_I2SIN_DAT (MTK_PIN_NO(33) | 3) +#define MT8135_PIN_33_MSDC0_RSTB__FUNC_PCM1_DI (MTK_PIN_NO(33) | 5) +#define MT8135_PIN_33_MSDC0_RSTB__FUNC_SPI1_MI (MTK_PIN_NO(33) | 6) +#define MT8135_PIN_33_MSDC0_RSTB__FUNC_NLD10 (MTK_PIN_NO(33) | 7) + +#define MT8135_PIN_34_IDDIG__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) +#define MT8135_PIN_34_IDDIG__FUNC_IDDIG (MTK_PIN_NO(34) | 1) +#define MT8135_PIN_34_IDDIG__FUNC_EINT34 (MTK_PIN_NO(34) | 2) + +#define MT8135_PIN_35_SCL3__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) +#define MT8135_PIN_35_SCL3__FUNC_SCL3 (MTK_PIN_NO(35) | 1) +#define MT8135_PIN_35_SCL3__FUNC_EINT96 (MTK_PIN_NO(35) | 2) +#define MT8135_PIN_35_SCL3__FUNC_CLKM6 (MTK_PIN_NO(35) | 3) +#define MT8135_PIN_35_SCL3__FUNC_PWM6 (MTK_PIN_NO(35) | 4) + +#define MT8135_PIN_36_SDA3__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) +#define MT8135_PIN_36_SDA3__FUNC_SDA3 (MTK_PIN_NO(36) | 1) +#define MT8135_PIN_36_SDA3__FUNC_EINT97 (MTK_PIN_NO(36) | 2) + +#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) +#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_AUD_CLK (MTK_PIN_NO(37) | 1) +#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_ADC_CK (MTK_PIN_NO(37) | 2) +#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_HDMI_SDATA0 (MTK_PIN_NO(37) | 3) +#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_EINT19 (MTK_PIN_NO(37) | 4) +#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_USB_TEST_IO_6 (MTK_PIN_NO(37) | 5) +#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_TESTA_OUT19 (MTK_PIN_NO(37) | 7) + +#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) +#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_AUD_DAT_MOSI (MTK_PIN_NO(38) | 1) +#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_ADC_WS (MTK_PIN_NO(38) | 2) +#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_AUD_DAT_MISO (MTK_PIN_NO(38) | 3) +#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_EINT21 (MTK_PIN_NO(38) | 4) +#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_USB_TEST_IO_7 (MTK_PIN_NO(38) | 5) +#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_TESTA_OUT20 (MTK_PIN_NO(38) | 7) + +#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) +#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_AUD_DAT_MISO (MTK_PIN_NO(39) | 1) +#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_ADC_DAT_IN (MTK_PIN_NO(39) | 2) +#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_AUD_DAT_MOSI (MTK_PIN_NO(39) | 3) +#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_EINT20 (MTK_PIN_NO(39) | 4) +#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_USB_TEST_IO_8 (MTK_PIN_NO(39) | 5) +#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_TESTA_OUT21 (MTK_PIN_NO(39) | 7) + +#define MT8135_PIN_40_DAC_CLK__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) +#define MT8135_PIN_40_DAC_CLK__FUNC_DAC_CK (MTK_PIN_NO(40) | 1) +#define MT8135_PIN_40_DAC_CLK__FUNC_EINT22 (MTK_PIN_NO(40) | 2) +#define MT8135_PIN_40_DAC_CLK__FUNC_HDMI_SDATA1 (MTK_PIN_NO(40) | 3) +#define MT8135_PIN_40_DAC_CLK__FUNC_USB_TEST_IO_9 (MTK_PIN_NO(40) | 5) +#define MT8135_PIN_40_DAC_CLK__FUNC_TESTA_OUT22 (MTK_PIN_NO(40) | 7) + +#define MT8135_PIN_41_DAC_WS__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) +#define MT8135_PIN_41_DAC_WS__FUNC_DAC_WS (MTK_PIN_NO(41) | 1) +#define MT8135_PIN_41_DAC_WS__FUNC_EINT24 (MTK_PIN_NO(41) | 2) +#define MT8135_PIN_41_DAC_WS__FUNC_HDMI_SDATA2 (MTK_PIN_NO(41) | 3) +#define MT8135_PIN_41_DAC_WS__FUNC_USB_TEST_IO_10 (MTK_PIN_NO(41) | 5) +#define MT8135_PIN_41_DAC_WS__FUNC_TESTA_OUT23 (MTK_PIN_NO(41) | 7) + +#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) +#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_DAC_DAT_OUT (MTK_PIN_NO(42) | 1) +#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_EINT23 (MTK_PIN_NO(42) | 2) +#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_HDMI_SDATA3 (MTK_PIN_NO(42) | 3) +#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_USB_TEST_IO_11 (MTK_PIN_NO(42) | 5) +#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_TESTA_OUT24 (MTK_PIN_NO(42) | 7) + +#define MT8135_PIN_43_PWRAP_SPI0_MO__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) +#define MT8135_PIN_43_PWRAP_SPI0_MO__FUNC_PWRAP_SPIDI (MTK_PIN_NO(43) | 1) +#define MT8135_PIN_43_PWRAP_SPI0_MO__FUNC_EINT29 (MTK_PIN_NO(43) | 2) + +#define MT8135_PIN_44_PWRAP_SPI0_MI__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) +#define MT8135_PIN_44_PWRAP_SPI0_MI__FUNC_PWRAP_SPIDO (MTK_PIN_NO(44) | 1) +#define MT8135_PIN_44_PWRAP_SPI0_MI__FUNC_EINT28 (MTK_PIN_NO(44) | 2) + +#define MT8135_PIN_45_PWRAP_SPI0_CSN__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) +#define MT8135_PIN_45_PWRAP_SPI0_CSN__FUNC_PWRAP_SPICS_B_I (MTK_PIN_NO(45) | 1) +#define MT8135_PIN_45_PWRAP_SPI0_CSN__FUNC_EINT27 (MTK_PIN_NO(45) | 2) + +#define MT8135_PIN_46_PWRAP_SPI0_CLK__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) +#define MT8135_PIN_46_PWRAP_SPI0_CLK__FUNC_PWRAP_SPICK_I (MTK_PIN_NO(46) | 1) +#define MT8135_PIN_46_PWRAP_SPI0_CLK__FUNC_EINT26 (MTK_PIN_NO(46) | 2) + +#define MT8135_PIN_47_PWRAP_EVENT__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) +#define MT8135_PIN_47_PWRAP_EVENT__FUNC_PWRAP_EVENT_IN (MTK_PIN_NO(47) | 1) +#define MT8135_PIN_47_PWRAP_EVENT__FUNC_EINT25 (MTK_PIN_NO(47) | 2) +#define MT8135_PIN_47_PWRAP_EVENT__FUNC_TESTA_OUT2 (MTK_PIN_NO(47) | 7) + +#define MT8135_PIN_48_RTC32K_CK__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) +#define MT8135_PIN_48_RTC32K_CK__FUNC_RTC32K_CK (MTK_PIN_NO(48) | 1) + +#define MT8135_PIN_49_WATCHDOG__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) +#define MT8135_PIN_49_WATCHDOG__FUNC_WATCHDOG (MTK_PIN_NO(49) | 1) +#define MT8135_PIN_49_WATCHDOG__FUNC_EINT36 (MTK_PIN_NO(49) | 2) + +#define MT8135_PIN_50_SRCLKENA__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) +#define MT8135_PIN_50_SRCLKENA__FUNC_SRCLKENA (MTK_PIN_NO(50) | 1) +#define MT8135_PIN_50_SRCLKENA__FUNC_EINT38 (MTK_PIN_NO(50) | 2) + +#define MT8135_PIN_51_SRCVOLTEN__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) +#define MT8135_PIN_51_SRCVOLTEN__FUNC_SRCVOLTEN (MTK_PIN_NO(51) | 1) +#define MT8135_PIN_51_SRCVOLTEN__FUNC_EINT37 (MTK_PIN_NO(51) | 2) + +#define MT8135_PIN_52_EINT0__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) +#define MT8135_PIN_52_EINT0__FUNC_EINT0 (MTK_PIN_NO(52) | 1) +#define MT8135_PIN_52_EINT0__FUNC_PWM1 (MTK_PIN_NO(52) | 2) +#define MT8135_PIN_52_EINT0__FUNC_CLKM0 (MTK_PIN_NO(52) | 3) +#define MT8135_PIN_52_EINT0__FUNC_SPDIF_OUT (MTK_PIN_NO(52) | 4) +#define MT8135_PIN_52_EINT0__FUNC_USB_TEST_IO_12 (MTK_PIN_NO(52) | 5) +#define MT8135_PIN_52_EINT0__FUNC_USB_SCL (MTK_PIN_NO(52) | 7) + +#define MT8135_PIN_53_URXD2__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) +#define MT8135_PIN_53_URXD2__FUNC_URXD2 (MTK_PIN_NO(53) | 1) +#define MT8135_PIN_53_URXD2__FUNC_EINT83 (MTK_PIN_NO(53) | 2) +#define MT8135_PIN_53_URXD2__FUNC_HDMI_LRCK (MTK_PIN_NO(53) | 4) +#define MT8135_PIN_53_URXD2__FUNC_CLKM3 (MTK_PIN_NO(53) | 5) +#define MT8135_PIN_53_URXD2__FUNC_UTXD2 (MTK_PIN_NO(53) | 7) + +#define MT8135_PIN_54_UTXD2__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) +#define MT8135_PIN_54_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(54) | 1) +#define MT8135_PIN_54_UTXD2__FUNC_EINT82 (MTK_PIN_NO(54) | 2) +#define MT8135_PIN_54_UTXD2__FUNC_HDMI_BCK_OUT (MTK_PIN_NO(54) | 4) +#define MT8135_PIN_54_UTXD2__FUNC_CLKM2 (MTK_PIN_NO(54) | 5) +#define MT8135_PIN_54_UTXD2__FUNC_URXD2 (MTK_PIN_NO(54) | 7) + +#define MT8135_PIN_55_UCTS2__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) +#define MT8135_PIN_55_UCTS2__FUNC_UCTS2 (MTK_PIN_NO(55) | 1) +#define MT8135_PIN_55_UCTS2__FUNC_EINT84 (MTK_PIN_NO(55) | 2) +#define MT8135_PIN_55_UCTS2__FUNC_PWM1 (MTK_PIN_NO(55) | 5) +#define MT8135_PIN_55_UCTS2__FUNC_URTS2 (MTK_PIN_NO(55) | 7) + +#define MT8135_PIN_56_URTS2__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) +#define MT8135_PIN_56_URTS2__FUNC_URTS2 (MTK_PIN_NO(56) | 1) +#define MT8135_PIN_56_URTS2__FUNC_EINT85 (MTK_PIN_NO(56) | 2) +#define MT8135_PIN_56_URTS2__FUNC_PWM2 (MTK_PIN_NO(56) | 5) +#define MT8135_PIN_56_URTS2__FUNC_UCTS2 (MTK_PIN_NO(56) | 7) + +#define MT8135_PIN_57_JTCK__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) +#define MT8135_PIN_57_JTCK__FUNC_JTCK (MTK_PIN_NO(57) | 1) +#define MT8135_PIN_57_JTCK__FUNC_EINT188 (MTK_PIN_NO(57) | 2) +#define MT8135_PIN_57_JTCK__FUNC_DSP1_ICK (MTK_PIN_NO(57) | 3) + +#define MT8135_PIN_58_JTDO__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) +#define MT8135_PIN_58_JTDO__FUNC_JTDO (MTK_PIN_NO(58) | 1) +#define MT8135_PIN_58_JTDO__FUNC_EINT190 (MTK_PIN_NO(58) | 2) +#define MT8135_PIN_58_JTDO__FUNC_DSP2_IMS (MTK_PIN_NO(58) | 3) + +#define MT8135_PIN_59_JTRST_B__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) +#define MT8135_PIN_59_JTRST_B__FUNC_JTRST_B (MTK_PIN_NO(59) | 1) +#define MT8135_PIN_59_JTRST_B__FUNC_EINT0 (MTK_PIN_NO(59) | 2) +#define MT8135_PIN_59_JTRST_B__FUNC_DSP2_ICK (MTK_PIN_NO(59) | 3) + +#define MT8135_PIN_60_JTDI__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) +#define MT8135_PIN_60_JTDI__FUNC_JTDI (MTK_PIN_NO(60) | 1) +#define MT8135_PIN_60_JTDI__FUNC_EINT189 (MTK_PIN_NO(60) | 2) +#define MT8135_PIN_60_JTDI__FUNC_DSP1_IMS (MTK_PIN_NO(60) | 3) + +#define MT8135_PIN_61_JRTCK__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) +#define MT8135_PIN_61_JRTCK__FUNC_JRTCK (MTK_PIN_NO(61) | 1) +#define MT8135_PIN_61_JRTCK__FUNC_EINT187 (MTK_PIN_NO(61) | 2) +#define MT8135_PIN_61_JRTCK__FUNC_DSP1_ID (MTK_PIN_NO(61) | 3) + +#define MT8135_PIN_62_JTMS__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) +#define MT8135_PIN_62_JTMS__FUNC_JTMS (MTK_PIN_NO(62) | 1) +#define MT8135_PIN_62_JTMS__FUNC_EINT191 (MTK_PIN_NO(62) | 2) +#define MT8135_PIN_62_JTMS__FUNC_DSP2_ID (MTK_PIN_NO(62) | 3) + +#define MT8135_PIN_63_MSDC1_INSI__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) +#define MT8135_PIN_63_MSDC1_INSI__FUNC_MSDC1_INSI (MTK_PIN_NO(63) | 1) +#define MT8135_PIN_63_MSDC1_INSI__FUNC_SCL5 (MTK_PIN_NO(63) | 3) +#define MT8135_PIN_63_MSDC1_INSI__FUNC_PWM6 (MTK_PIN_NO(63) | 4) +#define MT8135_PIN_63_MSDC1_INSI__FUNC_CLKM5 (MTK_PIN_NO(63) | 5) +#define MT8135_PIN_63_MSDC1_INSI__FUNC_TESTB_OUT6 (MTK_PIN_NO(63) | 7) + +#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) +#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_MSDC1_SDWPI (MTK_PIN_NO(64) | 1) +#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_EINT58 (MTK_PIN_NO(64) | 2) +#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_SDA5 (MTK_PIN_NO(64) | 3) +#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_PWM7 (MTK_PIN_NO(64) | 4) +#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_CLKM6 (MTK_PIN_NO(64) | 5) +#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_TESTB_OUT7 (MTK_PIN_NO(64) | 7) + +#define MT8135_PIN_65_MSDC2_INSI__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) +#define MT8135_PIN_65_MSDC2_INSI__FUNC_MSDC2_INSI (MTK_PIN_NO(65) | 1) +#define MT8135_PIN_65_MSDC2_INSI__FUNC_USB_TEST_IO_27 (MTK_PIN_NO(65) | 5) +#define MT8135_PIN_65_MSDC2_INSI__FUNC_TESTA_OUT3 (MTK_PIN_NO(65) | 7) + +#define MT8135_PIN_66_MSDC2_SDWPI__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) +#define MT8135_PIN_66_MSDC2_SDWPI__FUNC_MSDC2_SDWPI (MTK_PIN_NO(66) | 1) +#define MT8135_PIN_66_MSDC2_SDWPI__FUNC_EINT66 (MTK_PIN_NO(66) | 2) +#define MT8135_PIN_66_MSDC2_SDWPI__FUNC_USB_TEST_IO_28 (MTK_PIN_NO(66) | 5) + +#define MT8135_PIN_67_URXD4__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) +#define MT8135_PIN_67_URXD4__FUNC_URXD4 (MTK_PIN_NO(67) | 1) +#define MT8135_PIN_67_URXD4__FUNC_EINT89 (MTK_PIN_NO(67) | 2) +#define MT8135_PIN_67_URXD4__FUNC_URXD1 (MTK_PIN_NO(67) | 3) +#define MT8135_PIN_67_URXD4__FUNC_UTXD4 (MTK_PIN_NO(67) | 6) +#define MT8135_PIN_67_URXD4__FUNC_TESTB_OUT10 (MTK_PIN_NO(67) | 7) + +#define MT8135_PIN_68_UTXD4__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) +#define MT8135_PIN_68_UTXD4__FUNC_UTXD4 (MTK_PIN_NO(68) | 1) +#define MT8135_PIN_68_UTXD4__FUNC_EINT88 (MTK_PIN_NO(68) | 2) +#define MT8135_PIN_68_UTXD4__FUNC_UTXD1 (MTK_PIN_NO(68) | 3) +#define MT8135_PIN_68_UTXD4__FUNC_URXD4 (MTK_PIN_NO(68) | 6) +#define MT8135_PIN_68_UTXD4__FUNC_TESTB_OUT11 (MTK_PIN_NO(68) | 7) + +#define MT8135_PIN_69_URXD1__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) +#define MT8135_PIN_69_URXD1__FUNC_URXD1 (MTK_PIN_NO(69) | 1) +#define MT8135_PIN_69_URXD1__FUNC_EINT79 (MTK_PIN_NO(69) | 2) +#define MT8135_PIN_69_URXD1__FUNC_URXD4 (MTK_PIN_NO(69) | 3) +#define MT8135_PIN_69_URXD1__FUNC_UTXD1 (MTK_PIN_NO(69) | 6) +#define MT8135_PIN_69_URXD1__FUNC_TESTB_OUT24 (MTK_PIN_NO(69) | 7) + +#define MT8135_PIN_70_UTXD1__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) +#define MT8135_PIN_70_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(70) | 1) +#define MT8135_PIN_70_UTXD1__FUNC_EINT78 (MTK_PIN_NO(70) | 2) +#define MT8135_PIN_70_UTXD1__FUNC_UTXD4 (MTK_PIN_NO(70) | 3) +#define MT8135_PIN_70_UTXD1__FUNC_URXD1 (MTK_PIN_NO(70) | 6) +#define MT8135_PIN_70_UTXD1__FUNC_TESTB_OUT25 (MTK_PIN_NO(70) | 7) + +#define MT8135_PIN_71_UCTS1__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) +#define MT8135_PIN_71_UCTS1__FUNC_UCTS1 (MTK_PIN_NO(71) | 1) +#define MT8135_PIN_71_UCTS1__FUNC_EINT80 (MTK_PIN_NO(71) | 2) +#define MT8135_PIN_71_UCTS1__FUNC_CLKM0 (MTK_PIN_NO(71) | 5) +#define MT8135_PIN_71_UCTS1__FUNC_URTS1 (MTK_PIN_NO(71) | 6) +#define MT8135_PIN_71_UCTS1__FUNC_TESTB_OUT31 (MTK_PIN_NO(71) | 7) + +#define MT8135_PIN_72_URTS1__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) +#define MT8135_PIN_72_URTS1__FUNC_URTS1 (MTK_PIN_NO(72) | 1) +#define MT8135_PIN_72_URTS1__FUNC_EINT81 (MTK_PIN_NO(72) | 2) +#define MT8135_PIN_72_URTS1__FUNC_CLKM1 (MTK_PIN_NO(72) | 5) +#define MT8135_PIN_72_URTS1__FUNC_UCTS1 (MTK_PIN_NO(72) | 6) +#define MT8135_PIN_72_URTS1__FUNC_TESTB_OUT21 (MTK_PIN_NO(72) | 7) + +#define MT8135_PIN_73_PWM1__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) +#define MT8135_PIN_73_PWM1__FUNC_PWM1 (MTK_PIN_NO(73) | 1) +#define MT8135_PIN_73_PWM1__FUNC_EINT73 (MTK_PIN_NO(73) | 2) +#define MT8135_PIN_73_PWM1__FUNC_USB_DRVVBUS (MTK_PIN_NO(73) | 5) +#define MT8135_PIN_73_PWM1__FUNC_DISP_PWM (MTK_PIN_NO(73) | 6) +#define MT8135_PIN_73_PWM1__FUNC_TESTB_OUT8 (MTK_PIN_NO(73) | 7) + +#define MT8135_PIN_74_PWM2__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) +#define MT8135_PIN_74_PWM2__FUNC_PWM2 (MTK_PIN_NO(74) | 1) +#define MT8135_PIN_74_PWM2__FUNC_EINT74 (MTK_PIN_NO(74) | 2) +#define MT8135_PIN_74_PWM2__FUNC_DPI33_CK (MTK_PIN_NO(74) | 3) +#define MT8135_PIN_74_PWM2__FUNC_PWM5 (MTK_PIN_NO(74) | 4) +#define MT8135_PIN_74_PWM2__FUNC_URXD2 (MTK_PIN_NO(74) | 5) +#define MT8135_PIN_74_PWM2__FUNC_DISP_PWM (MTK_PIN_NO(74) | 6) +#define MT8135_PIN_74_PWM2__FUNC_TESTB_OUT9 (MTK_PIN_NO(74) | 7) + +#define MT8135_PIN_75_PWM3__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) +#define MT8135_PIN_75_PWM3__FUNC_PWM3 (MTK_PIN_NO(75) | 1) +#define MT8135_PIN_75_PWM3__FUNC_EINT75 (MTK_PIN_NO(75) | 2) +#define MT8135_PIN_75_PWM3__FUNC_DPI33_D0 (MTK_PIN_NO(75) | 3) +#define MT8135_PIN_75_PWM3__FUNC_PWM6 (MTK_PIN_NO(75) | 4) +#define MT8135_PIN_75_PWM3__FUNC_UTXD2 (MTK_PIN_NO(75) | 5) +#define MT8135_PIN_75_PWM3__FUNC_DISP_PWM (MTK_PIN_NO(75) | 6) +#define MT8135_PIN_75_PWM3__FUNC_TESTB_OUT12 (MTK_PIN_NO(75) | 7) + +#define MT8135_PIN_76_PWM4__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) +#define MT8135_PIN_76_PWM4__FUNC_PWM4 (MTK_PIN_NO(76) | 1) +#define MT8135_PIN_76_PWM4__FUNC_EINT76 (MTK_PIN_NO(76) | 2) +#define MT8135_PIN_76_PWM4__FUNC_DPI33_D1 (MTK_PIN_NO(76) | 3) +#define MT8135_PIN_76_PWM4__FUNC_PWM7 (MTK_PIN_NO(76) | 4) +#define MT8135_PIN_76_PWM4__FUNC_DISP_PWM (MTK_PIN_NO(76) | 6) +#define MT8135_PIN_76_PWM4__FUNC_TESTB_OUT13 (MTK_PIN_NO(76) | 7) + +#define MT8135_PIN_77_MSDC2_DAT2__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) +#define MT8135_PIN_77_MSDC2_DAT2__FUNC_MSDC2_DAT2 (MTK_PIN_NO(77) | 1) +#define MT8135_PIN_77_MSDC2_DAT2__FUNC_EINT63 (MTK_PIN_NO(77) | 2) +#define MT8135_PIN_77_MSDC2_DAT2__FUNC_DSP2_IMS (MTK_PIN_NO(77) | 4) +#define MT8135_PIN_77_MSDC2_DAT2__FUNC_DPI33_D6 (MTK_PIN_NO(77) | 6) +#define MT8135_PIN_77_MSDC2_DAT2__FUNC_TESTA_OUT25 (MTK_PIN_NO(77) | 7) + +#define MT8135_PIN_78_MSDC2_DAT3__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) +#define MT8135_PIN_78_MSDC2_DAT3__FUNC_MSDC2_DAT3 (MTK_PIN_NO(78) | 1) +#define MT8135_PIN_78_MSDC2_DAT3__FUNC_EINT64 (MTK_PIN_NO(78) | 2) +#define MT8135_PIN_78_MSDC2_DAT3__FUNC_DSP2_ID (MTK_PIN_NO(78) | 4) +#define MT8135_PIN_78_MSDC2_DAT3__FUNC_DPI33_D7 (MTK_PIN_NO(78) | 6) +#define MT8135_PIN_78_MSDC2_DAT3__FUNC_TESTA_OUT26 (MTK_PIN_NO(78) | 7) + +#define MT8135_PIN_79_MSDC2_CMD__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) +#define MT8135_PIN_79_MSDC2_CMD__FUNC_MSDC2_CMD (MTK_PIN_NO(79) | 1) +#define MT8135_PIN_79_MSDC2_CMD__FUNC_EINT60 (MTK_PIN_NO(79) | 2) +#define MT8135_PIN_79_MSDC2_CMD__FUNC_DSP1_IMS (MTK_PIN_NO(79) | 4) +#define MT8135_PIN_79_MSDC2_CMD__FUNC_PCM1_WS (MTK_PIN_NO(79) | 5) +#define MT8135_PIN_79_MSDC2_CMD__FUNC_DPI33_D3 (MTK_PIN_NO(79) | 6) +#define MT8135_PIN_79_MSDC2_CMD__FUNC_TESTA_OUT0 (MTK_PIN_NO(79) | 7) + +#define MT8135_PIN_80_MSDC2_CLK__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) +#define MT8135_PIN_80_MSDC2_CLK__FUNC_MSDC2_CLK (MTK_PIN_NO(80) | 1) +#define MT8135_PIN_80_MSDC2_CLK__FUNC_EINT59 (MTK_PIN_NO(80) | 2) +#define MT8135_PIN_80_MSDC2_CLK__FUNC_DSP1_ICK (MTK_PIN_NO(80) | 4) +#define MT8135_PIN_80_MSDC2_CLK__FUNC_PCM1_CK (MTK_PIN_NO(80) | 5) +#define MT8135_PIN_80_MSDC2_CLK__FUNC_DPI33_D2 (MTK_PIN_NO(80) | 6) +#define MT8135_PIN_80_MSDC2_CLK__FUNC_TESTA_OUT1 (MTK_PIN_NO(80) | 7) + +#define MT8135_PIN_81_MSDC2_DAT1__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) +#define MT8135_PIN_81_MSDC2_DAT1__FUNC_MSDC2_DAT1 (MTK_PIN_NO(81) | 1) +#define MT8135_PIN_81_MSDC2_DAT1__FUNC_EINT62 (MTK_PIN_NO(81) | 2) +#define MT8135_PIN_81_MSDC2_DAT1__FUNC_DSP2_ICK (MTK_PIN_NO(81) | 4) +#define MT8135_PIN_81_MSDC2_DAT1__FUNC_PCM1_DO (MTK_PIN_NO(81) | 5) +#define MT8135_PIN_81_MSDC2_DAT1__FUNC_DPI33_D5 (MTK_PIN_NO(81) | 6) + +#define MT8135_PIN_82_MSDC2_DAT0__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) +#define MT8135_PIN_82_MSDC2_DAT0__FUNC_MSDC2_DAT0 (MTK_PIN_NO(82) | 1) +#define MT8135_PIN_82_MSDC2_DAT0__FUNC_EINT61 (MTK_PIN_NO(82) | 2) +#define MT8135_PIN_82_MSDC2_DAT0__FUNC_DSP1_ID (MTK_PIN_NO(82) | 4) +#define MT8135_PIN_82_MSDC2_DAT0__FUNC_PCM1_DI (MTK_PIN_NO(82) | 5) +#define MT8135_PIN_82_MSDC2_DAT0__FUNC_DPI33_D4 (MTK_PIN_NO(82) | 6) + +#define MT8135_PIN_83_MSDC1_DAT0__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) +#define MT8135_PIN_83_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(83) | 1) +#define MT8135_PIN_83_MSDC1_DAT0__FUNC_EINT53 (MTK_PIN_NO(83) | 2) +#define MT8135_PIN_83_MSDC1_DAT0__FUNC_SCL1 (MTK_PIN_NO(83) | 3) +#define MT8135_PIN_83_MSDC1_DAT0__FUNC_PWM2 (MTK_PIN_NO(83) | 4) +#define MT8135_PIN_83_MSDC1_DAT0__FUNC_CLKM1 (MTK_PIN_NO(83) | 5) +#define MT8135_PIN_83_MSDC1_DAT0__FUNC_TESTB_OUT2 (MTK_PIN_NO(83) | 7) + +#define MT8135_PIN_84_MSDC1_DAT1__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) +#define MT8135_PIN_84_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(84) | 1) +#define MT8135_PIN_84_MSDC1_DAT1__FUNC_EINT54 (MTK_PIN_NO(84) | 2) +#define MT8135_PIN_84_MSDC1_DAT1__FUNC_SDA1 (MTK_PIN_NO(84) | 3) +#define MT8135_PIN_84_MSDC1_DAT1__FUNC_PWM3 (MTK_PIN_NO(84) | 4) +#define MT8135_PIN_84_MSDC1_DAT1__FUNC_CLKM2 (MTK_PIN_NO(84) | 5) +#define MT8135_PIN_84_MSDC1_DAT1__FUNC_TESTB_OUT3 (MTK_PIN_NO(84) | 7) + +#define MT8135_PIN_85_MSDC1_CMD__FUNC_GPIO85 (MTK_PIN_NO(85) | 0) +#define MT8135_PIN_85_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(85) | 1) +#define MT8135_PIN_85_MSDC1_CMD__FUNC_EINT52 (MTK_PIN_NO(85) | 2) +#define MT8135_PIN_85_MSDC1_CMD__FUNC_SDA0 (MTK_PIN_NO(85) | 3) +#define MT8135_PIN_85_MSDC1_CMD__FUNC_PWM1 (MTK_PIN_NO(85) | 4) +#define MT8135_PIN_85_MSDC1_CMD__FUNC_CLKM0 (MTK_PIN_NO(85) | 5) +#define MT8135_PIN_85_MSDC1_CMD__FUNC_TESTB_OUT1 (MTK_PIN_NO(85) | 7) + +#define MT8135_PIN_86_MSDC1_CLK__FUNC_GPIO86 (MTK_PIN_NO(86) | 0) +#define MT8135_PIN_86_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(86) | 1) +#define MT8135_PIN_86_MSDC1_CLK__FUNC_EINT51 (MTK_PIN_NO(86) | 2) +#define MT8135_PIN_86_MSDC1_CLK__FUNC_SCL0 (MTK_PIN_NO(86) | 3) +#define MT8135_PIN_86_MSDC1_CLK__FUNC_DISP_PWM (MTK_PIN_NO(86) | 4) +#define MT8135_PIN_86_MSDC1_CLK__FUNC_TESTB_OUT0 (MTK_PIN_NO(86) | 7) + +#define MT8135_PIN_87_MSDC1_DAT2__FUNC_GPIO87 (MTK_PIN_NO(87) | 0) +#define MT8135_PIN_87_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(87) | 1) +#define MT8135_PIN_87_MSDC1_DAT2__FUNC_EINT55 (MTK_PIN_NO(87) | 2) +#define MT8135_PIN_87_MSDC1_DAT2__FUNC_SCL4 (MTK_PIN_NO(87) | 3) +#define MT8135_PIN_87_MSDC1_DAT2__FUNC_PWM4 (MTK_PIN_NO(87) | 4) +#define MT8135_PIN_87_MSDC1_DAT2__FUNC_CLKM3 (MTK_PIN_NO(87) | 5) +#define MT8135_PIN_87_MSDC1_DAT2__FUNC_TESTB_OUT4 (MTK_PIN_NO(87) | 7) + +#define MT8135_PIN_88_MSDC1_DAT3__FUNC_GPIO88 (MTK_PIN_NO(88) | 0) +#define MT8135_PIN_88_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(88) | 1) +#define MT8135_PIN_88_MSDC1_DAT3__FUNC_EINT56 (MTK_PIN_NO(88) | 2) +#define MT8135_PIN_88_MSDC1_DAT3__FUNC_SDA4 (MTK_PIN_NO(88) | 3) +#define MT8135_PIN_88_MSDC1_DAT3__FUNC_PWM5 (MTK_PIN_NO(88) | 4) +#define MT8135_PIN_88_MSDC1_DAT3__FUNC_CLKM4 (MTK_PIN_NO(88) | 5) +#define MT8135_PIN_88_MSDC1_DAT3__FUNC_TESTB_OUT5 (MTK_PIN_NO(88) | 7) + +#define MT8135_PIN_89_MSDC4_DAT0__FUNC_GPIO89 (MTK_PIN_NO(89) | 0) +#define MT8135_PIN_89_MSDC4_DAT0__FUNC_MSDC4_DAT0 (MTK_PIN_NO(89) | 1) +#define MT8135_PIN_89_MSDC4_DAT0__FUNC_EINT133 (MTK_PIN_NO(89) | 2) +#define MT8135_PIN_89_MSDC4_DAT0__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(89) | 4) +#define MT8135_PIN_89_MSDC4_DAT0__FUNC_USB_DRVVBUS (MTK_PIN_NO(89) | 5) +#define MT8135_PIN_89_MSDC4_DAT0__FUNC_A_FUNC_DIN_9 (MTK_PIN_NO(89) | 6) +#define MT8135_PIN_89_MSDC4_DAT0__FUNC_LPTE (MTK_PIN_NO(89) | 7) + +#define MT8135_PIN_90_MSDC4_DAT1__FUNC_GPIO90 (MTK_PIN_NO(90) | 0) +#define MT8135_PIN_90_MSDC4_DAT1__FUNC_MSDC4_DAT1 (MTK_PIN_NO(90) | 1) +#define MT8135_PIN_90_MSDC4_DAT1__FUNC_EINT134 (MTK_PIN_NO(90) | 2) +#define MT8135_PIN_90_MSDC4_DAT1__FUNC_A_FUNC_DIN_10 (MTK_PIN_NO(90) | 6) +#define MT8135_PIN_90_MSDC4_DAT1__FUNC_LRSTB_1X (MTK_PIN_NO(90) | 7) + +#define MT8135_PIN_91_MSDC4_DAT5__FUNC_GPIO91 (MTK_PIN_NO(91) | 0) +#define MT8135_PIN_91_MSDC4_DAT5__FUNC_MSDC4_DAT5 (MTK_PIN_NO(91) | 1) +#define MT8135_PIN_91_MSDC4_DAT5__FUNC_EINT136 (MTK_PIN_NO(91) | 2) +#define MT8135_PIN_91_MSDC4_DAT5__FUNC_I2SIN_WS (MTK_PIN_NO(91) | 3) +#define MT8135_PIN_91_MSDC4_DAT5__FUNC_DAC_WS (MTK_PIN_NO(91) | 4) +#define MT8135_PIN_91_MSDC4_DAT5__FUNC_PCM1_WS (MTK_PIN_NO(91) | 5) +#define MT8135_PIN_91_MSDC4_DAT5__FUNC_A_FUNC_DIN_11 (MTK_PIN_NO(91) | 6) +#define MT8135_PIN_91_MSDC4_DAT5__FUNC_SPI1_CSN (MTK_PIN_NO(91) | 7) + +#define MT8135_PIN_92_MSDC4_DAT6__FUNC_GPIO92 (MTK_PIN_NO(92) | 0) +#define MT8135_PIN_92_MSDC4_DAT6__FUNC_MSDC4_DAT6 (MTK_PIN_NO(92) | 1) +#define MT8135_PIN_92_MSDC4_DAT6__FUNC_EINT137 (MTK_PIN_NO(92) | 2) +#define MT8135_PIN_92_MSDC4_DAT6__FUNC_I2SOUT_DAT (MTK_PIN_NO(92) | 3) +#define MT8135_PIN_92_MSDC4_DAT6__FUNC_DAC_DAT_OUT (MTK_PIN_NO(92) | 4) +#define MT8135_PIN_92_MSDC4_DAT6__FUNC_PCM1_DO (MTK_PIN_NO(92) | 5) +#define MT8135_PIN_92_MSDC4_DAT6__FUNC_A_FUNC_DIN_12 (MTK_PIN_NO(92) | 6) +#define MT8135_PIN_92_MSDC4_DAT6__FUNC_SPI1_MO (MTK_PIN_NO(92) | 7) + +#define MT8135_PIN_93_MSDC4_DAT7__FUNC_GPIO93 (MTK_PIN_NO(93) | 0) +#define MT8135_PIN_93_MSDC4_DAT7__FUNC_MSDC4_DAT7 (MTK_PIN_NO(93) | 1) +#define MT8135_PIN_93_MSDC4_DAT7__FUNC_EINT138 (MTK_PIN_NO(93) | 2) +#define MT8135_PIN_93_MSDC4_DAT7__FUNC_I2SIN_DAT (MTK_PIN_NO(93) | 3) +#define MT8135_PIN_93_MSDC4_DAT7__FUNC_PCM1_DI (MTK_PIN_NO(93) | 5) +#define MT8135_PIN_93_MSDC4_DAT7__FUNC_A_FUNC_DIN_13 (MTK_PIN_NO(93) | 6) +#define MT8135_PIN_93_MSDC4_DAT7__FUNC_SPI1_MI (MTK_PIN_NO(93) | 7) + +#define MT8135_PIN_94_MSDC4_DAT4__FUNC_GPIO94 (MTK_PIN_NO(94) | 0) +#define MT8135_PIN_94_MSDC4_DAT4__FUNC_MSDC4_DAT4 (MTK_PIN_NO(94) | 1) +#define MT8135_PIN_94_MSDC4_DAT4__FUNC_EINT135 (MTK_PIN_NO(94) | 2) +#define MT8135_PIN_94_MSDC4_DAT4__FUNC_I2SIN_CK (MTK_PIN_NO(94) | 3) +#define MT8135_PIN_94_MSDC4_DAT4__FUNC_DAC_CK (MTK_PIN_NO(94) | 4) +#define MT8135_PIN_94_MSDC4_DAT4__FUNC_PCM1_CK (MTK_PIN_NO(94) | 5) +#define MT8135_PIN_94_MSDC4_DAT4__FUNC_A_FUNC_DIN_14 (MTK_PIN_NO(94) | 6) +#define MT8135_PIN_94_MSDC4_DAT4__FUNC_SPI1_CLK (MTK_PIN_NO(94) | 7) + +#define MT8135_PIN_95_MSDC4_DAT2__FUNC_GPIO95 (MTK_PIN_NO(95) | 0) +#define MT8135_PIN_95_MSDC4_DAT2__FUNC_MSDC4_DAT2 (MTK_PIN_NO(95) | 1) +#define MT8135_PIN_95_MSDC4_DAT2__FUNC_EINT131 (MTK_PIN_NO(95) | 2) +#define MT8135_PIN_95_MSDC4_DAT2__FUNC_I2SIN_WS (MTK_PIN_NO(95) | 3) +#define MT8135_PIN_95_MSDC4_DAT2__FUNC_CM2PDN_2X (MTK_PIN_NO(95) | 4) +#define MT8135_PIN_95_MSDC4_DAT2__FUNC_DAC_WS (MTK_PIN_NO(95) | 5) +#define MT8135_PIN_95_MSDC4_DAT2__FUNC_PCM1_WS (MTK_PIN_NO(95) | 6) +#define MT8135_PIN_95_MSDC4_DAT2__FUNC_LSCE0B_1X (MTK_PIN_NO(95) | 7) + +#define MT8135_PIN_96_MSDC4_CLK__FUNC_GPIO96 (MTK_PIN_NO(96) | 0) +#define MT8135_PIN_96_MSDC4_CLK__FUNC_MSDC4_CLK (MTK_PIN_NO(96) | 1) +#define MT8135_PIN_96_MSDC4_CLK__FUNC_EINT129 (MTK_PIN_NO(96) | 2) +#define MT8135_PIN_96_MSDC4_CLK__FUNC_DPI1_CK_2X (MTK_PIN_NO(96) | 3) +#define MT8135_PIN_96_MSDC4_CLK__FUNC_CM2PCLK_2X (MTK_PIN_NO(96) | 4) +#define MT8135_PIN_96_MSDC4_CLK__FUNC_PWM4 (MTK_PIN_NO(96) | 5) +#define MT8135_PIN_96_MSDC4_CLK__FUNC_PCM1_DI (MTK_PIN_NO(96) | 6) +#define MT8135_PIN_96_MSDC4_CLK__FUNC_LSCK_1X (MTK_PIN_NO(96) | 7) + +#define MT8135_PIN_97_MSDC4_DAT3__FUNC_GPIO97 (MTK_PIN_NO(97) | 0) +#define MT8135_PIN_97_MSDC4_DAT3__FUNC_MSDC4_DAT3 (MTK_PIN_NO(97) | 1) +#define MT8135_PIN_97_MSDC4_DAT3__FUNC_EINT132 (MTK_PIN_NO(97) | 2) +#define MT8135_PIN_97_MSDC4_DAT3__FUNC_I2SOUT_DAT (MTK_PIN_NO(97) | 3) +#define MT8135_PIN_97_MSDC4_DAT3__FUNC_CM2RST_2X (MTK_PIN_NO(97) | 4) +#define MT8135_PIN_97_MSDC4_DAT3__FUNC_DAC_DAT_OUT (MTK_PIN_NO(97) | 5) +#define MT8135_PIN_97_MSDC4_DAT3__FUNC_PCM1_DO (MTK_PIN_NO(97) | 6) +#define MT8135_PIN_97_MSDC4_DAT3__FUNC_LSCE1B_1X (MTK_PIN_NO(97) | 7) + +#define MT8135_PIN_98_MSDC4_CMD__FUNC_GPIO98 (MTK_PIN_NO(98) | 0) +#define MT8135_PIN_98_MSDC4_CMD__FUNC_MSDC4_CMD (MTK_PIN_NO(98) | 1) +#define MT8135_PIN_98_MSDC4_CMD__FUNC_EINT128 (MTK_PIN_NO(98) | 2) +#define MT8135_PIN_98_MSDC4_CMD__FUNC_DPI1_DE_2X (MTK_PIN_NO(98) | 3) +#define MT8135_PIN_98_MSDC4_CMD__FUNC_PWM3 (MTK_PIN_NO(98) | 5) +#define MT8135_PIN_98_MSDC4_CMD__FUNC_LSDA_1X (MTK_PIN_NO(98) | 7) + +#define MT8135_PIN_99_MSDC4_RSTB__FUNC_GPIO99 (MTK_PIN_NO(99) | 0) +#define MT8135_PIN_99_MSDC4_RSTB__FUNC_MSDC4_RSTB (MTK_PIN_NO(99) | 1) +#define MT8135_PIN_99_MSDC4_RSTB__FUNC_EINT130 (MTK_PIN_NO(99) | 2) +#define MT8135_PIN_99_MSDC4_RSTB__FUNC_I2SIN_CK (MTK_PIN_NO(99) | 3) +#define MT8135_PIN_99_MSDC4_RSTB__FUNC_CM2MCLK_2X (MTK_PIN_NO(99) | 4) +#define MT8135_PIN_99_MSDC4_RSTB__FUNC_DAC_CK (MTK_PIN_NO(99) | 5) +#define MT8135_PIN_99_MSDC4_RSTB__FUNC_PCM1_CK (MTK_PIN_NO(99) | 6) +#define MT8135_PIN_99_MSDC4_RSTB__FUNC_LSA0_1X (MTK_PIN_NO(99) | 7) + +#define MT8135_PIN_100_SDA0__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) +#define MT8135_PIN_100_SDA0__FUNC_SDA0 (MTK_PIN_NO(100) | 1) +#define MT8135_PIN_100_SDA0__FUNC_EINT91 (MTK_PIN_NO(100) | 2) +#define MT8135_PIN_100_SDA0__FUNC_CLKM1 (MTK_PIN_NO(100) | 3) +#define MT8135_PIN_100_SDA0__FUNC_PWM1 (MTK_PIN_NO(100) | 4) +#define MT8135_PIN_100_SDA0__FUNC_A_FUNC_DIN_15 (MTK_PIN_NO(100) | 7) + +#define MT8135_PIN_101_SCL0__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) +#define MT8135_PIN_101_SCL0__FUNC_SCL0 (MTK_PIN_NO(101) | 1) +#define MT8135_PIN_101_SCL0__FUNC_EINT90 (MTK_PIN_NO(101) | 2) +#define MT8135_PIN_101_SCL0__FUNC_CLKM0 (MTK_PIN_NO(101) | 3) +#define MT8135_PIN_101_SCL0__FUNC_DISP_PWM (MTK_PIN_NO(101) | 4) +#define MT8135_PIN_101_SCL0__FUNC_A_FUNC_DIN_16 (MTK_PIN_NO(101) | 7) + +#define MT8135_PIN_102_EINT10_AUXIN2__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) +#define MT8135_PIN_102_EINT10_AUXIN2__FUNC_EINT10 (MTK_PIN_NO(102) | 1) +#define MT8135_PIN_102_EINT10_AUXIN2__FUNC_USB_TEST_IO_16 (MTK_PIN_NO(102) | 5) +#define MT8135_PIN_102_EINT10_AUXIN2__FUNC_TESTB_OUT16 (MTK_PIN_NO(102) | 6) +#define MT8135_PIN_102_EINT10_AUXIN2__FUNC_A_FUNC_DIN_17 (MTK_PIN_NO(102) | 7) + +#define MT8135_PIN_103_EINT11_AUXIN3__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) +#define MT8135_PIN_103_EINT11_AUXIN3__FUNC_EINT11 (MTK_PIN_NO(103) | 1) +#define MT8135_PIN_103_EINT11_AUXIN3__FUNC_USB_TEST_IO_17 (MTK_PIN_NO(103) | 5) +#define MT8135_PIN_103_EINT11_AUXIN3__FUNC_TESTB_OUT17 (MTK_PIN_NO(103) | 6) +#define MT8135_PIN_103_EINT11_AUXIN3__FUNC_A_FUNC_DIN_18 (MTK_PIN_NO(103) | 7) + +#define MT8135_PIN_104_EINT16_AUXIN4__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) +#define MT8135_PIN_104_EINT16_AUXIN4__FUNC_EINT16 (MTK_PIN_NO(104) | 1) +#define MT8135_PIN_104_EINT16_AUXIN4__FUNC_USB_TEST_IO_18 (MTK_PIN_NO(104) | 5) +#define MT8135_PIN_104_EINT16_AUXIN4__FUNC_TESTB_OUT18 (MTK_PIN_NO(104) | 6) +#define MT8135_PIN_104_EINT16_AUXIN4__FUNC_A_FUNC_DIN_19 (MTK_PIN_NO(104) | 7) + +#define MT8135_PIN_105_I2S_CLK__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) +#define MT8135_PIN_105_I2S_CLK__FUNC_I2SIN_CK (MTK_PIN_NO(105) | 1) +#define MT8135_PIN_105_I2S_CLK__FUNC_EINT10 (MTK_PIN_NO(105) | 2) +#define MT8135_PIN_105_I2S_CLK__FUNC_DAC_CK (MTK_PIN_NO(105) | 3) +#define MT8135_PIN_105_I2S_CLK__FUNC_PCM1_CK (MTK_PIN_NO(105) | 4) +#define MT8135_PIN_105_I2S_CLK__FUNC_USB_TEST_IO_19 (MTK_PIN_NO(105) | 5) +#define MT8135_PIN_105_I2S_CLK__FUNC_TESTB_OUT19 (MTK_PIN_NO(105) | 6) +#define MT8135_PIN_105_I2S_CLK__FUNC_A_FUNC_DIN_20 (MTK_PIN_NO(105) | 7) + +#define MT8135_PIN_106_I2S_WS__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) +#define MT8135_PIN_106_I2S_WS__FUNC_I2SIN_WS (MTK_PIN_NO(106) | 1) +#define MT8135_PIN_106_I2S_WS__FUNC_EINT13 (MTK_PIN_NO(106) | 2) +#define MT8135_PIN_106_I2S_WS__FUNC_DAC_WS (MTK_PIN_NO(106) | 3) +#define MT8135_PIN_106_I2S_WS__FUNC_PCM1_WS (MTK_PIN_NO(106) | 4) +#define MT8135_PIN_106_I2S_WS__FUNC_USB_TEST_IO_20 (MTK_PIN_NO(106) | 5) +#define MT8135_PIN_106_I2S_WS__FUNC_TESTB_OUT20 (MTK_PIN_NO(106) | 6) +#define MT8135_PIN_106_I2S_WS__FUNC_A_FUNC_DIN_21 (MTK_PIN_NO(106) | 7) + +#define MT8135_PIN_107_I2S_DATA_IN__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) +#define MT8135_PIN_107_I2S_DATA_IN__FUNC_I2SIN_DAT (MTK_PIN_NO(107) | 1) +#define MT8135_PIN_107_I2S_DATA_IN__FUNC_EINT11 (MTK_PIN_NO(107) | 2) +#define MT8135_PIN_107_I2S_DATA_IN__FUNC_PCM1_DI (MTK_PIN_NO(107) | 4) +#define MT8135_PIN_107_I2S_DATA_IN__FUNC_USB_TEST_IO_21 (MTK_PIN_NO(107) | 5) +#define MT8135_PIN_107_I2S_DATA_IN__FUNC_TESTB_OUT22 (MTK_PIN_NO(107) | 6) +#define MT8135_PIN_107_I2S_DATA_IN__FUNC_A_FUNC_DIN_22 (MTK_PIN_NO(107) | 7) + +#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) +#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_I2SOUT_DAT (MTK_PIN_NO(108) | 1) +#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_EINT12 (MTK_PIN_NO(108) | 2) +#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_DAC_DAT_OUT (MTK_PIN_NO(108) | 3) +#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_PCM1_DO (MTK_PIN_NO(108) | 4) +#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_USB_TEST_IO_22 (MTK_PIN_NO(108) | 5) +#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_TESTB_OUT23 (MTK_PIN_NO(108) | 6) +#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_A_FUNC_DIN_23 (MTK_PIN_NO(108) | 7) + +#define MT8135_PIN_109_EINT5__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) +#define MT8135_PIN_109_EINT5__FUNC_EINT5 (MTK_PIN_NO(109) | 1) +#define MT8135_PIN_109_EINT5__FUNC_PWM5 (MTK_PIN_NO(109) | 2) +#define MT8135_PIN_109_EINT5__FUNC_CLKM3 (MTK_PIN_NO(109) | 3) +#define MT8135_PIN_109_EINT5__FUNC_GPU_JTRSTB (MTK_PIN_NO(109) | 4) +#define MT8135_PIN_109_EINT5__FUNC_USB_TEST_IO_23 (MTK_PIN_NO(109) | 5) +#define MT8135_PIN_109_EINT5__FUNC_TESTB_OUT26 (MTK_PIN_NO(109) | 6) +#define MT8135_PIN_109_EINT5__FUNC_A_FUNC_DIN_24 (MTK_PIN_NO(109) | 7) + +#define MT8135_PIN_110_EINT6__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) +#define MT8135_PIN_110_EINT6__FUNC_EINT6 (MTK_PIN_NO(110) | 1) +#define MT8135_PIN_110_EINT6__FUNC_PWM6 (MTK_PIN_NO(110) | 2) +#define MT8135_PIN_110_EINT6__FUNC_CLKM4 (MTK_PIN_NO(110) | 3) +#define MT8135_PIN_110_EINT6__FUNC_GPU_JTMS (MTK_PIN_NO(110) | 4) +#define MT8135_PIN_110_EINT6__FUNC_USB_TEST_IO_24 (MTK_PIN_NO(110) | 5) +#define MT8135_PIN_110_EINT6__FUNC_TESTB_OUT27 (MTK_PIN_NO(110) | 6) +#define MT8135_PIN_110_EINT6__FUNC_A_FUNC_DIN_25 (MTK_PIN_NO(110) | 7) + +#define MT8135_PIN_111_EINT7__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) +#define MT8135_PIN_111_EINT7__FUNC_EINT7 (MTK_PIN_NO(111) | 1) +#define MT8135_PIN_111_EINT7__FUNC_PWM7 (MTK_PIN_NO(111) | 2) +#define MT8135_PIN_111_EINT7__FUNC_CLKM5 (MTK_PIN_NO(111) | 3) +#define MT8135_PIN_111_EINT7__FUNC_GPU_JTDO (MTK_PIN_NO(111) | 4) +#define MT8135_PIN_111_EINT7__FUNC_USB_TEST_IO_25 (MTK_PIN_NO(111) | 5) +#define MT8135_PIN_111_EINT7__FUNC_TESTB_OUT28 (MTK_PIN_NO(111) | 6) +#define MT8135_PIN_111_EINT7__FUNC_A_FUNC_DIN_26 (MTK_PIN_NO(111) | 7) + +#define MT8135_PIN_112_EINT8__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) +#define MT8135_PIN_112_EINT8__FUNC_EINT8 (MTK_PIN_NO(112) | 1) +#define MT8135_PIN_112_EINT8__FUNC_DISP_PWM (MTK_PIN_NO(112) | 2) +#define MT8135_PIN_112_EINT8__FUNC_CLKM6 (MTK_PIN_NO(112) | 3) +#define MT8135_PIN_112_EINT8__FUNC_GPU_JTDI (MTK_PIN_NO(112) | 4) +#define MT8135_PIN_112_EINT8__FUNC_USB_TEST_IO_26 (MTK_PIN_NO(112) | 5) +#define MT8135_PIN_112_EINT8__FUNC_TESTB_OUT29 (MTK_PIN_NO(112) | 6) +#define MT8135_PIN_112_EINT8__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(112) | 7) + +#define MT8135_PIN_113_EINT9__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) +#define MT8135_PIN_113_EINT9__FUNC_EINT9 (MTK_PIN_NO(113) | 1) +#define MT8135_PIN_113_EINT9__FUNC_GPU_JTCK (MTK_PIN_NO(113) | 4) +#define MT8135_PIN_113_EINT9__FUNC_USB_DRVVBUS (MTK_PIN_NO(113) | 5) +#define MT8135_PIN_113_EINT9__FUNC_TESTB_OUT30 (MTK_PIN_NO(113) | 6) +#define MT8135_PIN_113_EINT9__FUNC_A_FUNC_DIN_27 (MTK_PIN_NO(113) | 7) + +#define MT8135_PIN_114_LPCE1B__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) +#define MT8135_PIN_114_LPCE1B__FUNC_LPCE1B (MTK_PIN_NO(114) | 1) +#define MT8135_PIN_114_LPCE1B__FUNC_EINT127 (MTK_PIN_NO(114) | 2) +#define MT8135_PIN_114_LPCE1B__FUNC_PWM2 (MTK_PIN_NO(114) | 5) +#define MT8135_PIN_114_LPCE1B__FUNC_TESTB_OUT14 (MTK_PIN_NO(114) | 6) +#define MT8135_PIN_114_LPCE1B__FUNC_A_FUNC_DIN_28 (MTK_PIN_NO(114) | 7) + +#define MT8135_PIN_115_LPCE0B__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) +#define MT8135_PIN_115_LPCE0B__FUNC_LPCE0B (MTK_PIN_NO(115) | 1) +#define MT8135_PIN_115_LPCE0B__FUNC_EINT126 (MTK_PIN_NO(115) | 2) +#define MT8135_PIN_115_LPCE0B__FUNC_PWM1 (MTK_PIN_NO(115) | 5) +#define MT8135_PIN_115_LPCE0B__FUNC_TESTB_OUT15 (MTK_PIN_NO(115) | 6) +#define MT8135_PIN_115_LPCE0B__FUNC_A_FUNC_DIN_29 (MTK_PIN_NO(115) | 7) + +#define MT8135_PIN_116_DISP_PWM__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) +#define MT8135_PIN_116_DISP_PWM__FUNC_DISP_PWM (MTK_PIN_NO(116) | 1) +#define MT8135_PIN_116_DISP_PWM__FUNC_EINT77 (MTK_PIN_NO(116) | 2) +#define MT8135_PIN_116_DISP_PWM__FUNC_LSDI (MTK_PIN_NO(116) | 3) +#define MT8135_PIN_116_DISP_PWM__FUNC_PWM1 (MTK_PIN_NO(116) | 4) +#define MT8135_PIN_116_DISP_PWM__FUNC_PWM2 (MTK_PIN_NO(116) | 5) +#define MT8135_PIN_116_DISP_PWM__FUNC_PWM3 (MTK_PIN_NO(116) | 7) + +#define MT8135_PIN_117_EINT1__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) +#define MT8135_PIN_117_EINT1__FUNC_EINT1 (MTK_PIN_NO(117) | 1) +#define MT8135_PIN_117_EINT1__FUNC_PWM2 (MTK_PIN_NO(117) | 2) +#define MT8135_PIN_117_EINT1__FUNC_CLKM1 (MTK_PIN_NO(117) | 3) +#define MT8135_PIN_117_EINT1__FUNC_USB_TEST_IO_13 (MTK_PIN_NO(117) | 5) +#define MT8135_PIN_117_EINT1__FUNC_USB_SDA (MTK_PIN_NO(117) | 7) + +#define MT8135_PIN_118_EINT2__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) +#define MT8135_PIN_118_EINT2__FUNC_EINT2 (MTK_PIN_NO(118) | 1) +#define MT8135_PIN_118_EINT2__FUNC_PWM3 (MTK_PIN_NO(118) | 2) +#define MT8135_PIN_118_EINT2__FUNC_CLKM2 (MTK_PIN_NO(118) | 3) +#define MT8135_PIN_118_EINT2__FUNC_USB_TEST_IO_14 (MTK_PIN_NO(118) | 5) +#define MT8135_PIN_118_EINT2__FUNC_SRCLKENAI2 (MTK_PIN_NO(118) | 6) +#define MT8135_PIN_118_EINT2__FUNC_A_FUNC_DIN_30 (MTK_PIN_NO(118) | 7) + +#define MT8135_PIN_119_EINT3__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) +#define MT8135_PIN_119_EINT3__FUNC_EINT3 (MTK_PIN_NO(119) | 1) +#define MT8135_PIN_119_EINT3__FUNC_USB_TEST_IO_15 (MTK_PIN_NO(119) | 5) +#define MT8135_PIN_119_EINT3__FUNC_SRCLKENAI1 (MTK_PIN_NO(119) | 6) +#define MT8135_PIN_119_EINT3__FUNC_EXT_26M_CK (MTK_PIN_NO(119) | 7) + +#define MT8135_PIN_120_EINT4__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) +#define MT8135_PIN_120_EINT4__FUNC_EINT4 (MTK_PIN_NO(120) | 1) +#define MT8135_PIN_120_EINT4__FUNC_PWM4 (MTK_PIN_NO(120) | 2) +#define MT8135_PIN_120_EINT4__FUNC_USB_DRVVBUS (MTK_PIN_NO(120) | 5) +#define MT8135_PIN_120_EINT4__FUNC_A_FUNC_DIN_31 (MTK_PIN_NO(120) | 7) + +#define MT8135_PIN_121_DPIDE__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) +#define MT8135_PIN_121_DPIDE__FUNC_DPI0_DE (MTK_PIN_NO(121) | 1) +#define MT8135_PIN_121_DPIDE__FUNC_EINT100 (MTK_PIN_NO(121) | 2) +#define MT8135_PIN_121_DPIDE__FUNC_I2SOUT_DAT (MTK_PIN_NO(121) | 3) +#define MT8135_PIN_121_DPIDE__FUNC_DAC_DAT_OUT (MTK_PIN_NO(121) | 4) +#define MT8135_PIN_121_DPIDE__FUNC_PCM1_DO (MTK_PIN_NO(121) | 5) +#define MT8135_PIN_121_DPIDE__FUNC_IRDA_TXD (MTK_PIN_NO(121) | 6) + +#define MT8135_PIN_122_DPICK__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) +#define MT8135_PIN_122_DPICK__FUNC_DPI0_CK (MTK_PIN_NO(122) | 1) +#define MT8135_PIN_122_DPICK__FUNC_EINT101 (MTK_PIN_NO(122) | 2) +#define MT8135_PIN_122_DPICK__FUNC_I2SIN_DAT (MTK_PIN_NO(122) | 3) +#define MT8135_PIN_122_DPICK__FUNC_PCM1_DI (MTK_PIN_NO(122) | 5) +#define MT8135_PIN_122_DPICK__FUNC_IRDA_PDN (MTK_PIN_NO(122) | 6) + +#define MT8135_PIN_123_DPIG4__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) +#define MT8135_PIN_123_DPIG4__FUNC_DPI0_G4 (MTK_PIN_NO(123) | 1) +#define MT8135_PIN_123_DPIG4__FUNC_EINT114 (MTK_PIN_NO(123) | 2) +#define MT8135_PIN_123_DPIG4__FUNC_CM2DAT_2X_0 (MTK_PIN_NO(123) | 4) +#define MT8135_PIN_123_DPIG4__FUNC_DSP2_ID (MTK_PIN_NO(123) | 5) + +#define MT8135_PIN_124_DPIG5__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) +#define MT8135_PIN_124_DPIG5__FUNC_DPI0_G5 (MTK_PIN_NO(124) | 1) +#define MT8135_PIN_124_DPIG5__FUNC_EINT115 (MTK_PIN_NO(124) | 2) +#define MT8135_PIN_124_DPIG5__FUNC_CM2DAT_2X_1 (MTK_PIN_NO(124) | 4) +#define MT8135_PIN_124_DPIG5__FUNC_DSP2_ICK (MTK_PIN_NO(124) | 5) + +#define MT8135_PIN_125_DPIR3__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) +#define MT8135_PIN_125_DPIR3__FUNC_DPI0_R3 (MTK_PIN_NO(125) | 1) +#define MT8135_PIN_125_DPIR3__FUNC_EINT121 (MTK_PIN_NO(125) | 2) +#define MT8135_PIN_125_DPIR3__FUNC_CM2DAT_2X_7 (MTK_PIN_NO(125) | 4) + +#define MT8135_PIN_126_DPIG1__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) +#define MT8135_PIN_126_DPIG1__FUNC_DPI0_G1 (MTK_PIN_NO(126) | 1) +#define MT8135_PIN_126_DPIG1__FUNC_EINT111 (MTK_PIN_NO(126) | 2) +#define MT8135_PIN_126_DPIG1__FUNC_DSP1_ICK (MTK_PIN_NO(126) | 5) + +#define MT8135_PIN_127_DPIVSYNC__FUNC_GPIO127 (MTK_PIN_NO(127) | 0) +#define MT8135_PIN_127_DPIVSYNC__FUNC_DPI0_VSYNC (MTK_PIN_NO(127) | 1) +#define MT8135_PIN_127_DPIVSYNC__FUNC_EINT98 (MTK_PIN_NO(127) | 2) +#define MT8135_PIN_127_DPIVSYNC__FUNC_I2SIN_CK (MTK_PIN_NO(127) | 3) +#define MT8135_PIN_127_DPIVSYNC__FUNC_DAC_CK (MTK_PIN_NO(127) | 4) +#define MT8135_PIN_127_DPIVSYNC__FUNC_PCM1_CK (MTK_PIN_NO(127) | 5) + +#define MT8135_PIN_128_DPIHSYNC__FUNC_GPIO128 (MTK_PIN_NO(128) | 0) +#define MT8135_PIN_128_DPIHSYNC__FUNC_DPI0_HSYNC (MTK_PIN_NO(128) | 1) +#define MT8135_PIN_128_DPIHSYNC__FUNC_EINT99 (MTK_PIN_NO(128) | 2) +#define MT8135_PIN_128_DPIHSYNC__FUNC_I2SIN_WS (MTK_PIN_NO(128) | 3) +#define MT8135_PIN_128_DPIHSYNC__FUNC_DAC_WS (MTK_PIN_NO(128) | 4) +#define MT8135_PIN_128_DPIHSYNC__FUNC_PCM1_WS (MTK_PIN_NO(128) | 5) +#define MT8135_PIN_128_DPIHSYNC__FUNC_IRDA_RXD (MTK_PIN_NO(128) | 6) + +#define MT8135_PIN_129_DPIB0__FUNC_GPIO129 (MTK_PIN_NO(129) | 0) +#define MT8135_PIN_129_DPIB0__FUNC_DPI0_B0 (MTK_PIN_NO(129) | 1) +#define MT8135_PIN_129_DPIB0__FUNC_EINT102 (MTK_PIN_NO(129) | 2) +#define MT8135_PIN_129_DPIB0__FUNC_SCL0 (MTK_PIN_NO(129) | 4) +#define MT8135_PIN_129_DPIB0__FUNC_DISP_PWM (MTK_PIN_NO(129) | 5) + +#define MT8135_PIN_130_DPIB1__FUNC_GPIO130 (MTK_PIN_NO(130) | 0) +#define MT8135_PIN_130_DPIB1__FUNC_DPI0_B1 (MTK_PIN_NO(130) | 1) +#define MT8135_PIN_130_DPIB1__FUNC_EINT103 (MTK_PIN_NO(130) | 2) +#define MT8135_PIN_130_DPIB1__FUNC_CLKM0 (MTK_PIN_NO(130) | 3) +#define MT8135_PIN_130_DPIB1__FUNC_SDA0 (MTK_PIN_NO(130) | 4) +#define MT8135_PIN_130_DPIB1__FUNC_PWM1 (MTK_PIN_NO(130) | 5) + +#define MT8135_PIN_131_DPIB2__FUNC_GPIO131 (MTK_PIN_NO(131) | 0) +#define MT8135_PIN_131_DPIB2__FUNC_DPI0_B2 (MTK_PIN_NO(131) | 1) +#define MT8135_PIN_131_DPIB2__FUNC_EINT104 (MTK_PIN_NO(131) | 2) +#define MT8135_PIN_131_DPIB2__FUNC_CLKM1 (MTK_PIN_NO(131) | 3) +#define MT8135_PIN_131_DPIB2__FUNC_SCL1 (MTK_PIN_NO(131) | 4) +#define MT8135_PIN_131_DPIB2__FUNC_PWM2 (MTK_PIN_NO(131) | 5) + +#define MT8135_PIN_132_DPIB3__FUNC_GPIO132 (MTK_PIN_NO(132) | 0) +#define MT8135_PIN_132_DPIB3__FUNC_DPI0_B3 (MTK_PIN_NO(132) | 1) +#define MT8135_PIN_132_DPIB3__FUNC_EINT105 (MTK_PIN_NO(132) | 2) +#define MT8135_PIN_132_DPIB3__FUNC_CLKM2 (MTK_PIN_NO(132) | 3) +#define MT8135_PIN_132_DPIB3__FUNC_SDA1 (MTK_PIN_NO(132) | 4) +#define MT8135_PIN_132_DPIB3__FUNC_PWM3 (MTK_PIN_NO(132) | 5) + +#define MT8135_PIN_133_DPIB4__FUNC_GPIO133 (MTK_PIN_NO(133) | 0) +#define MT8135_PIN_133_DPIB4__FUNC_DPI0_B4 (MTK_PIN_NO(133) | 1) +#define MT8135_PIN_133_DPIB4__FUNC_EINT106 (MTK_PIN_NO(133) | 2) +#define MT8135_PIN_133_DPIB4__FUNC_CLKM3 (MTK_PIN_NO(133) | 3) +#define MT8135_PIN_133_DPIB4__FUNC_SCL2 (MTK_PIN_NO(133) | 4) +#define MT8135_PIN_133_DPIB4__FUNC_PWM4 (MTK_PIN_NO(133) | 5) + +#define MT8135_PIN_134_DPIB5__FUNC_GPIO134 (MTK_PIN_NO(134) | 0) +#define MT8135_PIN_134_DPIB5__FUNC_DPI0_B5 (MTK_PIN_NO(134) | 1) +#define MT8135_PIN_134_DPIB5__FUNC_EINT107 (MTK_PIN_NO(134) | 2) +#define MT8135_PIN_134_DPIB5__FUNC_CLKM4 (MTK_PIN_NO(134) | 3) +#define MT8135_PIN_134_DPIB5__FUNC_SDA2 (MTK_PIN_NO(134) | 4) +#define MT8135_PIN_134_DPIB5__FUNC_PWM5 (MTK_PIN_NO(134) | 5) + +#define MT8135_PIN_135_DPIB6__FUNC_GPIO135 (MTK_PIN_NO(135) | 0) +#define MT8135_PIN_135_DPIB6__FUNC_DPI0_B6 (MTK_PIN_NO(135) | 1) +#define MT8135_PIN_135_DPIB6__FUNC_EINT108 (MTK_PIN_NO(135) | 2) +#define MT8135_PIN_135_DPIB6__FUNC_CLKM5 (MTK_PIN_NO(135) | 3) +#define MT8135_PIN_135_DPIB6__FUNC_SCL3 (MTK_PIN_NO(135) | 4) +#define MT8135_PIN_135_DPIB6__FUNC_PWM6 (MTK_PIN_NO(135) | 5) + +#define MT8135_PIN_136_DPIB7__FUNC_GPIO136 (MTK_PIN_NO(136) | 0) +#define MT8135_PIN_136_DPIB7__FUNC_DPI0_B7 (MTK_PIN_NO(136) | 1) +#define MT8135_PIN_136_DPIB7__FUNC_EINT109 (MTK_PIN_NO(136) | 2) +#define MT8135_PIN_136_DPIB7__FUNC_CLKM6 (MTK_PIN_NO(136) | 3) +#define MT8135_PIN_136_DPIB7__FUNC_SDA3 (MTK_PIN_NO(136) | 4) +#define MT8135_PIN_136_DPIB7__FUNC_PWM7 (MTK_PIN_NO(136) | 5) + +#define MT8135_PIN_137_DPIG0__FUNC_GPIO137 (MTK_PIN_NO(137) | 0) +#define MT8135_PIN_137_DPIG0__FUNC_DPI0_G0 (MTK_PIN_NO(137) | 1) +#define MT8135_PIN_137_DPIG0__FUNC_EINT110 (MTK_PIN_NO(137) | 2) +#define MT8135_PIN_137_DPIG0__FUNC_DSP1_ID (MTK_PIN_NO(137) | 5) + +#define MT8135_PIN_138_DPIG2__FUNC_GPIO138 (MTK_PIN_NO(138) | 0) +#define MT8135_PIN_138_DPIG2__FUNC_DPI0_G2 (MTK_PIN_NO(138) | 1) +#define MT8135_PIN_138_DPIG2__FUNC_EINT112 (MTK_PIN_NO(138) | 2) +#define MT8135_PIN_138_DPIG2__FUNC_DSP1_IMS (MTK_PIN_NO(138) | 5) + +#define MT8135_PIN_139_DPIG3__FUNC_GPIO139 (MTK_PIN_NO(139) | 0) +#define MT8135_PIN_139_DPIG3__FUNC_DPI0_G3 (MTK_PIN_NO(139) | 1) +#define MT8135_PIN_139_DPIG3__FUNC_EINT113 (MTK_PIN_NO(139) | 2) +#define MT8135_PIN_139_DPIG3__FUNC_DSP2_IMS (MTK_PIN_NO(139) | 5) + +#define MT8135_PIN_140_DPIG6__FUNC_GPIO140 (MTK_PIN_NO(140) | 0) +#define MT8135_PIN_140_DPIG6__FUNC_DPI0_G6 (MTK_PIN_NO(140) | 1) +#define MT8135_PIN_140_DPIG6__FUNC_EINT116 (MTK_PIN_NO(140) | 2) +#define MT8135_PIN_140_DPIG6__FUNC_CM2DAT_2X_2 (MTK_PIN_NO(140) | 4) + +#define MT8135_PIN_141_DPIG7__FUNC_GPIO141 (MTK_PIN_NO(141) | 0) +#define MT8135_PIN_141_DPIG7__FUNC_DPI0_G7 (MTK_PIN_NO(141) | 1) +#define MT8135_PIN_141_DPIG7__FUNC_EINT117 (MTK_PIN_NO(141) | 2) +#define MT8135_PIN_141_DPIG7__FUNC_CM2DAT_2X_3 (MTK_PIN_NO(141) | 4) + +#define MT8135_PIN_142_DPIR0__FUNC_GPIO142 (MTK_PIN_NO(142) | 0) +#define MT8135_PIN_142_DPIR0__FUNC_DPI0_R0 (MTK_PIN_NO(142) | 1) +#define MT8135_PIN_142_DPIR0__FUNC_EINT118 (MTK_PIN_NO(142) | 2) +#define MT8135_PIN_142_DPIR0__FUNC_CM2DAT_2X_4 (MTK_PIN_NO(142) | 4) + +#define MT8135_PIN_143_DPIR1__FUNC_GPIO143 (MTK_PIN_NO(143) | 0) +#define MT8135_PIN_143_DPIR1__FUNC_DPI0_R1 (MTK_PIN_NO(143) | 1) +#define MT8135_PIN_143_DPIR1__FUNC_EINT119 (MTK_PIN_NO(143) | 2) +#define MT8135_PIN_143_DPIR1__FUNC_CM2DAT_2X_5 (MTK_PIN_NO(143) | 4) + +#define MT8135_PIN_144_DPIR2__FUNC_GPIO144 (MTK_PIN_NO(144) | 0) +#define MT8135_PIN_144_DPIR2__FUNC_DPI0_R2 (MTK_PIN_NO(144) | 1) +#define MT8135_PIN_144_DPIR2__FUNC_EINT120 (MTK_PIN_NO(144) | 2) +#define MT8135_PIN_144_DPIR2__FUNC_CM2DAT_2X_6 (MTK_PIN_NO(144) | 4) + +#define MT8135_PIN_145_DPIR4__FUNC_GPIO145 (MTK_PIN_NO(145) | 0) +#define MT8135_PIN_145_DPIR4__FUNC_DPI0_R4 (MTK_PIN_NO(145) | 1) +#define MT8135_PIN_145_DPIR4__FUNC_EINT122 (MTK_PIN_NO(145) | 2) +#define MT8135_PIN_145_DPIR4__FUNC_CM2DAT_2X_8 (MTK_PIN_NO(145) | 4) + +#define MT8135_PIN_146_DPIR5__FUNC_GPIO146 (MTK_PIN_NO(146) | 0) +#define MT8135_PIN_146_DPIR5__FUNC_DPI0_R5 (MTK_PIN_NO(146) | 1) +#define MT8135_PIN_146_DPIR5__FUNC_EINT123 (MTK_PIN_NO(146) | 2) +#define MT8135_PIN_146_DPIR5__FUNC_CM2DAT_2X_9 (MTK_PIN_NO(146) | 4) + +#define MT8135_PIN_147_DPIR6__FUNC_GPIO147 (MTK_PIN_NO(147) | 0) +#define MT8135_PIN_147_DPIR6__FUNC_DPI0_R6 (MTK_PIN_NO(147) | 1) +#define MT8135_PIN_147_DPIR6__FUNC_EINT124 (MTK_PIN_NO(147) | 2) +#define MT8135_PIN_147_DPIR6__FUNC_CM2VSYNC_2X (MTK_PIN_NO(147) | 4) + +#define MT8135_PIN_148_DPIR7__FUNC_GPIO148 (MTK_PIN_NO(148) | 0) +#define MT8135_PIN_148_DPIR7__FUNC_DPI0_R7 (MTK_PIN_NO(148) | 1) +#define MT8135_PIN_148_DPIR7__FUNC_EINT125 (MTK_PIN_NO(148) | 2) +#define MT8135_PIN_148_DPIR7__FUNC_CM2HSYNC_2X (MTK_PIN_NO(148) | 4) + +#define MT8135_PIN_149_TDN3__FUNC_GPIO149 (MTK_PIN_NO(149) | 0) +#define MT8135_PIN_149_TDN3__FUNC_EINT36 (MTK_PIN_NO(149) | 2) + +#define MT8135_PIN_150_TDP3__FUNC_GPIO150 (MTK_PIN_NO(150) | 0) +#define MT8135_PIN_150_TDP3__FUNC_EINT35 (MTK_PIN_NO(150) | 2) + +#define MT8135_PIN_151_TDN2__FUNC_GPIO151 (MTK_PIN_NO(151) | 0) +#define MT8135_PIN_151_TDN2__FUNC_EINT169 (MTK_PIN_NO(151) | 2) + +#define MT8135_PIN_152_TDP2__FUNC_GPIO152 (MTK_PIN_NO(152) | 0) +#define MT8135_PIN_152_TDP2__FUNC_EINT168 (MTK_PIN_NO(152) | 2) + +#define MT8135_PIN_153_TCN__FUNC_GPIO153 (MTK_PIN_NO(153) | 0) +#define MT8135_PIN_153_TCN__FUNC_EINT163 (MTK_PIN_NO(153) | 2) + +#define MT8135_PIN_154_TCP__FUNC_GPIO154 (MTK_PIN_NO(154) | 0) +#define MT8135_PIN_154_TCP__FUNC_EINT162 (MTK_PIN_NO(154) | 2) + +#define MT8135_PIN_155_TDN1__FUNC_GPIO155 (MTK_PIN_NO(155) | 0) +#define MT8135_PIN_155_TDN1__FUNC_EINT167 (MTK_PIN_NO(155) | 2) + +#define MT8135_PIN_156_TDP1__FUNC_GPIO156 (MTK_PIN_NO(156) | 0) +#define MT8135_PIN_156_TDP1__FUNC_EINT166 (MTK_PIN_NO(156) | 2) + +#define MT8135_PIN_157_TDN0__FUNC_GPIO157 (MTK_PIN_NO(157) | 0) +#define MT8135_PIN_157_TDN0__FUNC_EINT165 (MTK_PIN_NO(157) | 2) + +#define MT8135_PIN_158_TDP0__FUNC_GPIO158 (MTK_PIN_NO(158) | 0) +#define MT8135_PIN_158_TDP0__FUNC_EINT164 (MTK_PIN_NO(158) | 2) + +#define MT8135_PIN_159_RDN3__FUNC_GPIO159 (MTK_PIN_NO(159) | 0) +#define MT8135_PIN_159_RDN3__FUNC_EINT18 (MTK_PIN_NO(159) | 2) + +#define MT8135_PIN_160_RDP3__FUNC_GPIO160 (MTK_PIN_NO(160) | 0) +#define MT8135_PIN_160_RDP3__FUNC_EINT30 (MTK_PIN_NO(160) | 2) + +#define MT8135_PIN_161_RDN2__FUNC_GPIO161 (MTK_PIN_NO(161) | 0) +#define MT8135_PIN_161_RDN2__FUNC_EINT31 (MTK_PIN_NO(161) | 2) + +#define MT8135_PIN_162_RDP2__FUNC_GPIO162 (MTK_PIN_NO(162) | 0) +#define MT8135_PIN_162_RDP2__FUNC_EINT32 (MTK_PIN_NO(162) | 2) + +#define MT8135_PIN_163_RCN__FUNC_GPIO163 (MTK_PIN_NO(163) | 0) +#define MT8135_PIN_163_RCN__FUNC_EINT33 (MTK_PIN_NO(163) | 2) + +#define MT8135_PIN_164_RCP__FUNC_GPIO164 (MTK_PIN_NO(164) | 0) +#define MT8135_PIN_164_RCP__FUNC_EINT39 (MTK_PIN_NO(164) | 2) + +#define MT8135_PIN_165_RDN1__FUNC_GPIO165 (MTK_PIN_NO(165) | 0) + +#define MT8135_PIN_166_RDP1__FUNC_GPIO166 (MTK_PIN_NO(166) | 0) + +#define MT8135_PIN_167_RDN0__FUNC_GPIO167 (MTK_PIN_NO(167) | 0) + +#define MT8135_PIN_168_RDP0__FUNC_GPIO168 (MTK_PIN_NO(168) | 0) + +#define MT8135_PIN_169_RDN1_A__FUNC_GPIO169 (MTK_PIN_NO(169) | 0) +#define MT8135_PIN_169_RDN1_A__FUNC_CMDAT6 (MTK_PIN_NO(169) | 1) +#define MT8135_PIN_169_RDN1_A__FUNC_EINT175 (MTK_PIN_NO(169) | 2) + +#define MT8135_PIN_170_RDP1_A__FUNC_GPIO170 (MTK_PIN_NO(170) | 0) +#define MT8135_PIN_170_RDP1_A__FUNC_CMDAT7 (MTK_PIN_NO(170) | 1) +#define MT8135_PIN_170_RDP1_A__FUNC_EINT174 (MTK_PIN_NO(170) | 2) + +#define MT8135_PIN_171_RCN_A__FUNC_GPIO171 (MTK_PIN_NO(171) | 0) +#define MT8135_PIN_171_RCN_A__FUNC_CMDAT8 (MTK_PIN_NO(171) | 1) +#define MT8135_PIN_171_RCN_A__FUNC_EINT171 (MTK_PIN_NO(171) | 2) + +#define MT8135_PIN_172_RCP_A__FUNC_GPIO172 (MTK_PIN_NO(172) | 0) +#define MT8135_PIN_172_RCP_A__FUNC_CMDAT9 (MTK_PIN_NO(172) | 1) +#define MT8135_PIN_172_RCP_A__FUNC_EINT170 (MTK_PIN_NO(172) | 2) + +#define MT8135_PIN_173_RDN0_A__FUNC_GPIO173 (MTK_PIN_NO(173) | 0) +#define MT8135_PIN_173_RDN0_A__FUNC_CMHSYNC (MTK_PIN_NO(173) | 1) +#define MT8135_PIN_173_RDN0_A__FUNC_EINT173 (MTK_PIN_NO(173) | 2) + +#define MT8135_PIN_174_RDP0_A__FUNC_GPIO174 (MTK_PIN_NO(174) | 0) +#define MT8135_PIN_174_RDP0_A__FUNC_CMVSYNC (MTK_PIN_NO(174) | 1) +#define MT8135_PIN_174_RDP0_A__FUNC_EINT172 (MTK_PIN_NO(174) | 2) + +#define MT8135_PIN_175_RDN1_B__FUNC_GPIO175 (MTK_PIN_NO(175) | 0) +#define MT8135_PIN_175_RDN1_B__FUNC_CMDAT2 (MTK_PIN_NO(175) | 1) +#define MT8135_PIN_175_RDN1_B__FUNC_EINT181 (MTK_PIN_NO(175) | 2) +#define MT8135_PIN_175_RDN1_B__FUNC_CMCSD2 (MTK_PIN_NO(175) | 3) + +#define MT8135_PIN_176_RDP1_B__FUNC_GPIO176 (MTK_PIN_NO(176) | 0) +#define MT8135_PIN_176_RDP1_B__FUNC_CMDAT3 (MTK_PIN_NO(176) | 1) +#define MT8135_PIN_176_RDP1_B__FUNC_EINT180 (MTK_PIN_NO(176) | 2) +#define MT8135_PIN_176_RDP1_B__FUNC_CMCSD3 (MTK_PIN_NO(176) | 3) + +#define MT8135_PIN_177_RCN_B__FUNC_GPIO177 (MTK_PIN_NO(177) | 0) +#define MT8135_PIN_177_RCN_B__FUNC_CMDAT4 (MTK_PIN_NO(177) | 1) +#define MT8135_PIN_177_RCN_B__FUNC_EINT177 (MTK_PIN_NO(177) | 2) + +#define MT8135_PIN_178_RCP_B__FUNC_GPIO178 (MTK_PIN_NO(178) | 0) +#define MT8135_PIN_178_RCP_B__FUNC_CMDAT5 (MTK_PIN_NO(178) | 1) +#define MT8135_PIN_178_RCP_B__FUNC_EINT176 (MTK_PIN_NO(178) | 2) + +#define MT8135_PIN_179_RDN0_B__FUNC_GPIO179 (MTK_PIN_NO(179) | 0) +#define MT8135_PIN_179_RDN0_B__FUNC_CMDAT0 (MTK_PIN_NO(179) | 1) +#define MT8135_PIN_179_RDN0_B__FUNC_EINT179 (MTK_PIN_NO(179) | 2) +#define MT8135_PIN_179_RDN0_B__FUNC_CMCSD0 (MTK_PIN_NO(179) | 3) + +#define MT8135_PIN_180_RDP0_B__FUNC_GPIO180 (MTK_PIN_NO(180) | 0) +#define MT8135_PIN_180_RDP0_B__FUNC_CMDAT1 (MTK_PIN_NO(180) | 1) +#define MT8135_PIN_180_RDP0_B__FUNC_EINT178 (MTK_PIN_NO(180) | 2) +#define MT8135_PIN_180_RDP0_B__FUNC_CMCSD1 (MTK_PIN_NO(180) | 3) + +#define MT8135_PIN_181_CMPCLK__FUNC_GPIO181 (MTK_PIN_NO(181) | 0) +#define MT8135_PIN_181_CMPCLK__FUNC_CMPCLK (MTK_PIN_NO(181) | 1) +#define MT8135_PIN_181_CMPCLK__FUNC_EINT182 (MTK_PIN_NO(181) | 2) +#define MT8135_PIN_181_CMPCLK__FUNC_CMCSK (MTK_PIN_NO(181) | 3) +#define MT8135_PIN_181_CMPCLK__FUNC_CM2MCLK_4X (MTK_PIN_NO(181) | 4) +#define MT8135_PIN_181_CMPCLK__FUNC_TS_AUXADC_SEL_3 (MTK_PIN_NO(181) | 5) +#define MT8135_PIN_181_CMPCLK__FUNC_VENC_TEST_CK (MTK_PIN_NO(181) | 6) +#define MT8135_PIN_181_CMPCLK__FUNC_TESTA_OUT27 (MTK_PIN_NO(181) | 7) + +#define MT8135_PIN_182_CMMCLK__FUNC_GPIO182 (MTK_PIN_NO(182) | 0) +#define MT8135_PIN_182_CMMCLK__FUNC_CMMCLK (MTK_PIN_NO(182) | 1) +#define MT8135_PIN_182_CMMCLK__FUNC_EINT183 (MTK_PIN_NO(182) | 2) +#define MT8135_PIN_182_CMMCLK__FUNC_TS_AUXADC_SEL_2 (MTK_PIN_NO(182) | 5) +#define MT8135_PIN_182_CMMCLK__FUNC_TESTA_OUT28 (MTK_PIN_NO(182) | 7) + +#define MT8135_PIN_183_CMRST__FUNC_GPIO183 (MTK_PIN_NO(183) | 0) +#define MT8135_PIN_183_CMRST__FUNC_CMRST (MTK_PIN_NO(183) | 1) +#define MT8135_PIN_183_CMRST__FUNC_EINT185 (MTK_PIN_NO(183) | 2) +#define MT8135_PIN_183_CMRST__FUNC_TS_AUXADC_SEL_1 (MTK_PIN_NO(183) | 5) +#define MT8135_PIN_183_CMRST__FUNC_TESTA_OUT30 (MTK_PIN_NO(183) | 7) + +#define MT8135_PIN_184_CMPDN__FUNC_GPIO184 (MTK_PIN_NO(184) | 0) +#define MT8135_PIN_184_CMPDN__FUNC_CMPDN (MTK_PIN_NO(184) | 1) +#define MT8135_PIN_184_CMPDN__FUNC_EINT184 (MTK_PIN_NO(184) | 2) +#define MT8135_PIN_184_CMPDN__FUNC_TS_AUXADC_SEL_0 (MTK_PIN_NO(184) | 5) +#define MT8135_PIN_184_CMPDN__FUNC_TESTA_OUT29 (MTK_PIN_NO(184) | 7) + +#define MT8135_PIN_185_CMFLASH__FUNC_GPIO185 (MTK_PIN_NO(185) | 0) +#define MT8135_PIN_185_CMFLASH__FUNC_CMFLASH (MTK_PIN_NO(185) | 1) +#define MT8135_PIN_185_CMFLASH__FUNC_EINT186 (MTK_PIN_NO(185) | 2) +#define MT8135_PIN_185_CMFLASH__FUNC_CM2MCLK_3X (MTK_PIN_NO(185) | 3) +#define MT8135_PIN_185_CMFLASH__FUNC_MFG_TEST_CK_1 (MTK_PIN_NO(185) | 6) +#define MT8135_PIN_185_CMFLASH__FUNC_TESTA_OUT31 (MTK_PIN_NO(185) | 7) + +#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_GPIO186 (MTK_PIN_NO(186) | 0) +#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_MRG_I2S_P_CLK (MTK_PIN_NO(186) | 1) +#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_EINT14 (MTK_PIN_NO(186) | 2) +#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_I2SIN_CK (MTK_PIN_NO(186) | 3) +#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_PCM0_CK (MTK_PIN_NO(186) | 4) +#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_DSP2_ICK (MTK_PIN_NO(186) | 5) +#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_IMG_TEST_CK (MTK_PIN_NO(186) | 6) +#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_USB_SCL (MTK_PIN_NO(186) | 7) + +#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_GPIO187 (MTK_PIN_NO(187) | 0) +#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_MRG_I2S_SYNC (MTK_PIN_NO(187) | 1) +#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_EINT16 (MTK_PIN_NO(187) | 2) +#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_I2SIN_WS (MTK_PIN_NO(187) | 3) +#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_PCM0_WS (MTK_PIN_NO(187) | 4) +#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_DISP_TEST_CK (MTK_PIN_NO(187) | 6) + +#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_GPIO188 (MTK_PIN_NO(188) | 0) +#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_MRG_I2S_PCM_RX (MTK_PIN_NO(188) | 1) +#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_EINT15 (MTK_PIN_NO(188) | 2) +#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_I2SIN_DAT (MTK_PIN_NO(188) | 3) +#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_PCM0_DI (MTK_PIN_NO(188) | 4) +#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_DSP2_ID (MTK_PIN_NO(188) | 5) +#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_MFG_TEST_CK (MTK_PIN_NO(188) | 6) +#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_USB_SDA (MTK_PIN_NO(188) | 7) + +#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_GPIO189 (MTK_PIN_NO(189) | 0) +#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_MRG_I2S_PCM_TX (MTK_PIN_NO(189) | 1) +#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_EINT17 (MTK_PIN_NO(189) | 2) +#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_I2SOUT_DAT (MTK_PIN_NO(189) | 3) +#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_PCM0_DO (MTK_PIN_NO(189) | 4) +#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_VDEC_TEST_CK (MTK_PIN_NO(189) | 6) + +#define MT8135_PIN_190_SRCLKENAI__FUNC_GPIO190 (MTK_PIN_NO(190) | 0) +#define MT8135_PIN_190_SRCLKENAI__FUNC_SRCLKENAI (MTK_PIN_NO(190) | 1) + +#define MT8135_PIN_191_URXD3__FUNC_GPIO191 (MTK_PIN_NO(191) | 0) +#define MT8135_PIN_191_URXD3__FUNC_URXD3 (MTK_PIN_NO(191) | 1) +#define MT8135_PIN_191_URXD3__FUNC_EINT87 (MTK_PIN_NO(191) | 2) +#define MT8135_PIN_191_URXD3__FUNC_UTXD3 (MTK_PIN_NO(191) | 3) +#define MT8135_PIN_191_URXD3__FUNC_TS_AUX_ST (MTK_PIN_NO(191) | 5) +#define MT8135_PIN_191_URXD3__FUNC_PWM4 (MTK_PIN_NO(191) | 6) + +#define MT8135_PIN_192_UTXD3__FUNC_GPIO192 (MTK_PIN_NO(192) | 0) +#define MT8135_PIN_192_UTXD3__FUNC_UTXD3 (MTK_PIN_NO(192) | 1) +#define MT8135_PIN_192_UTXD3__FUNC_EINT86 (MTK_PIN_NO(192) | 2) +#define MT8135_PIN_192_UTXD3__FUNC_URXD3 (MTK_PIN_NO(192) | 3) +#define MT8135_PIN_192_UTXD3__FUNC_TS_AUX_CS_B (MTK_PIN_NO(192) | 5) +#define MT8135_PIN_192_UTXD3__FUNC_PWM3 (MTK_PIN_NO(192) | 6) + +#define MT8135_PIN_193_SDA2__FUNC_GPIO193 (MTK_PIN_NO(193) | 0) +#define MT8135_PIN_193_SDA2__FUNC_SDA2 (MTK_PIN_NO(193) | 1) +#define MT8135_PIN_193_SDA2__FUNC_EINT95 (MTK_PIN_NO(193) | 2) +#define MT8135_PIN_193_SDA2__FUNC_CLKM5 (MTK_PIN_NO(193) | 3) +#define MT8135_PIN_193_SDA2__FUNC_PWM5 (MTK_PIN_NO(193) | 4) +#define MT8135_PIN_193_SDA2__FUNC_TS_AUX_PWDB (MTK_PIN_NO(193) | 5) + +#define MT8135_PIN_194_SCL2__FUNC_GPIO194 (MTK_PIN_NO(194) | 0) +#define MT8135_PIN_194_SCL2__FUNC_SCL2 (MTK_PIN_NO(194) | 1) +#define MT8135_PIN_194_SCL2__FUNC_EINT94 (MTK_PIN_NO(194) | 2) +#define MT8135_PIN_194_SCL2__FUNC_CLKM4 (MTK_PIN_NO(194) | 3) +#define MT8135_PIN_194_SCL2__FUNC_PWM4 (MTK_PIN_NO(194) | 4) +#define MT8135_PIN_194_SCL2__FUNC_TS_AUXADC_TEST_CK (MTK_PIN_NO(194) | 5) + +#define MT8135_PIN_195_SDA1__FUNC_GPIO195 (MTK_PIN_NO(195) | 0) +#define MT8135_PIN_195_SDA1__FUNC_SDA1 (MTK_PIN_NO(195) | 1) +#define MT8135_PIN_195_SDA1__FUNC_EINT93 (MTK_PIN_NO(195) | 2) +#define MT8135_PIN_195_SDA1__FUNC_CLKM3 (MTK_PIN_NO(195) | 3) +#define MT8135_PIN_195_SDA1__FUNC_PWM3 (MTK_PIN_NO(195) | 4) +#define MT8135_PIN_195_SDA1__FUNC_TS_AUX_SCLK_PWDB (MTK_PIN_NO(195) | 5) + +#define MT8135_PIN_196_SCL1__FUNC_GPIO196 (MTK_PIN_NO(196) | 0) +#define MT8135_PIN_196_SCL1__FUNC_SCL1 (MTK_PIN_NO(196) | 1) +#define MT8135_PIN_196_SCL1__FUNC_EINT92 (MTK_PIN_NO(196) | 2) +#define MT8135_PIN_196_SCL1__FUNC_CLKM2 (MTK_PIN_NO(196) | 3) +#define MT8135_PIN_196_SCL1__FUNC_PWM2 (MTK_PIN_NO(196) | 4) +#define MT8135_PIN_196_SCL1__FUNC_TS_AUX_DIN (MTK_PIN_NO(196) | 5) + +#define MT8135_PIN_197_MSDC3_DAT2__FUNC_GPIO197 (MTK_PIN_NO(197) | 0) +#define MT8135_PIN_197_MSDC3_DAT2__FUNC_MSDC3_DAT2 (MTK_PIN_NO(197) | 1) +#define MT8135_PIN_197_MSDC3_DAT2__FUNC_EINT71 (MTK_PIN_NO(197) | 2) +#define MT8135_PIN_197_MSDC3_DAT2__FUNC_SCL6 (MTK_PIN_NO(197) | 3) +#define MT8135_PIN_197_MSDC3_DAT2__FUNC_PWM5 (MTK_PIN_NO(197) | 4) +#define MT8135_PIN_197_MSDC3_DAT2__FUNC_CLKM4 (MTK_PIN_NO(197) | 5) +#define MT8135_PIN_197_MSDC3_DAT2__FUNC_MFG_TEST_CK_2 (MTK_PIN_NO(197) | 6) + +#define MT8135_PIN_198_MSDC3_DAT3__FUNC_GPIO198 (MTK_PIN_NO(198) | 0) +#define MT8135_PIN_198_MSDC3_DAT3__FUNC_MSDC3_DAT3 (MTK_PIN_NO(198) | 1) +#define MT8135_PIN_198_MSDC3_DAT3__FUNC_EINT72 (MTK_PIN_NO(198) | 2) +#define MT8135_PIN_198_MSDC3_DAT3__FUNC_SDA6 (MTK_PIN_NO(198) | 3) +#define MT8135_PIN_198_MSDC3_DAT3__FUNC_PWM6 (MTK_PIN_NO(198) | 4) +#define MT8135_PIN_198_MSDC3_DAT3__FUNC_CLKM5 (MTK_PIN_NO(198) | 5) +#define MT8135_PIN_198_MSDC3_DAT3__FUNC_MFG_TEST_CK_3 (MTK_PIN_NO(198) | 6) + +#define MT8135_PIN_199_MSDC3_CMD__FUNC_GPIO199 (MTK_PIN_NO(199) | 0) +#define MT8135_PIN_199_MSDC3_CMD__FUNC_MSDC3_CMD (MTK_PIN_NO(199) | 1) +#define MT8135_PIN_199_MSDC3_CMD__FUNC_EINT68 (MTK_PIN_NO(199) | 2) +#define MT8135_PIN_199_MSDC3_CMD__FUNC_SDA2 (MTK_PIN_NO(199) | 3) +#define MT8135_PIN_199_MSDC3_CMD__FUNC_PWM2 (MTK_PIN_NO(199) | 4) +#define MT8135_PIN_199_MSDC3_CMD__FUNC_CLKM1 (MTK_PIN_NO(199) | 5) +#define MT8135_PIN_199_MSDC3_CMD__FUNC_MFG_TEST_CK_4 (MTK_PIN_NO(199) | 6) + +#define MT8135_PIN_200_MSDC3_CLK__FUNC_GPIO200 (MTK_PIN_NO(200) | 0) +#define MT8135_PIN_200_MSDC3_CLK__FUNC_MSDC3_CLK (MTK_PIN_NO(200) | 1) +#define MT8135_PIN_200_MSDC3_CLK__FUNC_EINT67 (MTK_PIN_NO(200) | 2) +#define MT8135_PIN_200_MSDC3_CLK__FUNC_SCL2 (MTK_PIN_NO(200) | 3) +#define MT8135_PIN_200_MSDC3_CLK__FUNC_PWM1 (MTK_PIN_NO(200) | 4) +#define MT8135_PIN_200_MSDC3_CLK__FUNC_CLKM0 (MTK_PIN_NO(200) | 5) + +#define MT8135_PIN_201_MSDC3_DAT1__FUNC_GPIO201 (MTK_PIN_NO(201) | 0) +#define MT8135_PIN_201_MSDC3_DAT1__FUNC_MSDC3_DAT1 (MTK_PIN_NO(201) | 1) +#define MT8135_PIN_201_MSDC3_DAT1__FUNC_EINT70 (MTK_PIN_NO(201) | 2) +#define MT8135_PIN_201_MSDC3_DAT1__FUNC_SDA3 (MTK_PIN_NO(201) | 3) +#define MT8135_PIN_201_MSDC3_DAT1__FUNC_PWM4 (MTK_PIN_NO(201) | 4) +#define MT8135_PIN_201_MSDC3_DAT1__FUNC_CLKM3 (MTK_PIN_NO(201) | 5) + +#define MT8135_PIN_202_MSDC3_DAT0__FUNC_GPIO202 (MTK_PIN_NO(202) | 0) +#define MT8135_PIN_202_MSDC3_DAT0__FUNC_MSDC3_DAT0 (MTK_PIN_NO(202) | 1) +#define MT8135_PIN_202_MSDC3_DAT0__FUNC_EINT69 (MTK_PIN_NO(202) | 2) +#define MT8135_PIN_202_MSDC3_DAT0__FUNC_SCL3 (MTK_PIN_NO(202) | 3) +#define MT8135_PIN_202_MSDC3_DAT0__FUNC_PWM3 (MTK_PIN_NO(202) | 4) +#define MT8135_PIN_202_MSDC3_DAT0__FUNC_CLKM2 (MTK_PIN_NO(202) | 5) + +#endif /* __DTS_MT8135_PINFUNC_H */ diff --git a/include/dt-bindings/pinctrl/mt8183-pinfunc.h b/include/dt-bindings/pinctrl/mt8183-pinfunc.h new file mode 100644 index 000000000000..6221cd712718 --- /dev/null +++ b/include/dt-bindings/pinctrl/mt8183-pinfunc.h @@ -0,0 +1,1120 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 MediaTek Inc. + * Author: Zhiyong Tao <zhiyong.tao@mediatek.com> + * + */ + +#ifndef __MT8183_PINFUNC_H +#define __MT8183_PINFUNC_H + +#include <dt-bindings/pinctrl/mt65xx.h> + +#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define PINMUX_GPIO0__FUNC_MRG_SYNC (MTK_PIN_NO(0) | 1) +#define PINMUX_GPIO0__FUNC_PCM0_SYNC (MTK_PIN_NO(0) | 2) +#define PINMUX_GPIO0__FUNC_TP_GPIO0_AO (MTK_PIN_NO(0) | 3) +#define PINMUX_GPIO0__FUNC_SRCLKENAI0 (MTK_PIN_NO(0) | 4) +#define PINMUX_GPIO0__FUNC_SCP_SPI2_CS (MTK_PIN_NO(0) | 5) +#define PINMUX_GPIO0__FUNC_I2S3_MCK (MTK_PIN_NO(0) | 6) +#define PINMUX_GPIO0__FUNC_SPI2_CSB (MTK_PIN_NO(0) | 7) + +#define PINMUX_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define PINMUX_GPIO1__FUNC_MRG_CLK (MTK_PIN_NO(1) | 1) +#define PINMUX_GPIO1__FUNC_PCM0_CLK (MTK_PIN_NO(1) | 2) +#define PINMUX_GPIO1__FUNC_TP_GPIO1_AO (MTK_PIN_NO(1) | 3) +#define PINMUX_GPIO1__FUNC_CLKM3 (MTK_PIN_NO(1) | 4) +#define PINMUX_GPIO1__FUNC_SCP_SPI2_MO (MTK_PIN_NO(1) | 5) +#define PINMUX_GPIO1__FUNC_I2S3_BCK (MTK_PIN_NO(1) | 6) +#define PINMUX_GPIO1__FUNC_SPI2_MO (MTK_PIN_NO(1) | 7) + +#define PINMUX_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define PINMUX_GPIO2__FUNC_MRG_DO (MTK_PIN_NO(2) | 1) +#define PINMUX_GPIO2__FUNC_PCM0_DO (MTK_PIN_NO(2) | 2) +#define PINMUX_GPIO2__FUNC_TP_GPIO2_AO (MTK_PIN_NO(2) | 3) +#define PINMUX_GPIO2__FUNC_SCL6 (MTK_PIN_NO(2) | 4) +#define PINMUX_GPIO2__FUNC_SCP_SPI2_CK (MTK_PIN_NO(2) | 5) +#define PINMUX_GPIO2__FUNC_I2S3_LRCK (MTK_PIN_NO(2) | 6) +#define PINMUX_GPIO2__FUNC_SPI2_CLK (MTK_PIN_NO(2) | 7) + +#define PINMUX_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define PINMUX_GPIO3__FUNC_MRG_DI (MTK_PIN_NO(3) | 1) +#define PINMUX_GPIO3__FUNC_PCM0_DI (MTK_PIN_NO(3) | 2) +#define PINMUX_GPIO3__FUNC_TP_GPIO3_AO (MTK_PIN_NO(3) | 3) +#define PINMUX_GPIO3__FUNC_SDA6 (MTK_PIN_NO(3) | 4) +#define PINMUX_GPIO3__FUNC_TDM_MCK (MTK_PIN_NO(3) | 5) +#define PINMUX_GPIO3__FUNC_I2S3_DO (MTK_PIN_NO(3) | 6) +#define PINMUX_GPIO3__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(3) | 7) + +#define PINMUX_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define PINMUX_GPIO4__FUNC_PWM_B (MTK_PIN_NO(4) | 1) +#define PINMUX_GPIO4__FUNC_I2S0_MCK (MTK_PIN_NO(4) | 2) +#define PINMUX_GPIO4__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(4) | 3) +#define PINMUX_GPIO4__FUNC_MD_URXD1 (MTK_PIN_NO(4) | 4) +#define PINMUX_GPIO4__FUNC_TDM_BCK (MTK_PIN_NO(4) | 5) +#define PINMUX_GPIO4__FUNC_TP_GPIO4_AO (MTK_PIN_NO(4) | 6) +#define PINMUX_GPIO4__FUNC_DAP_MD32_SWD (MTK_PIN_NO(4) | 7) + +#define PINMUX_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define PINMUX_GPIO5__FUNC_PWM_C (MTK_PIN_NO(5) | 1) +#define PINMUX_GPIO5__FUNC_I2S0_BCK (MTK_PIN_NO(5) | 2) +#define PINMUX_GPIO5__FUNC_SSPM_URXD_AO (MTK_PIN_NO(5) | 3) +#define PINMUX_GPIO5__FUNC_MD_UTXD1 (MTK_PIN_NO(5) | 4) +#define PINMUX_GPIO5__FUNC_TDM_LRCK (MTK_PIN_NO(5) | 5) +#define PINMUX_GPIO5__FUNC_TP_GPIO5_AO (MTK_PIN_NO(5) | 6) +#define PINMUX_GPIO5__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(5) | 7) + +#define PINMUX_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define PINMUX_GPIO6__FUNC_PWM_A (MTK_PIN_NO(6) | 1) +#define PINMUX_GPIO6__FUNC_I2S0_LRCK (MTK_PIN_NO(6) | 2) +#define PINMUX_GPIO6__FUNC_IDDIG (MTK_PIN_NO(6) | 3) +#define PINMUX_GPIO6__FUNC_MD_URXD0 (MTK_PIN_NO(6) | 4) +#define PINMUX_GPIO6__FUNC_TDM_DATA0 (MTK_PIN_NO(6) | 5) +#define PINMUX_GPIO6__FUNC_TP_GPIO6_AO (MTK_PIN_NO(6) | 6) +#define PINMUX_GPIO6__FUNC_CMFLASH (MTK_PIN_NO(6) | 7) + +#define PINMUX_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +#define PINMUX_GPIO7__FUNC_SPI1_B_MI (MTK_PIN_NO(7) | 1) +#define PINMUX_GPIO7__FUNC_I2S0_DI (MTK_PIN_NO(7) | 2) +#define PINMUX_GPIO7__FUNC_USB_DRVVBUS (MTK_PIN_NO(7) | 3) +#define PINMUX_GPIO7__FUNC_MD_UTXD0 (MTK_PIN_NO(7) | 4) +#define PINMUX_GPIO7__FUNC_TDM_DATA1 (MTK_PIN_NO(7) | 5) +#define PINMUX_GPIO7__FUNC_TP_GPIO7_AO (MTK_PIN_NO(7) | 6) +#define PINMUX_GPIO7__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(7) | 7) + +#define PINMUX_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +#define PINMUX_GPIO8__FUNC_SPI1_B_CSB (MTK_PIN_NO(8) | 1) +#define PINMUX_GPIO8__FUNC_ANT_SEL3 (MTK_PIN_NO(8) | 2) +#define PINMUX_GPIO8__FUNC_SCL7 (MTK_PIN_NO(8) | 3) +#define PINMUX_GPIO8__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(8) | 4) +#define PINMUX_GPIO8__FUNC_TDM_DATA2 (MTK_PIN_NO(8) | 5) +#define PINMUX_GPIO8__FUNC_MD_INT0 (MTK_PIN_NO(8) | 6) +#define PINMUX_GPIO8__FUNC_JTRSTN_SEL1 (MTK_PIN_NO(8) | 7) + +#define PINMUX_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +#define PINMUX_GPIO9__FUNC_SPI1_B_MO (MTK_PIN_NO(9) | 1) +#define PINMUX_GPIO9__FUNC_ANT_SEL4 (MTK_PIN_NO(9) | 2) +#define PINMUX_GPIO9__FUNC_CMMCLK2 (MTK_PIN_NO(9) | 3) +#define PINMUX_GPIO9__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(9) | 4) +#define PINMUX_GPIO9__FUNC_SSPM_JTAG_TRSTN (MTK_PIN_NO(9) | 5) +#define PINMUX_GPIO9__FUNC_IO_JTAG_TRSTN (MTK_PIN_NO(9) | 6) +#define PINMUX_GPIO9__FUNC_DBG_MON_B10 (MTK_PIN_NO(9) | 7) + +#define PINMUX_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +#define PINMUX_GPIO10__FUNC_SPI1_B_CLK (MTK_PIN_NO(10) | 1) +#define PINMUX_GPIO10__FUNC_ANT_SEL5 (MTK_PIN_NO(10) | 2) +#define PINMUX_GPIO10__FUNC_CMMCLK3 (MTK_PIN_NO(10) | 3) +#define PINMUX_GPIO10__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(10) | 4) +#define PINMUX_GPIO10__FUNC_TDM_DATA3 (MTK_PIN_NO(10) | 5) +#define PINMUX_GPIO10__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(10) | 6) +#define PINMUX_GPIO10__FUNC_DBG_MON_B11 (MTK_PIN_NO(10) | 7) + +#define PINMUX_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +#define PINMUX_GPIO11__FUNC_TP_URXD1_AO (MTK_PIN_NO(11) | 1) +#define PINMUX_GPIO11__FUNC_IDDIG (MTK_PIN_NO(11) | 2) +#define PINMUX_GPIO11__FUNC_SCL6 (MTK_PIN_NO(11) | 3) +#define PINMUX_GPIO11__FUNC_UCTS1 (MTK_PIN_NO(11) | 4) +#define PINMUX_GPIO11__FUNC_UCTS0 (MTK_PIN_NO(11) | 5) +#define PINMUX_GPIO11__FUNC_SRCLKENAI1 (MTK_PIN_NO(11) | 6) +#define PINMUX_GPIO11__FUNC_I2S5_MCK (MTK_PIN_NO(11) | 7) + +#define PINMUX_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +#define PINMUX_GPIO12__FUNC_TP_UTXD1_AO (MTK_PIN_NO(12) | 1) +#define PINMUX_GPIO12__FUNC_USB_DRVVBUS (MTK_PIN_NO(12) | 2) +#define PINMUX_GPIO12__FUNC_SDA6 (MTK_PIN_NO(12) | 3) +#define PINMUX_GPIO12__FUNC_URTS1 (MTK_PIN_NO(12) | 4) +#define PINMUX_GPIO12__FUNC_URTS0 (MTK_PIN_NO(12) | 5) +#define PINMUX_GPIO12__FUNC_I2S2_DI2 (MTK_PIN_NO(12) | 6) +#define PINMUX_GPIO12__FUNC_I2S5_BCK (MTK_PIN_NO(12) | 7) + +#define PINMUX_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) +#define PINMUX_GPIO13__FUNC_DBPI_D0 (MTK_PIN_NO(13) | 1) +#define PINMUX_GPIO13__FUNC_SPI5_MI (MTK_PIN_NO(13) | 2) +#define PINMUX_GPIO13__FUNC_PCM0_SYNC (MTK_PIN_NO(13) | 3) +#define PINMUX_GPIO13__FUNC_MD_URXD0 (MTK_PIN_NO(13) | 4) +#define PINMUX_GPIO13__FUNC_ANT_SEL3 (MTK_PIN_NO(13) | 5) +#define PINMUX_GPIO13__FUNC_I2S0_MCK (MTK_PIN_NO(13) | 6) +#define PINMUX_GPIO13__FUNC_DBG_MON_B15 (MTK_PIN_NO(13) | 7) + +#define PINMUX_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) +#define PINMUX_GPIO14__FUNC_DBPI_D1 (MTK_PIN_NO(14) | 1) +#define PINMUX_GPIO14__FUNC_SPI5_CSB (MTK_PIN_NO(14) | 2) +#define PINMUX_GPIO14__FUNC_PCM0_CLK (MTK_PIN_NO(14) | 3) +#define PINMUX_GPIO14__FUNC_MD_UTXD0 (MTK_PIN_NO(14) | 4) +#define PINMUX_GPIO14__FUNC_ANT_SEL4 (MTK_PIN_NO(14) | 5) +#define PINMUX_GPIO14__FUNC_I2S0_BCK (MTK_PIN_NO(14) | 6) +#define PINMUX_GPIO14__FUNC_DBG_MON_B16 (MTK_PIN_NO(14) | 7) + +#define PINMUX_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) +#define PINMUX_GPIO15__FUNC_DBPI_D2 (MTK_PIN_NO(15) | 1) +#define PINMUX_GPIO15__FUNC_SPI5_MO (MTK_PIN_NO(15) | 2) +#define PINMUX_GPIO15__FUNC_PCM0_DO (MTK_PIN_NO(15) | 3) +#define PINMUX_GPIO15__FUNC_MD_URXD1 (MTK_PIN_NO(15) | 4) +#define PINMUX_GPIO15__FUNC_ANT_SEL5 (MTK_PIN_NO(15) | 5) +#define PINMUX_GPIO15__FUNC_I2S0_LRCK (MTK_PIN_NO(15) | 6) +#define PINMUX_GPIO15__FUNC_DBG_MON_B17 (MTK_PIN_NO(15) | 7) + +#define PINMUX_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) +#define PINMUX_GPIO16__FUNC_DBPI_D3 (MTK_PIN_NO(16) | 1) +#define PINMUX_GPIO16__FUNC_SPI5_CLK (MTK_PIN_NO(16) | 2) +#define PINMUX_GPIO16__FUNC_PCM0_DI (MTK_PIN_NO(16) | 3) +#define PINMUX_GPIO16__FUNC_MD_UTXD1 (MTK_PIN_NO(16) | 4) +#define PINMUX_GPIO16__FUNC_ANT_SEL6 (MTK_PIN_NO(16) | 5) +#define PINMUX_GPIO16__FUNC_I2S0_DI (MTK_PIN_NO(16) | 6) +#define PINMUX_GPIO16__FUNC_DBG_MON_B23 (MTK_PIN_NO(16) | 7) + +#define PINMUX_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) +#define PINMUX_GPIO17__FUNC_DBPI_D4 (MTK_PIN_NO(17) | 1) +#define PINMUX_GPIO17__FUNC_SPI4_MI (MTK_PIN_NO(17) | 2) +#define PINMUX_GPIO17__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(17) | 3) +#define PINMUX_GPIO17__FUNC_MD_INT0 (MTK_PIN_NO(17) | 4) +#define PINMUX_GPIO17__FUNC_ANT_SEL7 (MTK_PIN_NO(17) | 5) +#define PINMUX_GPIO17__FUNC_I2S3_MCK (MTK_PIN_NO(17) | 6) +#define PINMUX_GPIO17__FUNC_DBG_MON_A1 (MTK_PIN_NO(17) | 7) + +#define PINMUX_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) +#define PINMUX_GPIO18__FUNC_DBPI_D5 (MTK_PIN_NO(18) | 1) +#define PINMUX_GPIO18__FUNC_SPI4_CSB (MTK_PIN_NO(18) | 2) +#define PINMUX_GPIO18__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(18) | 3) +#define PINMUX_GPIO18__FUNC_MD_INT0 (MTK_PIN_NO(18) | 4) +#define PINMUX_GPIO18__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(18) | 5) +#define PINMUX_GPIO18__FUNC_I2S3_BCK (MTK_PIN_NO(18) | 6) +#define PINMUX_GPIO18__FUNC_DBG_MON_A2 (MTK_PIN_NO(18) | 7) + +#define PINMUX_GPIO19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) +#define PINMUX_GPIO19__FUNC_DBPI_D6 (MTK_PIN_NO(19) | 1) +#define PINMUX_GPIO19__FUNC_SPI4_MO (MTK_PIN_NO(19) | 2) +#define PINMUX_GPIO19__FUNC_CONN_MCU_TDO (MTK_PIN_NO(19) | 3) +#define PINMUX_GPIO19__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(19) | 4) +#define PINMUX_GPIO19__FUNC_URXD1 (MTK_PIN_NO(19) | 5) +#define PINMUX_GPIO19__FUNC_I2S3_LRCK (MTK_PIN_NO(19) | 6) +#define PINMUX_GPIO19__FUNC_DBG_MON_A3 (MTK_PIN_NO(19) | 7) + +#define PINMUX_GPIO20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) +#define PINMUX_GPIO20__FUNC_DBPI_D7 (MTK_PIN_NO(20) | 1) +#define PINMUX_GPIO20__FUNC_SPI4_CLK (MTK_PIN_NO(20) | 2) +#define PINMUX_GPIO20__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(20) | 3) +#define PINMUX_GPIO20__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(20) | 4) +#define PINMUX_GPIO20__FUNC_UTXD1 (MTK_PIN_NO(20) | 5) +#define PINMUX_GPIO20__FUNC_I2S3_DO (MTK_PIN_NO(20) | 6) +#define PINMUX_GPIO20__FUNC_DBG_MON_A19 (MTK_PIN_NO(20) | 7) + +#define PINMUX_GPIO21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) +#define PINMUX_GPIO21__FUNC_DBPI_D8 (MTK_PIN_NO(21) | 1) +#define PINMUX_GPIO21__FUNC_SPI3_MI (MTK_PIN_NO(21) | 2) +#define PINMUX_GPIO21__FUNC_CONN_MCU_TMS (MTK_PIN_NO(21) | 3) +#define PINMUX_GPIO21__FUNC_DAP_MD32_SWD (MTK_PIN_NO(21) | 4) +#define PINMUX_GPIO21__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(21) | 5) +#define PINMUX_GPIO21__FUNC_I2S2_MCK (MTK_PIN_NO(21) | 6) +#define PINMUX_GPIO21__FUNC_DBG_MON_B5 (MTK_PIN_NO(21) | 7) + +#define PINMUX_GPIO22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) +#define PINMUX_GPIO22__FUNC_DBPI_D9 (MTK_PIN_NO(22) | 1) +#define PINMUX_GPIO22__FUNC_SPI3_CSB (MTK_PIN_NO(22) | 2) +#define PINMUX_GPIO22__FUNC_CONN_MCU_TCK (MTK_PIN_NO(22) | 3) +#define PINMUX_GPIO22__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(22) | 4) +#define PINMUX_GPIO22__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(22) | 5) +#define PINMUX_GPIO22__FUNC_I2S2_BCK (MTK_PIN_NO(22) | 6) +#define PINMUX_GPIO22__FUNC_DBG_MON_B6 (MTK_PIN_NO(22) | 7) + +#define PINMUX_GPIO23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) +#define PINMUX_GPIO23__FUNC_DBPI_D10 (MTK_PIN_NO(23) | 1) +#define PINMUX_GPIO23__FUNC_SPI3_MO (MTK_PIN_NO(23) | 2) +#define PINMUX_GPIO23__FUNC_CONN_MCU_TDI (MTK_PIN_NO(23) | 3) +#define PINMUX_GPIO23__FUNC_UCTS1 (MTK_PIN_NO(23) | 4) +#define PINMUX_GPIO23__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(23) | 5) +#define PINMUX_GPIO23__FUNC_I2S2_LRCK (MTK_PIN_NO(23) | 6) +#define PINMUX_GPIO23__FUNC_DBG_MON_B7 (MTK_PIN_NO(23) | 7) + +#define PINMUX_GPIO24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) +#define PINMUX_GPIO24__FUNC_DBPI_D11 (MTK_PIN_NO(24) | 1) +#define PINMUX_GPIO24__FUNC_SPI3_CLK (MTK_PIN_NO(24) | 2) +#define PINMUX_GPIO24__FUNC_SRCLKENAI0 (MTK_PIN_NO(24) | 3) +#define PINMUX_GPIO24__FUNC_URTS1 (MTK_PIN_NO(24) | 4) +#define PINMUX_GPIO24__FUNC_IO_JTAG_TCK (MTK_PIN_NO(24) | 5) +#define PINMUX_GPIO24__FUNC_I2S2_DI (MTK_PIN_NO(24) | 6) +#define PINMUX_GPIO24__FUNC_DBG_MON_B31 (MTK_PIN_NO(24) | 7) + +#define PINMUX_GPIO25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) +#define PINMUX_GPIO25__FUNC_DBPI_HSYNC (MTK_PIN_NO(25) | 1) +#define PINMUX_GPIO25__FUNC_ANT_SEL0 (MTK_PIN_NO(25) | 2) +#define PINMUX_GPIO25__FUNC_SCL6 (MTK_PIN_NO(25) | 3) +#define PINMUX_GPIO25__FUNC_KPCOL2 (MTK_PIN_NO(25) | 4) +#define PINMUX_GPIO25__FUNC_IO_JTAG_TMS (MTK_PIN_NO(25) | 5) +#define PINMUX_GPIO25__FUNC_I2S1_MCK (MTK_PIN_NO(25) | 6) +#define PINMUX_GPIO25__FUNC_DBG_MON_B0 (MTK_PIN_NO(25) | 7) + +#define PINMUX_GPIO26__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) +#define PINMUX_GPIO26__FUNC_DBPI_VSYNC (MTK_PIN_NO(26) | 1) +#define PINMUX_GPIO26__FUNC_ANT_SEL1 (MTK_PIN_NO(26) | 2) +#define PINMUX_GPIO26__FUNC_SDA6 (MTK_PIN_NO(26) | 3) +#define PINMUX_GPIO26__FUNC_KPROW2 (MTK_PIN_NO(26) | 4) +#define PINMUX_GPIO26__FUNC_IO_JTAG_TDI (MTK_PIN_NO(26) | 5) +#define PINMUX_GPIO26__FUNC_I2S1_BCK (MTK_PIN_NO(26) | 6) +#define PINMUX_GPIO26__FUNC_DBG_MON_B1 (MTK_PIN_NO(26) | 7) + +#define PINMUX_GPIO27__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) +#define PINMUX_GPIO27__FUNC_DBPI_DE (MTK_PIN_NO(27) | 1) +#define PINMUX_GPIO27__FUNC_ANT_SEL2 (MTK_PIN_NO(27) | 2) +#define PINMUX_GPIO27__FUNC_SCL7 (MTK_PIN_NO(27) | 3) +#define PINMUX_GPIO27__FUNC_DMIC_CLK (MTK_PIN_NO(27) | 4) +#define PINMUX_GPIO27__FUNC_IO_JTAG_TDO (MTK_PIN_NO(27) | 5) +#define PINMUX_GPIO27__FUNC_I2S1_LRCK (MTK_PIN_NO(27) | 6) +#define PINMUX_GPIO27__FUNC_DBG_MON_B9 (MTK_PIN_NO(27) | 7) + +#define PINMUX_GPIO28__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) +#define PINMUX_GPIO28__FUNC_DBPI_CK (MTK_PIN_NO(28) | 1) +#define PINMUX_GPIO28__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(28) | 2) +#define PINMUX_GPIO28__FUNC_SDA7 (MTK_PIN_NO(28) | 3) +#define PINMUX_GPIO28__FUNC_DMIC_DAT (MTK_PIN_NO(28) | 4) +#define PINMUX_GPIO28__FUNC_IO_JTAG_TRSTN (MTK_PIN_NO(28) | 5) +#define PINMUX_GPIO28__FUNC_I2S1_DO (MTK_PIN_NO(28) | 6) +#define PINMUX_GPIO28__FUNC_DBG_MON_B32 (MTK_PIN_NO(28) | 7) + +#define PINMUX_GPIO29__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) +#define PINMUX_GPIO29__FUNC_MSDC1_CLK (MTK_PIN_NO(29) | 1) +#define PINMUX_GPIO29__FUNC_IO_JTAG_TCK (MTK_PIN_NO(29) | 2) +#define PINMUX_GPIO29__FUNC_UDI_TCK (MTK_PIN_NO(29) | 3) +#define PINMUX_GPIO29__FUNC_CONN_DSP_JCK (MTK_PIN_NO(29) | 4) +#define PINMUX_GPIO29__FUNC_SSPM_JTAG_TCK (MTK_PIN_NO(29) | 5) +#define PINMUX_GPIO29__FUNC_PCM1_CLK (MTK_PIN_NO(29) | 6) +#define PINMUX_GPIO29__FUNC_DBG_MON_A6 (MTK_PIN_NO(29) | 7) + +#define PINMUX_GPIO30__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) +#define PINMUX_GPIO30__FUNC_MSDC1_DAT3 (MTK_PIN_NO(30) | 1) +#define PINMUX_GPIO30__FUNC_DAP_MD32_SWD (MTK_PIN_NO(30) | 2) +#define PINMUX_GPIO30__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(30) | 3) +#define PINMUX_GPIO30__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(30) | 4) +#define PINMUX_GPIO30__FUNC_SSPM_JTAG_TRSTN (MTK_PIN_NO(30) | 5) +#define PINMUX_GPIO30__FUNC_PCM1_DI (MTK_PIN_NO(30) | 6) +#define PINMUX_GPIO30__FUNC_DBG_MON_A7 (MTK_PIN_NO(30) | 7) + +#define PINMUX_GPIO31__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) +#define PINMUX_GPIO31__FUNC_MSDC1_CMD (MTK_PIN_NO(31) | 1) +#define PINMUX_GPIO31__FUNC_IO_JTAG_TMS (MTK_PIN_NO(31) | 2) +#define PINMUX_GPIO31__FUNC_UDI_TMS (MTK_PIN_NO(31) | 3) +#define PINMUX_GPIO31__FUNC_CONN_DSP_JMS (MTK_PIN_NO(31) | 4) +#define PINMUX_GPIO31__FUNC_SSPM_JTAG_TMS (MTK_PIN_NO(31) | 5) +#define PINMUX_GPIO31__FUNC_PCM1_SYNC (MTK_PIN_NO(31) | 6) +#define PINMUX_GPIO31__FUNC_DBG_MON_A8 (MTK_PIN_NO(31) | 7) + +#define PINMUX_GPIO32__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) +#define PINMUX_GPIO32__FUNC_MSDC1_DAT0 (MTK_PIN_NO(32) | 1) +#define PINMUX_GPIO32__FUNC_IO_JTAG_TDI (MTK_PIN_NO(32) | 2) +#define PINMUX_GPIO32__FUNC_UDI_TDI (MTK_PIN_NO(32) | 3) +#define PINMUX_GPIO32__FUNC_CONN_DSP_JDI (MTK_PIN_NO(32) | 4) +#define PINMUX_GPIO32__FUNC_SSPM_JTAG_TDI (MTK_PIN_NO(32) | 5) +#define PINMUX_GPIO32__FUNC_PCM1_DO0 (MTK_PIN_NO(32) | 6) +#define PINMUX_GPIO32__FUNC_DBG_MON_A9 (MTK_PIN_NO(32) | 7) + +#define PINMUX_GPIO33__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) +#define PINMUX_GPIO33__FUNC_MSDC1_DAT2 (MTK_PIN_NO(33) | 1) +#define PINMUX_GPIO33__FUNC_IO_JTAG_TRSTN (MTK_PIN_NO(33) | 2) +#define PINMUX_GPIO33__FUNC_UDI_NTRST (MTK_PIN_NO(33) | 3) +#define PINMUX_GPIO33__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(33) | 4) +#define PINMUX_GPIO33__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(33) | 5) +#define PINMUX_GPIO33__FUNC_PCM1_DO2 (MTK_PIN_NO(33) | 6) +#define PINMUX_GPIO33__FUNC_DBG_MON_A10 (MTK_PIN_NO(33) | 7) + +#define PINMUX_GPIO34__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) +#define PINMUX_GPIO34__FUNC_MSDC1_DAT1 (MTK_PIN_NO(34) | 1) +#define PINMUX_GPIO34__FUNC_IO_JTAG_TDO (MTK_PIN_NO(34) | 2) +#define PINMUX_GPIO34__FUNC_UDI_TDO (MTK_PIN_NO(34) | 3) +#define PINMUX_GPIO34__FUNC_CONN_DSP_JDO (MTK_PIN_NO(34) | 4) +#define PINMUX_GPIO34__FUNC_SSPM_JTAG_TDO (MTK_PIN_NO(34) | 5) +#define PINMUX_GPIO34__FUNC_PCM1_DO1 (MTK_PIN_NO(34) | 6) +#define PINMUX_GPIO34__FUNC_DBG_MON_A11 (MTK_PIN_NO(34) | 7) + +#define PINMUX_GPIO35__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) +#define PINMUX_GPIO35__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(35) | 1) +#define PINMUX_GPIO35__FUNC_CCU_JTAG_TDO (MTK_PIN_NO(35) | 2) +#define PINMUX_GPIO35__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(35) | 3) +#define PINMUX_GPIO35__FUNC_SCP_JTAG_TDO (MTK_PIN_NO(35) | 5) +#define PINMUX_GPIO35__FUNC_CONN_DSP_JMS (MTK_PIN_NO(35) | 6) +#define PINMUX_GPIO35__FUNC_DBG_MON_A28 (MTK_PIN_NO(35) | 7) + +#define PINMUX_GPIO36__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) +#define PINMUX_GPIO36__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(36) | 1) +#define PINMUX_GPIO36__FUNC_CCU_JTAG_TMS (MTK_PIN_NO(36) | 2) +#define PINMUX_GPIO36__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(36) | 3) +#define PINMUX_GPIO36__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(36) | 4) +#define PINMUX_GPIO36__FUNC_SCP_JTAG_TMS (MTK_PIN_NO(36) | 5) +#define PINMUX_GPIO36__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(36) | 6) +#define PINMUX_GPIO36__FUNC_DBG_MON_A29 (MTK_PIN_NO(36) | 7) + +#define PINMUX_GPIO37__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) +#define PINMUX_GPIO37__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(37) | 1) +#define PINMUX_GPIO37__FUNC_CCU_JTAG_TDI (MTK_PIN_NO(37) | 2) +#define PINMUX_GPIO37__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(37) | 3) +#define PINMUX_GPIO37__FUNC_SCP_JTAG_TDI (MTK_PIN_NO(37) | 5) +#define PINMUX_GPIO37__FUNC_CONN_DSP_JDO (MTK_PIN_NO(37) | 6) +#define PINMUX_GPIO37__FUNC_DBG_MON_A30 (MTK_PIN_NO(37) | 7) + +#define PINMUX_GPIO38__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) +#define PINMUX_GPIO38__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(38) | 1) +#define PINMUX_GPIO38__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(38) | 3) +#define PINMUX_GPIO38__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(38) | 4) +#define PINMUX_GPIO38__FUNC_DBG_MON_A20 (MTK_PIN_NO(38) | 7) + +#define PINMUX_GPIO39__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) +#define PINMUX_GPIO39__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(39) | 1) +#define PINMUX_GPIO39__FUNC_CCU_JTAG_TCK (MTK_PIN_NO(39) | 2) +#define PINMUX_GPIO39__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(39) | 3) +#define PINMUX_GPIO39__FUNC_SCP_JTAG_TCK (MTK_PIN_NO(39) | 5) +#define PINMUX_GPIO39__FUNC_CONN_DSP_JCK (MTK_PIN_NO(39) | 6) +#define PINMUX_GPIO39__FUNC_DBG_MON_A31 (MTK_PIN_NO(39) | 7) + +#define PINMUX_GPIO40__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) +#define PINMUX_GPIO40__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(40) | 1) +#define PINMUX_GPIO40__FUNC_CCU_JTAG_TRST (MTK_PIN_NO(40) | 2) +#define PINMUX_GPIO40__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(40) | 3) +#define PINMUX_GPIO40__FUNC_SCP_JTAG_TRSTN (MTK_PIN_NO(40) | 5) +#define PINMUX_GPIO40__FUNC_CONN_DSP_JDI (MTK_PIN_NO(40) | 6) +#define PINMUX_GPIO40__FUNC_DBG_MON_A32 (MTK_PIN_NO(40) | 7) + +#define PINMUX_GPIO41__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) +#define PINMUX_GPIO41__FUNC_IDDIG (MTK_PIN_NO(41) | 1) +#define PINMUX_GPIO41__FUNC_URXD1 (MTK_PIN_NO(41) | 2) +#define PINMUX_GPIO41__FUNC_UCTS0 (MTK_PIN_NO(41) | 3) +#define PINMUX_GPIO41__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(41) | 4) +#define PINMUX_GPIO41__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(41) | 5) +#define PINMUX_GPIO41__FUNC_DMIC_CLK (MTK_PIN_NO(41) | 6) + +#define PINMUX_GPIO42__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) +#define PINMUX_GPIO42__FUNC_USB_DRVVBUS (MTK_PIN_NO(42) | 1) +#define PINMUX_GPIO42__FUNC_UTXD1 (MTK_PIN_NO(42) | 2) +#define PINMUX_GPIO42__FUNC_URTS0 (MTK_PIN_NO(42) | 3) +#define PINMUX_GPIO42__FUNC_SSPM_URXD_AO (MTK_PIN_NO(42) | 4) +#define PINMUX_GPIO42__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(42) | 5) +#define PINMUX_GPIO42__FUNC_DMIC_DAT (MTK_PIN_NO(42) | 6) + +#define PINMUX_GPIO43__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) +#define PINMUX_GPIO43__FUNC_DISP_PWM (MTK_PIN_NO(43) | 1) + +#define PINMUX_GPIO44__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) +#define PINMUX_GPIO44__FUNC_DSI_TE (MTK_PIN_NO(44) | 1) + +#define PINMUX_GPIO45__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) +#define PINMUX_GPIO45__FUNC_LCM_RST (MTK_PIN_NO(45) | 1) + +#define PINMUX_GPIO46__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) +#define PINMUX_GPIO46__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(46) | 1) +#define PINMUX_GPIO46__FUNC_URXD1 (MTK_PIN_NO(46) | 2) +#define PINMUX_GPIO46__FUNC_UCTS1 (MTK_PIN_NO(46) | 3) +#define PINMUX_GPIO46__FUNC_CCU_UTXD_AO (MTK_PIN_NO(46) | 4) +#define PINMUX_GPIO46__FUNC_TP_UCTS1_AO (MTK_PIN_NO(46) | 5) +#define PINMUX_GPIO46__FUNC_IDDIG (MTK_PIN_NO(46) | 6) +#define PINMUX_GPIO46__FUNC_I2S5_LRCK (MTK_PIN_NO(46) | 7) + +#define PINMUX_GPIO47__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) +#define PINMUX_GPIO47__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(47) | 1) +#define PINMUX_GPIO47__FUNC_UTXD1 (MTK_PIN_NO(47) | 2) +#define PINMUX_GPIO47__FUNC_URTS1 (MTK_PIN_NO(47) | 3) +#define PINMUX_GPIO47__FUNC_CCU_URXD_AO (MTK_PIN_NO(47) | 4) +#define PINMUX_GPIO47__FUNC_TP_URTS1_AO (MTK_PIN_NO(47) | 5) +#define PINMUX_GPIO47__FUNC_USB_DRVVBUS (MTK_PIN_NO(47) | 6) +#define PINMUX_GPIO47__FUNC_I2S5_DO (MTK_PIN_NO(47) | 7) + +#define PINMUX_GPIO48__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) +#define PINMUX_GPIO48__FUNC_SCL5 (MTK_PIN_NO(48) | 1) + +#define PINMUX_GPIO49__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) +#define PINMUX_GPIO49__FUNC_SDA5 (MTK_PIN_NO(49) | 1) + +#define PINMUX_GPIO50__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) +#define PINMUX_GPIO50__FUNC_SCL3 (MTK_PIN_NO(50) | 1) + +#define PINMUX_GPIO51__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) +#define PINMUX_GPIO51__FUNC_SDA3 (MTK_PIN_NO(51) | 1) + +#define PINMUX_GPIO52__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) +#define PINMUX_GPIO52__FUNC_BPI_ANT2 (MTK_PIN_NO(52) | 1) + +#define PINMUX_GPIO53__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) +#define PINMUX_GPIO53__FUNC_BPI_ANT0 (MTK_PIN_NO(53) | 1) + +#define PINMUX_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) +#define PINMUX_GPIO54__FUNC_BPI_OLAT1 (MTK_PIN_NO(54) | 1) + +#define PINMUX_GPIO55__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) +#define PINMUX_GPIO55__FUNC_BPI_BUS8 (MTK_PIN_NO(55) | 1) + +#define PINMUX_GPIO56__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) +#define PINMUX_GPIO56__FUNC_BPI_BUS9 (MTK_PIN_NO(56) | 1) +#define PINMUX_GPIO56__FUNC_SCL_6306 (MTK_PIN_NO(56) | 2) + +#define PINMUX_GPIO57__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) +#define PINMUX_GPIO57__FUNC_BPI_BUS10 (MTK_PIN_NO(57) | 1) +#define PINMUX_GPIO57__FUNC_SDA_6306 (MTK_PIN_NO(57) | 2) + +#define PINMUX_GPIO58__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) +#define PINMUX_GPIO58__FUNC_RFIC0_BSI_D2 (MTK_PIN_NO(58) | 1) +#define PINMUX_GPIO58__FUNC_SPM_BSI_D2 (MTK_PIN_NO(58) | 2) +#define PINMUX_GPIO58__FUNC_PWM_B (MTK_PIN_NO(58) | 3) + +#define PINMUX_GPIO59__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) +#define PINMUX_GPIO59__FUNC_RFIC0_BSI_D1 (MTK_PIN_NO(59) | 1) +#define PINMUX_GPIO59__FUNC_SPM_BSI_D1 (MTK_PIN_NO(59) | 2) + +#define PINMUX_GPIO60__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) +#define PINMUX_GPIO60__FUNC_RFIC0_BSI_D0 (MTK_PIN_NO(60) | 1) +#define PINMUX_GPIO60__FUNC_SPM_BSI_D0 (MTK_PIN_NO(60) | 2) + +#define PINMUX_GPIO61__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) +#define PINMUX_GPIO61__FUNC_MIPI1_SDATA (MTK_PIN_NO(61) | 1) + +#define PINMUX_GPIO62__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) +#define PINMUX_GPIO62__FUNC_MIPI1_SCLK (MTK_PIN_NO(62) | 1) + +#define PINMUX_GPIO63__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) +#define PINMUX_GPIO63__FUNC_MIPI0_SDATA (MTK_PIN_NO(63) | 1) + +#define PINMUX_GPIO64__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) +#define PINMUX_GPIO64__FUNC_MIPI0_SCLK (MTK_PIN_NO(64) | 1) + +#define PINMUX_GPIO65__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) +#define PINMUX_GPIO65__FUNC_MIPI3_SDATA (MTK_PIN_NO(65) | 1) +#define PINMUX_GPIO65__FUNC_BPI_OLAT2 (MTK_PIN_NO(65) | 2) + +#define PINMUX_GPIO66__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) +#define PINMUX_GPIO66__FUNC_MIPI3_SCLK (MTK_PIN_NO(66) | 1) +#define PINMUX_GPIO66__FUNC_BPI_OLAT3 (MTK_PIN_NO(66) | 2) + +#define PINMUX_GPIO67__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) +#define PINMUX_GPIO67__FUNC_MIPI2_SDATA (MTK_PIN_NO(67) | 1) + +#define PINMUX_GPIO68__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) +#define PINMUX_GPIO68__FUNC_MIPI2_SCLK (MTK_PIN_NO(68) | 1) + +#define PINMUX_GPIO69__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) +#define PINMUX_GPIO69__FUNC_BPI_BUS7 (MTK_PIN_NO(69) | 1) + +#define PINMUX_GPIO70__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) +#define PINMUX_GPIO70__FUNC_BPI_BUS6 (MTK_PIN_NO(70) | 1) + +#define PINMUX_GPIO71__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) +#define PINMUX_GPIO71__FUNC_BPI_BUS5 (MTK_PIN_NO(71) | 1) + +#define PINMUX_GPIO72__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) +#define PINMUX_GPIO72__FUNC_BPI_BUS4 (MTK_PIN_NO(72) | 1) + +#define PINMUX_GPIO73__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) +#define PINMUX_GPIO73__FUNC_BPI_BUS3 (MTK_PIN_NO(73) | 1) + +#define PINMUX_GPIO74__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) +#define PINMUX_GPIO74__FUNC_BPI_BUS2 (MTK_PIN_NO(74) | 1) + +#define PINMUX_GPIO75__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) +#define PINMUX_GPIO75__FUNC_BPI_BUS1 (MTK_PIN_NO(75) | 1) + +#define PINMUX_GPIO76__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) +#define PINMUX_GPIO76__FUNC_BPI_BUS0 (MTK_PIN_NO(76) | 1) + +#define PINMUX_GPIO77__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) +#define PINMUX_GPIO77__FUNC_BPI_ANT1 (MTK_PIN_NO(77) | 1) + +#define PINMUX_GPIO78__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) +#define PINMUX_GPIO78__FUNC_BPI_OLAT0 (MTK_PIN_NO(78) | 1) + +#define PINMUX_GPIO79__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) +#define PINMUX_GPIO79__FUNC_BPI_PA_VM1 (MTK_PIN_NO(79) | 1) +#define PINMUX_GPIO79__FUNC_MIPI4_SDATA (MTK_PIN_NO(79) | 2) + +#define PINMUX_GPIO80__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) +#define PINMUX_GPIO80__FUNC_BPI_PA_VM0 (MTK_PIN_NO(80) | 1) +#define PINMUX_GPIO80__FUNC_MIPI4_SCLK (MTK_PIN_NO(80) | 2) + +#define PINMUX_GPIO81__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) +#define PINMUX_GPIO81__FUNC_SDA1 (MTK_PIN_NO(81) | 1) + +#define PINMUX_GPIO82__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) +#define PINMUX_GPIO82__FUNC_SDA0 (MTK_PIN_NO(82) | 1) + +#define PINMUX_GPIO83__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) +#define PINMUX_GPIO83__FUNC_SCL0 (MTK_PIN_NO(83) | 1) + +#define PINMUX_GPIO84__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) +#define PINMUX_GPIO84__FUNC_SCL1 (MTK_PIN_NO(84) | 1) + +#define PINMUX_GPIO85__FUNC_GPIO85 (MTK_PIN_NO(85) | 0) +#define PINMUX_GPIO85__FUNC_SPI0_MI (MTK_PIN_NO(85) | 1) +#define PINMUX_GPIO85__FUNC_SCP_SPI0_MI (MTK_PIN_NO(85) | 2) +#define PINMUX_GPIO85__FUNC_CLKM3 (MTK_PIN_NO(85) | 3) +#define PINMUX_GPIO85__FUNC_I2S1_BCK (MTK_PIN_NO(85) | 4) +#define PINMUX_GPIO85__FUNC_MFG_DFD_JTAG_TDO (MTK_PIN_NO(85) | 5) +#define PINMUX_GPIO85__FUNC_DFD_TDO (MTK_PIN_NO(85) | 6) +#define PINMUX_GPIO85__FUNC_JTDO_SEL1 (MTK_PIN_NO(85) | 7) + +#define PINMUX_GPIO86__FUNC_GPIO86 (MTK_PIN_NO(86) | 0) +#define PINMUX_GPIO86__FUNC_SPI0_CSB (MTK_PIN_NO(86) | 1) +#define PINMUX_GPIO86__FUNC_SCP_SPI0_CS (MTK_PIN_NO(86) | 2) +#define PINMUX_GPIO86__FUNC_CLKM0 (MTK_PIN_NO(86) | 3) +#define PINMUX_GPIO86__FUNC_I2S1_LRCK (MTK_PIN_NO(86) | 4) +#define PINMUX_GPIO86__FUNC_MFG_DFD_JTAG_TMS (MTK_PIN_NO(86) | 5) +#define PINMUX_GPIO86__FUNC_DFD_TMS (MTK_PIN_NO(86) | 6) +#define PINMUX_GPIO86__FUNC_JTMS_SEL1 (MTK_PIN_NO(86) | 7) + +#define PINMUX_GPIO87__FUNC_GPIO87 (MTK_PIN_NO(87) | 0) +#define PINMUX_GPIO87__FUNC_SPI0_MO (MTK_PIN_NO(87) | 1) +#define PINMUX_GPIO87__FUNC_SCP_SPI0_MO (MTK_PIN_NO(87) | 2) +#define PINMUX_GPIO87__FUNC_SDA1 (MTK_PIN_NO(87) | 3) +#define PINMUX_GPIO87__FUNC_I2S1_DO (MTK_PIN_NO(87) | 4) +#define PINMUX_GPIO87__FUNC_MFG_DFD_JTAG_TDI (MTK_PIN_NO(87) | 5) +#define PINMUX_GPIO87__FUNC_DFD_TDI (MTK_PIN_NO(87) | 6) +#define PINMUX_GPIO87__FUNC_JTDI_SEL1 (MTK_PIN_NO(87) | 7) + +#define PINMUX_GPIO88__FUNC_GPIO88 (MTK_PIN_NO(88) | 0) +#define PINMUX_GPIO88__FUNC_SPI0_CLK (MTK_PIN_NO(88) | 1) +#define PINMUX_GPIO88__FUNC_SCP_SPI0_CK (MTK_PIN_NO(88) | 2) +#define PINMUX_GPIO88__FUNC_SCL1 (MTK_PIN_NO(88) | 3) +#define PINMUX_GPIO88__FUNC_I2S1_MCK (MTK_PIN_NO(88) | 4) +#define PINMUX_GPIO88__FUNC_MFG_DFD_JTAG_TCK (MTK_PIN_NO(88) | 5) +#define PINMUX_GPIO88__FUNC_DFD_TCK_XI (MTK_PIN_NO(88) | 6) +#define PINMUX_GPIO88__FUNC_JTCK_SEL1 (MTK_PIN_NO(88) | 7) + +#define PINMUX_GPIO89__FUNC_GPIO89 (MTK_PIN_NO(89) | 0) +#define PINMUX_GPIO89__FUNC_SRCLKENAI0 (MTK_PIN_NO(89) | 1) +#define PINMUX_GPIO89__FUNC_PWM_C (MTK_PIN_NO(89) | 2) +#define PINMUX_GPIO89__FUNC_I2S5_BCK (MTK_PIN_NO(89) | 3) +#define PINMUX_GPIO89__FUNC_ANT_SEL6 (MTK_PIN_NO(89) | 4) +#define PINMUX_GPIO89__FUNC_SDA8 (MTK_PIN_NO(89) | 5) +#define PINMUX_GPIO89__FUNC_CMVREF0 (MTK_PIN_NO(89) | 6) +#define PINMUX_GPIO89__FUNC_DBG_MON_A21 (MTK_PIN_NO(89) | 7) + +#define PINMUX_GPIO90__FUNC_GPIO90 (MTK_PIN_NO(90) | 0) +#define PINMUX_GPIO90__FUNC_PWM_A (MTK_PIN_NO(90) | 1) +#define PINMUX_GPIO90__FUNC_CMMCLK2 (MTK_PIN_NO(90) | 2) +#define PINMUX_GPIO90__FUNC_I2S5_LRCK (MTK_PIN_NO(90) | 3) +#define PINMUX_GPIO90__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(90) | 4) +#define PINMUX_GPIO90__FUNC_SCL8 (MTK_PIN_NO(90) | 5) +#define PINMUX_GPIO90__FUNC_PTA_RXD (MTK_PIN_NO(90) | 6) +#define PINMUX_GPIO90__FUNC_DBG_MON_A22 (MTK_PIN_NO(90) | 7) + +#define PINMUX_GPIO91__FUNC_GPIO91 (MTK_PIN_NO(91) | 0) +#define PINMUX_GPIO91__FUNC_KPROW1 (MTK_PIN_NO(91) | 1) +#define PINMUX_GPIO91__FUNC_PWM_B (MTK_PIN_NO(91) | 2) +#define PINMUX_GPIO91__FUNC_I2S5_DO (MTK_PIN_NO(91) | 3) +#define PINMUX_GPIO91__FUNC_ANT_SEL7 (MTK_PIN_NO(91) | 4) +#define PINMUX_GPIO91__FUNC_CMMCLK3 (MTK_PIN_NO(91) | 5) +#define PINMUX_GPIO91__FUNC_PTA_TXD (MTK_PIN_NO(91) | 6) + +#define PINMUX_GPIO92__FUNC_GPIO92 (MTK_PIN_NO(92) | 0) +#define PINMUX_GPIO92__FUNC_KPROW0 (MTK_PIN_NO(92) | 1) + +#define PINMUX_GPIO93__FUNC_GPIO93 (MTK_PIN_NO(93) | 0) +#define PINMUX_GPIO93__FUNC_KPCOL0 (MTK_PIN_NO(93) | 1) +#define PINMUX_GPIO93__FUNC_DBG_MON_B27 (MTK_PIN_NO(93) | 7) + +#define PINMUX_GPIO94__FUNC_GPIO94 (MTK_PIN_NO(94) | 0) +#define PINMUX_GPIO94__FUNC_KPCOL1 (MTK_PIN_NO(94) | 1) +#define PINMUX_GPIO94__FUNC_I2S2_DI2 (MTK_PIN_NO(94) | 2) +#define PINMUX_GPIO94__FUNC_I2S5_MCK (MTK_PIN_NO(94) | 3) +#define PINMUX_GPIO94__FUNC_CMMCLK2 (MTK_PIN_NO(94) | 4) +#define PINMUX_GPIO94__FUNC_SCP_SPI2_MI (MTK_PIN_NO(94) | 5) +#define PINMUX_GPIO94__FUNC_SRCLKENAI1 (MTK_PIN_NO(94) | 6) +#define PINMUX_GPIO94__FUNC_SPI2_MI (MTK_PIN_NO(94) | 7) + +#define PINMUX_GPIO95__FUNC_GPIO95 (MTK_PIN_NO(95) | 0) +#define PINMUX_GPIO95__FUNC_URXD0 (MTK_PIN_NO(95) | 1) +#define PINMUX_GPIO95__FUNC_UTXD0 (MTK_PIN_NO(95) | 2) +#define PINMUX_GPIO95__FUNC_MD_URXD0 (MTK_PIN_NO(95) | 3) +#define PINMUX_GPIO95__FUNC_MD_URXD1 (MTK_PIN_NO(95) | 4) +#define PINMUX_GPIO95__FUNC_SSPM_URXD_AO (MTK_PIN_NO(95) | 5) +#define PINMUX_GPIO95__FUNC_CCU_URXD_AO (MTK_PIN_NO(95) | 6) + +#define PINMUX_GPIO96__FUNC_GPIO96 (MTK_PIN_NO(96) | 0) +#define PINMUX_GPIO96__FUNC_UTXD0 (MTK_PIN_NO(96) | 1) +#define PINMUX_GPIO96__FUNC_URXD0 (MTK_PIN_NO(96) | 2) +#define PINMUX_GPIO96__FUNC_MD_UTXD0 (MTK_PIN_NO(96) | 3) +#define PINMUX_GPIO96__FUNC_MD_UTXD1 (MTK_PIN_NO(96) | 4) +#define PINMUX_GPIO96__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(96) | 5) +#define PINMUX_GPIO96__FUNC_CCU_UTXD_AO (MTK_PIN_NO(96) | 6) +#define PINMUX_GPIO96__FUNC_DBG_MON_B2 (MTK_PIN_NO(96) | 7) + +#define PINMUX_GPIO97__FUNC_GPIO97 (MTK_PIN_NO(97) | 0) +#define PINMUX_GPIO97__FUNC_UCTS0 (MTK_PIN_NO(97) | 1) +#define PINMUX_GPIO97__FUNC_I2S2_MCK (MTK_PIN_NO(97) | 2) +#define PINMUX_GPIO97__FUNC_IDDIG (MTK_PIN_NO(97) | 3) +#define PINMUX_GPIO97__FUNC_CONN_MCU_TDO (MTK_PIN_NO(97) | 4) +#define PINMUX_GPIO97__FUNC_SSPM_JTAG_TDO (MTK_PIN_NO(97) | 5) +#define PINMUX_GPIO97__FUNC_IO_JTAG_TDO (MTK_PIN_NO(97) | 6) +#define PINMUX_GPIO97__FUNC_DBG_MON_B3 (MTK_PIN_NO(97) | 7) + +#define PINMUX_GPIO98__FUNC_GPIO98 (MTK_PIN_NO(98) | 0) +#define PINMUX_GPIO98__FUNC_URTS0 (MTK_PIN_NO(98) | 1) +#define PINMUX_GPIO98__FUNC_I2S2_BCK (MTK_PIN_NO(98) | 2) +#define PINMUX_GPIO98__FUNC_USB_DRVVBUS (MTK_PIN_NO(98) | 3) +#define PINMUX_GPIO98__FUNC_CONN_MCU_TMS (MTK_PIN_NO(98) | 4) +#define PINMUX_GPIO98__FUNC_SSPM_JTAG_TMS (MTK_PIN_NO(98) | 5) +#define PINMUX_GPIO98__FUNC_IO_JTAG_TMS (MTK_PIN_NO(98) | 6) +#define PINMUX_GPIO98__FUNC_DBG_MON_B4 (MTK_PIN_NO(98) | 7) + +#define PINMUX_GPIO99__FUNC_GPIO99 (MTK_PIN_NO(99) | 0) +#define PINMUX_GPIO99__FUNC_CMMCLK0 (MTK_PIN_NO(99) | 1) +#define PINMUX_GPIO99__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(99) | 4) +#define PINMUX_GPIO99__FUNC_DBG_MON_B28 (MTK_PIN_NO(99) | 7) + +#define PINMUX_GPIO100__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) +#define PINMUX_GPIO100__FUNC_CMMCLK1 (MTK_PIN_NO(100) | 1) +#define PINMUX_GPIO100__FUNC_PWM_C (MTK_PIN_NO(100) | 2) +#define PINMUX_GPIO100__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(100) | 3) +#define PINMUX_GPIO100__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(100) | 4) +#define PINMUX_GPIO100__FUNC_DBG_MON_B29 (MTK_PIN_NO(100) | 7) + +#define PINMUX_GPIO101__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) +#define PINMUX_GPIO101__FUNC_CLKM2 (MTK_PIN_NO(101) | 1) +#define PINMUX_GPIO101__FUNC_I2S2_LRCK (MTK_PIN_NO(101) | 2) +#define PINMUX_GPIO101__FUNC_CMVREF1 (MTK_PIN_NO(101) | 3) +#define PINMUX_GPIO101__FUNC_CONN_MCU_TCK (MTK_PIN_NO(101) | 4) +#define PINMUX_GPIO101__FUNC_SSPM_JTAG_TCK (MTK_PIN_NO(101) | 5) +#define PINMUX_GPIO101__FUNC_IO_JTAG_TCK (MTK_PIN_NO(101) | 6) + +#define PINMUX_GPIO102__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) +#define PINMUX_GPIO102__FUNC_CLKM1 (MTK_PIN_NO(102) | 1) +#define PINMUX_GPIO102__FUNC_I2S2_DI (MTK_PIN_NO(102) | 2) +#define PINMUX_GPIO102__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(102) | 3) +#define PINMUX_GPIO102__FUNC_CONN_MCU_TDI (MTK_PIN_NO(102) | 4) +#define PINMUX_GPIO102__FUNC_SSPM_JTAG_TDI (MTK_PIN_NO(102) | 5) +#define PINMUX_GPIO102__FUNC_IO_JTAG_TDI (MTK_PIN_NO(102) | 6) +#define PINMUX_GPIO102__FUNC_DBG_MON_B8 (MTK_PIN_NO(102) | 7) + +#define PINMUX_GPIO103__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) +#define PINMUX_GPIO103__FUNC_SCL2 (MTK_PIN_NO(103) | 1) + +#define PINMUX_GPIO104__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) +#define PINMUX_GPIO104__FUNC_SDA2 (MTK_PIN_NO(104) | 1) + +#define PINMUX_GPIO105__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) +#define PINMUX_GPIO105__FUNC_SCL4 (MTK_PIN_NO(105) | 1) + +#define PINMUX_GPIO106__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) +#define PINMUX_GPIO106__FUNC_SDA4 (MTK_PIN_NO(106) | 1) + +#define PINMUX_GPIO107__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) +#define PINMUX_GPIO107__FUNC_DMIC_CLK (MTK_PIN_NO(107) | 1) +#define PINMUX_GPIO107__FUNC_ANT_SEL0 (MTK_PIN_NO(107) | 2) +#define PINMUX_GPIO107__FUNC_CLKM0 (MTK_PIN_NO(107) | 3) +#define PINMUX_GPIO107__FUNC_SDA7 (MTK_PIN_NO(107) | 4) +#define PINMUX_GPIO107__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(107) | 5) +#define PINMUX_GPIO107__FUNC_PWM_A (MTK_PIN_NO(107) | 6) +#define PINMUX_GPIO107__FUNC_DBG_MON_B12 (MTK_PIN_NO(107) | 7) + +#define PINMUX_GPIO108__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) +#define PINMUX_GPIO108__FUNC_CMMCLK2 (MTK_PIN_NO(108) | 1) +#define PINMUX_GPIO108__FUNC_ANT_SEL1 (MTK_PIN_NO(108) | 2) +#define PINMUX_GPIO108__FUNC_CLKM1 (MTK_PIN_NO(108) | 3) +#define PINMUX_GPIO108__FUNC_SCL8 (MTK_PIN_NO(108) | 4) +#define PINMUX_GPIO108__FUNC_DAP_MD32_SWD (MTK_PIN_NO(108) | 5) +#define PINMUX_GPIO108__FUNC_PWM_B (MTK_PIN_NO(108) | 6) +#define PINMUX_GPIO108__FUNC_DBG_MON_B13 (MTK_PIN_NO(108) | 7) + +#define PINMUX_GPIO109__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) +#define PINMUX_GPIO109__FUNC_DMIC_DAT (MTK_PIN_NO(109) | 1) +#define PINMUX_GPIO109__FUNC_ANT_SEL2 (MTK_PIN_NO(109) | 2) +#define PINMUX_GPIO109__FUNC_CLKM2 (MTK_PIN_NO(109) | 3) +#define PINMUX_GPIO109__FUNC_SDA8 (MTK_PIN_NO(109) | 4) +#define PINMUX_GPIO109__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(109) | 5) +#define PINMUX_GPIO109__FUNC_PWM_C (MTK_PIN_NO(109) | 6) +#define PINMUX_GPIO109__FUNC_DBG_MON_B14 (MTK_PIN_NO(109) | 7) + +#define PINMUX_GPIO110__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) +#define PINMUX_GPIO110__FUNC_SCL7 (MTK_PIN_NO(110) | 1) +#define PINMUX_GPIO110__FUNC_ANT_SEL0 (MTK_PIN_NO(110) | 2) +#define PINMUX_GPIO110__FUNC_TP_URXD1_AO (MTK_PIN_NO(110) | 3) +#define PINMUX_GPIO110__FUNC_USB_DRVVBUS (MTK_PIN_NO(110) | 4) +#define PINMUX_GPIO110__FUNC_SRCLKENAI1 (MTK_PIN_NO(110) | 5) +#define PINMUX_GPIO110__FUNC_KPCOL2 (MTK_PIN_NO(110) | 6) +#define PINMUX_GPIO110__FUNC_URXD1 (MTK_PIN_NO(110) | 7) + +#define PINMUX_GPIO111__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) +#define PINMUX_GPIO111__FUNC_CMMCLK3 (MTK_PIN_NO(111) | 1) +#define PINMUX_GPIO111__FUNC_ANT_SEL1 (MTK_PIN_NO(111) | 2) +#define PINMUX_GPIO111__FUNC_SRCLKENAI0 (MTK_PIN_NO(111) | 3) +#define PINMUX_GPIO111__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(111) | 4) +#define PINMUX_GPIO111__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(111) | 5) +#define PINMUX_GPIO111__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(111) | 7) + +#define PINMUX_GPIO112__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) +#define PINMUX_GPIO112__FUNC_SDA7 (MTK_PIN_NO(112) | 1) +#define PINMUX_GPIO112__FUNC_ANT_SEL2 (MTK_PIN_NO(112) | 2) +#define PINMUX_GPIO112__FUNC_TP_UTXD1_AO (MTK_PIN_NO(112) | 3) +#define PINMUX_GPIO112__FUNC_IDDIG (MTK_PIN_NO(112) | 4) +#define PINMUX_GPIO112__FUNC_AGPS_SYNC (MTK_PIN_NO(112) | 5) +#define PINMUX_GPIO112__FUNC_KPROW2 (MTK_PIN_NO(112) | 6) +#define PINMUX_GPIO112__FUNC_UTXD1 (MTK_PIN_NO(112) | 7) + +#define PINMUX_GPIO113__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) +#define PINMUX_GPIO113__FUNC_CONN_TOP_CLK (MTK_PIN_NO(113) | 1) +#define PINMUX_GPIO113__FUNC_SCL6 (MTK_PIN_NO(113) | 3) +#define PINMUX_GPIO113__FUNC_AUXIF_CLK0 (MTK_PIN_NO(113) | 4) +#define PINMUX_GPIO113__FUNC_TP_UCTS1_AO (MTK_PIN_NO(113) | 6) + +#define PINMUX_GPIO114__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) +#define PINMUX_GPIO114__FUNC_CONN_TOP_DATA (MTK_PIN_NO(114) | 1) +#define PINMUX_GPIO114__FUNC_SDA6 (MTK_PIN_NO(114) | 3) +#define PINMUX_GPIO114__FUNC_AUXIF_ST0 (MTK_PIN_NO(114) | 4) +#define PINMUX_GPIO114__FUNC_TP_URTS1_AO (MTK_PIN_NO(114) | 6) + +#define PINMUX_GPIO115__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) +#define PINMUX_GPIO115__FUNC_CONN_BT_CLK (MTK_PIN_NO(115) | 1) +#define PINMUX_GPIO115__FUNC_UTXD1 (MTK_PIN_NO(115) | 2) +#define PINMUX_GPIO115__FUNC_PTA_TXD (MTK_PIN_NO(115) | 3) +#define PINMUX_GPIO115__FUNC_AUXIF_CLK1 (MTK_PIN_NO(115) | 4) +#define PINMUX_GPIO115__FUNC_DAP_MD32_SWD (MTK_PIN_NO(115) | 5) +#define PINMUX_GPIO115__FUNC_TP_UTXD1_AO (MTK_PIN_NO(115) | 6) + +#define PINMUX_GPIO116__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) +#define PINMUX_GPIO116__FUNC_CONN_BT_DATA (MTK_PIN_NO(116) | 1) +#define PINMUX_GPIO116__FUNC_IPU_JTAG_TRST (MTK_PIN_NO(116) | 2) +#define PINMUX_GPIO116__FUNC_AUXIF_ST1 (MTK_PIN_NO(116) | 4) +#define PINMUX_GPIO116__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(116) | 5) +#define PINMUX_GPIO116__FUNC_TP_URXD2_AO (MTK_PIN_NO(116) | 6) +#define PINMUX_GPIO116__FUNC_DBG_MON_A0 (MTK_PIN_NO(116) | 7) + +#define PINMUX_GPIO117__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) +#define PINMUX_GPIO117__FUNC_CONN_WF_HB0 (MTK_PIN_NO(117) | 1) +#define PINMUX_GPIO117__FUNC_IPU_JTAG_TDO (MTK_PIN_NO(117) | 2) +#define PINMUX_GPIO117__FUNC_TP_UTXD2_AO (MTK_PIN_NO(117) | 6) +#define PINMUX_GPIO117__FUNC_DBG_MON_A4 (MTK_PIN_NO(117) | 7) + +#define PINMUX_GPIO118__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) +#define PINMUX_GPIO118__FUNC_CONN_WF_HB1 (MTK_PIN_NO(118) | 1) +#define PINMUX_GPIO118__FUNC_IPU_JTAG_TDI (MTK_PIN_NO(118) | 2) +#define PINMUX_GPIO118__FUNC_SSPM_URXD_AO (MTK_PIN_NO(118) | 5) +#define PINMUX_GPIO118__FUNC_TP_UCTS2_AO (MTK_PIN_NO(118) | 6) +#define PINMUX_GPIO118__FUNC_DBG_MON_A5 (MTK_PIN_NO(118) | 7) + +#define PINMUX_GPIO119__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) +#define PINMUX_GPIO119__FUNC_CONN_WF_HB2 (MTK_PIN_NO(119) | 1) +#define PINMUX_GPIO119__FUNC_IPU_JTAG_TCK (MTK_PIN_NO(119) | 2) +#define PINMUX_GPIO119__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(119) | 5) +#define PINMUX_GPIO119__FUNC_TP_URTS2_AO (MTK_PIN_NO(119) | 6) + +#define PINMUX_GPIO120__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) +#define PINMUX_GPIO120__FUNC_CONN_WB_PTA (MTK_PIN_NO(120) | 1) +#define PINMUX_GPIO120__FUNC_IPU_JTAG_TMS (MTK_PIN_NO(120) | 2) +#define PINMUX_GPIO120__FUNC_CCU_URXD_AO (MTK_PIN_NO(120) | 5) + +#define PINMUX_GPIO121__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) +#define PINMUX_GPIO121__FUNC_CONN_HRST_B (MTK_PIN_NO(121) | 1) +#define PINMUX_GPIO121__FUNC_URXD1 (MTK_PIN_NO(121) | 2) +#define PINMUX_GPIO121__FUNC_PTA_RXD (MTK_PIN_NO(121) | 3) +#define PINMUX_GPIO121__FUNC_CCU_UTXD_AO (MTK_PIN_NO(121) | 5) +#define PINMUX_GPIO121__FUNC_TP_URXD1_AO (MTK_PIN_NO(121) | 6) + +#define PINMUX_GPIO122__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) +#define PINMUX_GPIO122__FUNC_MSDC0_CMD (MTK_PIN_NO(122) | 1) +#define PINMUX_GPIO122__FUNC_SSPM_URXD2_AO (MTK_PIN_NO(122) | 2) +#define PINMUX_GPIO122__FUNC_ANT_SEL1 (MTK_PIN_NO(122) | 3) +#define PINMUX_GPIO122__FUNC_DBG_MON_A12 (MTK_PIN_NO(122) | 7) + +#define PINMUX_GPIO123__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) +#define PINMUX_GPIO123__FUNC_MSDC0_DAT0 (MTK_PIN_NO(123) | 1) +#define PINMUX_GPIO123__FUNC_ANT_SEL0 (MTK_PIN_NO(123) | 3) +#define PINMUX_GPIO123__FUNC_DBG_MON_A13 (MTK_PIN_NO(123) | 7) + +#define PINMUX_GPIO124__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) +#define PINMUX_GPIO124__FUNC_MSDC0_CLK (MTK_PIN_NO(124) | 1) +#define PINMUX_GPIO124__FUNC_DBG_MON_A14 (MTK_PIN_NO(124) | 7) + +#define PINMUX_GPIO125__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) +#define PINMUX_GPIO125__FUNC_MSDC0_DAT2 (MTK_PIN_NO(125) | 1) +#define PINMUX_GPIO125__FUNC_MRG_CLK (MTK_PIN_NO(125) | 3) +#define PINMUX_GPIO125__FUNC_DBG_MON_A15 (MTK_PIN_NO(125) | 7) + +#define PINMUX_GPIO126__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) +#define PINMUX_GPIO126__FUNC_MSDC0_DAT4 (MTK_PIN_NO(126) | 1) +#define PINMUX_GPIO126__FUNC_ANT_SEL5 (MTK_PIN_NO(126) | 3) +#define PINMUX_GPIO126__FUNC_UFS_MPHY_SCL (MTK_PIN_NO(126) | 6) +#define PINMUX_GPIO126__FUNC_DBG_MON_A16 (MTK_PIN_NO(126) | 7) + +#define PINMUX_GPIO127__FUNC_GPIO127 (MTK_PIN_NO(127) | 0) +#define PINMUX_GPIO127__FUNC_MSDC0_DAT6 (MTK_PIN_NO(127) | 1) +#define PINMUX_GPIO127__FUNC_ANT_SEL4 (MTK_PIN_NO(127) | 3) +#define PINMUX_GPIO127__FUNC_UFS_MPHY_SDA (MTK_PIN_NO(127) | 6) +#define PINMUX_GPIO127__FUNC_DBG_MON_A17 (MTK_PIN_NO(127) | 7) + +#define PINMUX_GPIO128__FUNC_GPIO128 (MTK_PIN_NO(128) | 0) +#define PINMUX_GPIO128__FUNC_MSDC0_DAT1 (MTK_PIN_NO(128) | 1) +#define PINMUX_GPIO128__FUNC_ANT_SEL2 (MTK_PIN_NO(128) | 3) +#define PINMUX_GPIO128__FUNC_UFS_UNIPRO_SDA (MTK_PIN_NO(128) | 6) +#define PINMUX_GPIO128__FUNC_DBG_MON_A18 (MTK_PIN_NO(128) | 7) + +#define PINMUX_GPIO129__FUNC_GPIO129 (MTK_PIN_NO(129) | 0) +#define PINMUX_GPIO129__FUNC_MSDC0_DAT5 (MTK_PIN_NO(129) | 1) +#define PINMUX_GPIO129__FUNC_ANT_SEL3 (MTK_PIN_NO(129) | 3) +#define PINMUX_GPIO129__FUNC_UFS_UNIPRO_SCL (MTK_PIN_NO(129) | 6) +#define PINMUX_GPIO129__FUNC_DBG_MON_A23 (MTK_PIN_NO(129) | 7) + +#define PINMUX_GPIO130__FUNC_GPIO130 (MTK_PIN_NO(130) | 0) +#define PINMUX_GPIO130__FUNC_MSDC0_DAT7 (MTK_PIN_NO(130) | 1) +#define PINMUX_GPIO130__FUNC_MRG_DO (MTK_PIN_NO(130) | 3) +#define PINMUX_GPIO130__FUNC_DBG_MON_A24 (MTK_PIN_NO(130) | 7) + +#define PINMUX_GPIO131__FUNC_GPIO131 (MTK_PIN_NO(131) | 0) +#define PINMUX_GPIO131__FUNC_MSDC0_DSL (MTK_PIN_NO(131) | 1) +#define PINMUX_GPIO131__FUNC_MRG_SYNC (MTK_PIN_NO(131) | 3) +#define PINMUX_GPIO131__FUNC_DBG_MON_A25 (MTK_PIN_NO(131) | 7) + +#define PINMUX_GPIO132__FUNC_GPIO132 (MTK_PIN_NO(132) | 0) +#define PINMUX_GPIO132__FUNC_MSDC0_DAT3 (MTK_PIN_NO(132) | 1) +#define PINMUX_GPIO132__FUNC_MRG_DI (MTK_PIN_NO(132) | 3) +#define PINMUX_GPIO132__FUNC_DBG_MON_A26 (MTK_PIN_NO(132) | 7) + +#define PINMUX_GPIO133__FUNC_GPIO133 (MTK_PIN_NO(133) | 0) +#define PINMUX_GPIO133__FUNC_MSDC0_RSTB (MTK_PIN_NO(133) | 1) +#define PINMUX_GPIO133__FUNC_AGPS_SYNC (MTK_PIN_NO(133) | 3) +#define PINMUX_GPIO133__FUNC_DBG_MON_A27 (MTK_PIN_NO(133) | 7) + +#define PINMUX_GPIO134__FUNC_GPIO134 (MTK_PIN_NO(134) | 0) +#define PINMUX_GPIO134__FUNC_RTC32K_CK (MTK_PIN_NO(134) | 1) + +#define PINMUX_GPIO135__FUNC_GPIO135 (MTK_PIN_NO(135) | 0) +#define PINMUX_GPIO135__FUNC_WATCHDOG (MTK_PIN_NO(135) | 1) + +#define PINMUX_GPIO136__FUNC_GPIO136 (MTK_PIN_NO(136) | 0) +#define PINMUX_GPIO136__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(136) | 1) +#define PINMUX_GPIO136__FUNC_AUD_CLK_MISO (MTK_PIN_NO(136) | 2) +#define PINMUX_GPIO136__FUNC_I2S1_MCK (MTK_PIN_NO(136) | 3) +#define PINMUX_GPIO136__FUNC_UFS_UNIPRO_SCL (MTK_PIN_NO(136) | 6) + +#define PINMUX_GPIO137__FUNC_GPIO137 (MTK_PIN_NO(137) | 0) +#define PINMUX_GPIO137__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(137) | 1) +#define PINMUX_GPIO137__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(137) | 2) +#define PINMUX_GPIO137__FUNC_I2S1_BCK (MTK_PIN_NO(137) | 3) + +#define PINMUX_GPIO138__FUNC_GPIO138 (MTK_PIN_NO(138) | 0) +#define PINMUX_GPIO138__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(138) | 1) +#define PINMUX_GPIO138__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(138) | 2) +#define PINMUX_GPIO138__FUNC_I2S1_LRCK (MTK_PIN_NO(138) | 3) +#define PINMUX_GPIO138__FUNC_DBG_MON_B24 (MTK_PIN_NO(138) | 7) + +#define PINMUX_GPIO139__FUNC_GPIO139 (MTK_PIN_NO(139) | 0) +#define PINMUX_GPIO139__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(139) | 1) +#define PINMUX_GPIO139__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(139) | 2) +#define PINMUX_GPIO139__FUNC_I2S1_DO (MTK_PIN_NO(139) | 3) +#define PINMUX_GPIO139__FUNC_UFS_MPHY_SDA (MTK_PIN_NO(139) | 6) + +#define PINMUX_GPIO140__FUNC_GPIO140 (MTK_PIN_NO(140) | 0) +#define PINMUX_GPIO140__FUNC_AUD_CLK_MISO (MTK_PIN_NO(140) | 1) +#define PINMUX_GPIO140__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(140) | 2) +#define PINMUX_GPIO140__FUNC_I2S0_MCK (MTK_PIN_NO(140) | 3) +#define PINMUX_GPIO140__FUNC_UFS_UNIPRO_SDA (MTK_PIN_NO(140) | 6) + +#define PINMUX_GPIO141__FUNC_GPIO141 (MTK_PIN_NO(141) | 0) +#define PINMUX_GPIO141__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(141) | 1) +#define PINMUX_GPIO141__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(141) | 2) +#define PINMUX_GPIO141__FUNC_I2S0_BCK (MTK_PIN_NO(141) | 3) + +#define PINMUX_GPIO142__FUNC_GPIO142 (MTK_PIN_NO(142) | 0) +#define PINMUX_GPIO142__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(142) | 1) +#define PINMUX_GPIO142__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(142) | 2) +#define PINMUX_GPIO142__FUNC_I2S0_LRCK (MTK_PIN_NO(142) | 3) +#define PINMUX_GPIO142__FUNC_VOW_DAT_MISO (MTK_PIN_NO(142) | 4) +#define PINMUX_GPIO142__FUNC_DBG_MON_B25 (MTK_PIN_NO(142) | 7) + +#define PINMUX_GPIO143__FUNC_GPIO143 (MTK_PIN_NO(143) | 0) +#define PINMUX_GPIO143__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(143) | 1) +#define PINMUX_GPIO143__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(143) | 2) +#define PINMUX_GPIO143__FUNC_I2S0_DI (MTK_PIN_NO(143) | 3) +#define PINMUX_GPIO143__FUNC_VOW_CLK_MISO (MTK_PIN_NO(143) | 4) +#define PINMUX_GPIO143__FUNC_UFS_MPHY_SCL (MTK_PIN_NO(143) | 6) +#define PINMUX_GPIO143__FUNC_DBG_MON_B26 (MTK_PIN_NO(143) | 7) + +#define PINMUX_GPIO144__FUNC_GPIO144 (MTK_PIN_NO(144) | 0) +#define PINMUX_GPIO144__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(144) | 1) +#define PINMUX_GPIO144__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(144) | 2) + +#define PINMUX_GPIO145__FUNC_GPIO145 (MTK_PIN_NO(145) | 0) +#define PINMUX_GPIO145__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(145) | 1) + +#define PINMUX_GPIO146__FUNC_GPIO146 (MTK_PIN_NO(146) | 0) +#define PINMUX_GPIO146__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(146) | 1) +#define PINMUX_GPIO146__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(146) | 2) + +#define PINMUX_GPIO147__FUNC_GPIO147 (MTK_PIN_NO(147) | 0) +#define PINMUX_GPIO147__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(147) | 1) + +#define PINMUX_GPIO148__FUNC_GPIO148 (MTK_PIN_NO(148) | 0) +#define PINMUX_GPIO148__FUNC_SRCLKENA0 (MTK_PIN_NO(148) | 1) + +#define PINMUX_GPIO149__FUNC_GPIO149 (MTK_PIN_NO(149) | 0) +#define PINMUX_GPIO149__FUNC_SRCLKENA1 (MTK_PIN_NO(149) | 1) + +#define PINMUX_GPIO150__FUNC_GPIO150 (MTK_PIN_NO(150) | 0) +#define PINMUX_GPIO150__FUNC_PWM_A (MTK_PIN_NO(150) | 1) +#define PINMUX_GPIO150__FUNC_CMFLASH (MTK_PIN_NO(150) | 2) +#define PINMUX_GPIO150__FUNC_CLKM0 (MTK_PIN_NO(150) | 3) +#define PINMUX_GPIO150__FUNC_DBG_MON_B30 (MTK_PIN_NO(150) | 7) + +#define PINMUX_GPIO151__FUNC_GPIO151 (MTK_PIN_NO(151) | 0) +#define PINMUX_GPIO151__FUNC_PWM_B (MTK_PIN_NO(151) | 1) +#define PINMUX_GPIO151__FUNC_CMVREF0 (MTK_PIN_NO(151) | 2) +#define PINMUX_GPIO151__FUNC_CLKM1 (MTK_PIN_NO(151) | 3) +#define PINMUX_GPIO151__FUNC_DBG_MON_B20 (MTK_PIN_NO(151) | 7) + +#define PINMUX_GPIO152__FUNC_GPIO152 (MTK_PIN_NO(152) | 0) +#define PINMUX_GPIO152__FUNC_PWM_C (MTK_PIN_NO(152) | 1) +#define PINMUX_GPIO152__FUNC_CMFLASH (MTK_PIN_NO(152) | 2) +#define PINMUX_GPIO152__FUNC_CLKM2 (MTK_PIN_NO(152) | 3) +#define PINMUX_GPIO152__FUNC_DBG_MON_B21 (MTK_PIN_NO(152) | 7) + +#define PINMUX_GPIO153__FUNC_GPIO153 (MTK_PIN_NO(153) | 0) +#define PINMUX_GPIO153__FUNC_PWM_A (MTK_PIN_NO(153) | 1) +#define PINMUX_GPIO153__FUNC_CMVREF0 (MTK_PIN_NO(153) | 2) +#define PINMUX_GPIO153__FUNC_CLKM3 (MTK_PIN_NO(153) | 3) +#define PINMUX_GPIO153__FUNC_DBG_MON_B22 (MTK_PIN_NO(153) | 7) + +#define PINMUX_GPIO154__FUNC_GPIO154 (MTK_PIN_NO(154) | 0) +#define PINMUX_GPIO154__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(154) | 1) +#define PINMUX_GPIO154__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(154) | 2) +#define PINMUX_GPIO154__FUNC_DBG_MON_B18 (MTK_PIN_NO(154) | 7) + +#define PINMUX_GPIO155__FUNC_GPIO155 (MTK_PIN_NO(155) | 0) +#define PINMUX_GPIO155__FUNC_ANT_SEL0 (MTK_PIN_NO(155) | 1) +#define PINMUX_GPIO155__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(155) | 2) +#define PINMUX_GPIO155__FUNC_CMVREF1 (MTK_PIN_NO(155) | 3) +#define PINMUX_GPIO155__FUNC_SCP_JTAG_TDI (MTK_PIN_NO(155) | 7) + +#define PINMUX_GPIO156__FUNC_GPIO156 (MTK_PIN_NO(156) | 0) +#define PINMUX_GPIO156__FUNC_ANT_SEL1 (MTK_PIN_NO(156) | 1) +#define PINMUX_GPIO156__FUNC_SRCLKENAI0 (MTK_PIN_NO(156) | 2) +#define PINMUX_GPIO156__FUNC_SCL6 (MTK_PIN_NO(156) | 3) +#define PINMUX_GPIO156__FUNC_KPCOL2 (MTK_PIN_NO(156) | 4) +#define PINMUX_GPIO156__FUNC_IDDIG (MTK_PIN_NO(156) | 5) +#define PINMUX_GPIO156__FUNC_SCP_JTAG_TCK (MTK_PIN_NO(156) | 7) + +#define PINMUX_GPIO157__FUNC_GPIO157 (MTK_PIN_NO(157) | 0) +#define PINMUX_GPIO157__FUNC_ANT_SEL2 (MTK_PIN_NO(157) | 1) +#define PINMUX_GPIO157__FUNC_SRCLKENAI1 (MTK_PIN_NO(157) | 2) +#define PINMUX_GPIO157__FUNC_SDA6 (MTK_PIN_NO(157) | 3) +#define PINMUX_GPIO157__FUNC_KPROW2 (MTK_PIN_NO(157) | 4) +#define PINMUX_GPIO157__FUNC_USB_DRVVBUS (MTK_PIN_NO(157) | 5) +#define PINMUX_GPIO157__FUNC_SCP_JTAG_TRSTN (MTK_PIN_NO(157) | 7) + +#define PINMUX_GPIO158__FUNC_GPIO158 (MTK_PIN_NO(158) | 0) +#define PINMUX_GPIO158__FUNC_ANT_SEL3 (MTK_PIN_NO(158) | 1) + +#define PINMUX_GPIO159__FUNC_GPIO159 (MTK_PIN_NO(159) | 0) +#define PINMUX_GPIO159__FUNC_ANT_SEL4 (MTK_PIN_NO(159) | 1) + +#define PINMUX_GPIO160__FUNC_GPIO160 (MTK_PIN_NO(160) | 0) +#define PINMUX_GPIO160__FUNC_ANT_SEL5 (MTK_PIN_NO(160) | 1) + +#define PINMUX_GPIO161__FUNC_GPIO161 (MTK_PIN_NO(161) | 0) +#define PINMUX_GPIO161__FUNC_SPI1_A_MI (MTK_PIN_NO(161) | 1) +#define PINMUX_GPIO161__FUNC_SCP_SPI1_MI (MTK_PIN_NO(161) | 2) +#define PINMUX_GPIO161__FUNC_IDDIG (MTK_PIN_NO(161) | 3) +#define PINMUX_GPIO161__FUNC_ANT_SEL6 (MTK_PIN_NO(161) | 4) +#define PINMUX_GPIO161__FUNC_KPCOL2 (MTK_PIN_NO(161) | 5) +#define PINMUX_GPIO161__FUNC_PTA_RXD (MTK_PIN_NO(161) | 6) +#define PINMUX_GPIO161__FUNC_DBG_MON_B19 (MTK_PIN_NO(161) | 7) + +#define PINMUX_GPIO162__FUNC_GPIO162 (MTK_PIN_NO(162) | 0) +#define PINMUX_GPIO162__FUNC_SPI1_A_CSB (MTK_PIN_NO(162) | 1) +#define PINMUX_GPIO162__FUNC_SCP_SPI1_CS (MTK_PIN_NO(162) | 2) +#define PINMUX_GPIO162__FUNC_USB_DRVVBUS (MTK_PIN_NO(162) | 3) +#define PINMUX_GPIO162__FUNC_ANT_SEL5 (MTK_PIN_NO(162) | 4) +#define PINMUX_GPIO162__FUNC_KPROW2 (MTK_PIN_NO(162) | 5) +#define PINMUX_GPIO162__FUNC_PTA_TXD (MTK_PIN_NO(162) | 6) + +#define PINMUX_GPIO163__FUNC_GPIO163 (MTK_PIN_NO(163) | 0) +#define PINMUX_GPIO163__FUNC_SPI1_A_MO (MTK_PIN_NO(163) | 1) +#define PINMUX_GPIO163__FUNC_SCP_SPI1_MO (MTK_PIN_NO(163) | 2) +#define PINMUX_GPIO163__FUNC_SDA1 (MTK_PIN_NO(163) | 3) +#define PINMUX_GPIO163__FUNC_ANT_SEL4 (MTK_PIN_NO(163) | 4) +#define PINMUX_GPIO163__FUNC_CMMCLK2 (MTK_PIN_NO(163) | 5) +#define PINMUX_GPIO163__FUNC_DMIC_CLK (MTK_PIN_NO(163) | 6) + +#define PINMUX_GPIO164__FUNC_GPIO164 (MTK_PIN_NO(164) | 0) +#define PINMUX_GPIO164__FUNC_SPI1_A_CLK (MTK_PIN_NO(164) | 1) +#define PINMUX_GPIO164__FUNC_SCP_SPI1_CK (MTK_PIN_NO(164) | 2) +#define PINMUX_GPIO164__FUNC_SCL1 (MTK_PIN_NO(164) | 3) +#define PINMUX_GPIO164__FUNC_ANT_SEL3 (MTK_PIN_NO(164) | 4) +#define PINMUX_GPIO164__FUNC_CMMCLK3 (MTK_PIN_NO(164) | 5) +#define PINMUX_GPIO164__FUNC_DMIC_DAT (MTK_PIN_NO(164) | 6) + +#define PINMUX_GPIO165__FUNC_GPIO165 (MTK_PIN_NO(165) | 0) +#define PINMUX_GPIO165__FUNC_PWM_B (MTK_PIN_NO(165) | 1) +#define PINMUX_GPIO165__FUNC_CMMCLK2 (MTK_PIN_NO(165) | 2) +#define PINMUX_GPIO165__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(165) | 3) +#define PINMUX_GPIO165__FUNC_TDM_MCK_2ND (MTK_PIN_NO(165) | 6) +#define PINMUX_GPIO165__FUNC_SCP_JTAG_TDO (MTK_PIN_NO(165) | 7) + +#define PINMUX_GPIO166__FUNC_GPIO166 (MTK_PIN_NO(166) | 0) +#define PINMUX_GPIO166__FUNC_ANT_SEL6 (MTK_PIN_NO(166) | 1) + +#define PINMUX_GPIO167__FUNC_GPIO167 (MTK_PIN_NO(167) | 0) +#define PINMUX_GPIO167__FUNC_RFIC0_BSI_EN (MTK_PIN_NO(167) | 1) +#define PINMUX_GPIO167__FUNC_SPM_BSI_EN (MTK_PIN_NO(167) | 2) + +#define PINMUX_GPIO168__FUNC_GPIO168 (MTK_PIN_NO(168) | 0) +#define PINMUX_GPIO168__FUNC_RFIC0_BSI_CK (MTK_PIN_NO(168) | 1) +#define PINMUX_GPIO168__FUNC_SPM_BSI_CK (MTK_PIN_NO(168) | 2) + +#define PINMUX_GPIO169__FUNC_GPIO169 (MTK_PIN_NO(169) | 0) +#define PINMUX_GPIO169__FUNC_PWM_C (MTK_PIN_NO(169) | 1) +#define PINMUX_GPIO169__FUNC_CMMCLK3 (MTK_PIN_NO(169) | 2) +#define PINMUX_GPIO169__FUNC_CMVREF1 (MTK_PIN_NO(169) | 3) +#define PINMUX_GPIO169__FUNC_ANT_SEL7 (MTK_PIN_NO(169) | 4) +#define PINMUX_GPIO169__FUNC_AGPS_SYNC (MTK_PIN_NO(169) | 5) +#define PINMUX_GPIO169__FUNC_TDM_BCK_2ND (MTK_PIN_NO(169) | 6) +#define PINMUX_GPIO169__FUNC_SCP_JTAG_TMS (MTK_PIN_NO(169) | 7) + +#define PINMUX_GPIO170__FUNC_GPIO170 (MTK_PIN_NO(170) | 0) +#define PINMUX_GPIO170__FUNC_I2S1_BCK (MTK_PIN_NO(170) | 1) +#define PINMUX_GPIO170__FUNC_I2S3_BCK (MTK_PIN_NO(170) | 2) +#define PINMUX_GPIO170__FUNC_SCL7 (MTK_PIN_NO(170) | 3) +#define PINMUX_GPIO170__FUNC_I2S5_BCK (MTK_PIN_NO(170) | 4) +#define PINMUX_GPIO170__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(170) | 5) +#define PINMUX_GPIO170__FUNC_TDM_LRCK_2ND (MTK_PIN_NO(170) | 6) +#define PINMUX_GPIO170__FUNC_ANT_SEL3 (MTK_PIN_NO(170) | 7) + +#define PINMUX_GPIO171__FUNC_GPIO171 (MTK_PIN_NO(171) | 0) +#define PINMUX_GPIO171__FUNC_I2S1_LRCK (MTK_PIN_NO(171) | 1) +#define PINMUX_GPIO171__FUNC_I2S3_LRCK (MTK_PIN_NO(171) | 2) +#define PINMUX_GPIO171__FUNC_SDA7 (MTK_PIN_NO(171) | 3) +#define PINMUX_GPIO171__FUNC_I2S5_LRCK (MTK_PIN_NO(171) | 4) +#define PINMUX_GPIO171__FUNC_URXD1 (MTK_PIN_NO(171) | 5) +#define PINMUX_GPIO171__FUNC_TDM_DATA0_2ND (MTK_PIN_NO(171) | 6) +#define PINMUX_GPIO171__FUNC_ANT_SEL4 (MTK_PIN_NO(171) | 7) + +#define PINMUX_GPIO172__FUNC_GPIO172 (MTK_PIN_NO(172) | 0) +#define PINMUX_GPIO172__FUNC_I2S1_DO (MTK_PIN_NO(172) | 1) +#define PINMUX_GPIO172__FUNC_I2S3_DO (MTK_PIN_NO(172) | 2) +#define PINMUX_GPIO172__FUNC_SCL8 (MTK_PIN_NO(172) | 3) +#define PINMUX_GPIO172__FUNC_I2S5_DO (MTK_PIN_NO(172) | 4) +#define PINMUX_GPIO172__FUNC_UTXD1 (MTK_PIN_NO(172) | 5) +#define PINMUX_GPIO172__FUNC_TDM_DATA1_2ND (MTK_PIN_NO(172) | 6) +#define PINMUX_GPIO172__FUNC_ANT_SEL5 (MTK_PIN_NO(172) | 7) + +#define PINMUX_GPIO173__FUNC_GPIO173 (MTK_PIN_NO(173) | 0) +#define PINMUX_GPIO173__FUNC_I2S1_MCK (MTK_PIN_NO(173) | 1) +#define PINMUX_GPIO173__FUNC_I2S3_MCK (MTK_PIN_NO(173) | 2) +#define PINMUX_GPIO173__FUNC_SDA8 (MTK_PIN_NO(173) | 3) +#define PINMUX_GPIO173__FUNC_I2S5_MCK (MTK_PIN_NO(173) | 4) +#define PINMUX_GPIO173__FUNC_UCTS0 (MTK_PIN_NO(173) | 5) +#define PINMUX_GPIO173__FUNC_TDM_DATA2_2ND (MTK_PIN_NO(173) | 6) +#define PINMUX_GPIO173__FUNC_ANT_SEL6 (MTK_PIN_NO(173) | 7) + +#define PINMUX_GPIO174__FUNC_GPIO174 (MTK_PIN_NO(174) | 0) +#define PINMUX_GPIO174__FUNC_I2S2_DI (MTK_PIN_NO(174) | 1) +#define PINMUX_GPIO174__FUNC_I2S0_DI (MTK_PIN_NO(174) | 2) +#define PINMUX_GPIO174__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(174) | 3) +#define PINMUX_GPIO174__FUNC_I2S2_DI2 (MTK_PIN_NO(174) | 4) +#define PINMUX_GPIO174__FUNC_URTS0 (MTK_PIN_NO(174) | 5) +#define PINMUX_GPIO174__FUNC_TDM_DATA3_2ND (MTK_PIN_NO(174) | 6) +#define PINMUX_GPIO174__FUNC_ANT_SEL7 (MTK_PIN_NO(174) | 7) + +#define PINMUX_GPIO175__FUNC_GPIO175 (MTK_PIN_NO(175) | 0) +#define PINMUX_GPIO175__FUNC_ANT_SEL7 (MTK_PIN_NO(175) | 1) + +#define PINMUX_GPIO176__FUNC_GPIO176 (MTK_PIN_NO(176) | 0) + +#define PINMUX_GPIO177__FUNC_GPIO177 (MTK_PIN_NO(177) | 0) + +#define PINMUX_GPIO178__FUNC_GPIO178 (MTK_PIN_NO(178) | 0) + +#define PINMUX_GPIO179__FUNC_GPIO179 (MTK_PIN_NO(179) | 0) + +#endif /* __MT8183-PINFUNC_H */ diff --git a/include/dt-bindings/pinctrl/mt8186-pinfunc.h b/include/dt-bindings/pinctrl/mt8186-pinfunc.h new file mode 100644 index 000000000000..18d6683c6f65 --- /dev/null +++ b/include/dt-bindings/pinctrl/mt8186-pinfunc.h @@ -0,0 +1,1174 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2021 MediaTek Inc. + * Author: Guodong Liu <Guodong.Liu@mediatek.com> + * + */ + +#ifndef __MT8186_PINFUNC_H +#define __MT8186_PINFUNC_H + +#include "mt65xx.h" + +#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define PINMUX_GPIO0__FUNC_I2S0_MCK (MTK_PIN_NO(0) | 1) +#define PINMUX_GPIO0__FUNC_SPI0_CLK_B (MTK_PIN_NO(0) | 2) +#define PINMUX_GPIO0__FUNC_I2S2_MCK (MTK_PIN_NO(0) | 3) +#define PINMUX_GPIO0__FUNC_CMFLASH0 (MTK_PIN_NO(0) | 4) +#define PINMUX_GPIO0__FUNC_SCP_SPI0_CK (MTK_PIN_NO(0) | 5) +#define PINMUX_GPIO0__FUNC_TP_GPIO0_AO (MTK_PIN_NO(0) | 6) +#define PINMUX_GPIO0__FUNC_DBG_MON_A0 (MTK_PIN_NO(0) | 7) + +#define PINMUX_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define PINMUX_GPIO1__FUNC_I2S0_BCK (MTK_PIN_NO(1) | 1) +#define PINMUX_GPIO1__FUNC_SPI0_CSB_B (MTK_PIN_NO(1) | 2) +#define PINMUX_GPIO1__FUNC_I2S2_BCK (MTK_PIN_NO(1) | 3) +#define PINMUX_GPIO1__FUNC_CMFLASH1 (MTK_PIN_NO(1) | 4) +#define PINMUX_GPIO1__FUNC_SCP_SPI0_CS (MTK_PIN_NO(1) | 5) +#define PINMUX_GPIO1__FUNC_TP_GPIO1_AO (MTK_PIN_NO(1) | 6) + +#define PINMUX_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define PINMUX_GPIO2__FUNC_I2S0_LRCK (MTK_PIN_NO(2) | 1) +#define PINMUX_GPIO2__FUNC_SPI0_MO_B (MTK_PIN_NO(2) | 2) +#define PINMUX_GPIO2__FUNC_I2S2_LRCK (MTK_PIN_NO(2) | 3) +#define PINMUX_GPIO2__FUNC_CMFLASH2 (MTK_PIN_NO(2) | 4) +#define PINMUX_GPIO2__FUNC_SCP_SPI0_MO (MTK_PIN_NO(2) | 5) +#define PINMUX_GPIO2__FUNC_TP_GPIO2_AO (MTK_PIN_NO(2) | 6) + +#define PINMUX_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define PINMUX_GPIO3__FUNC_I2S0_DI (MTK_PIN_NO(3) | 1) +#define PINMUX_GPIO3__FUNC_SPI0_MI_B (MTK_PIN_NO(3) | 2) +#define PINMUX_GPIO3__FUNC_I2S2_DI (MTK_PIN_NO(3) | 3) +#define PINMUX_GPIO3__FUNC_SRCLKENAI1 (MTK_PIN_NO(3) | 4) +#define PINMUX_GPIO3__FUNC_SCP_SPI0_MI (MTK_PIN_NO(3) | 5) +#define PINMUX_GPIO3__FUNC_TP_GPIO3_AO (MTK_PIN_NO(3) | 6) + +#define PINMUX_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define PINMUX_GPIO4__FUNC_I2S3_DO (MTK_PIN_NO(4) | 1) +#define PINMUX_GPIO4__FUNC_I2S1_DO (MTK_PIN_NO(4) | 3) +#define PINMUX_GPIO4__FUNC_TP_GPIO4_AO (MTK_PIN_NO(4) | 6) + +#define PINMUX_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define PINMUX_GPIO5__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(5) | 1) +#define PINMUX_GPIO5__FUNC_TP_GPIO5_AO (MTK_PIN_NO(5) | 6) + +#define PINMUX_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define PINMUX_GPIO6__FUNC_I2S3_MCK (MTK_PIN_NO(6) | 1) +#define PINMUX_GPIO6__FUNC_SPI1_CLK_B (MTK_PIN_NO(6) | 2) +#define PINMUX_GPIO6__FUNC_I2S1_MCK (MTK_PIN_NO(6) | 3) +#define PINMUX_GPIO6__FUNC_DPI_DATA22 (MTK_PIN_NO(6) | 4) +#define PINMUX_GPIO6__FUNC_TP_GPIO6_AO (MTK_PIN_NO(6) | 6) + +#define PINMUX_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +#define PINMUX_GPIO7__FUNC_I2S3_BCK (MTK_PIN_NO(7) | 1) +#define PINMUX_GPIO7__FUNC_SPI1_CSB_B (MTK_PIN_NO(7) | 2) +#define PINMUX_GPIO7__FUNC_I2S1_BCK (MTK_PIN_NO(7) | 3) +#define PINMUX_GPIO7__FUNC_DPI_DATA23 (MTK_PIN_NO(7) | 4) +#define PINMUX_GPIO7__FUNC_TP_GPIO7_AO (MTK_PIN_NO(7) | 6) + +#define PINMUX_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +#define PINMUX_GPIO8__FUNC_I2S3_LRCK (MTK_PIN_NO(8) | 1) +#define PINMUX_GPIO8__FUNC_SPI1_MO_B (MTK_PIN_NO(8) | 2) +#define PINMUX_GPIO8__FUNC_I2S1_LRCK (MTK_PIN_NO(8) | 3) +#define PINMUX_GPIO8__FUNC_CONN_UART0_RXD (MTK_PIN_NO(8) | 4) +#define PINMUX_GPIO8__FUNC_SSPM_URXD_AO (MTK_PIN_NO(8) | 5) +#define PINMUX_GPIO8__FUNC_ADSP_UART_RX (MTK_PIN_NO(8) | 6) +#define PINMUX_GPIO8__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(8) | 7) + +#define PINMUX_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +#define PINMUX_GPIO9__FUNC_I2S3_DO (MTK_PIN_NO(9) | 1) +#define PINMUX_GPIO9__FUNC_SPI1_MI_B (MTK_PIN_NO(9) | 2) +#define PINMUX_GPIO9__FUNC_I2S1_DO (MTK_PIN_NO(9) | 3) +#define PINMUX_GPIO9__FUNC_CONN_UART0_TXD (MTK_PIN_NO(9) | 4) +#define PINMUX_GPIO9__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(9) | 5) +#define PINMUX_GPIO9__FUNC_ADSP_UART_TX (MTK_PIN_NO(9) | 6) +#define PINMUX_GPIO9__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(9) | 7) + +#define PINMUX_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +#define PINMUX_GPIO10__FUNC_I2S0_MCK (MTK_PIN_NO(10) | 1) +#define PINMUX_GPIO10__FUNC_SPI4_CLK_A (MTK_PIN_NO(10) | 2) +#define PINMUX_GPIO10__FUNC_I2S2_MCK (MTK_PIN_NO(10) | 3) +#define PINMUX_GPIO10__FUNC_SPM_JTAG_TDI (MTK_PIN_NO(10) | 4) +#define PINMUX_GPIO10__FUNC_SCP_JTAG_TDI (MTK_PIN_NO(10) | 5) +#define PINMUX_GPIO10__FUNC_ADSP_JTAG_TDI (MTK_PIN_NO(10) | 6) +#define PINMUX_GPIO10__FUNC_CONN_MCU_TDI (MTK_PIN_NO(10) | 7) + +#define PINMUX_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +#define PINMUX_GPIO11__FUNC_I2S0_BCK (MTK_PIN_NO(11) | 1) +#define PINMUX_GPIO11__FUNC_SPI4_CSB_A (MTK_PIN_NO(11) | 2) +#define PINMUX_GPIO11__FUNC_I2S2_BCK (MTK_PIN_NO(11) | 3) +#define PINMUX_GPIO11__FUNC_SPM_JTAG_TRSTN (MTK_PIN_NO(11) | 4) +#define PINMUX_GPIO11__FUNC_SCP_JTAG_TRSTN (MTK_PIN_NO(11) | 5) +#define PINMUX_GPIO11__FUNC_ADSP_JTAG_TRSTN (MTK_PIN_NO(11) | 6) +#define PINMUX_GPIO11__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(11) | 7) + +#define PINMUX_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +#define PINMUX_GPIO12__FUNC_I2S0_LRCK (MTK_PIN_NO(12) | 1) +#define PINMUX_GPIO12__FUNC_SPI4_MO_A (MTK_PIN_NO(12) | 2) +#define PINMUX_GPIO12__FUNC_I2S2_LRCK (MTK_PIN_NO(12) | 3) +#define PINMUX_GPIO12__FUNC_SPM_JTAG_TCK (MTK_PIN_NO(12) | 4) +#define PINMUX_GPIO12__FUNC_SCP_JTAG_TCK (MTK_PIN_NO(12) | 5) +#define PINMUX_GPIO12__FUNC_ADSP_JTAG_TCK (MTK_PIN_NO(12) | 6) +#define PINMUX_GPIO12__FUNC_CONN_MCU_TCK (MTK_PIN_NO(12) | 7) + +#define PINMUX_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) +#define PINMUX_GPIO13__FUNC_I2S0_DI (MTK_PIN_NO(13) | 1) +#define PINMUX_GPIO13__FUNC_SPI4_MI_A (MTK_PIN_NO(13) | 2) +#define PINMUX_GPIO13__FUNC_I2S2_DI (MTK_PIN_NO(13) | 3) +#define PINMUX_GPIO13__FUNC_SPM_JTAG_TDO (MTK_PIN_NO(13) | 4) +#define PINMUX_GPIO13__FUNC_SCP_JTAG_TDO (MTK_PIN_NO(13) | 5) +#define PINMUX_GPIO13__FUNC_ADSP_JTAG_TDO (MTK_PIN_NO(13) | 6) +#define PINMUX_GPIO13__FUNC_CONN_MCU_TDO (MTK_PIN_NO(13) | 7) + +#define PINMUX_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) +#define PINMUX_GPIO14__FUNC_CLKM0 (MTK_PIN_NO(14) | 3) +#define PINMUX_GPIO14__FUNC_SPM_JTAG_TMS (MTK_PIN_NO(14) | 4) +#define PINMUX_GPIO14__FUNC_SCP_JTAG_TMS (MTK_PIN_NO(14) | 5) +#define PINMUX_GPIO14__FUNC_ADSP_JTAG_TMS (MTK_PIN_NO(14) | 6) +#define PINMUX_GPIO14__FUNC_CONN_MCU_TMS (MTK_PIN_NO(14) | 7) + +#define PINMUX_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) +#define PINMUX_GPIO15__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(15) | 1) +#define PINMUX_GPIO15__FUNC_SRCLKENAI1 (MTK_PIN_NO(15) | 2) +#define PINMUX_GPIO15__FUNC_CLKM1 (MTK_PIN_NO(15) | 3) +#define PINMUX_GPIO15__FUNC_PWM0 (MTK_PIN_NO(15) | 4) + +#define PINMUX_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) +#define PINMUX_GPIO16__FUNC_CONN_WIFI_TXD (MTK_PIN_NO(16) | 1) +#define PINMUX_GPIO16__FUNC_SRCLKENAI0 (MTK_PIN_NO(16) | 2) +#define PINMUX_GPIO16__FUNC_CLKM2 (MTK_PIN_NO(16) | 3) +#define PINMUX_GPIO16__FUNC_PWM1 (MTK_PIN_NO(16) | 4) + +#define PINMUX_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) +#define PINMUX_GPIO17__FUNC_CLKM3 (MTK_PIN_NO(17) | 3) +#define PINMUX_GPIO17__FUNC_PWM2 (MTK_PIN_NO(17) | 4) +#define PINMUX_GPIO17__FUNC_DBG_MON_A32 (MTK_PIN_NO(17) | 7) + +#define PINMUX_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) +#define PINMUX_GPIO18__FUNC_CMVREF0 (MTK_PIN_NO(18) | 2) +#define PINMUX_GPIO18__FUNC_SPI2_CLK_B (MTK_PIN_NO(18) | 6) +#define PINMUX_GPIO18__FUNC_DBG_MON_A26 (MTK_PIN_NO(18) | 7) + +#define PINMUX_GPIO19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) +#define PINMUX_GPIO19__FUNC_CMVREF1 (MTK_PIN_NO(19) | 2) +#define PINMUX_GPIO19__FUNC_ANT_SEL3 (MTK_PIN_NO(19) | 5) +#define PINMUX_GPIO19__FUNC_SPI2_CSB_B (MTK_PIN_NO(19) | 6) +#define PINMUX_GPIO19__FUNC_DBG_MON_A2 (MTK_PIN_NO(19) | 7) + +#define PINMUX_GPIO20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) +#define PINMUX_GPIO20__FUNC_CMVREF2 (MTK_PIN_NO(20) | 2) +#define PINMUX_GPIO20__FUNC_ANT_SEL4 (MTK_PIN_NO(20) | 5) +#define PINMUX_GPIO20__FUNC_SPI2_MO_B (MTK_PIN_NO(20) | 6) +#define PINMUX_GPIO20__FUNC_DBG_MON_A3 (MTK_PIN_NO(20) | 7) + +#define PINMUX_GPIO21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) +#define PINMUX_GPIO21__FUNC_I2S0_MCK (MTK_PIN_NO(21) | 1) +#define PINMUX_GPIO21__FUNC_I2S1_MCK (MTK_PIN_NO(21) | 2) +#define PINMUX_GPIO21__FUNC_I2S3_MCK (MTK_PIN_NO(21) | 3) +#define PINMUX_GPIO21__FUNC_ANT_SEL5 (MTK_PIN_NO(21) | 5) +#define PINMUX_GPIO21__FUNC_SPI2_MI_B (MTK_PIN_NO(21) | 6) +#define PINMUX_GPIO21__FUNC_DBG_MON_A4 (MTK_PIN_NO(21) | 7) + +#define PINMUX_GPIO22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) +#define PINMUX_GPIO22__FUNC_I2S0_BCK (MTK_PIN_NO(22) | 1) +#define PINMUX_GPIO22__FUNC_I2S1_BCK (MTK_PIN_NO(22) | 2) +#define PINMUX_GPIO22__FUNC_I2S3_BCK (MTK_PIN_NO(22) | 3) +#define PINMUX_GPIO22__FUNC_TDM_RX_LRCK (MTK_PIN_NO(22) | 4) +#define PINMUX_GPIO22__FUNC_ANT_SEL6 (MTK_PIN_NO(22) | 5) +#define PINMUX_GPIO22__FUNC_DBG_MON_A5 (MTK_PIN_NO(22) | 7) + +#define PINMUX_GPIO23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) +#define PINMUX_GPIO23__FUNC_I2S0_LRCK (MTK_PIN_NO(23) | 1) +#define PINMUX_GPIO23__FUNC_I2S1_LRCK (MTK_PIN_NO(23) | 2) +#define PINMUX_GPIO23__FUNC_I2S3_LRCK (MTK_PIN_NO(23) | 3) +#define PINMUX_GPIO23__FUNC_TDM_RX_BCK (MTK_PIN_NO(23) | 4) +#define PINMUX_GPIO23__FUNC_ANT_SEL7 (MTK_PIN_NO(23) | 5) +#define PINMUX_GPIO23__FUNC_DBG_MON_A6 (MTK_PIN_NO(23) | 7) + +#define PINMUX_GPIO24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) +#define PINMUX_GPIO24__FUNC_I2S0_DI (MTK_PIN_NO(24) | 1) +#define PINMUX_GPIO24__FUNC_I2S1_DO (MTK_PIN_NO(24) | 2) +#define PINMUX_GPIO24__FUNC_I2S3_DO (MTK_PIN_NO(24) | 3) +#define PINMUX_GPIO24__FUNC_TDM_RX_MCK (MTK_PIN_NO(24) | 4) +#define PINMUX_GPIO24__FUNC_DBG_MON_A7 (MTK_PIN_NO(24) | 7) + +#define PINMUX_GPIO25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) +#define PINMUX_GPIO25__FUNC_I2S2_MCK (MTK_PIN_NO(25) | 1) +#define PINMUX_GPIO25__FUNC_PCM_CLK (MTK_PIN_NO(25) | 2) +#define PINMUX_GPIO25__FUNC_SPI4_CLK_B (MTK_PIN_NO(25) | 3) +#define PINMUX_GPIO25__FUNC_TDM_RX_DATA0 (MTK_PIN_NO(25) | 4) +#define PINMUX_GPIO25__FUNC_DBG_MON_A8 (MTK_PIN_NO(25) | 7) + +#define PINMUX_GPIO26__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) +#define PINMUX_GPIO26__FUNC_I2S2_BCK (MTK_PIN_NO(26) | 1) +#define PINMUX_GPIO26__FUNC_PCM_SYNC (MTK_PIN_NO(26) | 2) +#define PINMUX_GPIO26__FUNC_SPI4_CSB_B (MTK_PIN_NO(26) | 3) +#define PINMUX_GPIO26__FUNC_TDM_RX_DATA1 (MTK_PIN_NO(26) | 4) +#define PINMUX_GPIO26__FUNC_DBG_MON_A9 (MTK_PIN_NO(26) | 7) + +#define PINMUX_GPIO27__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) +#define PINMUX_GPIO27__FUNC_I2S2_LRCK (MTK_PIN_NO(27) | 1) +#define PINMUX_GPIO27__FUNC_PCM_DI (MTK_PIN_NO(27) | 2) +#define PINMUX_GPIO27__FUNC_SPI4_MO_B (MTK_PIN_NO(27) | 3) +#define PINMUX_GPIO27__FUNC_TDM_RX_DATA2 (MTK_PIN_NO(27) | 4) +#define PINMUX_GPIO27__FUNC_DBG_MON_A10 (MTK_PIN_NO(27) | 7) + +#define PINMUX_GPIO28__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) +#define PINMUX_GPIO28__FUNC_I2S2_DI (MTK_PIN_NO(28) | 1) +#define PINMUX_GPIO28__FUNC_PCM_DO (MTK_PIN_NO(28) | 2) +#define PINMUX_GPIO28__FUNC_SPI4_MI_B (MTK_PIN_NO(28) | 3) +#define PINMUX_GPIO28__FUNC_TDM_RX_DATA3 (MTK_PIN_NO(28) | 4) + +#define PINMUX_GPIO29__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) +#define PINMUX_GPIO29__FUNC_ANT_SEL0 (MTK_PIN_NO(29) | 1) +#define PINMUX_GPIO29__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(29) | 2) + +#define PINMUX_GPIO30__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) +#define PINMUX_GPIO30__FUNC_ANT_SEL1 (MTK_PIN_NO(30) | 1) + +#define PINMUX_GPIO31__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) +#define PINMUX_GPIO31__FUNC_ANT_SEL2 (MTK_PIN_NO(31) | 1) +#define PINMUX_GPIO31__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(31) | 2) +#define PINMUX_GPIO31__FUNC_SRCLKENAI1 (MTK_PIN_NO(31) | 3) + +#define PINMUX_GPIO32__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) +#define PINMUX_GPIO32__FUNC_URXD0 (MTK_PIN_NO(32) | 1) +#define PINMUX_GPIO32__FUNC_UTXD0 (MTK_PIN_NO(32) | 2) +#define PINMUX_GPIO32__FUNC_ADSP_UART_RX (MTK_PIN_NO(32) | 3) +#define PINMUX_GPIO32__FUNC_TP_URXD1_AO (MTK_PIN_NO(32) | 4) + +#define PINMUX_GPIO33__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) +#define PINMUX_GPIO33__FUNC_UTXD0 (MTK_PIN_NO(33) | 1) +#define PINMUX_GPIO33__FUNC_URXD0 (MTK_PIN_NO(33) | 2) +#define PINMUX_GPIO33__FUNC_ADSP_UART_TX (MTK_PIN_NO(33) | 3) +#define PINMUX_GPIO33__FUNC_TP_UTXD1_AO (MTK_PIN_NO(33) | 4) + +#define PINMUX_GPIO34__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) +#define PINMUX_GPIO34__FUNC_URXD1 (MTK_PIN_NO(34) | 1) +#define PINMUX_GPIO34__FUNC_TP_URXD2_AO (MTK_PIN_NO(34) | 2) +#define PINMUX_GPIO34__FUNC_SSPM_URXD_AO (MTK_PIN_NO(34) | 3) +#define PINMUX_GPIO34__FUNC_ADSP_UART_RX (MTK_PIN_NO(34) | 4) +#define PINMUX_GPIO34__FUNC_CONN_UART0_RXD (MTK_PIN_NO(34) | 5) + +#define PINMUX_GPIO35__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) +#define PINMUX_GPIO35__FUNC_UTXD1 (MTK_PIN_NO(35) | 1) +#define PINMUX_GPIO35__FUNC_TP_UTXD2_AO (MTK_PIN_NO(35) | 2) +#define PINMUX_GPIO35__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(35) | 3) +#define PINMUX_GPIO35__FUNC_ADSP_UART_TX (MTK_PIN_NO(35) | 4) +#define PINMUX_GPIO35__FUNC_CONN_UART0_TXD (MTK_PIN_NO(35) | 5) +#define PINMUX_GPIO35__FUNC_CONN_WIFI_TXD (MTK_PIN_NO(35) | 6) + +#define PINMUX_GPIO36__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) +#define PINMUX_GPIO36__FUNC_SPI0_CLK_A (MTK_PIN_NO(36) | 1) +#define PINMUX_GPIO36__FUNC_CLKM0 (MTK_PIN_NO(36) | 2) +#define PINMUX_GPIO36__FUNC_SCP_SPI0_CK (MTK_PIN_NO(36) | 4) +#define PINMUX_GPIO36__FUNC_SPINOR_CK (MTK_PIN_NO(36) | 5) +#define PINMUX_GPIO36__FUNC_DBG_MON_A11 (MTK_PIN_NO(36) | 7) + +#define PINMUX_GPIO37__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) +#define PINMUX_GPIO37__FUNC_SPI0_CSB_A (MTK_PIN_NO(37) | 1) +#define PINMUX_GPIO37__FUNC_CLKM1 (MTK_PIN_NO(37) | 2) +#define PINMUX_GPIO37__FUNC_PWM0 (MTK_PIN_NO(37) | 3) +#define PINMUX_GPIO37__FUNC_SCP_SPI0_CS (MTK_PIN_NO(37) | 4) +#define PINMUX_GPIO37__FUNC_SPINOR_CS (MTK_PIN_NO(37) | 5) +#define PINMUX_GPIO37__FUNC_DBG_MON_A12 (MTK_PIN_NO(37) | 7) + +#define PINMUX_GPIO38__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) +#define PINMUX_GPIO38__FUNC_SPI0_MO_A (MTK_PIN_NO(38) | 1) +#define PINMUX_GPIO38__FUNC_CLKM2 (MTK_PIN_NO(38) | 2) +#define PINMUX_GPIO38__FUNC_PWM1 (MTK_PIN_NO(38) | 3) +#define PINMUX_GPIO38__FUNC_SCP_SPI0_MO (MTK_PIN_NO(38) | 4) +#define PINMUX_GPIO38__FUNC_SPINOR_IO0 (MTK_PIN_NO(38) | 5) +#define PINMUX_GPIO38__FUNC_DBG_MON_A13 (MTK_PIN_NO(38) | 7) + +#define PINMUX_GPIO39__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) +#define PINMUX_GPIO39__FUNC_SPI0_MI_A (MTK_PIN_NO(39) | 1) +#define PINMUX_GPIO39__FUNC_CLKM3 (MTK_PIN_NO(39) | 2) +#define PINMUX_GPIO39__FUNC_PWM2 (MTK_PIN_NO(39) | 3) +#define PINMUX_GPIO39__FUNC_SCP_SPI0_MI (MTK_PIN_NO(39) | 4) +#define PINMUX_GPIO39__FUNC_SPINOR_IO1 (MTK_PIN_NO(39) | 5) +#define PINMUX_GPIO39__FUNC_DBG_MON_A14 (MTK_PIN_NO(39) | 7) + +#define PINMUX_GPIO40__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) +#define PINMUX_GPIO40__FUNC_SPI1_CLK_A (MTK_PIN_NO(40) | 1) +#define PINMUX_GPIO40__FUNC_SCP_SPI1_CK (MTK_PIN_NO(40) | 2) +#define PINMUX_GPIO40__FUNC_UCTS0 (MTK_PIN_NO(40) | 4) +#define PINMUX_GPIO40__FUNC_SPINOR_IO2 (MTK_PIN_NO(40) | 5) +#define PINMUX_GPIO40__FUNC_TP_UCTS1_AO (MTK_PIN_NO(40) | 6) +#define PINMUX_GPIO40__FUNC_DBG_MON_A15 (MTK_PIN_NO(40) | 7) + +#define PINMUX_GPIO41__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) +#define PINMUX_GPIO41__FUNC_SPI1_CSB_A (MTK_PIN_NO(41) | 1) +#define PINMUX_GPIO41__FUNC_SCP_SPI1_CS (MTK_PIN_NO(41) | 2) +#define PINMUX_GPIO41__FUNC_PWM0 (MTK_PIN_NO(41) | 3) +#define PINMUX_GPIO41__FUNC_URTS0 (MTK_PIN_NO(41) | 4) +#define PINMUX_GPIO41__FUNC_SPINOR_IO3 (MTK_PIN_NO(41) | 5) +#define PINMUX_GPIO41__FUNC_TP_URTS1_AO (MTK_PIN_NO(41) | 6) +#define PINMUX_GPIO41__FUNC_DBG_MON_A16 (MTK_PIN_NO(41) | 7) + +#define PINMUX_GPIO42__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) +#define PINMUX_GPIO42__FUNC_SPI1_MO_A (MTK_PIN_NO(42) | 1) +#define PINMUX_GPIO42__FUNC_SCP_SPI1_MO (MTK_PIN_NO(42) | 2) +#define PINMUX_GPIO42__FUNC_PWM1 (MTK_PIN_NO(42) | 3) +#define PINMUX_GPIO42__FUNC_UCTS1 (MTK_PIN_NO(42) | 4) +#define PINMUX_GPIO42__FUNC_TP_UCTS2_AO (MTK_PIN_NO(42) | 6) +#define PINMUX_GPIO42__FUNC_DBG_MON_A17 (MTK_PIN_NO(42) | 7) + +#define PINMUX_GPIO43__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) +#define PINMUX_GPIO43__FUNC_SPI1_MI_A (MTK_PIN_NO(43) | 1) +#define PINMUX_GPIO43__FUNC_SCP_SPI1_MI (MTK_PIN_NO(43) | 2) +#define PINMUX_GPIO43__FUNC_PWM2 (MTK_PIN_NO(43) | 3) +#define PINMUX_GPIO43__FUNC_URTS1 (MTK_PIN_NO(43) | 4) +#define PINMUX_GPIO43__FUNC_TP_URTS2_AO (MTK_PIN_NO(43) | 6) +#define PINMUX_GPIO43__FUNC_DBG_MON_A18 (MTK_PIN_NO(43) | 7) + +#define PINMUX_GPIO44__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) +#define PINMUX_GPIO44__FUNC_SPI2_CLK_A (MTK_PIN_NO(44) | 1) +#define PINMUX_GPIO44__FUNC_SCP_SPI0_CK (MTK_PIN_NO(44) | 2) +#define PINMUX_GPIO44__FUNC_DBG_MON_A19 (MTK_PIN_NO(44) | 7) + +#define PINMUX_GPIO45__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) +#define PINMUX_GPIO45__FUNC_SPI2_CSB_A (MTK_PIN_NO(45) | 1) +#define PINMUX_GPIO45__FUNC_SCP_SPI0_CS (MTK_PIN_NO(45) | 2) +#define PINMUX_GPIO45__FUNC_DBG_MON_A20 (MTK_PIN_NO(45) | 7) + +#define PINMUX_GPIO46__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) +#define PINMUX_GPIO46__FUNC_SPI2_MO_A (MTK_PIN_NO(46) | 1) +#define PINMUX_GPIO46__FUNC_SCP_SPI0_MO (MTK_PIN_NO(46) | 2) +#define PINMUX_GPIO46__FUNC_DBG_MON_A21 (MTK_PIN_NO(46) | 7) + +#define PINMUX_GPIO47__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) +#define PINMUX_GPIO47__FUNC_SPI2_MI_A (MTK_PIN_NO(47) | 1) +#define PINMUX_GPIO47__FUNC_SCP_SPI0_MI (MTK_PIN_NO(47) | 2) +#define PINMUX_GPIO47__FUNC_DBG_MON_A22 (MTK_PIN_NO(47) | 7) + +#define PINMUX_GPIO48__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) +#define PINMUX_GPIO48__FUNC_SPI3_CLK (MTK_PIN_NO(48) | 1) +#define PINMUX_GPIO48__FUNC_TP_URXD1_AO (MTK_PIN_NO(48) | 2) +#define PINMUX_GPIO48__FUNC_TP_URXD2_AO (MTK_PIN_NO(48) | 3) +#define PINMUX_GPIO48__FUNC_URXD1 (MTK_PIN_NO(48) | 4) +#define PINMUX_GPIO48__FUNC_I2S2_MCK (MTK_PIN_NO(48) | 5) +#define PINMUX_GPIO48__FUNC_SCP_SPI0_CK (MTK_PIN_NO(48) | 6) + +#define PINMUX_GPIO49__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) +#define PINMUX_GPIO49__FUNC_SPI3_CSB (MTK_PIN_NO(49) | 1) +#define PINMUX_GPIO49__FUNC_TP_UTXD1_AO (MTK_PIN_NO(49) | 2) +#define PINMUX_GPIO49__FUNC_TP_UTXD2_AO (MTK_PIN_NO(49) | 3) +#define PINMUX_GPIO49__FUNC_UTXD1 (MTK_PIN_NO(49) | 4) +#define PINMUX_GPIO49__FUNC_I2S2_BCK (MTK_PIN_NO(49) | 5) +#define PINMUX_GPIO49__FUNC_SCP_SPI0_CS (MTK_PIN_NO(49) | 6) + +#define PINMUX_GPIO50__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) +#define PINMUX_GPIO50__FUNC_SPI3_MO (MTK_PIN_NO(50) | 1) +#define PINMUX_GPIO50__FUNC_I2S2_LRCK (MTK_PIN_NO(50) | 5) +#define PINMUX_GPIO50__FUNC_SCP_SPI0_MO (MTK_PIN_NO(50) | 6) + +#define PINMUX_GPIO51__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) +#define PINMUX_GPIO51__FUNC_SPI3_MI (MTK_PIN_NO(51) | 1) +#define PINMUX_GPIO51__FUNC_I2S2_DI (MTK_PIN_NO(51) | 5) +#define PINMUX_GPIO51__FUNC_SCP_SPI0_MI (MTK_PIN_NO(51) | 6) + +#define PINMUX_GPIO52__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) +#define PINMUX_GPIO52__FUNC_SPI5_CLK (MTK_PIN_NO(52) | 1) +#define PINMUX_GPIO52__FUNC_I2S2_MCK (MTK_PIN_NO(52) | 2) +#define PINMUX_GPIO52__FUNC_I2S1_MCK (MTK_PIN_NO(52) | 3) +#define PINMUX_GPIO52__FUNC_SCP_SPI1_CK (MTK_PIN_NO(52) | 4) +#define PINMUX_GPIO52__FUNC_LVTS_26M (MTK_PIN_NO(52) | 5) +#define PINMUX_GPIO52__FUNC_DFD_TCK_XI (MTK_PIN_NO(52) | 6) +#define PINMUX_GPIO52__FUNC_DBG_MON_B30 (MTK_PIN_NO(52) | 7) + +#define PINMUX_GPIO53__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) +#define PINMUX_GPIO53__FUNC_SPI5_CSB (MTK_PIN_NO(53) | 1) +#define PINMUX_GPIO53__FUNC_I2S2_BCK (MTK_PIN_NO(53) | 2) +#define PINMUX_GPIO53__FUNC_I2S1_BCK (MTK_PIN_NO(53) | 3) +#define PINMUX_GPIO53__FUNC_SCP_SPI1_CS (MTK_PIN_NO(53) | 4) +#define PINMUX_GPIO53__FUNC_LVTS_FOUT (MTK_PIN_NO(53) | 5) +#define PINMUX_GPIO53__FUNC_DFD_TDI (MTK_PIN_NO(53) | 6) +#define PINMUX_GPIO53__FUNC_DBG_MON_B31 (MTK_PIN_NO(53) | 7) + +#define PINMUX_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) +#define PINMUX_GPIO54__FUNC_SPI5_MO (MTK_PIN_NO(54) | 1) +#define PINMUX_GPIO54__FUNC_I2S2_LRCK (MTK_PIN_NO(54) | 2) +#define PINMUX_GPIO54__FUNC_I2S1_LRCK (MTK_PIN_NO(54) | 3) +#define PINMUX_GPIO54__FUNC_SCP_SPI1_MO (MTK_PIN_NO(54) | 4) +#define PINMUX_GPIO54__FUNC_LVTS_SCK (MTK_PIN_NO(54) | 5) +#define PINMUX_GPIO54__FUNC_DFD_TDO (MTK_PIN_NO(54) | 6) +#define PINMUX_GPIO54__FUNC_DBG_MON_A1 (MTK_PIN_NO(54) | 7) + +#define PINMUX_GPIO55__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) +#define PINMUX_GPIO55__FUNC_SPI5_MI (MTK_PIN_NO(55) | 1) +#define PINMUX_GPIO55__FUNC_I2S2_DI (MTK_PIN_NO(55) | 2) +#define PINMUX_GPIO55__FUNC_I2S1_DO (MTK_PIN_NO(55) | 3) +#define PINMUX_GPIO55__FUNC_SCP_SPI1_MI (MTK_PIN_NO(55) | 4) +#define PINMUX_GPIO55__FUNC_LVTS_SDO (MTK_PIN_NO(55) | 5) +#define PINMUX_GPIO55__FUNC_DFD_TMS (MTK_PIN_NO(55) | 6) +#define PINMUX_GPIO55__FUNC_DBG_MON_B32 (MTK_PIN_NO(55) | 7) + +#define PINMUX_GPIO56__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) +#define PINMUX_GPIO56__FUNC_I2S1_DO (MTK_PIN_NO(56) | 1) +#define PINMUX_GPIO56__FUNC_I2S3_DO (MTK_PIN_NO(56) | 2) +#define PINMUX_GPIO56__FUNC_DBG_MON_A23 (MTK_PIN_NO(56) | 7) + +#define PINMUX_GPIO57__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) +#define PINMUX_GPIO57__FUNC_I2S1_BCK (MTK_PIN_NO(57) | 1) +#define PINMUX_GPIO57__FUNC_I2S3_BCK (MTK_PIN_NO(57) | 2) +#define PINMUX_GPIO57__FUNC_DBG_MON_A24 (MTK_PIN_NO(57) | 7) + +#define PINMUX_GPIO58__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) +#define PINMUX_GPIO58__FUNC_I2S1_LRCK (MTK_PIN_NO(58) | 1) +#define PINMUX_GPIO58__FUNC_I2S3_LRCK (MTK_PIN_NO(58) | 2) +#define PINMUX_GPIO58__FUNC_DBG_MON_A25 (MTK_PIN_NO(58) | 7) + +#define PINMUX_GPIO59__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) +#define PINMUX_GPIO59__FUNC_I2S1_MCK (MTK_PIN_NO(59) | 1) +#define PINMUX_GPIO59__FUNC_I2S3_MCK (MTK_PIN_NO(59) | 2) +#define PINMUX_GPIO59__FUNC_DBG_MON_A27 (MTK_PIN_NO(59) | 7) + +#define PINMUX_GPIO60__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) +#define PINMUX_GPIO60__FUNC_TDM_RX_LRCK (MTK_PIN_NO(60) | 1) +#define PINMUX_GPIO60__FUNC_ANT_SEL3 (MTK_PIN_NO(60) | 2) +#define PINMUX_GPIO60__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(60) | 5) + +#define PINMUX_GPIO61__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) +#define PINMUX_GPIO61__FUNC_TDM_RX_BCK (MTK_PIN_NO(61) | 1) +#define PINMUX_GPIO61__FUNC_ANT_SEL4 (MTK_PIN_NO(61) | 2) +#define PINMUX_GPIO61__FUNC_SPINOR_CK (MTK_PIN_NO(61) | 4) +#define PINMUX_GPIO61__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(61) | 5) + +#define PINMUX_GPIO62__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) +#define PINMUX_GPIO62__FUNC_TDM_RX_MCK (MTK_PIN_NO(62) | 1) +#define PINMUX_GPIO62__FUNC_ANT_SEL5 (MTK_PIN_NO(62) | 2) +#define PINMUX_GPIO62__FUNC_SPINOR_CS (MTK_PIN_NO(62) | 4) +#define PINMUX_GPIO62__FUNC_CONN_MCU_TDI (MTK_PIN_NO(62) | 5) + +#define PINMUX_GPIO63__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) +#define PINMUX_GPIO63__FUNC_TDM_RX_DATA0 (MTK_PIN_NO(63) | 1) +#define PINMUX_GPIO63__FUNC_ANT_SEL6 (MTK_PIN_NO(63) | 2) +#define PINMUX_GPIO63__FUNC_SPINOR_IO0 (MTK_PIN_NO(63) | 4) +#define PINMUX_GPIO63__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(63) | 5) + +#define PINMUX_GPIO64__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) +#define PINMUX_GPIO64__FUNC_TDM_RX_DATA1 (MTK_PIN_NO(64) | 1) +#define PINMUX_GPIO64__FUNC_ANT_SEL7 (MTK_PIN_NO(64) | 2) +#define PINMUX_GPIO64__FUNC_PWM0 (MTK_PIN_NO(64) | 3) +#define PINMUX_GPIO64__FUNC_SPINOR_IO1 (MTK_PIN_NO(64) | 4) +#define PINMUX_GPIO64__FUNC_CONN_MCU_TCK (MTK_PIN_NO(64) | 5) + +#define PINMUX_GPIO65__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) +#define PINMUX_GPIO65__FUNC_TDM_RX_DATA2 (MTK_PIN_NO(65) | 1) +#define PINMUX_GPIO65__FUNC_UCTS0 (MTK_PIN_NO(65) | 2) +#define PINMUX_GPIO65__FUNC_PWM1 (MTK_PIN_NO(65) | 3) +#define PINMUX_GPIO65__FUNC_SPINOR_IO2 (MTK_PIN_NO(65) | 4) +#define PINMUX_GPIO65__FUNC_CONN_MCU_TDO (MTK_PIN_NO(65) | 5) +#define PINMUX_GPIO65__FUNC_TP_UCTS1_AO (MTK_PIN_NO(65) | 6) +#define PINMUX_GPIO65__FUNC_TP_UCTS2_AO (MTK_PIN_NO(65) | 7) + +#define PINMUX_GPIO66__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) +#define PINMUX_GPIO66__FUNC_TDM_RX_DATA3 (MTK_PIN_NO(66) | 1) +#define PINMUX_GPIO66__FUNC_URTS0 (MTK_PIN_NO(66) | 2) +#define PINMUX_GPIO66__FUNC_PWM2 (MTK_PIN_NO(66) | 3) +#define PINMUX_GPIO66__FUNC_SPINOR_IO3 (MTK_PIN_NO(66) | 4) +#define PINMUX_GPIO66__FUNC_CONN_MCU_TMS (MTK_PIN_NO(66) | 5) +#define PINMUX_GPIO66__FUNC_TP_URTS1_AO (MTK_PIN_NO(66) | 6) +#define PINMUX_GPIO66__FUNC_TP_URTS2_AO (MTK_PIN_NO(66) | 7) + +#define PINMUX_GPIO67__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) +#define PINMUX_GPIO67__FUNC_MSDC0_DSL (MTK_PIN_NO(67) | 1) + +#define PINMUX_GPIO68__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) +#define PINMUX_GPIO68__FUNC_MSDC0_CLK (MTK_PIN_NO(68) | 1) + +#define PINMUX_GPIO69__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) +#define PINMUX_GPIO69__FUNC_MSDC0_CMD (MTK_PIN_NO(69) | 1) + +#define PINMUX_GPIO70__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) +#define PINMUX_GPIO70__FUNC_MSDC0_RSTB (MTK_PIN_NO(70) | 1) + +#define PINMUX_GPIO71__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) +#define PINMUX_GPIO71__FUNC_MSDC0_DAT0 (MTK_PIN_NO(71) | 1) + +#define PINMUX_GPIO72__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) +#define PINMUX_GPIO72__FUNC_MSDC0_DAT1 (MTK_PIN_NO(72) | 1) + +#define PINMUX_GPIO73__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) +#define PINMUX_GPIO73__FUNC_MSDC0_DAT2 (MTK_PIN_NO(73) | 1) + +#define PINMUX_GPIO74__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) +#define PINMUX_GPIO74__FUNC_MSDC0_DAT3 (MTK_PIN_NO(74) | 1) + +#define PINMUX_GPIO75__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) +#define PINMUX_GPIO75__FUNC_MSDC0_DAT4 (MTK_PIN_NO(75) | 1) + +#define PINMUX_GPIO76__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) +#define PINMUX_GPIO76__FUNC_MSDC0_DAT5 (MTK_PIN_NO(76) | 1) + +#define PINMUX_GPIO77__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) +#define PINMUX_GPIO77__FUNC_MSDC0_DAT6 (MTK_PIN_NO(77) | 1) + +#define PINMUX_GPIO78__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) +#define PINMUX_GPIO78__FUNC_MSDC0_DAT7 (MTK_PIN_NO(78) | 1) + +#define PINMUX_GPIO79__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) +#define PINMUX_GPIO79__FUNC_KPCOL0 (MTK_PIN_NO(79) | 1) + +#define PINMUX_GPIO80__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) +#define PINMUX_GPIO80__FUNC_KPCOL1 (MTK_PIN_NO(80) | 1) +#define PINMUX_GPIO80__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(80) | 2) +#define PINMUX_GPIO80__FUNC_PWM0 (MTK_PIN_NO(80) | 3) +#define PINMUX_GPIO80__FUNC_CLKM0 (MTK_PIN_NO(80) | 4) + +#define PINMUX_GPIO81__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) +#define PINMUX_GPIO81__FUNC_KPROW0 (MTK_PIN_NO(81) | 1) +#define PINMUX_GPIO81__FUNC_PWM1 (MTK_PIN_NO(81) | 3) +#define PINMUX_GPIO81__FUNC_CLKM1 (MTK_PIN_NO(81) | 4) + +#define PINMUX_GPIO82__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) +#define PINMUX_GPIO82__FUNC_KPROW1 (MTK_PIN_NO(82) | 1) +#define PINMUX_GPIO82__FUNC_PWM2 (MTK_PIN_NO(82) | 3) +#define PINMUX_GPIO82__FUNC_CLKM2 (MTK_PIN_NO(82) | 4) + +#define PINMUX_GPIO83__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) +#define PINMUX_GPIO83__FUNC_AP_GOOD (MTK_PIN_NO(83) | 1) +#define PINMUX_GPIO83__FUNC_GPS_PPS (MTK_PIN_NO(83) | 2) +#define PINMUX_GPIO83__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(83) | 4) +#define PINMUX_GPIO83__FUNC_DBG_MON_A28 (MTK_PIN_NO(83) | 7) + +#define PINMUX_GPIO84__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) +#define PINMUX_GPIO84__FUNC_MSDC1_CLK (MTK_PIN_NO(84) | 1) +#define PINMUX_GPIO84__FUNC_ADSP_JTAG_TCK (MTK_PIN_NO(84) | 2) +#define PINMUX_GPIO84__FUNC_UDI_TCK (MTK_PIN_NO(84) | 4) +#define PINMUX_GPIO84__FUNC_CONN_DSP_JCK (MTK_PIN_NO(84) | 5) +#define PINMUX_GPIO84__FUNC_SSPM_JTAG_TCK (MTK_PIN_NO(84) | 6) +#define PINMUX_GPIO84__FUNC_DFD_TCK_XI (MTK_PIN_NO(84) | 7) + +#define PINMUX_GPIO85__FUNC_GPIO85 (MTK_PIN_NO(85) | 0) +#define PINMUX_GPIO85__FUNC_MSDC1_CMD (MTK_PIN_NO(85) | 1) +#define PINMUX_GPIO85__FUNC_ADSP_JTAG_TMS (MTK_PIN_NO(85) | 2) +#define PINMUX_GPIO85__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(85) | 3) +#define PINMUX_GPIO85__FUNC_UDI_TMS (MTK_PIN_NO(85) | 4) +#define PINMUX_GPIO85__FUNC_CONN_DSP_JMS (MTK_PIN_NO(85) | 5) +#define PINMUX_GPIO85__FUNC_SSPM_JTAG_TMS (MTK_PIN_NO(85) | 6) +#define PINMUX_GPIO85__FUNC_DFD_TMS (MTK_PIN_NO(85) | 7) + +#define PINMUX_GPIO86__FUNC_GPIO86 (MTK_PIN_NO(86) | 0) +#define PINMUX_GPIO86__FUNC_MSDC1_DAT0 (MTK_PIN_NO(86) | 1) +#define PINMUX_GPIO86__FUNC_ADSP_JTAG_TDI (MTK_PIN_NO(86) | 2) +#define PINMUX_GPIO86__FUNC_UDI_TDI (MTK_PIN_NO(86) | 4) +#define PINMUX_GPIO86__FUNC_CONN_DSP_JDI (MTK_PIN_NO(86) | 5) +#define PINMUX_GPIO86__FUNC_SSPM_JTAG_TDI (MTK_PIN_NO(86) | 6) +#define PINMUX_GPIO86__FUNC_DFD_TDI (MTK_PIN_NO(86) | 7) + +#define PINMUX_GPIO87__FUNC_GPIO87 (MTK_PIN_NO(87) | 0) +#define PINMUX_GPIO87__FUNC_MSDC1_DAT1 (MTK_PIN_NO(87) | 1) +#define PINMUX_GPIO87__FUNC_ADSP_JTAG_TDO (MTK_PIN_NO(87) | 2) +#define PINMUX_GPIO87__FUNC_UDI_TDO (MTK_PIN_NO(87) | 4) +#define PINMUX_GPIO87__FUNC_CONN_DSP_JDO (MTK_PIN_NO(87) | 5) +#define PINMUX_GPIO87__FUNC_SSPM_JTAG_TDO (MTK_PIN_NO(87) | 6) +#define PINMUX_GPIO87__FUNC_DFD_TDO (MTK_PIN_NO(87) | 7) + +#define PINMUX_GPIO88__FUNC_GPIO88 (MTK_PIN_NO(88) | 0) +#define PINMUX_GPIO88__FUNC_MSDC1_DAT2 (MTK_PIN_NO(88) | 1) +#define PINMUX_GPIO88__FUNC_ADSP_JTAG_TRSTN (MTK_PIN_NO(88) | 2) +#define PINMUX_GPIO88__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(88) | 3) +#define PINMUX_GPIO88__FUNC_UDI_NTRST (MTK_PIN_NO(88) | 4) +#define PINMUX_GPIO88__FUNC_CONN_WIFI_TXD (MTK_PIN_NO(88) | 5) +#define PINMUX_GPIO88__FUNC_SSPM_JTAG_TRSTN (MTK_PIN_NO(88) | 6) + +#define PINMUX_GPIO89__FUNC_GPIO89 (MTK_PIN_NO(89) | 0) +#define PINMUX_GPIO89__FUNC_MSDC1_DAT3 (MTK_PIN_NO(89) | 1) +#define PINMUX_GPIO89__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(89) | 5) + +#define PINMUX_GPIO90__FUNC_GPIO90 (MTK_PIN_NO(90) | 0) +#define PINMUX_GPIO90__FUNC_IDDIG_P0 (MTK_PIN_NO(90) | 1) +#define PINMUX_GPIO90__FUNC_PGD_HV_HSC_PWR4 (MTK_PIN_NO(90) | 4) +#define PINMUX_GPIO90__FUNC_GDU_SUM_TROOP2_2 (MTK_PIN_NO(90) | 5) + +#define PINMUX_GPIO91__FUNC_GPIO91 (MTK_PIN_NO(91) | 0) +#define PINMUX_GPIO91__FUNC_USB_DRVVBUS_P0 (MTK_PIN_NO(91) | 1) +#define PINMUX_GPIO91__FUNC_PGD_HV_HSC_PWR5 (MTK_PIN_NO(91) | 4) +#define PINMUX_GPIO91__FUNC_GDU_TROOPS_DET0 (MTK_PIN_NO(91) | 5) + +#define PINMUX_GPIO92__FUNC_GPIO92 (MTK_PIN_NO(92) | 0) +#define PINMUX_GPIO92__FUNC_VBUS_VALID_P0 (MTK_PIN_NO(92) | 1) +#define PINMUX_GPIO92__FUNC_PGD_DA_EFUSE_RDY (MTK_PIN_NO(92) | 4) +#define PINMUX_GPIO92__FUNC_GDU_TROOPS_DET1 (MTK_PIN_NO(92) | 5) + +#define PINMUX_GPIO93__FUNC_GPIO93 (MTK_PIN_NO(93) | 0) +#define PINMUX_GPIO93__FUNC_IDDIG_P1 (MTK_PIN_NO(93) | 1) +#define PINMUX_GPIO93__FUNC_PWM0 (MTK_PIN_NO(93) | 2) +#define PINMUX_GPIO93__FUNC_CLKM0 (MTK_PIN_NO(93) | 3) +#define PINMUX_GPIO93__FUNC_PGD_DA_EFUSE_RDY_PRE (MTK_PIN_NO(93) | 4) +#define PINMUX_GPIO93__FUNC_GDU_TROOPS_DET2 (MTK_PIN_NO(93) | 5) + +#define PINMUX_GPIO94__FUNC_GPIO94 (MTK_PIN_NO(94) | 0) +#define PINMUX_GPIO94__FUNC_USB_DRVVBUS_P1 (MTK_PIN_NO(94) | 1) +#define PINMUX_GPIO94__FUNC_PWM1 (MTK_PIN_NO(94) | 2) +#define PINMUX_GPIO94__FUNC_CLKM1 (MTK_PIN_NO(94) | 3) +#define PINMUX_GPIO94__FUNC_PGD_DA_PWRGD_RESET (MTK_PIN_NO(94) | 4) + +#define PINMUX_GPIO95__FUNC_GPIO95 (MTK_PIN_NO(95) | 0) +#define PINMUX_GPIO95__FUNC_VBUS_VALID_P1 (MTK_PIN_NO(95) | 1) +#define PINMUX_GPIO95__FUNC_PWM2 (MTK_PIN_NO(95) | 2) +#define PINMUX_GPIO95__FUNC_CLKM2 (MTK_PIN_NO(95) | 3) +#define PINMUX_GPIO95__FUNC_PGD_DA_PWRGD_ENB (MTK_PIN_NO(95) | 4) + +#define PINMUX_GPIO96__FUNC_GPIO96 (MTK_PIN_NO(96) | 0) +#define PINMUX_GPIO96__FUNC_DSI_TE (MTK_PIN_NO(96) | 1) +#define PINMUX_GPIO96__FUNC_DBG_MON_A29 (MTK_PIN_NO(96) | 7) + +#define PINMUX_GPIO97__FUNC_GPIO97 (MTK_PIN_NO(97) | 0) +#define PINMUX_GPIO97__FUNC_DISP_PWM (MTK_PIN_NO(97) | 1) +#define PINMUX_GPIO97__FUNC_DBG_MON_A30 (MTK_PIN_NO(97) | 7) + +#define PINMUX_GPIO98__FUNC_GPIO98 (MTK_PIN_NO(98) | 0) +#define PINMUX_GPIO98__FUNC_LCM_RST (MTK_PIN_NO(98) | 1) + +#define PINMUX_GPIO99__FUNC_GPIO99 (MTK_PIN_NO(99) | 0) +#define PINMUX_GPIO99__FUNC_DPI_PCLK (MTK_PIN_NO(99) | 1) +#define PINMUX_GPIO99__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(99) | 2) +#define PINMUX_GPIO99__FUNC_SSPM_JTAG_TCK (MTK_PIN_NO(99) | 3) +#define PINMUX_GPIO99__FUNC_ANT_SEL0 (MTK_PIN_NO(99) | 5) +#define PINMUX_GPIO99__FUNC_TP_GPIO0_AO (MTK_PIN_NO(99) | 6) +#define PINMUX_GPIO99__FUNC_PGD_LV_LSC_PWR0 (MTK_PIN_NO(99) | 7) + +#define PINMUX_GPIO100__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) +#define PINMUX_GPIO100__FUNC_DPI_VSYNC (MTK_PIN_NO(100) | 1) +#define PINMUX_GPIO100__FUNC_KPCOL2 (MTK_PIN_NO(100) | 2) +#define PINMUX_GPIO100__FUNC_SSPM_JTAG_TMS (MTK_PIN_NO(100) | 3) +#define PINMUX_GPIO100__FUNC_ANT_SEL1 (MTK_PIN_NO(100) | 5) +#define PINMUX_GPIO100__FUNC_TP_GPIO1_AO (MTK_PIN_NO(100) | 6) +#define PINMUX_GPIO100__FUNC_PGD_LV_LSC_PWR1 (MTK_PIN_NO(100) | 7) + +#define PINMUX_GPIO101__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) +#define PINMUX_GPIO101__FUNC_DPI_HSYNC (MTK_PIN_NO(101) | 1) +#define PINMUX_GPIO101__FUNC_KPROW2 (MTK_PIN_NO(101) | 2) +#define PINMUX_GPIO101__FUNC_SSPM_JTAG_TDI (MTK_PIN_NO(101) | 3) +#define PINMUX_GPIO101__FUNC_ANT_SEL2 (MTK_PIN_NO(101) | 5) +#define PINMUX_GPIO101__FUNC_TP_GPIO2_AO (MTK_PIN_NO(101) | 6) +#define PINMUX_GPIO101__FUNC_PGD_LV_LSC_PWR2 (MTK_PIN_NO(101) | 7) + +#define PINMUX_GPIO102__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) +#define PINMUX_GPIO102__FUNC_DPI_DE (MTK_PIN_NO(102) | 1) +#define PINMUX_GPIO102__FUNC_SSPM_JTAG_TDO (MTK_PIN_NO(102) | 3) +#define PINMUX_GPIO102__FUNC_ANT_SEL3 (MTK_PIN_NO(102) | 5) +#define PINMUX_GPIO102__FUNC_TP_GPIO3_AO (MTK_PIN_NO(102) | 6) +#define PINMUX_GPIO102__FUNC_PGD_LV_LSC_PWR3 (MTK_PIN_NO(102) | 7) + +#define PINMUX_GPIO103__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) +#define PINMUX_GPIO103__FUNC_DPI_DATA0 (MTK_PIN_NO(103) | 1) +#define PINMUX_GPIO103__FUNC_SSPM_JTAG_TRSTN (MTK_PIN_NO(103) | 3) +#define PINMUX_GPIO103__FUNC_CLKM0 (MTK_PIN_NO(103) | 4) +#define PINMUX_GPIO103__FUNC_ANT_SEL4 (MTK_PIN_NO(103) | 5) +#define PINMUX_GPIO103__FUNC_TP_GPIO4_AO (MTK_PIN_NO(103) | 6) +#define PINMUX_GPIO103__FUNC_PGD_LV_LSC_PWR4 (MTK_PIN_NO(103) | 7) + +#define PINMUX_GPIO104__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) +#define PINMUX_GPIO104__FUNC_DPI_DATA1 (MTK_PIN_NO(104) | 1) +#define PINMUX_GPIO104__FUNC_GPS_PPS (MTK_PIN_NO(104) | 2) +#define PINMUX_GPIO104__FUNC_UCTS2 (MTK_PIN_NO(104) | 3) +#define PINMUX_GPIO104__FUNC_CLKM1 (MTK_PIN_NO(104) | 4) +#define PINMUX_GPIO104__FUNC_ANT_SEL5 (MTK_PIN_NO(104) | 5) +#define PINMUX_GPIO104__FUNC_TP_GPIO5_AO (MTK_PIN_NO(104) | 6) +#define PINMUX_GPIO104__FUNC_PGD_LV_LSC_PWR5 (MTK_PIN_NO(104) | 7) + +#define PINMUX_GPIO105__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) +#define PINMUX_GPIO105__FUNC_DPI_DATA2 (MTK_PIN_NO(105) | 1) +#define PINMUX_GPIO105__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(105) | 2) +#define PINMUX_GPIO105__FUNC_URTS2 (MTK_PIN_NO(105) | 3) +#define PINMUX_GPIO105__FUNC_CLKM2 (MTK_PIN_NO(105) | 4) +#define PINMUX_GPIO105__FUNC_ANT_SEL6 (MTK_PIN_NO(105) | 5) +#define PINMUX_GPIO105__FUNC_TP_GPIO6_AO (MTK_PIN_NO(105) | 6) +#define PINMUX_GPIO105__FUNC_PGD_LV_HSC_PWR0 (MTK_PIN_NO(105) | 7) + +#define PINMUX_GPIO106__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) +#define PINMUX_GPIO106__FUNC_DPI_DATA3 (MTK_PIN_NO(106) | 1) +#define PINMUX_GPIO106__FUNC_TP_UTXD1_AO (MTK_PIN_NO(106) | 2) +#define PINMUX_GPIO106__FUNC_UTXD2 (MTK_PIN_NO(106) | 3) +#define PINMUX_GPIO106__FUNC_PWM0 (MTK_PIN_NO(106) | 4) +#define PINMUX_GPIO106__FUNC_ANT_SEL7 (MTK_PIN_NO(106) | 5) +#define PINMUX_GPIO106__FUNC_TP_GPIO7_AO (MTK_PIN_NO(106) | 6) +#define PINMUX_GPIO106__FUNC_PGD_LV_HSC_PWR1 (MTK_PIN_NO(106) | 7) + +#define PINMUX_GPIO107__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) +#define PINMUX_GPIO107__FUNC_DPI_DATA4 (MTK_PIN_NO(107) | 1) +#define PINMUX_GPIO107__FUNC_TP_URXD1_AO (MTK_PIN_NO(107) | 2) +#define PINMUX_GPIO107__FUNC_URXD2 (MTK_PIN_NO(107) | 3) +#define PINMUX_GPIO107__FUNC_PWM1 (MTK_PIN_NO(107) | 4) +#define PINMUX_GPIO107__FUNC_GDU_SUM_TROOP0_0 (MTK_PIN_NO(107) | 6) +#define PINMUX_GPIO107__FUNC_PGD_LV_HSC_PWR2 (MTK_PIN_NO(107) | 7) + +#define PINMUX_GPIO108__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) +#define PINMUX_GPIO108__FUNC_DPI_DATA5 (MTK_PIN_NO(108) | 1) +#define PINMUX_GPIO108__FUNC_TP_UCTS1_AO (MTK_PIN_NO(108) | 2) +#define PINMUX_GPIO108__FUNC_UCTS0 (MTK_PIN_NO(108) | 3) +#define PINMUX_GPIO108__FUNC_PWM2 (MTK_PIN_NO(108) | 4) +#define PINMUX_GPIO108__FUNC_GDU_SUM_TROOP0_1 (MTK_PIN_NO(108) | 6) +#define PINMUX_GPIO108__FUNC_PGD_LV_HSC_PWR3 (MTK_PIN_NO(108) | 7) + +#define PINMUX_GPIO109__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) +#define PINMUX_GPIO109__FUNC_DPI_DATA6 (MTK_PIN_NO(109) | 1) +#define PINMUX_GPIO109__FUNC_TP_URTS1_AO (MTK_PIN_NO(109) | 2) +#define PINMUX_GPIO109__FUNC_URTS0 (MTK_PIN_NO(109) | 3) +#define PINMUX_GPIO109__FUNC_I2S0_DI (MTK_PIN_NO(109) | 4) +#define PINMUX_GPIO109__FUNC_I2S2_DI (MTK_PIN_NO(109) | 5) +#define PINMUX_GPIO109__FUNC_GDU_SUM_TROOP0_2 (MTK_PIN_NO(109) | 6) +#define PINMUX_GPIO109__FUNC_PGD_LV_HSC_PWR4 (MTK_PIN_NO(109) | 7) + +#define PINMUX_GPIO110__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) +#define PINMUX_GPIO110__FUNC_DPI_DATA7 (MTK_PIN_NO(110) | 1) +#define PINMUX_GPIO110__FUNC_TP_UCTS2_AO (MTK_PIN_NO(110) | 2) +#define PINMUX_GPIO110__FUNC_UCTS1 (MTK_PIN_NO(110) | 3) +#define PINMUX_GPIO110__FUNC_I2S3_BCK (MTK_PIN_NO(110) | 4) +#define PINMUX_GPIO110__FUNC_I2S1_BCK (MTK_PIN_NO(110) | 5) +#define PINMUX_GPIO110__FUNC_GDU_SUM_TROOP1_0 (MTK_PIN_NO(110) | 6) +#define PINMUX_GPIO110__FUNC_PGD_LV_HSC_PWR5 (MTK_PIN_NO(110) | 7) + +#define PINMUX_GPIO111__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) +#define PINMUX_GPIO111__FUNC_DPI_DATA8 (MTK_PIN_NO(111) | 1) +#define PINMUX_GPIO111__FUNC_TP_URTS2_AO (MTK_PIN_NO(111) | 2) +#define PINMUX_GPIO111__FUNC_URTS1 (MTK_PIN_NO(111) | 3) +#define PINMUX_GPIO111__FUNC_I2S3_MCK (MTK_PIN_NO(111) | 4) +#define PINMUX_GPIO111__FUNC_I2S1_MCK (MTK_PIN_NO(111) | 5) +#define PINMUX_GPIO111__FUNC_GDU_SUM_TROOP1_1 (MTK_PIN_NO(111) | 6) +#define PINMUX_GPIO111__FUNC_PGD_HV_HSC_PWR0 (MTK_PIN_NO(111) | 7) + +#define PINMUX_GPIO112__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) +#define PINMUX_GPIO112__FUNC_DPI_DATA9 (MTK_PIN_NO(112) | 1) +#define PINMUX_GPIO112__FUNC_TP_URXD2_AO (MTK_PIN_NO(112) | 2) +#define PINMUX_GPIO112__FUNC_URXD1 (MTK_PIN_NO(112) | 3) +#define PINMUX_GPIO112__FUNC_I2S3_LRCK (MTK_PIN_NO(112) | 4) +#define PINMUX_GPIO112__FUNC_I2S1_LRCK (MTK_PIN_NO(112) | 5) +#define PINMUX_GPIO112__FUNC_GDU_SUM_TROOP1_2 (MTK_PIN_NO(112) | 6) +#define PINMUX_GPIO112__FUNC_PGD_HV_HSC_PWR1 (MTK_PIN_NO(112) | 7) + +#define PINMUX_GPIO113__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) +#define PINMUX_GPIO113__FUNC_DPI_DATA10 (MTK_PIN_NO(113) | 1) +#define PINMUX_GPIO113__FUNC_TP_UTXD2_AO (MTK_PIN_NO(113) | 2) +#define PINMUX_GPIO113__FUNC_UTXD1 (MTK_PIN_NO(113) | 3) +#define PINMUX_GPIO113__FUNC_I2S3_DO (MTK_PIN_NO(113) | 4) +#define PINMUX_GPIO113__FUNC_I2S1_DO (MTK_PIN_NO(113) | 5) +#define PINMUX_GPIO113__FUNC_GDU_SUM_TROOP2_0 (MTK_PIN_NO(113) | 6) +#define PINMUX_GPIO113__FUNC_PGD_HV_HSC_PWR2 (MTK_PIN_NO(113) | 7) + +#define PINMUX_GPIO114__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) +#define PINMUX_GPIO114__FUNC_DPI_DATA11 (MTK_PIN_NO(114) | 1) +#define PINMUX_GPIO114__FUNC_GDU_SUM_TROOP2_1 (MTK_PIN_NO(114) | 6) +#define PINMUX_GPIO114__FUNC_PGD_HV_HSC_PWR3 (MTK_PIN_NO(114) | 7) + +#define PINMUX_GPIO115__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) +#define PINMUX_GPIO115__FUNC_PCM_CLK (MTK_PIN_NO(115) | 1) +#define PINMUX_GPIO115__FUNC_I2S0_BCK (MTK_PIN_NO(115) | 2) +#define PINMUX_GPIO115__FUNC_I2S2_BCK (MTK_PIN_NO(115) | 3) + +#define PINMUX_GPIO116__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) +#define PINMUX_GPIO116__FUNC_PCM_SYNC (MTK_PIN_NO(116) | 1) +#define PINMUX_GPIO116__FUNC_I2S0_LRCK (MTK_PIN_NO(116) | 2) +#define PINMUX_GPIO116__FUNC_I2S2_LRCK (MTK_PIN_NO(116) | 3) + +#define PINMUX_GPIO117__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) +#define PINMUX_GPIO117__FUNC_PCM_DI (MTK_PIN_NO(117) | 1) +#define PINMUX_GPIO117__FUNC_I2S0_DI (MTK_PIN_NO(117) | 2) +#define PINMUX_GPIO117__FUNC_I2S2_DI (MTK_PIN_NO(117) | 3) + +#define PINMUX_GPIO118__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) +#define PINMUX_GPIO118__FUNC_PCM_DO (MTK_PIN_NO(118) | 1) +#define PINMUX_GPIO118__FUNC_I2S0_MCK (MTK_PIN_NO(118) | 2) +#define PINMUX_GPIO118__FUNC_I2S2_MCK (MTK_PIN_NO(118) | 3) +#define PINMUX_GPIO118__FUNC_I2S3_DO (MTK_PIN_NO(118) | 4) +#define PINMUX_GPIO118__FUNC_I2S1_DO (MTK_PIN_NO(118) | 5) + +#define PINMUX_GPIO119__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) +#define PINMUX_GPIO119__FUNC_JTMS_SEL1 (MTK_PIN_NO(119) | 1) +#define PINMUX_GPIO119__FUNC_UDI_TMS (MTK_PIN_NO(119) | 2) +#define PINMUX_GPIO119__FUNC_DFD_TMS (MTK_PIN_NO(119) | 3) +#define PINMUX_GPIO119__FUNC_SPM_JTAG_TMS (MTK_PIN_NO(119) | 4) +#define PINMUX_GPIO119__FUNC_SCP_JTAG_TMS (MTK_PIN_NO(119) | 5) +#define PINMUX_GPIO119__FUNC_ADSP_JTAG_TMS (MTK_PIN_NO(119) | 6) + +#define PINMUX_GPIO120__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) +#define PINMUX_GPIO120__FUNC_JTCK_SEL1 (MTK_PIN_NO(120) | 1) +#define PINMUX_GPIO120__FUNC_UDI_TCK (MTK_PIN_NO(120) | 2) +#define PINMUX_GPIO120__FUNC_DFD_TCK_XI (MTK_PIN_NO(120) | 3) +#define PINMUX_GPIO120__FUNC_SPM_JTAG_TCK (MTK_PIN_NO(120) | 4) +#define PINMUX_GPIO120__FUNC_SCP_JTAG_TCK (MTK_PIN_NO(120) | 5) +#define PINMUX_GPIO120__FUNC_ADSP_JTAG_TCK (MTK_PIN_NO(120) | 6) + +#define PINMUX_GPIO121__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) +#define PINMUX_GPIO121__FUNC_JTDI_SEL1 (MTK_PIN_NO(121) | 1) +#define PINMUX_GPIO121__FUNC_UDI_TDI (MTK_PIN_NO(121) | 2) +#define PINMUX_GPIO121__FUNC_DFD_TDI (MTK_PIN_NO(121) | 3) +#define PINMUX_GPIO121__FUNC_SPM_JTAG_TDI (MTK_PIN_NO(121) | 4) +#define PINMUX_GPIO121__FUNC_SCP_JTAG_TDI (MTK_PIN_NO(121) | 5) +#define PINMUX_GPIO121__FUNC_ADSP_JTAG_TDI (MTK_PIN_NO(121) | 6) + +#define PINMUX_GPIO122__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) +#define PINMUX_GPIO122__FUNC_JTDO_SEL1 (MTK_PIN_NO(122) | 1) +#define PINMUX_GPIO122__FUNC_UDI_TDO (MTK_PIN_NO(122) | 2) +#define PINMUX_GPIO122__FUNC_DFD_TDO (MTK_PIN_NO(122) | 3) +#define PINMUX_GPIO122__FUNC_SPM_JTAG_TDO (MTK_PIN_NO(122) | 4) +#define PINMUX_GPIO122__FUNC_SCP_JTAG_TDO (MTK_PIN_NO(122) | 5) +#define PINMUX_GPIO122__FUNC_ADSP_JTAG_TDO (MTK_PIN_NO(122) | 6) + +#define PINMUX_GPIO123__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) +#define PINMUX_GPIO123__FUNC_JTRSTN_SEL1 (MTK_PIN_NO(123) | 1) +#define PINMUX_GPIO123__FUNC_UDI_NTRST (MTK_PIN_NO(123) | 2) +#define PINMUX_GPIO123__FUNC_SPM_JTAG_TRSTN (MTK_PIN_NO(123) | 4) +#define PINMUX_GPIO123__FUNC_SCP_JTAG_TRSTN (MTK_PIN_NO(123) | 5) +#define PINMUX_GPIO123__FUNC_ADSP_JTAG_TRSTN (MTK_PIN_NO(123) | 6) + +#define PINMUX_GPIO124__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) +#define PINMUX_GPIO124__FUNC_CMMCLK0 (MTK_PIN_NO(124) | 1) +#define PINMUX_GPIO124__FUNC_CLKM0 (MTK_PIN_NO(124) | 2) +#define PINMUX_GPIO124__FUNC_PWM0 (MTK_PIN_NO(124) | 3) + +#define PINMUX_GPIO125__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) +#define PINMUX_GPIO125__FUNC_CMMCLK1 (MTK_PIN_NO(125) | 1) +#define PINMUX_GPIO125__FUNC_CLKM1 (MTK_PIN_NO(125) | 2) +#define PINMUX_GPIO125__FUNC_PWM1 (MTK_PIN_NO(125) | 3) +#define PINMUX_GPIO125__FUNC_DBG_MON_B0 (MTK_PIN_NO(125) | 7) + +#define PINMUX_GPIO126__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) +#define PINMUX_GPIO126__FUNC_CMMCLK2 (MTK_PIN_NO(126) | 1) +#define PINMUX_GPIO126__FUNC_CLKM2 (MTK_PIN_NO(126) | 2) +#define PINMUX_GPIO126__FUNC_PWM2 (MTK_PIN_NO(126) | 3) +#define PINMUX_GPIO126__FUNC_DBG_MON_B1 (MTK_PIN_NO(126) | 7) + +#define PINMUX_GPIO127__FUNC_GPIO127 (MTK_PIN_NO(127) | 0) +#define PINMUX_GPIO127__FUNC_SCL0 (MTK_PIN_NO(127) | 1) +#define PINMUX_GPIO127__FUNC_SCP_SCL0 (MTK_PIN_NO(127) | 4) +#define PINMUX_GPIO127__FUNC_SCP_SCL1 (MTK_PIN_NO(127) | 5) + +#define PINMUX_GPIO128__FUNC_GPIO128 (MTK_PIN_NO(128) | 0) +#define PINMUX_GPIO128__FUNC_SDA0 (MTK_PIN_NO(128) | 1) +#define PINMUX_GPIO128__FUNC_SCP_SDA0 (MTK_PIN_NO(128) | 4) +#define PINMUX_GPIO128__FUNC_SCP_SDA1 (MTK_PIN_NO(128) | 5) + +#define PINMUX_GPIO129__FUNC_GPIO129 (MTK_PIN_NO(129) | 0) +#define PINMUX_GPIO129__FUNC_SCL1 (MTK_PIN_NO(129) | 1) +#define PINMUX_GPIO129__FUNC_SCP_SCL0 (MTK_PIN_NO(129) | 4) +#define PINMUX_GPIO129__FUNC_SCP_SCL1 (MTK_PIN_NO(129) | 5) +#define PINMUX_GPIO129__FUNC_DBG_MON_B4 (MTK_PIN_NO(129) | 7) + +#define PINMUX_GPIO130__FUNC_GPIO130 (MTK_PIN_NO(130) | 0) +#define PINMUX_GPIO130__FUNC_SDA1 (MTK_PIN_NO(130) | 1) +#define PINMUX_GPIO130__FUNC_SCP_SDA0 (MTK_PIN_NO(130) | 4) +#define PINMUX_GPIO130__FUNC_SCP_SDA1 (MTK_PIN_NO(130) | 5) +#define PINMUX_GPIO130__FUNC_DBG_MON_B5 (MTK_PIN_NO(130) | 7) + +#define PINMUX_GPIO131__FUNC_GPIO131 (MTK_PIN_NO(131) | 0) +#define PINMUX_GPIO131__FUNC_SCL2 (MTK_PIN_NO(131) | 1) +#define PINMUX_GPIO131__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(131) | 2) +#define PINMUX_GPIO131__FUNC_CONN_UART0_TXD (MTK_PIN_NO(131) | 3) +#define PINMUX_GPIO131__FUNC_SCP_SCL0 (MTK_PIN_NO(131) | 4) +#define PINMUX_GPIO131__FUNC_SCP_SCL1 (MTK_PIN_NO(131) | 5) +#define PINMUX_GPIO131__FUNC_DBG_MON_B6 (MTK_PIN_NO(131) | 7) + +#define PINMUX_GPIO132__FUNC_GPIO132 (MTK_PIN_NO(132) | 0) +#define PINMUX_GPIO132__FUNC_SDA2 (MTK_PIN_NO(132) | 1) +#define PINMUX_GPIO132__FUNC_SSPM_URXD_AO (MTK_PIN_NO(132) | 2) +#define PINMUX_GPIO132__FUNC_CONN_UART0_RXD (MTK_PIN_NO(132) | 3) +#define PINMUX_GPIO132__FUNC_SCP_SDA0 (MTK_PIN_NO(132) | 4) +#define PINMUX_GPIO132__FUNC_SCP_SDA1 (MTK_PIN_NO(132) | 5) +#define PINMUX_GPIO132__FUNC_DBG_MON_B7 (MTK_PIN_NO(132) | 7) + +#define PINMUX_GPIO133__FUNC_GPIO133 (MTK_PIN_NO(133) | 0) +#define PINMUX_GPIO133__FUNC_SCL3 (MTK_PIN_NO(133) | 1) +#define PINMUX_GPIO133__FUNC_SCP_SCL0 (MTK_PIN_NO(133) | 4) +#define PINMUX_GPIO133__FUNC_SCP_SCL1 (MTK_PIN_NO(133) | 5) +#define PINMUX_GPIO133__FUNC_DBG_MON_B8 (MTK_PIN_NO(133) | 7) + +#define PINMUX_GPIO134__FUNC_GPIO134 (MTK_PIN_NO(134) | 0) +#define PINMUX_GPIO134__FUNC_SDA3 (MTK_PIN_NO(134) | 1) +#define PINMUX_GPIO134__FUNC_GPS_PPS (MTK_PIN_NO(134) | 3) +#define PINMUX_GPIO134__FUNC_SCP_SDA0 (MTK_PIN_NO(134) | 4) +#define PINMUX_GPIO134__FUNC_SCP_SDA1 (MTK_PIN_NO(134) | 5) +#define PINMUX_GPIO134__FUNC_DBG_MON_B9 (MTK_PIN_NO(134) | 7) + +#define PINMUX_GPIO135__FUNC_GPIO135 (MTK_PIN_NO(135) | 0) +#define PINMUX_GPIO135__FUNC_SCL4 (MTK_PIN_NO(135) | 1) +#define PINMUX_GPIO135__FUNC_TP_UTXD1_AO (MTK_PIN_NO(135) | 2) +#define PINMUX_GPIO135__FUNC_UTXD1 (MTK_PIN_NO(135) | 3) +#define PINMUX_GPIO135__FUNC_SCP_SCL0 (MTK_PIN_NO(135) | 4) +#define PINMUX_GPIO135__FUNC_SCP_SCL1 (MTK_PIN_NO(135) | 5) +#define PINMUX_GPIO135__FUNC_DBG_MON_B10 (MTK_PIN_NO(135) | 7) + +#define PINMUX_GPIO136__FUNC_GPIO136 (MTK_PIN_NO(136) | 0) +#define PINMUX_GPIO136__FUNC_SDA4 (MTK_PIN_NO(136) | 1) +#define PINMUX_GPIO136__FUNC_TP_URXD1_AO (MTK_PIN_NO(136) | 2) +#define PINMUX_GPIO136__FUNC_URXD1 (MTK_PIN_NO(136) | 3) +#define PINMUX_GPIO136__FUNC_SCP_SDA0 (MTK_PIN_NO(136) | 4) +#define PINMUX_GPIO136__FUNC_SCP_SDA1 (MTK_PIN_NO(136) | 5) +#define PINMUX_GPIO136__FUNC_DBG_MON_B11 (MTK_PIN_NO(136) | 7) + +#define PINMUX_GPIO137__FUNC_GPIO137 (MTK_PIN_NO(137) | 0) +#define PINMUX_GPIO137__FUNC_SCL5 (MTK_PIN_NO(137) | 1) +#define PINMUX_GPIO137__FUNC_UTXD2 (MTK_PIN_NO(137) | 2) +#define PINMUX_GPIO137__FUNC_UCTS1 (MTK_PIN_NO(137) | 3) +#define PINMUX_GPIO137__FUNC_SCP_SCL0 (MTK_PIN_NO(137) | 4) +#define PINMUX_GPIO137__FUNC_SCP_SCL1 (MTK_PIN_NO(137) | 5) + +#define PINMUX_GPIO138__FUNC_GPIO138 (MTK_PIN_NO(138) | 0) +#define PINMUX_GPIO138__FUNC_SDA5 (MTK_PIN_NO(138) | 1) +#define PINMUX_GPIO138__FUNC_URXD2 (MTK_PIN_NO(138) | 2) +#define PINMUX_GPIO138__FUNC_URTS1 (MTK_PIN_NO(138) | 3) +#define PINMUX_GPIO138__FUNC_SCP_SDA0 (MTK_PIN_NO(138) | 4) +#define PINMUX_GPIO138__FUNC_SCP_SDA1 (MTK_PIN_NO(138) | 5) + +#define PINMUX_GPIO139__FUNC_GPIO139 (MTK_PIN_NO(139) | 0) +#define PINMUX_GPIO139__FUNC_SCL6 (MTK_PIN_NO(139) | 1) +#define PINMUX_GPIO139__FUNC_UTXD1 (MTK_PIN_NO(139) | 2) +#define PINMUX_GPIO139__FUNC_TP_UTXD1_AO (MTK_PIN_NO(139) | 3) +#define PINMUX_GPIO139__FUNC_SCP_SCL0 (MTK_PIN_NO(139) | 4) +#define PINMUX_GPIO139__FUNC_SCP_SCL1 (MTK_PIN_NO(139) | 5) +#define PINMUX_GPIO139__FUNC_DBG_MON_B12 (MTK_PIN_NO(139) | 7) + +#define PINMUX_GPIO140__FUNC_GPIO140 (MTK_PIN_NO(140) | 0) +#define PINMUX_GPIO140__FUNC_SDA6 (MTK_PIN_NO(140) | 1) +#define PINMUX_GPIO140__FUNC_URXD1 (MTK_PIN_NO(140) | 2) +#define PINMUX_GPIO140__FUNC_TP_URXD1_AO (MTK_PIN_NO(140) | 3) +#define PINMUX_GPIO140__FUNC_SCP_SDA0 (MTK_PIN_NO(140) | 4) +#define PINMUX_GPIO140__FUNC_SCP_SDA1 (MTK_PIN_NO(140) | 5) +#define PINMUX_GPIO140__FUNC_DBG_MON_B13 (MTK_PIN_NO(140) | 7) + +#define PINMUX_GPIO141__FUNC_GPIO141 (MTK_PIN_NO(141) | 0) +#define PINMUX_GPIO141__FUNC_SCL7 (MTK_PIN_NO(141) | 1) +#define PINMUX_GPIO141__FUNC_URTS0 (MTK_PIN_NO(141) | 2) +#define PINMUX_GPIO141__FUNC_TP_URTS1_AO (MTK_PIN_NO(141) | 3) +#define PINMUX_GPIO141__FUNC_SCP_SCL0 (MTK_PIN_NO(141) | 4) +#define PINMUX_GPIO141__FUNC_SCP_SCL1 (MTK_PIN_NO(141) | 5) +#define PINMUX_GPIO141__FUNC_UDI_TCK (MTK_PIN_NO(141) | 6) +#define PINMUX_GPIO141__FUNC_DBG_MON_B14 (MTK_PIN_NO(141) | 7) + +#define PINMUX_GPIO142__FUNC_GPIO142 (MTK_PIN_NO(142) | 0) +#define PINMUX_GPIO142__FUNC_SDA7 (MTK_PIN_NO(142) | 1) +#define PINMUX_GPIO142__FUNC_UCTS0 (MTK_PIN_NO(142) | 2) +#define PINMUX_GPIO142__FUNC_TP_UCTS1_AO (MTK_PIN_NO(142) | 3) +#define PINMUX_GPIO142__FUNC_SCP_SDA0 (MTK_PIN_NO(142) | 4) +#define PINMUX_GPIO142__FUNC_SCP_SDA1 (MTK_PIN_NO(142) | 5) + +#define PINMUX_GPIO143__FUNC_GPIO143 (MTK_PIN_NO(143) | 0) +#define PINMUX_GPIO143__FUNC_SCL8 (MTK_PIN_NO(143) | 1) +#define PINMUX_GPIO143__FUNC_SCP_SCL0 (MTK_PIN_NO(143) | 4) +#define PINMUX_GPIO143__FUNC_SCP_SCL1 (MTK_PIN_NO(143) | 5) +#define PINMUX_GPIO143__FUNC_DBG_MON_B16 (MTK_PIN_NO(143) | 7) + +#define PINMUX_GPIO144__FUNC_GPIO144 (MTK_PIN_NO(144) | 0) +#define PINMUX_GPIO144__FUNC_SDA8 (MTK_PIN_NO(144) | 1) +#define PINMUX_GPIO144__FUNC_SCP_SDA0 (MTK_PIN_NO(144) | 4) +#define PINMUX_GPIO144__FUNC_SCP_SDA1 (MTK_PIN_NO(144) | 5) +#define PINMUX_GPIO144__FUNC_DBG_MON_B17 (MTK_PIN_NO(144) | 7) + +#define PINMUX_GPIO145__FUNC_GPIO145 (MTK_PIN_NO(145) | 0) +#define PINMUX_GPIO145__FUNC_SCL9 (MTK_PIN_NO(145) | 1) +#define PINMUX_GPIO145__FUNC_CMVREF1 (MTK_PIN_NO(145) | 2) +#define PINMUX_GPIO145__FUNC_GPS_PPS (MTK_PIN_NO(145) | 3) +#define PINMUX_GPIO145__FUNC_SCP_SCL0 (MTK_PIN_NO(145) | 4) +#define PINMUX_GPIO145__FUNC_SCP_SCL1 (MTK_PIN_NO(145) | 5) +#define PINMUX_GPIO145__FUNC_DBG_MON_B18 (MTK_PIN_NO(145) | 7) + +#define PINMUX_GPIO146__FUNC_GPIO146 (MTK_PIN_NO(146) | 0) +#define PINMUX_GPIO146__FUNC_SDA9 (MTK_PIN_NO(146) | 1) +#define PINMUX_GPIO146__FUNC_CMVREF0 (MTK_PIN_NO(146) | 2) +#define PINMUX_GPIO146__FUNC_SCP_SDA0 (MTK_PIN_NO(146) | 4) +#define PINMUX_GPIO146__FUNC_SCP_SDA1 (MTK_PIN_NO(146) | 5) +#define PINMUX_GPIO146__FUNC_DBG_MON_B19 (MTK_PIN_NO(146) | 7) + +#define PINMUX_GPIO147__FUNC_GPIO147 (MTK_PIN_NO(147) | 0) +#define PINMUX_GPIO147__FUNC_CMFLASH0 (MTK_PIN_NO(147) | 1) +#define PINMUX_GPIO147__FUNC_LVTS_SDI (MTK_PIN_NO(147) | 2) +#define PINMUX_GPIO147__FUNC_DPI_DATA12 (MTK_PIN_NO(147) | 3) +#define PINMUX_GPIO147__FUNC_TP_GPIO0_AO (MTK_PIN_NO(147) | 4) +#define PINMUX_GPIO147__FUNC_ANT_SEL3 (MTK_PIN_NO(147) | 5) +#define PINMUX_GPIO147__FUNC_DFD_TCK_XI (MTK_PIN_NO(147) | 6) +#define PINMUX_GPIO147__FUNC_DBG_MON_B20 (MTK_PIN_NO(147) | 7) + +#define PINMUX_GPIO148__FUNC_GPIO148 (MTK_PIN_NO(148) | 0) +#define PINMUX_GPIO148__FUNC_CMFLASH1 (MTK_PIN_NO(148) | 1) +#define PINMUX_GPIO148__FUNC_LVTS_SCF (MTK_PIN_NO(148) | 2) +#define PINMUX_GPIO148__FUNC_DPI_DATA13 (MTK_PIN_NO(148) | 3) +#define PINMUX_GPIO148__FUNC_TP_GPIO1_AO (MTK_PIN_NO(148) | 4) +#define PINMUX_GPIO148__FUNC_ANT_SEL4 (MTK_PIN_NO(148) | 5) +#define PINMUX_GPIO148__FUNC_DFD_TMS (MTK_PIN_NO(148) | 6) +#define PINMUX_GPIO148__FUNC_DBG_MON_B21 (MTK_PIN_NO(148) | 7) + +#define PINMUX_GPIO149__FUNC_GPIO149 (MTK_PIN_NO(149) | 0) +#define PINMUX_GPIO149__FUNC_CMFLASH2 (MTK_PIN_NO(149) | 1) +#define PINMUX_GPIO149__FUNC_CLKM0 (MTK_PIN_NO(149) | 2) +#define PINMUX_GPIO149__FUNC_DPI_DATA14 (MTK_PIN_NO(149) | 3) +#define PINMUX_GPIO149__FUNC_TP_GPIO2_AO (MTK_PIN_NO(149) | 4) +#define PINMUX_GPIO149__FUNC_ANT_SEL5 (MTK_PIN_NO(149) | 5) +#define PINMUX_GPIO149__FUNC_DFD_TDI (MTK_PIN_NO(149) | 6) +#define PINMUX_GPIO149__FUNC_DBG_MON_B22 (MTK_PIN_NO(149) | 7) + +#define PINMUX_GPIO150__FUNC_GPIO150 (MTK_PIN_NO(150) | 0) +#define PINMUX_GPIO150__FUNC_CLKM1 (MTK_PIN_NO(150) | 2) +#define PINMUX_GPIO150__FUNC_DPI_DATA15 (MTK_PIN_NO(150) | 3) +#define PINMUX_GPIO150__FUNC_TP_GPIO3_AO (MTK_PIN_NO(150) | 4) +#define PINMUX_GPIO150__FUNC_ANT_SEL6 (MTK_PIN_NO(150) | 5) +#define PINMUX_GPIO150__FUNC_DFD_TDO (MTK_PIN_NO(150) | 6) +#define PINMUX_GPIO150__FUNC_DBG_MON_B23 (MTK_PIN_NO(150) | 7) + +#define PINMUX_GPIO151__FUNC_GPIO151 (MTK_PIN_NO(151) | 0) +#define PINMUX_GPIO151__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(151) | 1) +#define PINMUX_GPIO151__FUNC_CLKM2 (MTK_PIN_NO(151) | 2) +#define PINMUX_GPIO151__FUNC_DPI_DATA16 (MTK_PIN_NO(151) | 3) +#define PINMUX_GPIO151__FUNC_TP_GPIO4_AO (MTK_PIN_NO(151) | 4) +#define PINMUX_GPIO151__FUNC_ANT_SEL7 (MTK_PIN_NO(151) | 5) +#define PINMUX_GPIO151__FUNC_UDI_TMS (MTK_PIN_NO(151) | 6) +#define PINMUX_GPIO151__FUNC_DBG_MON_B24 (MTK_PIN_NO(151) | 7) + +#define PINMUX_GPIO152__FUNC_GPIO152 (MTK_PIN_NO(152) | 0) +#define PINMUX_GPIO152__FUNC_CLKM3 (MTK_PIN_NO(152) | 2) +#define PINMUX_GPIO152__FUNC_DPI_DATA17 (MTK_PIN_NO(152) | 3) +#define PINMUX_GPIO152__FUNC_TP_GPIO5_AO (MTK_PIN_NO(152) | 4) + +#define PINMUX_GPIO153__FUNC_GPIO153 (MTK_PIN_NO(153) | 0) +#define PINMUX_GPIO153__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(153) | 1) +#define PINMUX_GPIO153__FUNC_DPI_DATA18 (MTK_PIN_NO(153) | 3) +#define PINMUX_GPIO153__FUNC_TP_GPIO6_AO (MTK_PIN_NO(153) | 4) +#define PINMUX_GPIO153__FUNC_UDI_TDI (MTK_PIN_NO(153) | 6) +#define PINMUX_GPIO153__FUNC_DBG_MON_B26 (MTK_PIN_NO(153) | 7) + +#define PINMUX_GPIO154__FUNC_GPIO154 (MTK_PIN_NO(154) | 0) +#define PINMUX_GPIO154__FUNC_PWM0 (MTK_PIN_NO(154) | 1) +#define PINMUX_GPIO154__FUNC_CMVREF2 (MTK_PIN_NO(154) | 2) +#define PINMUX_GPIO154__FUNC_DPI_DATA19 (MTK_PIN_NO(154) | 3) +#define PINMUX_GPIO154__FUNC_TP_GPIO7_AO (MTK_PIN_NO(154) | 4) +#define PINMUX_GPIO154__FUNC_UDI_TDO (MTK_PIN_NO(154) | 6) +#define PINMUX_GPIO154__FUNC_DBG_MON_B27 (MTK_PIN_NO(154) | 7) + +#define PINMUX_GPIO155__FUNC_GPIO155 (MTK_PIN_NO(155) | 0) +#define PINMUX_GPIO155__FUNC_PWM1 (MTK_PIN_NO(155) | 1) +#define PINMUX_GPIO155__FUNC_CMVREF1 (MTK_PIN_NO(155) | 2) +#define PINMUX_GPIO155__FUNC_DPI_DATA20 (MTK_PIN_NO(155) | 3) +#define PINMUX_GPIO155__FUNC_UDI_NTRST (MTK_PIN_NO(155) | 6) +#define PINMUX_GPIO155__FUNC_DBG_MON_B28 (MTK_PIN_NO(155) | 7) + +#define PINMUX_GPIO156__FUNC_GPIO156 (MTK_PIN_NO(156) | 0) +#define PINMUX_GPIO156__FUNC_PWM2 (MTK_PIN_NO(156) | 1) +#define PINMUX_GPIO156__FUNC_CMVREF0 (MTK_PIN_NO(156) | 2) +#define PINMUX_GPIO156__FUNC_DPI_DATA21 (MTK_PIN_NO(156) | 3) + +#define PINMUX_GPIO157__FUNC_GPIO157 (MTK_PIN_NO(157) | 0) +#define PINMUX_GPIO157__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(157) | 1) + +#define PINMUX_GPIO158__FUNC_GPIO158 (MTK_PIN_NO(158) | 0) +#define PINMUX_GPIO158__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(158) | 1) + +#define PINMUX_GPIO159__FUNC_GPIO159 (MTK_PIN_NO(159) | 0) +#define PINMUX_GPIO159__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(159) | 1) +#define PINMUX_GPIO159__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(159) | 2) + +#define PINMUX_GPIO160__FUNC_GPIO160 (MTK_PIN_NO(160) | 0) +#define PINMUX_GPIO160__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(160) | 1) +#define PINMUX_GPIO160__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(160) | 2) + +#define PINMUX_GPIO161__FUNC_GPIO161 (MTK_PIN_NO(161) | 0) +#define PINMUX_GPIO161__FUNC_SRCLKENA0 (MTK_PIN_NO(161) | 1) + +#define PINMUX_GPIO162__FUNC_GPIO162 (MTK_PIN_NO(162) | 0) +#define PINMUX_GPIO162__FUNC_SRCLKENA1 (MTK_PIN_NO(162) | 1) +#define PINMUX_GPIO162__FUNC_DBG_MON_A31 (MTK_PIN_NO(162) | 7) + +#define PINMUX_GPIO163__FUNC_GPIO163 (MTK_PIN_NO(163) | 0) +#define PINMUX_GPIO163__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(163) | 1) +#define PINMUX_GPIO163__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(163) | 2) + +#define PINMUX_GPIO164__FUNC_GPIO164 (MTK_PIN_NO(164) | 0) +#define PINMUX_GPIO164__FUNC_RTC32K_CK (MTK_PIN_NO(164) | 1) + +#define PINMUX_GPIO165__FUNC_GPIO165 (MTK_PIN_NO(165) | 0) +#define PINMUX_GPIO165__FUNC_WATCHDOG (MTK_PIN_NO(165) | 1) + +#define PINMUX_GPIO166__FUNC_GPIO166 (MTK_PIN_NO(166) | 0) +#define PINMUX_GPIO166__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(166) | 1) +#define PINMUX_GPIO166__FUNC_AUD_CLK_MISO (MTK_PIN_NO(166) | 2) +#define PINMUX_GPIO166__FUNC_I2S1_MCK (MTK_PIN_NO(166) | 3) + +#define PINMUX_GPIO167__FUNC_GPIO167 (MTK_PIN_NO(167) | 0) +#define PINMUX_GPIO167__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(167) | 1) +#define PINMUX_GPIO167__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(167) | 2) +#define PINMUX_GPIO167__FUNC_I2S1_BCK (MTK_PIN_NO(167) | 3) + +#define PINMUX_GPIO168__FUNC_GPIO168 (MTK_PIN_NO(168) | 0) +#define PINMUX_GPIO168__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(168) | 1) +#define PINMUX_GPIO168__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(168) | 2) +#define PINMUX_GPIO168__FUNC_I2S1_LRCK (MTK_PIN_NO(168) | 3) + +#define PINMUX_GPIO169__FUNC_GPIO169 (MTK_PIN_NO(169) | 0) +#define PINMUX_GPIO169__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(169) | 1) +#define PINMUX_GPIO169__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(169) | 2) +#define PINMUX_GPIO169__FUNC_I2S1_DO (MTK_PIN_NO(169) | 3) + +#define PINMUX_GPIO170__FUNC_GPIO170 (MTK_PIN_NO(170) | 0) +#define PINMUX_GPIO170__FUNC_AUD_CLK_MISO (MTK_PIN_NO(170) | 1) +#define PINMUX_GPIO170__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(170) | 2) +#define PINMUX_GPIO170__FUNC_I2S2_MCK (MTK_PIN_NO(170) | 3) + +#define PINMUX_GPIO171__FUNC_GPIO171 (MTK_PIN_NO(171) | 0) +#define PINMUX_GPIO171__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(171) | 1) +#define PINMUX_GPIO171__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(171) | 2) +#define PINMUX_GPIO171__FUNC_I2S2_BCK (MTK_PIN_NO(171) | 3) + +#define PINMUX_GPIO172__FUNC_GPIO172 (MTK_PIN_NO(172) | 0) +#define PINMUX_GPIO172__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(172) | 1) +#define PINMUX_GPIO172__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(172) | 2) +#define PINMUX_GPIO172__FUNC_I2S2_LRCK (MTK_PIN_NO(172) | 3) +#define PINMUX_GPIO172__FUNC_VOW_DAT_MISO (MTK_PIN_NO(172) | 4) + +#define PINMUX_GPIO173__FUNC_GPIO173 (MTK_PIN_NO(173) | 0) +#define PINMUX_GPIO173__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(173) | 1) +#define PINMUX_GPIO173__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(173) | 2) +#define PINMUX_GPIO173__FUNC_I2S2_DI (MTK_PIN_NO(173) | 3) +#define PINMUX_GPIO173__FUNC_VOW_CLK_MISO (MTK_PIN_NO(173) | 4) + +#define PINMUX_GPIO174__FUNC_GPIO174 (MTK_PIN_NO(174) | 0) +#define PINMUX_GPIO174__FUNC_CONN_TOP_CLK (MTK_PIN_NO(174) | 1) +#define PINMUX_GPIO174__FUNC_AUXIF_CLK (MTK_PIN_NO(174) | 2) +#define PINMUX_GPIO174__FUNC_DFD_TCK_XI (MTK_PIN_NO(174) | 3) +#define PINMUX_GPIO174__FUNC_DBG_MON_B3 (MTK_PIN_NO(174) | 7) + +#define PINMUX_GPIO175__FUNC_GPIO175 (MTK_PIN_NO(175) | 0) +#define PINMUX_GPIO175__FUNC_CONN_TOP_DATA (MTK_PIN_NO(175) | 1) +#define PINMUX_GPIO175__FUNC_AUXIF_ST (MTK_PIN_NO(175) | 2) +#define PINMUX_GPIO175__FUNC_DFD_TMS (MTK_PIN_NO(175) | 3) +#define PINMUX_GPIO175__FUNC_DBG_MON_B15 (MTK_PIN_NO(175) | 7) + +#define PINMUX_GPIO176__FUNC_GPIO176 (MTK_PIN_NO(176) | 0) +#define PINMUX_GPIO176__FUNC_CONN_BT_CLK (MTK_PIN_NO(176) | 1) +#define PINMUX_GPIO176__FUNC_DFD_TDI (MTK_PIN_NO(176) | 3) +#define PINMUX_GPIO176__FUNC_DBG_MON_B2 (MTK_PIN_NO(176) | 7) + +#define PINMUX_GPIO177__FUNC_GPIO177 (MTK_PIN_NO(177) | 0) +#define PINMUX_GPIO177__FUNC_CONN_BT_DATA (MTK_PIN_NO(177) | 1) +#define PINMUX_GPIO177__FUNC_DFD_TDO (MTK_PIN_NO(177) | 3) + +#define PINMUX_GPIO178__FUNC_GPIO178 (MTK_PIN_NO(178) | 0) +#define PINMUX_GPIO178__FUNC_CONN_HRST_B (MTK_PIN_NO(178) | 1) +#define PINMUX_GPIO178__FUNC_UDI_TMS (MTK_PIN_NO(178) | 3) +#define PINMUX_GPIO178__FUNC_DBG_MON_B25 (MTK_PIN_NO(178) | 7) + +#define PINMUX_GPIO179__FUNC_GPIO179 (MTK_PIN_NO(179) | 0) +#define PINMUX_GPIO179__FUNC_CONN_WB_PTA (MTK_PIN_NO(179) | 1) +#define PINMUX_GPIO179__FUNC_UDI_TCK (MTK_PIN_NO(179) | 3) +#define PINMUX_GPIO179__FUNC_DBG_MON_B29 (MTK_PIN_NO(179) | 7) + +#define PINMUX_GPIO180__FUNC_GPIO180 (MTK_PIN_NO(180) | 0) +#define PINMUX_GPIO180__FUNC_CONN_WF_CTRL0 (MTK_PIN_NO(180) | 1) +#define PINMUX_GPIO180__FUNC_UDI_TDI (MTK_PIN_NO(180) | 3) + +#define PINMUX_GPIO181__FUNC_GPIO181 (MTK_PIN_NO(181) | 0) +#define PINMUX_GPIO181__FUNC_CONN_WF_CTRL1 (MTK_PIN_NO(181) | 1) +#define PINMUX_GPIO181__FUNC_UDI_TDO (MTK_PIN_NO(181) | 3) + +#define PINMUX_GPIO182__FUNC_GPIO182 (MTK_PIN_NO(182) | 0) +#define PINMUX_GPIO182__FUNC_CONN_WF_CTRL2 (MTK_PIN_NO(182) | 1) +#define PINMUX_GPIO182__FUNC_UDI_NTRST (MTK_PIN_NO(182) | 3) + +#define PINMUX_GPIO183__FUNC_GPIO183 (MTK_PIN_NO(183) | 0) +#define PINMUX_GPIO183__FUNC_SPMI_SCL (MTK_PIN_NO(183) | 1) + +#define PINMUX_GPIO184__FUNC_GPIO184 (MTK_PIN_NO(184) | 0) +#define PINMUX_GPIO184__FUNC_SPMI_SDA (MTK_PIN_NO(184) | 1) + +#endif /* __MT8186_PINFUNC_H */ diff --git a/include/dt-bindings/pinctrl/mt8192-pinfunc.h b/include/dt-bindings/pinctrl/mt8192-pinfunc.h new file mode 100644 index 000000000000..71ffe3a52578 --- /dev/null +++ b/include/dt-bindings/pinctrl/mt8192-pinfunc.h @@ -0,0 +1,1344 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 MediaTek Inc. + * Author: Zhiyong Tao <zhiyong.tao@mediatek.com> + * + */ + +#ifndef __MT8192_PINFUNC_H +#define __MT8192_PINFUNC_H + +#include "mt65xx.h" + +#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define PINMUX_GPIO0__FUNC_SPI6_CLK (MTK_PIN_NO(0) | 1) +#define PINMUX_GPIO0__FUNC_I2S5_MCK (MTK_PIN_NO(0) | 2) +#define PINMUX_GPIO0__FUNC_PWM_0 (MTK_PIN_NO(0) | 3) +#define PINMUX_GPIO0__FUNC_TDM_LRCK (MTK_PIN_NO(0) | 4) +#define PINMUX_GPIO0__FUNC_TP_GPIO0_AO (MTK_PIN_NO(0) | 5) +#define PINMUX_GPIO0__FUNC_MD_INT0 (MTK_PIN_NO(0) | 6) + +#define PINMUX_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define PINMUX_GPIO1__FUNC_SPI6_CSB (MTK_PIN_NO(1) | 1) +#define PINMUX_GPIO1__FUNC_I2S5_BCK (MTK_PIN_NO(1) | 2) +#define PINMUX_GPIO1__FUNC_PWM_1 (MTK_PIN_NO(1) | 3) +#define PINMUX_GPIO1__FUNC_TDM_BCK (MTK_PIN_NO(1) | 4) +#define PINMUX_GPIO1__FUNC_TP_GPIO1_AO (MTK_PIN_NO(1) | 5) +#define PINMUX_GPIO1__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(1) | 6) +#define PINMUX_GPIO1__FUNC_DBG_MON_A9 (MTK_PIN_NO(1) | 7) + +#define PINMUX_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define PINMUX_GPIO2__FUNC_SPI6_MI (MTK_PIN_NO(2) | 1) +#define PINMUX_GPIO2__FUNC_I2S5_LRCK (MTK_PIN_NO(2) | 2) +#define PINMUX_GPIO2__FUNC_PWM_2 (MTK_PIN_NO(2) | 3) +#define PINMUX_GPIO2__FUNC_TDM_MCK (MTK_PIN_NO(2) | 4) +#define PINMUX_GPIO2__FUNC_TP_GPIO2_AO (MTK_PIN_NO(2) | 5) +#define PINMUX_GPIO2__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(2) | 6) +#define PINMUX_GPIO2__FUNC_DBG_MON_A10 (MTK_PIN_NO(2) | 7) + +#define PINMUX_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define PINMUX_GPIO3__FUNC_SPI6_MO (MTK_PIN_NO(3) | 1) +#define PINMUX_GPIO3__FUNC_I2S5_DO (MTK_PIN_NO(3) | 2) +#define PINMUX_GPIO3__FUNC_PWM_3 (MTK_PIN_NO(3) | 3) +#define PINMUX_GPIO3__FUNC_TDM_DATA0 (MTK_PIN_NO(3) | 4) +#define PINMUX_GPIO3__FUNC_TP_GPIO3_AO (MTK_PIN_NO(3) | 5) +#define PINMUX_GPIO3__FUNC_CLKM0 (MTK_PIN_NO(3) | 6) +#define PINMUX_GPIO3__FUNC_DBG_MON_A11 (MTK_PIN_NO(3) | 7) + +#define PINMUX_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define PINMUX_GPIO4__FUNC_SPI4_A_CLK (MTK_PIN_NO(4) | 1) +#define PINMUX_GPIO4__FUNC_I2S2_MCK (MTK_PIN_NO(4) | 2) +#define PINMUX_GPIO4__FUNC_DMIC1_CLK (MTK_PIN_NO(4) | 3) +#define PINMUX_GPIO4__FUNC_TDM_DATA1 (MTK_PIN_NO(4) | 4) +#define PINMUX_GPIO4__FUNC_TP_GPIO4_AO (MTK_PIN_NO(4) | 5) +#define PINMUX_GPIO4__FUNC_PCM1_DI (MTK_PIN_NO(4) | 6) +#define PINMUX_GPIO4__FUNC_IDDIG (MTK_PIN_NO(4) | 7) + +#define PINMUX_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define PINMUX_GPIO5__FUNC_SPI4_A_CSB (MTK_PIN_NO(5) | 1) +#define PINMUX_GPIO5__FUNC_I2S2_BCK (MTK_PIN_NO(5) | 2) +#define PINMUX_GPIO5__FUNC_DMIC1_DAT (MTK_PIN_NO(5) | 3) +#define PINMUX_GPIO5__FUNC_TDM_DATA2 (MTK_PIN_NO(5) | 4) +#define PINMUX_GPIO5__FUNC_TP_GPIO5_AO (MTK_PIN_NO(5) | 5) +#define PINMUX_GPIO5__FUNC_PCM1_CLK (MTK_PIN_NO(5) | 6) +#define PINMUX_GPIO5__FUNC_USB_DRVVBUS (MTK_PIN_NO(5) | 7) + +#define PINMUX_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define PINMUX_GPIO6__FUNC_SPI4_A_MI (MTK_PIN_NO(6) | 1) +#define PINMUX_GPIO6__FUNC_I2S2_LRCK (MTK_PIN_NO(6) | 2) +#define PINMUX_GPIO6__FUNC_DMIC_CLK (MTK_PIN_NO(6) | 3) +#define PINMUX_GPIO6__FUNC_TDM_DATA3 (MTK_PIN_NO(6) | 4) +#define PINMUX_GPIO6__FUNC_TP_GPIO6_AO (MTK_PIN_NO(6) | 5) +#define PINMUX_GPIO6__FUNC_PCM1_SYNC (MTK_PIN_NO(6) | 6) + +#define PINMUX_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +#define PINMUX_GPIO7__FUNC_SPI4_A_MO (MTK_PIN_NO(7) | 1) +#define PINMUX_GPIO7__FUNC_I2S2_DI (MTK_PIN_NO(7) | 2) +#define PINMUX_GPIO7__FUNC_DMIC_DAT (MTK_PIN_NO(7) | 3) +#define PINMUX_GPIO7__FUNC_WIFI_TXD (MTK_PIN_NO(7) | 4) +#define PINMUX_GPIO7__FUNC_TP_GPIO7_AO (MTK_PIN_NO(7) | 5) +#define PINMUX_GPIO7__FUNC_PCM1_DO0 (MTK_PIN_NO(7) | 6) + +#define PINMUX_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +#define PINMUX_GPIO8__FUNC_SRCLKENAI1 (MTK_PIN_NO(8) | 1) +#define PINMUX_GPIO8__FUNC_I2S2_DI2 (MTK_PIN_NO(8) | 2) +#define PINMUX_GPIO8__FUNC_KPCOL2 (MTK_PIN_NO(8) | 3) +#define PINMUX_GPIO8__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(8) | 4) +#define PINMUX_GPIO8__FUNC_CLKM1 (MTK_PIN_NO(8) | 5) +#define PINMUX_GPIO8__FUNC_PCM1_DO1 (MTK_PIN_NO(8) | 6) +#define PINMUX_GPIO8__FUNC_DBG_MON_A12 (MTK_PIN_NO(8) | 7) + +#define PINMUX_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +#define PINMUX_GPIO9__FUNC_SRCLKENAI0 (MTK_PIN_NO(9) | 1) +#define PINMUX_GPIO9__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(9) | 2) +#define PINMUX_GPIO9__FUNC_KPROW2 (MTK_PIN_NO(9) | 3) +#define PINMUX_GPIO9__FUNC_CMMCLK4 (MTK_PIN_NO(9) | 4) +#define PINMUX_GPIO9__FUNC_CLKM3 (MTK_PIN_NO(9) | 5) +#define PINMUX_GPIO9__FUNC_PCM1_DO2 (MTK_PIN_NO(9) | 6) +#define PINMUX_GPIO9__FUNC_DBG_MON_A13 (MTK_PIN_NO(9) | 7) + +#define PINMUX_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +#define PINMUX_GPIO10__FUNC_MSDC2_CLK (MTK_PIN_NO(10) | 1) +#define PINMUX_GPIO10__FUNC_SPI4_B_CLK (MTK_PIN_NO(10) | 2) +#define PINMUX_GPIO10__FUNC_I2S8_MCK (MTK_PIN_NO(10) | 3) +#define PINMUX_GPIO10__FUNC_MD_INT0 (MTK_PIN_NO(10) | 5) +#define PINMUX_GPIO10__FUNC_TP_GPIO8_AO (MTK_PIN_NO(10) | 6) + +#define PINMUX_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +#define PINMUX_GPIO11__FUNC_MSDC2_CMD (MTK_PIN_NO(11) | 1) +#define PINMUX_GPIO11__FUNC_SPI4_B_CSB (MTK_PIN_NO(11) | 2) +#define PINMUX_GPIO11__FUNC_I2S8_BCK (MTK_PIN_NO(11) | 3) +#define PINMUX_GPIO11__FUNC_PCIE_CLKREQ_N (MTK_PIN_NO(11) | 4) +#define PINMUX_GPIO11__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(11) | 5) +#define PINMUX_GPIO11__FUNC_TP_GPIO9_AO (MTK_PIN_NO(11) | 6) + +#define PINMUX_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +#define PINMUX_GPIO12__FUNC_MSDC2_DAT3 (MTK_PIN_NO(12) | 1) +#define PINMUX_GPIO12__FUNC_SPI4_B_MI (MTK_PIN_NO(12) | 2) +#define PINMUX_GPIO12__FUNC_I2S8_LRCK (MTK_PIN_NO(12) | 3) +#define PINMUX_GPIO12__FUNC_DMIC1_CLK (MTK_PIN_NO(12) | 4) +#define PINMUX_GPIO12__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(12) | 5) +#define PINMUX_GPIO12__FUNC_TP_GPIO10_AO (MTK_PIN_NO(12) | 6) + +#define PINMUX_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) +#define PINMUX_GPIO13__FUNC_MSDC2_DAT0 (MTK_PIN_NO(13) | 1) +#define PINMUX_GPIO13__FUNC_SPI4_B_MO (MTK_PIN_NO(13) | 2) +#define PINMUX_GPIO13__FUNC_I2S8_DI (MTK_PIN_NO(13) | 3) +#define PINMUX_GPIO13__FUNC_DMIC1_DAT (MTK_PIN_NO(13) | 4) +#define PINMUX_GPIO13__FUNC_ANT_SEL10 (MTK_PIN_NO(13) | 5) +#define PINMUX_GPIO13__FUNC_TP_GPIO11_AO (MTK_PIN_NO(13) | 6) + +#define PINMUX_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) +#define PINMUX_GPIO14__FUNC_MSDC2_DAT2 (MTK_PIN_NO(14) | 1) +#define PINMUX_GPIO14__FUNC_IDDIG (MTK_PIN_NO(14) | 2) +#define PINMUX_GPIO14__FUNC_SCL_6306 (MTK_PIN_NO(14) | 3) +#define PINMUX_GPIO14__FUNC_PCIE_PERESET_N (MTK_PIN_NO(14) | 4) +#define PINMUX_GPIO14__FUNC_ANT_SEL11 (MTK_PIN_NO(14) | 5) +#define PINMUX_GPIO14__FUNC_TP_GPIO12_AO (MTK_PIN_NO(14) | 6) + +#define PINMUX_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) +#define PINMUX_GPIO15__FUNC_MSDC2_DAT1 (MTK_PIN_NO(15) | 1) +#define PINMUX_GPIO15__FUNC_USB_DRVVBUS (MTK_PIN_NO(15) | 2) +#define PINMUX_GPIO15__FUNC_SDA_6306 (MTK_PIN_NO(15) | 3) +#define PINMUX_GPIO15__FUNC_PCIE_WAKE_N (MTK_PIN_NO(15) | 4) +#define PINMUX_GPIO15__FUNC_ANT_SEL12 (MTK_PIN_NO(15) | 5) +#define PINMUX_GPIO15__FUNC_TP_GPIO13_AO (MTK_PIN_NO(15) | 6) + +#define PINMUX_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) +#define PINMUX_GPIO16__FUNC_SRCLKENAI1 (MTK_PIN_NO(16) | 1) +#define PINMUX_GPIO16__FUNC_IDDIG (MTK_PIN_NO(16) | 2) +#define PINMUX_GPIO16__FUNC_TP_GPIO14_AO (MTK_PIN_NO(16) | 3) +#define PINMUX_GPIO16__FUNC_KPCOL2 (MTK_PIN_NO(16) | 4) +#define PINMUX_GPIO16__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(16) | 5) +#define PINMUX_GPIO16__FUNC_SPI7_A_MI (MTK_PIN_NO(16) | 6) +#define PINMUX_GPIO16__FUNC_DBG_MON_A0 (MTK_PIN_NO(16) | 7) + +#define PINMUX_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) +#define PINMUX_GPIO17__FUNC_SRCLKENAI0 (MTK_PIN_NO(17) | 1) +#define PINMUX_GPIO17__FUNC_USB_DRVVBUS (MTK_PIN_NO(17) | 2) +#define PINMUX_GPIO17__FUNC_TP_GPIO15_AO (MTK_PIN_NO(17) | 3) +#define PINMUX_GPIO17__FUNC_KPROW2 (MTK_PIN_NO(17) | 4) +#define PINMUX_GPIO17__FUNC_SPI7_A_MO (MTK_PIN_NO(17) | 6) +#define PINMUX_GPIO17__FUNC_DBG_MON_A1 (MTK_PIN_NO(17) | 7) + +#define PINMUX_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) +#define PINMUX_GPIO18__FUNC_SRCLKENAI0 (MTK_PIN_NO(18) | 1) +#define PINMUX_GPIO18__FUNC_SPI4_C_MI (MTK_PIN_NO(18) | 2) +#define PINMUX_GPIO18__FUNC_SPI1_B_MI (MTK_PIN_NO(18) | 3) +#define PINMUX_GPIO18__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(18) | 4) +#define PINMUX_GPIO18__FUNC_ANT_SEL10 (MTK_PIN_NO(18) | 5) +#define PINMUX_GPIO18__FUNC_MD_INT0 (MTK_PIN_NO(18) | 6) +#define PINMUX_GPIO18__FUNC_DBG_MON_B2 (MTK_PIN_NO(18) | 7) + +#define PINMUX_GPIO19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) +#define PINMUX_GPIO19__FUNC_SRCLKENAI1 (MTK_PIN_NO(19) | 1) +#define PINMUX_GPIO19__FUNC_SPI4_C_MO (MTK_PIN_NO(19) | 2) +#define PINMUX_GPIO19__FUNC_SPI1_B_MO (MTK_PIN_NO(19) | 3) +#define PINMUX_GPIO19__FUNC_ANT_SEL11 (MTK_PIN_NO(19) | 5) +#define PINMUX_GPIO19__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(19) | 6) +#define PINMUX_GPIO19__FUNC_DBG_MON_B3 (MTK_PIN_NO(19) | 7) + +#define PINMUX_GPIO20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) +#define PINMUX_GPIO20__FUNC_SRCLKENAI0 (MTK_PIN_NO(20) | 1) +#define PINMUX_GPIO20__FUNC_SPI4_C_CLK (MTK_PIN_NO(20) | 2) +#define PINMUX_GPIO20__FUNC_SPI1_B_CLK (MTK_PIN_NO(20) | 3) +#define PINMUX_GPIO20__FUNC_PWM_3 (MTK_PIN_NO(20) | 4) +#define PINMUX_GPIO20__FUNC_ANT_SEL12 (MTK_PIN_NO(20) | 5) +#define PINMUX_GPIO20__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(20) | 6) +#define PINMUX_GPIO20__FUNC_DBG_MON_B4 (MTK_PIN_NO(20) | 7) + +#define PINMUX_GPIO21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) +#define PINMUX_GPIO21__FUNC_SPI4_C_CSB (MTK_PIN_NO(21) | 2) +#define PINMUX_GPIO21__FUNC_SPI1_B_CSB (MTK_PIN_NO(21) | 3) +#define PINMUX_GPIO21__FUNC_IDDIG (MTK_PIN_NO(21) | 6) +#define PINMUX_GPIO21__FUNC_DBG_MON_B5 (MTK_PIN_NO(21) | 7) + +#define PINMUX_GPIO22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) +#define PINMUX_GPIO22__FUNC_SPI0_C_CLK (MTK_PIN_NO(22) | 2) +#define PINMUX_GPIO22__FUNC_SPI7_B_CLK (MTK_PIN_NO(22) | 3) +#define PINMUX_GPIO22__FUNC_I2S7_BCK (MTK_PIN_NO(22) | 4) +#define PINMUX_GPIO22__FUNC_I2S9_BCK (MTK_PIN_NO(22) | 5) +#define PINMUX_GPIO22__FUNC_SCL_6306 (MTK_PIN_NO(22) | 6) + +#define PINMUX_GPIO23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) +#define PINMUX_GPIO23__FUNC_SPI0_C_CSB (MTK_PIN_NO(23) | 2) +#define PINMUX_GPIO23__FUNC_SPI7_B_CSB (MTK_PIN_NO(23) | 3) +#define PINMUX_GPIO23__FUNC_I2S7_LRCK (MTK_PIN_NO(23) | 4) +#define PINMUX_GPIO23__FUNC_I2S9_LRCK (MTK_PIN_NO(23) | 5) +#define PINMUX_GPIO23__FUNC_SDA_6306 (MTK_PIN_NO(23) | 6) + +#define PINMUX_GPIO24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) +#define PINMUX_GPIO24__FUNC_SRCLKENAI1 (MTK_PIN_NO(24) | 1) +#define PINMUX_GPIO24__FUNC_SPI0_C_MI (MTK_PIN_NO(24) | 2) +#define PINMUX_GPIO24__FUNC_SPI7_B_MI (MTK_PIN_NO(24) | 3) +#define PINMUX_GPIO24__FUNC_I2S6_DI (MTK_PIN_NO(24) | 4) +#define PINMUX_GPIO24__FUNC_I2S8_DI (MTK_PIN_NO(24) | 5) +#define PINMUX_GPIO24__FUNC_SPINOR_CS (MTK_PIN_NO(24) | 6) + +#define PINMUX_GPIO25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) +#define PINMUX_GPIO25__FUNC_SRCLKENAI0 (MTK_PIN_NO(25) | 1) +#define PINMUX_GPIO25__FUNC_SPI0_C_MO (MTK_PIN_NO(25) | 2) +#define PINMUX_GPIO25__FUNC_SPI7_B_MO (MTK_PIN_NO(25) | 3) +#define PINMUX_GPIO25__FUNC_I2S7_DO (MTK_PIN_NO(25) | 4) +#define PINMUX_GPIO25__FUNC_I2S9_DO (MTK_PIN_NO(25) | 5) +#define PINMUX_GPIO25__FUNC_SPINOR_CK (MTK_PIN_NO(25) | 6) + +#define PINMUX_GPIO26__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) +#define PINMUX_GPIO26__FUNC_PWM_2 (MTK_PIN_NO(26) | 1) +#define PINMUX_GPIO26__FUNC_CLKM0 (MTK_PIN_NO(26) | 2) +#define PINMUX_GPIO26__FUNC_USB_DRVVBUS (MTK_PIN_NO(26) | 3) +#define PINMUX_GPIO26__FUNC_SPI5_C_MI (MTK_PIN_NO(26) | 4) +#define PINMUX_GPIO26__FUNC_I2S9_BCK (MTK_PIN_NO(26) | 5) + +#define PINMUX_GPIO27__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) +#define PINMUX_GPIO27__FUNC_PWM_3 (MTK_PIN_NO(27) | 1) +#define PINMUX_GPIO27__FUNC_CLKM1 (MTK_PIN_NO(27) | 2) +#define PINMUX_GPIO27__FUNC_SPI5_C_MO (MTK_PIN_NO(27) | 4) +#define PINMUX_GPIO27__FUNC_I2S9_LRCK (MTK_PIN_NO(27) | 5) +#define PINMUX_GPIO27__FUNC_SPINOR_IO0 (MTK_PIN_NO(27) | 6) + +#define PINMUX_GPIO28__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) +#define PINMUX_GPIO28__FUNC_PWM_0 (MTK_PIN_NO(28) | 1) +#define PINMUX_GPIO28__FUNC_CLKM2 (MTK_PIN_NO(28) | 2) +#define PINMUX_GPIO28__FUNC_SPI5_C_CSB (MTK_PIN_NO(28) | 4) +#define PINMUX_GPIO28__FUNC_I2S9_MCK (MTK_PIN_NO(28) | 5) +#define PINMUX_GPIO28__FUNC_SPINOR_IO1 (MTK_PIN_NO(28) | 6) + +#define PINMUX_GPIO29__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) +#define PINMUX_GPIO29__FUNC_PWM_1 (MTK_PIN_NO(29) | 1) +#define PINMUX_GPIO29__FUNC_CLKM3 (MTK_PIN_NO(29) | 2) +#define PINMUX_GPIO29__FUNC_SPI5_C_CLK (MTK_PIN_NO(29) | 4) +#define PINMUX_GPIO29__FUNC_I2S9_DO (MTK_PIN_NO(29) | 5) +#define PINMUX_GPIO29__FUNC_SPINOR_IO2 (MTK_PIN_NO(29) | 6) + +#define PINMUX_GPIO30__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) +#define PINMUX_GPIO30__FUNC_PWM_2 (MTK_PIN_NO(30) | 1) +#define PINMUX_GPIO30__FUNC_CLKM0 (MTK_PIN_NO(30) | 2) +#define PINMUX_GPIO30__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(30) | 3) +#define PINMUX_GPIO30__FUNC_I2S7_MCK (MTK_PIN_NO(30) | 4) +#define PINMUX_GPIO30__FUNC_I2S9_MCK (MTK_PIN_NO(30) | 5) +#define PINMUX_GPIO30__FUNC_SPINOR_IO3 (MTK_PIN_NO(30) | 6) + +#define PINMUX_GPIO31__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) +#define PINMUX_GPIO31__FUNC_I2S3_MCK (MTK_PIN_NO(31) | 1) +#define PINMUX_GPIO31__FUNC_I2S1_MCK (MTK_PIN_NO(31) | 2) +#define PINMUX_GPIO31__FUNC_I2S5_MCK (MTK_PIN_NO(31) | 3) +#define PINMUX_GPIO31__FUNC_SRCLKENAI0 (MTK_PIN_NO(31) | 4) +#define PINMUX_GPIO31__FUNC_I2S0_MCK (MTK_PIN_NO(31) | 5) + +#define PINMUX_GPIO32__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) +#define PINMUX_GPIO32__FUNC_I2S3_BCK (MTK_PIN_NO(32) | 1) +#define PINMUX_GPIO32__FUNC_I2S1_BCK (MTK_PIN_NO(32) | 2) +#define PINMUX_GPIO32__FUNC_I2S5_BCK (MTK_PIN_NO(32) | 3) +#define PINMUX_GPIO32__FUNC_PCM0_CLK (MTK_PIN_NO(32) | 4) +#define PINMUX_GPIO32__FUNC_I2S0_BCK (MTK_PIN_NO(32) | 5) + +#define PINMUX_GPIO33__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) +#define PINMUX_GPIO33__FUNC_I2S3_LRCK (MTK_PIN_NO(33) | 1) +#define PINMUX_GPIO33__FUNC_I2S1_LRCK (MTK_PIN_NO(33) | 2) +#define PINMUX_GPIO33__FUNC_I2S5_LRCK (MTK_PIN_NO(33) | 3) +#define PINMUX_GPIO33__FUNC_PCM0_SYNC (MTK_PIN_NO(33) | 4) +#define PINMUX_GPIO33__FUNC_I2S0_LRCK (MTK_PIN_NO(33) | 5) + +#define PINMUX_GPIO34__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) +#define PINMUX_GPIO34__FUNC_I2S0_DI (MTK_PIN_NO(34) | 1) +#define PINMUX_GPIO34__FUNC_I2S2_DI (MTK_PIN_NO(34) | 2) +#define PINMUX_GPIO34__FUNC_I2S2_DI2 (MTK_PIN_NO(34) | 3) +#define PINMUX_GPIO34__FUNC_PCM0_DI (MTK_PIN_NO(34) | 4) +#define PINMUX_GPIO34__FUNC_I2S0_DI_A (MTK_PIN_NO(34) | 5) + +#define PINMUX_GPIO35__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) +#define PINMUX_GPIO35__FUNC_I2S3_DO (MTK_PIN_NO(35) | 1) +#define PINMUX_GPIO35__FUNC_I2S1_DO (MTK_PIN_NO(35) | 2) +#define PINMUX_GPIO35__FUNC_I2S5_DO (MTK_PIN_NO(35) | 3) +#define PINMUX_GPIO35__FUNC_PCM0_DO (MTK_PIN_NO(35) | 4) + +#define PINMUX_GPIO36__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) +#define PINMUX_GPIO36__FUNC_SPI5_A_CLK (MTK_PIN_NO(36) | 1) +#define PINMUX_GPIO36__FUNC_DMIC1_CLK (MTK_PIN_NO(36) | 2) +#define PINMUX_GPIO36__FUNC_MD_URXD0 (MTK_PIN_NO(36) | 4) +#define PINMUX_GPIO36__FUNC_UCTS0 (MTK_PIN_NO(36) | 5) +#define PINMUX_GPIO36__FUNC_URXD1 (MTK_PIN_NO(36) | 6) + +#define PINMUX_GPIO37__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) +#define PINMUX_GPIO37__FUNC_SPI5_A_CSB (MTK_PIN_NO(37) | 1) +#define PINMUX_GPIO37__FUNC_DMIC1_DAT (MTK_PIN_NO(37) | 2) +#define PINMUX_GPIO37__FUNC_MD_UTXD0 (MTK_PIN_NO(37) | 4) +#define PINMUX_GPIO37__FUNC_URTS0 (MTK_PIN_NO(37) | 5) +#define PINMUX_GPIO37__FUNC_UTXD1 (MTK_PIN_NO(37) | 6) + +#define PINMUX_GPIO38__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) +#define PINMUX_GPIO38__FUNC_SPI5_A_MI (MTK_PIN_NO(38) | 1) +#define PINMUX_GPIO38__FUNC_DMIC_CLK (MTK_PIN_NO(38) | 2) +#define PINMUX_GPIO38__FUNC_MD_URXD1 (MTK_PIN_NO(38) | 4) +#define PINMUX_GPIO38__FUNC_URXD0 (MTK_PIN_NO(38) | 5) +#define PINMUX_GPIO38__FUNC_UCTS1 (MTK_PIN_NO(38) | 6) + +#define PINMUX_GPIO39__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) +#define PINMUX_GPIO39__FUNC_SPI5_A_MO (MTK_PIN_NO(39) | 1) +#define PINMUX_GPIO39__FUNC_DMIC_DAT (MTK_PIN_NO(39) | 2) +#define PINMUX_GPIO39__FUNC_MD_UTXD1 (MTK_PIN_NO(39) | 4) +#define PINMUX_GPIO39__FUNC_UTXD0 (MTK_PIN_NO(39) | 5) +#define PINMUX_GPIO39__FUNC_URTS1 (MTK_PIN_NO(39) | 6) + +#define PINMUX_GPIO40__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) +#define PINMUX_GPIO40__FUNC_DISP_PWM (MTK_PIN_NO(40) | 1) +#define PINMUX_GPIO40__FUNC_DBG_MON_A6 (MTK_PIN_NO(40) | 7) + +#define PINMUX_GPIO41__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) +#define PINMUX_GPIO41__FUNC_DSI_TE (MTK_PIN_NO(41) | 1) +#define PINMUX_GPIO41__FUNC_DBG_MON_A7 (MTK_PIN_NO(41) | 7) + +#define PINMUX_GPIO42__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) +#define PINMUX_GPIO42__FUNC_LCM_RST (MTK_PIN_NO(42) | 1) +#define PINMUX_GPIO42__FUNC_DBG_MON_A8 (MTK_PIN_NO(42) | 7) + +#define PINMUX_GPIO43__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) +#define PINMUX_GPIO43__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(43) | 1) +#define PINMUX_GPIO43__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(43) | 2) +#define PINMUX_GPIO43__FUNC_SCL_6306 (MTK_PIN_NO(43) | 3) +#define PINMUX_GPIO43__FUNC_ADSP_URXD0 (MTK_PIN_NO(43) | 4) +#define PINMUX_GPIO43__FUNC_PTA_RXD (MTK_PIN_NO(43) | 5) +#define PINMUX_GPIO43__FUNC_SSPM_URXD_AO (MTK_PIN_NO(43) | 6) +#define PINMUX_GPIO43__FUNC_DBG_MON_B0 (MTK_PIN_NO(43) | 7) + +#define PINMUX_GPIO44__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) +#define PINMUX_GPIO44__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(44) | 1) +#define PINMUX_GPIO44__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(44) | 2) +#define PINMUX_GPIO44__FUNC_SDA_6306 (MTK_PIN_NO(44) | 3) +#define PINMUX_GPIO44__FUNC_ADSP_UTXD0 (MTK_PIN_NO(44) | 4) +#define PINMUX_GPIO44__FUNC_PTA_TXD (MTK_PIN_NO(44) | 5) +#define PINMUX_GPIO44__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(44) | 6) +#define PINMUX_GPIO44__FUNC_DBG_MON_B1 (MTK_PIN_NO(44) | 7) + +#define PINMUX_GPIO45__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) +#define PINMUX_GPIO45__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(45) | 1) +#define PINMUX_GPIO45__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(45) | 2) +#define PINMUX_GPIO45__FUNC_MCUPM_JTAG_TDI (MTK_PIN_NO(45) | 3) +#define PINMUX_GPIO45__FUNC_APU_JTAG_TDI (MTK_PIN_NO(45) | 4) +#define PINMUX_GPIO45__FUNC_CCU_JTAG_TDI (MTK_PIN_NO(45) | 5) +#define PINMUX_GPIO45__FUNC_LVTS_SCK (MTK_PIN_NO(45) | 6) +#define PINMUX_GPIO45__FUNC_CONN_DSP_JDI (MTK_PIN_NO(45) | 7) + +#define PINMUX_GPIO46__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) +#define PINMUX_GPIO46__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(46) | 1) +#define PINMUX_GPIO46__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(46) | 2) +#define PINMUX_GPIO46__FUNC_MCUPM_JTAG_TMS (MTK_PIN_NO(46) | 3) +#define PINMUX_GPIO46__FUNC_APU_JTAG_TMS (MTK_PIN_NO(46) | 4) +#define PINMUX_GPIO46__FUNC_CCU_JTAG_TMS (MTK_PIN_NO(46) | 5) +#define PINMUX_GPIO46__FUNC_LVTS_SDI (MTK_PIN_NO(46) | 6) +#define PINMUX_GPIO46__FUNC_CONN_DSP_JMS (MTK_PIN_NO(46) | 7) + +#define PINMUX_GPIO47__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) +#define PINMUX_GPIO47__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(47) | 1) +#define PINMUX_GPIO47__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(47) | 2) +#define PINMUX_GPIO47__FUNC_MCUPM_JTAG_TDO (MTK_PIN_NO(47) | 3) +#define PINMUX_GPIO47__FUNC_APU_JTAG_TDO (MTK_PIN_NO(47) | 4) +#define PINMUX_GPIO47__FUNC_CCU_JTAG_TDO (MTK_PIN_NO(47) | 5) +#define PINMUX_GPIO47__FUNC_LVTS_SCF (MTK_PIN_NO(47) | 6) +#define PINMUX_GPIO47__FUNC_CONN_DSP_JDO (MTK_PIN_NO(47) | 7) + +#define PINMUX_GPIO48__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) +#define PINMUX_GPIO48__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(48) | 1) +#define PINMUX_GPIO48__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(48) | 2) +#define PINMUX_GPIO48__FUNC_MCUPM_JTAG_TRSTN (MTK_PIN_NO(48) | 3) +#define PINMUX_GPIO48__FUNC_APU_JTAG_TRST (MTK_PIN_NO(48) | 4) +#define PINMUX_GPIO48__FUNC_CCU_JTAG_TRST (MTK_PIN_NO(48) | 5) +#define PINMUX_GPIO48__FUNC_LVTS_FOUT (MTK_PIN_NO(48) | 6) +#define PINMUX_GPIO48__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(48) | 7) + +#define PINMUX_GPIO49__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) +#define PINMUX_GPIO49__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(49) | 1) +#define PINMUX_GPIO49__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(49) | 2) +#define PINMUX_GPIO49__FUNC_MCUPM_JTAG_TCK (MTK_PIN_NO(49) | 3) +#define PINMUX_GPIO49__FUNC_APU_JTAG_TCK (MTK_PIN_NO(49) | 4) +#define PINMUX_GPIO49__FUNC_CCU_JTAG_TCK (MTK_PIN_NO(49) | 5) +#define PINMUX_GPIO49__FUNC_LVTS_SDO (MTK_PIN_NO(49) | 6) +#define PINMUX_GPIO49__FUNC_CONN_DSP_JCK (MTK_PIN_NO(49) | 7) + +#define PINMUX_GPIO50__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) +#define PINMUX_GPIO50__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(50) | 1) +#define PINMUX_GPIO50__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(50) | 2) +#define PINMUX_GPIO50__FUNC_LVTS_26M (MTK_PIN_NO(50) | 6) + +#define PINMUX_GPIO51__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) +#define PINMUX_GPIO51__FUNC_MSDC1_CLK (MTK_PIN_NO(51) | 1) +#define PINMUX_GPIO51__FUNC_PCM1_CLK (MTK_PIN_NO(51) | 2) +#define PINMUX_GPIO51__FUNC_CONN_DSP_JCK (MTK_PIN_NO(51) | 3) +#define PINMUX_GPIO51__FUNC_UDI_TCK (MTK_PIN_NO(51) | 4) +#define PINMUX_GPIO51__FUNC_IPU_JTAG_TCK (MTK_PIN_NO(51) | 5) +#define PINMUX_GPIO51__FUNC_SSPM_JTAG_TCK (MTK_PIN_NO(51) | 6) +#define PINMUX_GPIO51__FUNC_JTCK_SEL3 (MTK_PIN_NO(51) | 7) + +#define PINMUX_GPIO52__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) +#define PINMUX_GPIO52__FUNC_MSDC1_CMD (MTK_PIN_NO(52) | 1) +#define PINMUX_GPIO52__FUNC_PCM1_SYNC (MTK_PIN_NO(52) | 2) +#define PINMUX_GPIO52__FUNC_CONN_DSP_JMS (MTK_PIN_NO(52) | 3) +#define PINMUX_GPIO52__FUNC_UDI_TMS (MTK_PIN_NO(52) | 4) +#define PINMUX_GPIO52__FUNC_IPU_JTAG_TMS (MTK_PIN_NO(52) | 5) +#define PINMUX_GPIO52__FUNC_SSPM_JTAG_TMS (MTK_PIN_NO(52) | 6) +#define PINMUX_GPIO52__FUNC_JTMS_SEL3 (MTK_PIN_NO(52) | 7) + +#define PINMUX_GPIO53__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) +#define PINMUX_GPIO53__FUNC_MSDC1_DAT3 (MTK_PIN_NO(53) | 1) +#define PINMUX_GPIO53__FUNC_PCM1_DI (MTK_PIN_NO(53) | 2) +#define PINMUX_GPIO53__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(53) | 3) +#define PINMUX_GPIO53__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(53) | 4) + +#define PINMUX_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) +#define PINMUX_GPIO54__FUNC_MSDC1_DAT0 (MTK_PIN_NO(54) | 1) +#define PINMUX_GPIO54__FUNC_PCM1_DO0 (MTK_PIN_NO(54) | 2) +#define PINMUX_GPIO54__FUNC_CONN_DSP_JDI (MTK_PIN_NO(54) | 3) +#define PINMUX_GPIO54__FUNC_UDI_TDI (MTK_PIN_NO(54) | 4) +#define PINMUX_GPIO54__FUNC_IPU_JTAG_TDI (MTK_PIN_NO(54) | 5) +#define PINMUX_GPIO54__FUNC_SSPM_JTAG_TDI (MTK_PIN_NO(54) | 6) +#define PINMUX_GPIO54__FUNC_JTDI_SEL3 (MTK_PIN_NO(54) | 7) + +#define PINMUX_GPIO55__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) +#define PINMUX_GPIO55__FUNC_MSDC1_DAT2 (MTK_PIN_NO(55) | 1) +#define PINMUX_GPIO55__FUNC_PCM1_DO2 (MTK_PIN_NO(55) | 2) +#define PINMUX_GPIO55__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(55) | 3) +#define PINMUX_GPIO55__FUNC_UDI_NTRST (MTK_PIN_NO(55) | 4) +#define PINMUX_GPIO55__FUNC_IPU_JTAG_TRST (MTK_PIN_NO(55) | 5) +#define PINMUX_GPIO55__FUNC_SSPM_JTAG_TRSTN (MTK_PIN_NO(55) | 6) +#define PINMUX_GPIO55__FUNC_JTRSTN_SEL3 (MTK_PIN_NO(55) | 7) + +#define PINMUX_GPIO56__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) +#define PINMUX_GPIO56__FUNC_MSDC1_DAT1 (MTK_PIN_NO(56) | 1) +#define PINMUX_GPIO56__FUNC_PCM1_DO1 (MTK_PIN_NO(56) | 2) +#define PINMUX_GPIO56__FUNC_CONN_DSP_JDO (MTK_PIN_NO(56) | 3) +#define PINMUX_GPIO56__FUNC_UDI_TDO (MTK_PIN_NO(56) | 4) +#define PINMUX_GPIO56__FUNC_IPU_JTAG_TDO (MTK_PIN_NO(56) | 5) +#define PINMUX_GPIO56__FUNC_SSPM_JTAG_TDO (MTK_PIN_NO(56) | 6) +#define PINMUX_GPIO56__FUNC_JTDO_SEL3 (MTK_PIN_NO(56) | 7) + +#define PINMUX_GPIO57__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) +#define PINMUX_GPIO57__FUNC_MIPI2_D_SCLK (MTK_PIN_NO(57) | 1) + +#define PINMUX_GPIO58__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) +#define PINMUX_GPIO58__FUNC_MIPI2_D_SDATA (MTK_PIN_NO(58) | 1) + +#define PINMUX_GPIO59__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) +#define PINMUX_GPIO59__FUNC_MIPI_M_SCLK (MTK_PIN_NO(59) | 1) + +#define PINMUX_GPIO60__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) +#define PINMUX_GPIO60__FUNC_MIPI_M_SDATA (MTK_PIN_NO(60) | 1) + +#define PINMUX_GPIO61__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) +#define PINMUX_GPIO61__FUNC_MD_UCNT_A_TGL (MTK_PIN_NO(61) | 1) + +#define PINMUX_GPIO62__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) +#define PINMUX_GPIO62__FUNC_DIGRF_IRQ (MTK_PIN_NO(62) | 1) + +#define PINMUX_GPIO63__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) +#define PINMUX_GPIO63__FUNC_BPI_BUS0 (MTK_PIN_NO(63) | 1) +#define PINMUX_GPIO63__FUNC_PCIE_WAKE_N (MTK_PIN_NO(63) | 3) + +#define PINMUX_GPIO64__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) +#define PINMUX_GPIO64__FUNC_BPI_BUS1 (MTK_PIN_NO(64) | 1) +#define PINMUX_GPIO64__FUNC_PCIE_PERESET_N (MTK_PIN_NO(64) | 3) + +#define PINMUX_GPIO65__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) +#define PINMUX_GPIO65__FUNC_BPI_BUS2 (MTK_PIN_NO(65) | 1) +#define PINMUX_GPIO65__FUNC_PCIE_CLKREQ_N (MTK_PIN_NO(65) | 3) + +#define PINMUX_GPIO66__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) +#define PINMUX_GPIO66__FUNC_BPI_BUS3 (MTK_PIN_NO(66) | 1) + +#define PINMUX_GPIO67__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) +#define PINMUX_GPIO67__FUNC_BPI_BUS4 (MTK_PIN_NO(67) | 1) + +#define PINMUX_GPIO68__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) +#define PINMUX_GPIO68__FUNC_BPI_BUS5 (MTK_PIN_NO(68) | 1) + +#define PINMUX_GPIO69__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) +#define PINMUX_GPIO69__FUNC_BPI_BUS6 (MTK_PIN_NO(69) | 1) +#define PINMUX_GPIO69__FUNC_CONN_BPI_BUS6 (MTK_PIN_NO(69) | 2) + +#define PINMUX_GPIO70__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) +#define PINMUX_GPIO70__FUNC_BPI_BUS7 (MTK_PIN_NO(70) | 1) +#define PINMUX_GPIO70__FUNC_CONN_BPI_BUS7 (MTK_PIN_NO(70) | 2) + +#define PINMUX_GPIO71__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) +#define PINMUX_GPIO71__FUNC_BPI_BUS8 (MTK_PIN_NO(71) | 1) +#define PINMUX_GPIO71__FUNC_CONN_BPI_BUS8 (MTK_PIN_NO(71) | 2) + +#define PINMUX_GPIO72__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) +#define PINMUX_GPIO72__FUNC_BPI_BUS9 (MTK_PIN_NO(72) | 1) +#define PINMUX_GPIO72__FUNC_CONN_BPI_BUS9 (MTK_PIN_NO(72) | 2) + +#define PINMUX_GPIO73__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) +#define PINMUX_GPIO73__FUNC_BPI_BUS10 (MTK_PIN_NO(73) | 1) +#define PINMUX_GPIO73__FUNC_CONN_BPI_BUS10 (MTK_PIN_NO(73) | 2) + +#define PINMUX_GPIO74__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) +#define PINMUX_GPIO74__FUNC_BPI_BUS11_OLAT0 (MTK_PIN_NO(74) | 1) +#define PINMUX_GPIO74__FUNC_CONN_BPI_BUS11_OLAT0 (MTK_PIN_NO(74) | 2) + +#define PINMUX_GPIO75__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) +#define PINMUX_GPIO75__FUNC_BPI_BUS12_OLAT1 (MTK_PIN_NO(75) | 1) +#define PINMUX_GPIO75__FUNC_CONN_BPI_BUS12_OLAT1 (MTK_PIN_NO(75) | 2) + +#define PINMUX_GPIO76__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) +#define PINMUX_GPIO76__FUNC_BPI_BUS13_OLAT2 (MTK_PIN_NO(76) | 1) +#define PINMUX_GPIO76__FUNC_CONN_BPI_BUS13_OLAT2 (MTK_PIN_NO(76) | 2) + +#define PINMUX_GPIO77__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) +#define PINMUX_GPIO77__FUNC_BPI_BUS14_OLAT3 (MTK_PIN_NO(77) | 1) +#define PINMUX_GPIO77__FUNC_CONN_BPI_BUS14_OLAT3 (MTK_PIN_NO(77) | 2) + +#define PINMUX_GPIO78__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) +#define PINMUX_GPIO78__FUNC_BPI_BUS15_OLAT4 (MTK_PIN_NO(78) | 1) +#define PINMUX_GPIO78__FUNC_CONN_BPI_BUS15_OLAT4 (MTK_PIN_NO(78) | 2) + +#define PINMUX_GPIO79__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) +#define PINMUX_GPIO79__FUNC_BPI_BUS16_OLAT5 (MTK_PIN_NO(79) | 1) +#define PINMUX_GPIO79__FUNC_CONN_BPI_BUS16_OLAT5 (MTK_PIN_NO(79) | 2) + +#define PINMUX_GPIO80__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) +#define PINMUX_GPIO80__FUNC_BPI_BUS17_ANT0 (MTK_PIN_NO(80) | 1) +#define PINMUX_GPIO80__FUNC_CONN_BPI_BUS17_ANT0 (MTK_PIN_NO(80) | 2) +#define PINMUX_GPIO80__FUNC_PCIE_WAKE_N (MTK_PIN_NO(80) | 3) + +#define PINMUX_GPIO81__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) +#define PINMUX_GPIO81__FUNC_BPI_BUS18_ANT1 (MTK_PIN_NO(81) | 1) +#define PINMUX_GPIO81__FUNC_CONN_BPI_BUS18_ANT1 (MTK_PIN_NO(81) | 2) +#define PINMUX_GPIO81__FUNC_PCIE_PERESET_N (MTK_PIN_NO(81) | 3) + +#define PINMUX_GPIO82__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) +#define PINMUX_GPIO82__FUNC_BPI_BUS19_ANT2 (MTK_PIN_NO(82) | 1) +#define PINMUX_GPIO82__FUNC_CONN_BPI_BUS19_ANT2 (MTK_PIN_NO(82) | 2) +#define PINMUX_GPIO82__FUNC_PCIE_CLKREQ_N (MTK_PIN_NO(82) | 3) + +#define PINMUX_GPIO83__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) +#define PINMUX_GPIO83__FUNC_BPI_BUS20_ANT3 (MTK_PIN_NO(83) | 1) +#define PINMUX_GPIO83__FUNC_CONN_BPI_BUS20_ANT3 (MTK_PIN_NO(83) | 2) + +#define PINMUX_GPIO84__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) +#define PINMUX_GPIO84__FUNC_BPI_BUS21_ANT4 (MTK_PIN_NO(84) | 1) +#define PINMUX_GPIO84__FUNC_CONN_BPI_BUS21_ANT4 (MTK_PIN_NO(84) | 2) + +#define PINMUX_GPIO85__FUNC_GPIO85 (MTK_PIN_NO(85) | 0) +#define PINMUX_GPIO85__FUNC_MIPI1_D_SCLK (MTK_PIN_NO(85) | 1) +#define PINMUX_GPIO85__FUNC_CONN_MIPI1_SCLK (MTK_PIN_NO(85) | 2) + +#define PINMUX_GPIO86__FUNC_GPIO86 (MTK_PIN_NO(86) | 0) +#define PINMUX_GPIO86__FUNC_MIPI1_D_SDATA (MTK_PIN_NO(86) | 1) +#define PINMUX_GPIO86__FUNC_CONN_MIPI1_SDATA (MTK_PIN_NO(86) | 2) + +#define PINMUX_GPIO87__FUNC_GPIO87 (MTK_PIN_NO(87) | 0) +#define PINMUX_GPIO87__FUNC_MIPI0_D_SCLK (MTK_PIN_NO(87) | 1) +#define PINMUX_GPIO87__FUNC_CONN_MIPI0_SCLK (MTK_PIN_NO(87) | 2) + +#define PINMUX_GPIO88__FUNC_GPIO88 (MTK_PIN_NO(88) | 0) +#define PINMUX_GPIO88__FUNC_MIPI0_D_SDATA (MTK_PIN_NO(88) | 1) +#define PINMUX_GPIO88__FUNC_CONN_MIPI0_SDATA (MTK_PIN_NO(88) | 2) + +#define PINMUX_GPIO89__FUNC_GPIO89 (MTK_PIN_NO(89) | 0) +#define PINMUX_GPIO89__FUNC_SPMI_SCL (MTK_PIN_NO(89) | 1) +#define PINMUX_GPIO89__FUNC_SCL10 (MTK_PIN_NO(89) | 2) + +#define PINMUX_GPIO90__FUNC_GPIO90 (MTK_PIN_NO(90) | 0) +#define PINMUX_GPIO90__FUNC_SPMI_SDA (MTK_PIN_NO(90) | 1) +#define PINMUX_GPIO90__FUNC_SDA10 (MTK_PIN_NO(90) | 2) + +#define PINMUX_GPIO91__FUNC_GPIO91 (MTK_PIN_NO(91) | 0) +#define PINMUX_GPIO91__FUNC_AP_GOOD (MTK_PIN_NO(91) | 1) + +#define PINMUX_GPIO92__FUNC_GPIO92 (MTK_PIN_NO(92) | 0) +#define PINMUX_GPIO92__FUNC_URXD0 (MTK_PIN_NO(92) | 1) +#define PINMUX_GPIO92__FUNC_MD_URXD0 (MTK_PIN_NO(92) | 2) +#define PINMUX_GPIO92__FUNC_MD_URXD1 (MTK_PIN_NO(92) | 3) +#define PINMUX_GPIO92__FUNC_SSPM_URXD_AO (MTK_PIN_NO(92) | 4) +#define PINMUX_GPIO92__FUNC_CONN_UART0_RXD (MTK_PIN_NO(92) | 5) + +#define PINMUX_GPIO93__FUNC_GPIO93 (MTK_PIN_NO(93) | 0) +#define PINMUX_GPIO93__FUNC_UTXD0 (MTK_PIN_NO(93) | 1) +#define PINMUX_GPIO93__FUNC_MD_UTXD0 (MTK_PIN_NO(93) | 2) +#define PINMUX_GPIO93__FUNC_MD_UTXD1 (MTK_PIN_NO(93) | 3) +#define PINMUX_GPIO93__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(93) | 4) +#define PINMUX_GPIO93__FUNC_CONN_UART0_TXD (MTK_PIN_NO(93) | 5) +#define PINMUX_GPIO93__FUNC_WIFI_TXD (MTK_PIN_NO(93) | 6) + +#define PINMUX_GPIO94__FUNC_GPIO94 (MTK_PIN_NO(94) | 0) +#define PINMUX_GPIO94__FUNC_URXD1 (MTK_PIN_NO(94) | 1) +#define PINMUX_GPIO94__FUNC_ADSP_URXD0 (MTK_PIN_NO(94) | 2) +#define PINMUX_GPIO94__FUNC_MD32_0_RXD (MTK_PIN_NO(94) | 3) +#define PINMUX_GPIO94__FUNC_SSPM_URXD_AO (MTK_PIN_NO(94) | 4) +#define PINMUX_GPIO94__FUNC_TP_URXD1_AO (MTK_PIN_NO(94) | 5) +#define PINMUX_GPIO94__FUNC_TP_URXD2_AO (MTK_PIN_NO(94) | 6) +#define PINMUX_GPIO94__FUNC_MBISTREADEN_TRIGGER (MTK_PIN_NO(94) | 7) + +#define PINMUX_GPIO95__FUNC_GPIO95 (MTK_PIN_NO(95) | 0) +#define PINMUX_GPIO95__FUNC_UTXD1 (MTK_PIN_NO(95) | 1) +#define PINMUX_GPIO95__FUNC_ADSP_UTXD0 (MTK_PIN_NO(95) | 2) +#define PINMUX_GPIO95__FUNC_MD32_0_TXD (MTK_PIN_NO(95) | 3) +#define PINMUX_GPIO95__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(95) | 4) +#define PINMUX_GPIO95__FUNC_TP_UTXD1_AO (MTK_PIN_NO(95) | 5) +#define PINMUX_GPIO95__FUNC_TP_UTXD2_AO (MTK_PIN_NO(95) | 6) +#define PINMUX_GPIO95__FUNC_MBISTWRITEEN_TRIGGER (MTK_PIN_NO(95) | 7) + +#define PINMUX_GPIO96__FUNC_GPIO96 (MTK_PIN_NO(96) | 0) +#define PINMUX_GPIO96__FUNC_TDM_LRCK (MTK_PIN_NO(96) | 1) +#define PINMUX_GPIO96__FUNC_I2S7_LRCK (MTK_PIN_NO(96) | 2) +#define PINMUX_GPIO96__FUNC_I2S9_LRCK (MTK_PIN_NO(96) | 3) +#define PINMUX_GPIO96__FUNC_DPI_D0 (MTK_PIN_NO(96) | 4) +#define PINMUX_GPIO96__FUNC_ADSP_JTAG0_TDI (MTK_PIN_NO(96) | 5) +#define PINMUX_GPIO96__FUNC_IO_JTAG_TDI (MTK_PIN_NO(96) | 7) + +#define PINMUX_GPIO97__FUNC_GPIO97 (MTK_PIN_NO(97) | 0) +#define PINMUX_GPIO97__FUNC_TDM_BCK (MTK_PIN_NO(97) | 1) +#define PINMUX_GPIO97__FUNC_I2S7_BCK (MTK_PIN_NO(97) | 2) +#define PINMUX_GPIO97__FUNC_I2S9_BCK (MTK_PIN_NO(97) | 3) +#define PINMUX_GPIO97__FUNC_DPI_D1 (MTK_PIN_NO(97) | 4) +#define PINMUX_GPIO97__FUNC_ADSP_JTAG0_TRSTN (MTK_PIN_NO(97) | 5) +#define PINMUX_GPIO97__FUNC_IO_JTAG_TRSTN (MTK_PIN_NO(97) | 7) + +#define PINMUX_GPIO98__FUNC_GPIO98 (MTK_PIN_NO(98) | 0) +#define PINMUX_GPIO98__FUNC_TDM_MCK (MTK_PIN_NO(98) | 1) +#define PINMUX_GPIO98__FUNC_I2S7_MCK (MTK_PIN_NO(98) | 2) +#define PINMUX_GPIO98__FUNC_I2S9_MCK (MTK_PIN_NO(98) | 3) +#define PINMUX_GPIO98__FUNC_DPI_D2 (MTK_PIN_NO(98) | 4) +#define PINMUX_GPIO98__FUNC_ADSP_JTAG0_TCK (MTK_PIN_NO(98) | 5) +#define PINMUX_GPIO98__FUNC_IO_JTAG_TCK (MTK_PIN_NO(98) | 7) + +#define PINMUX_GPIO99__FUNC_GPIO99 (MTK_PIN_NO(99) | 0) +#define PINMUX_GPIO99__FUNC_TDM_DATA0 (MTK_PIN_NO(99) | 1) +#define PINMUX_GPIO99__FUNC_I2S6_DI (MTK_PIN_NO(99) | 2) +#define PINMUX_GPIO99__FUNC_I2S8_DI (MTK_PIN_NO(99) | 3) +#define PINMUX_GPIO99__FUNC_DPI_D3 (MTK_PIN_NO(99) | 4) +#define PINMUX_GPIO99__FUNC_ADSP_JTAG0_TDO (MTK_PIN_NO(99) | 5) +#define PINMUX_GPIO99__FUNC_IO_JTAG_TDO (MTK_PIN_NO(99) | 7) + +#define PINMUX_GPIO100__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) +#define PINMUX_GPIO100__FUNC_TDM_DATA1 (MTK_PIN_NO(100) | 1) +#define PINMUX_GPIO100__FUNC_I2S7_DO (MTK_PIN_NO(100) | 2) +#define PINMUX_GPIO100__FUNC_I2S9_DO (MTK_PIN_NO(100) | 3) +#define PINMUX_GPIO100__FUNC_DPI_D4 (MTK_PIN_NO(100) | 4) +#define PINMUX_GPIO100__FUNC_ADSP_JTAG0_TMS (MTK_PIN_NO(100) | 5) +#define PINMUX_GPIO100__FUNC_IO_JTAG_TMS (MTK_PIN_NO(100) | 7) + +#define PINMUX_GPIO101__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) +#define PINMUX_GPIO101__FUNC_TDM_DATA2 (MTK_PIN_NO(101) | 1) +#define PINMUX_GPIO101__FUNC_DMIC1_CLK (MTK_PIN_NO(101) | 2) +#define PINMUX_GPIO101__FUNC_SRCLKENAI0 (MTK_PIN_NO(101) | 3) +#define PINMUX_GPIO101__FUNC_DPI_D5 (MTK_PIN_NO(101) | 4) +#define PINMUX_GPIO101__FUNC_CLKM0 (MTK_PIN_NO(101) | 5) +#define PINMUX_GPIO101__FUNC_DAP_MD32_SWD (MTK_PIN_NO(101) | 7) + +#define PINMUX_GPIO102__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) +#define PINMUX_GPIO102__FUNC_TDM_DATA3 (MTK_PIN_NO(102) | 1) +#define PINMUX_GPIO102__FUNC_DMIC1_DAT (MTK_PIN_NO(102) | 2) +#define PINMUX_GPIO102__FUNC_SRCLKENAI1 (MTK_PIN_NO(102) | 3) +#define PINMUX_GPIO102__FUNC_DPI_D6 (MTK_PIN_NO(102) | 4) +#define PINMUX_GPIO102__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(102) | 6) +#define PINMUX_GPIO102__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(102) | 7) + +#define PINMUX_GPIO103__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) +#define PINMUX_GPIO103__FUNC_SPI0_A_MI (MTK_PIN_NO(103) | 1) +#define PINMUX_GPIO103__FUNC_SCP_SPI0_MI (MTK_PIN_NO(103) | 2) +#define PINMUX_GPIO103__FUNC_DPI_D7 (MTK_PIN_NO(103) | 4) +#define PINMUX_GPIO103__FUNC_DFD_TDO (MTK_PIN_NO(103) | 5) +#define PINMUX_GPIO103__FUNC_SPM_JTAG_TDO (MTK_PIN_NO(103) | 6) +#define PINMUX_GPIO103__FUNC_JTDO_SEL1 (MTK_PIN_NO(103) | 7) + +#define PINMUX_GPIO104__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) +#define PINMUX_GPIO104__FUNC_SPI0_A_CSB (MTK_PIN_NO(104) | 1) +#define PINMUX_GPIO104__FUNC_SCP_SPI0_CS (MTK_PIN_NO(104) | 2) +#define PINMUX_GPIO104__FUNC_DPI_D8 (MTK_PIN_NO(104) | 4) +#define PINMUX_GPIO104__FUNC_DFD_TMS (MTK_PIN_NO(104) | 5) +#define PINMUX_GPIO104__FUNC_SPM_JTAG_TMS (MTK_PIN_NO(104) | 6) +#define PINMUX_GPIO104__FUNC_JTMS_SEL1 (MTK_PIN_NO(104) | 7) + +#define PINMUX_GPIO105__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) +#define PINMUX_GPIO105__FUNC_SPI0_A_MO (MTK_PIN_NO(105) | 1) +#define PINMUX_GPIO105__FUNC_SCP_SPI0_MO (MTK_PIN_NO(105) | 2) +#define PINMUX_GPIO105__FUNC_SCP_SDA0 (MTK_PIN_NO(105) | 3) +#define PINMUX_GPIO105__FUNC_DPI_D9 (MTK_PIN_NO(105) | 4) +#define PINMUX_GPIO105__FUNC_DFD_TDI (MTK_PIN_NO(105) | 5) +#define PINMUX_GPIO105__FUNC_SPM_JTAG_TDI (MTK_PIN_NO(105) | 6) +#define PINMUX_GPIO105__FUNC_JTDI_SEL1 (MTK_PIN_NO(105) | 7) + +#define PINMUX_GPIO106__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) +#define PINMUX_GPIO106__FUNC_SPI0_A_CLK (MTK_PIN_NO(106) | 1) +#define PINMUX_GPIO106__FUNC_SCP_SPI0_CK (MTK_PIN_NO(106) | 2) +#define PINMUX_GPIO106__FUNC_SCP_SCL0 (MTK_PIN_NO(106) | 3) +#define PINMUX_GPIO106__FUNC_DPI_D10 (MTK_PIN_NO(106) | 4) +#define PINMUX_GPIO106__FUNC_DFD_TCK_XI (MTK_PIN_NO(106) | 5) +#define PINMUX_GPIO106__FUNC_SPM_JTAG_TCK (MTK_PIN_NO(106) | 6) +#define PINMUX_GPIO106__FUNC_JTCK_SEL1 (MTK_PIN_NO(106) | 7) + +#define PINMUX_GPIO107__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) +#define PINMUX_GPIO107__FUNC_DMIC_CLK (MTK_PIN_NO(107) | 1) +#define PINMUX_GPIO107__FUNC_PWM_0 (MTK_PIN_NO(107) | 2) +#define PINMUX_GPIO107__FUNC_CLKM2 (MTK_PIN_NO(107) | 3) +#define PINMUX_GPIO107__FUNC_SPM_JTAG_TRSTN (MTK_PIN_NO(107) | 6) +#define PINMUX_GPIO107__FUNC_JTRSTN_SEL1 (MTK_PIN_NO(107) | 7) + +#define PINMUX_GPIO108__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) +#define PINMUX_GPIO108__FUNC_DMIC_DAT (MTK_PIN_NO(108) | 1) +#define PINMUX_GPIO108__FUNC_PWM_1 (MTK_PIN_NO(108) | 2) +#define PINMUX_GPIO108__FUNC_CLKM3 (MTK_PIN_NO(108) | 3) +#define PINMUX_GPIO108__FUNC_DAP_SONIC_SWD (MTK_PIN_NO(108) | 7) + +#define PINMUX_GPIO109__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) +#define PINMUX_GPIO109__FUNC_I2S1_MCK (MTK_PIN_NO(109) | 1) +#define PINMUX_GPIO109__FUNC_I2S3_MCK (MTK_PIN_NO(109) | 2) +#define PINMUX_GPIO109__FUNC_I2S2_MCK (MTK_PIN_NO(109) | 3) +#define PINMUX_GPIO109__FUNC_DPI_DE (MTK_PIN_NO(109) | 4) +#define PINMUX_GPIO109__FUNC_I2S2_MCK_A (MTK_PIN_NO(109) | 5) +#define PINMUX_GPIO109__FUNC_SRCLKENAI0 (MTK_PIN_NO(109) | 6) +#define PINMUX_GPIO109__FUNC_DAP_SONIC_SWCK (MTK_PIN_NO(109) | 7) + +#define PINMUX_GPIO110__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) +#define PINMUX_GPIO110__FUNC_I2S1_BCK (MTK_PIN_NO(110) | 1) +#define PINMUX_GPIO110__FUNC_I2S3_BCK (MTK_PIN_NO(110) | 2) +#define PINMUX_GPIO110__FUNC_I2S2_BCK (MTK_PIN_NO(110) | 3) +#define PINMUX_GPIO110__FUNC_DPI_D11 (MTK_PIN_NO(110) | 4) +#define PINMUX_GPIO110__FUNC_I2S2_BCK_A (MTK_PIN_NO(110) | 5) +#define PINMUX_GPIO110__FUNC_CONN_MCU_TDO (MTK_PIN_NO(110) | 6) + +#define PINMUX_GPIO111__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) +#define PINMUX_GPIO111__FUNC_I2S1_LRCK (MTK_PIN_NO(111) | 1) +#define PINMUX_GPIO111__FUNC_I2S3_LRCK (MTK_PIN_NO(111) | 2) +#define PINMUX_GPIO111__FUNC_I2S2_LRCK (MTK_PIN_NO(111) | 3) +#define PINMUX_GPIO111__FUNC_DPI_VSYNC (MTK_PIN_NO(111) | 4) +#define PINMUX_GPIO111__FUNC_I2S2_LRCK_A (MTK_PIN_NO(111) | 5) +#define PINMUX_GPIO111__FUNC_CONN_MCU_TDI (MTK_PIN_NO(111) | 6) + +#define PINMUX_GPIO112__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) +#define PINMUX_GPIO112__FUNC_I2S2_DI (MTK_PIN_NO(112) | 1) +#define PINMUX_GPIO112__FUNC_I2S0_DI (MTK_PIN_NO(112) | 2) +#define PINMUX_GPIO112__FUNC_I2S2_DI2 (MTK_PIN_NO(112) | 3) +#define PINMUX_GPIO112__FUNC_DPI_CK (MTK_PIN_NO(112) | 4) +#define PINMUX_GPIO112__FUNC_I2S2_DI_A (MTK_PIN_NO(112) | 5) +#define PINMUX_GPIO112__FUNC_CONN_MCU_TMS (MTK_PIN_NO(112) | 6) + +#define PINMUX_GPIO113__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) +#define PINMUX_GPIO113__FUNC_I2S1_DO (MTK_PIN_NO(113) | 1) +#define PINMUX_GPIO113__FUNC_I2S3_DO (MTK_PIN_NO(113) | 2) +#define PINMUX_GPIO113__FUNC_I2S5_DO (MTK_PIN_NO(113) | 3) +#define PINMUX_GPIO113__FUNC_DPI_HSYNC (MTK_PIN_NO(113) | 4) +#define PINMUX_GPIO113__FUNC_I2S2_DI2 (MTK_PIN_NO(113) | 5) +#define PINMUX_GPIO113__FUNC_CONN_MCU_TCK (MTK_PIN_NO(113) | 6) + +#define PINMUX_GPIO114__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) +#define PINMUX_GPIO114__FUNC_SPI2_MI (MTK_PIN_NO(114) | 1) +#define PINMUX_GPIO114__FUNC_SCP_SPI2_MI (MTK_PIN_NO(114) | 2) +#define PINMUX_GPIO114__FUNC_PCM0_DI (MTK_PIN_NO(114) | 4) +#define PINMUX_GPIO114__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(114) | 6) + +#define PINMUX_GPIO115__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) +#define PINMUX_GPIO115__FUNC_SPI2_CSB (MTK_PIN_NO(115) | 1) +#define PINMUX_GPIO115__FUNC_SCP_SPI2_CS (MTK_PIN_NO(115) | 2) +#define PINMUX_GPIO115__FUNC_PCM0_SYNC (MTK_PIN_NO(115) | 4) +#define PINMUX_GPIO115__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(115) | 6) + +#define PINMUX_GPIO116__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) +#define PINMUX_GPIO116__FUNC_SPI2_MO (MTK_PIN_NO(116) | 1) +#define PINMUX_GPIO116__FUNC_SCP_SPI2_MO (MTK_PIN_NO(116) | 2) +#define PINMUX_GPIO116__FUNC_SCP_SDA1 (MTK_PIN_NO(116) | 3) +#define PINMUX_GPIO116__FUNC_PCM0_DO (MTK_PIN_NO(116) | 4) +#define PINMUX_GPIO116__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(116) | 6) + +#define PINMUX_GPIO117__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) +#define PINMUX_GPIO117__FUNC_SPI2_CLK (MTK_PIN_NO(117) | 1) +#define PINMUX_GPIO117__FUNC_SCP_SPI2_CK (MTK_PIN_NO(117) | 2) +#define PINMUX_GPIO117__FUNC_SCP_SCL1 (MTK_PIN_NO(117) | 3) +#define PINMUX_GPIO117__FUNC_PCM0_CLK (MTK_PIN_NO(117) | 4) + +#define PINMUX_GPIO118__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) +#define PINMUX_GPIO118__FUNC_SCL1 (MTK_PIN_NO(118) | 1) +#define PINMUX_GPIO118__FUNC_SCP_SCL0 (MTK_PIN_NO(118) | 2) +#define PINMUX_GPIO118__FUNC_SCP_SCL1 (MTK_PIN_NO(118) | 3) + +#define PINMUX_GPIO119__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) +#define PINMUX_GPIO119__FUNC_SDA1 (MTK_PIN_NO(119) | 1) +#define PINMUX_GPIO119__FUNC_SCP_SDA0 (MTK_PIN_NO(119) | 2) +#define PINMUX_GPIO119__FUNC_SCP_SDA1 (MTK_PIN_NO(119) | 3) + +#define PINMUX_GPIO120__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) +#define PINMUX_GPIO120__FUNC_SCL9 (MTK_PIN_NO(120) | 1) +#define PINMUX_GPIO120__FUNC_SCP_SCL0 (MTK_PIN_NO(120) | 2) + +#define PINMUX_GPIO121__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) +#define PINMUX_GPIO121__FUNC_SDA9 (MTK_PIN_NO(121) | 1) +#define PINMUX_GPIO121__FUNC_SCP_SDA0 (MTK_PIN_NO(121) | 2) + +#define PINMUX_GPIO122__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) +#define PINMUX_GPIO122__FUNC_SCL8 (MTK_PIN_NO(122) | 1) +#define PINMUX_GPIO122__FUNC_SCP_SDA0 (MTK_PIN_NO(122) | 2) + +#define PINMUX_GPIO123__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) +#define PINMUX_GPIO123__FUNC_SDA8 (MTK_PIN_NO(123) | 1) +#define PINMUX_GPIO123__FUNC_SCP_SCL0 (MTK_PIN_NO(123) | 2) + +#define PINMUX_GPIO124__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) +#define PINMUX_GPIO124__FUNC_SCL7 (MTK_PIN_NO(124) | 1) +#define PINMUX_GPIO124__FUNC_DMIC1_CLK (MTK_PIN_NO(124) | 2) + +#define PINMUX_GPIO125__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) +#define PINMUX_GPIO125__FUNC_SDA7 (MTK_PIN_NO(125) | 1) +#define PINMUX_GPIO125__FUNC_DMIC1_DAT (MTK_PIN_NO(125) | 2) + +#define PINMUX_GPIO126__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) +#define PINMUX_GPIO126__FUNC_CMFLASH0 (MTK_PIN_NO(126) | 1) +#define PINMUX_GPIO126__FUNC_PWM_2 (MTK_PIN_NO(126) | 2) +#define PINMUX_GPIO126__FUNC_TP_UCTS1_AO (MTK_PIN_NO(126) | 3) +#define PINMUX_GPIO126__FUNC_UCTS0 (MTK_PIN_NO(126) | 4) +#define PINMUX_GPIO126__FUNC_SCL11 (MTK_PIN_NO(126) | 5) +#define PINMUX_GPIO126__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(126) | 6) +#define PINMUX_GPIO126__FUNC_DBG_MON_A14 (MTK_PIN_NO(126) | 7) + +#define PINMUX_GPIO127__FUNC_GPIO127 (MTK_PIN_NO(127) | 0) +#define PINMUX_GPIO127__FUNC_CMFLASH1 (MTK_PIN_NO(127) | 1) +#define PINMUX_GPIO127__FUNC_PWM_3 (MTK_PIN_NO(127) | 2) +#define PINMUX_GPIO127__FUNC_TP_URTS1_AO (MTK_PIN_NO(127) | 3) +#define PINMUX_GPIO127__FUNC_URTS0 (MTK_PIN_NO(127) | 4) +#define PINMUX_GPIO127__FUNC_SDA11 (MTK_PIN_NO(127) | 5) +#define PINMUX_GPIO127__FUNC_DBG_MON_A15 (MTK_PIN_NO(127) | 7) + +#define PINMUX_GPIO128__FUNC_GPIO128 (MTK_PIN_NO(128) | 0) +#define PINMUX_GPIO128__FUNC_CMFLASH2 (MTK_PIN_NO(128) | 1) +#define PINMUX_GPIO128__FUNC_PWM_0 (MTK_PIN_NO(128) | 2) +#define PINMUX_GPIO128__FUNC_TP_UCTS2_AO (MTK_PIN_NO(128) | 3) +#define PINMUX_GPIO128__FUNC_UCTS1 (MTK_PIN_NO(128) | 4) +#define PINMUX_GPIO128__FUNC_SCL_6306 (MTK_PIN_NO(128) | 5) +#define PINMUX_GPIO128__FUNC_DBG_MON_A16 (MTK_PIN_NO(128) | 7) + +#define PINMUX_GPIO129__FUNC_GPIO129 (MTK_PIN_NO(129) | 0) +#define PINMUX_GPIO129__FUNC_CMFLASH3 (MTK_PIN_NO(129) | 1) +#define PINMUX_GPIO129__FUNC_PWM_1 (MTK_PIN_NO(129) | 2) +#define PINMUX_GPIO129__FUNC_TP_URTS2_AO (MTK_PIN_NO(129) | 3) +#define PINMUX_GPIO129__FUNC_URTS1 (MTK_PIN_NO(129) | 4) +#define PINMUX_GPIO129__FUNC_SDA_6306 (MTK_PIN_NO(129) | 5) +#define PINMUX_GPIO129__FUNC_DBG_MON_A17 (MTK_PIN_NO(129) | 7) + +#define PINMUX_GPIO130__FUNC_GPIO130 (MTK_PIN_NO(130) | 0) +#define PINMUX_GPIO130__FUNC_CMVREF0 (MTK_PIN_NO(130) | 1) +#define PINMUX_GPIO130__FUNC_ANT_SEL10 (MTK_PIN_NO(130) | 2) +#define PINMUX_GPIO130__FUNC_SCP_JTAG0_TDO (MTK_PIN_NO(130) | 3) +#define PINMUX_GPIO130__FUNC_MD32_0_JTAG_TDO (MTK_PIN_NO(130) | 4) +#define PINMUX_GPIO130__FUNC_SCL11 (MTK_PIN_NO(130) | 5) +#define PINMUX_GPIO130__FUNC_SPI5_B_CLK (MTK_PIN_NO(130) | 6) +#define PINMUX_GPIO130__FUNC_DBG_MON_A22 (MTK_PIN_NO(130) | 7) + +#define PINMUX_GPIO131__FUNC_GPIO131 (MTK_PIN_NO(131) | 0) +#define PINMUX_GPIO131__FUNC_CMVREF1 (MTK_PIN_NO(131) | 1) +#define PINMUX_GPIO131__FUNC_ANT_SEL11 (MTK_PIN_NO(131) | 2) +#define PINMUX_GPIO131__FUNC_SCP_JTAG0_TDI (MTK_PIN_NO(131) | 3) +#define PINMUX_GPIO131__FUNC_MD32_0_JTAG_TDI (MTK_PIN_NO(131) | 4) +#define PINMUX_GPIO131__FUNC_SDA11 (MTK_PIN_NO(131) | 5) +#define PINMUX_GPIO131__FUNC_SPI5_B_MO (MTK_PIN_NO(131) | 6) +#define PINMUX_GPIO131__FUNC_DBG_MON_A25 (MTK_PIN_NO(131) | 7) + +#define PINMUX_GPIO132__FUNC_GPIO132 (MTK_PIN_NO(132) | 0) +#define PINMUX_GPIO132__FUNC_CMVREF2 (MTK_PIN_NO(132) | 1) +#define PINMUX_GPIO132__FUNC_ANT_SEL12 (MTK_PIN_NO(132) | 2) +#define PINMUX_GPIO132__FUNC_SCP_JTAG0_TMS (MTK_PIN_NO(132) | 3) +#define PINMUX_GPIO132__FUNC_MD32_0_JTAG_TMS (MTK_PIN_NO(132) | 4) +#define PINMUX_GPIO132__FUNC_DBG_MON_A28 (MTK_PIN_NO(132) | 7) + +#define PINMUX_GPIO133__FUNC_GPIO133 (MTK_PIN_NO(133) | 0) +#define PINMUX_GPIO133__FUNC_CMVREF3 (MTK_PIN_NO(133) | 1) +#define PINMUX_GPIO133__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(133) | 2) +#define PINMUX_GPIO133__FUNC_SCP_JTAG0_TCK (MTK_PIN_NO(133) | 3) +#define PINMUX_GPIO133__FUNC_MD32_0_JTAG_TCK (MTK_PIN_NO(133) | 4) +#define PINMUX_GPIO133__FUNC_SPI5_B_CSB (MTK_PIN_NO(133) | 6) +#define PINMUX_GPIO133__FUNC_DBG_MON_A23 (MTK_PIN_NO(133) | 7) + +#define PINMUX_GPIO134__FUNC_GPIO134 (MTK_PIN_NO(134) | 0) +#define PINMUX_GPIO134__FUNC_CMVREF4 (MTK_PIN_NO(134) | 1) +#define PINMUX_GPIO134__FUNC_SCP_JTAG0_TRSTN (MTK_PIN_NO(134) | 3) +#define PINMUX_GPIO134__FUNC_MD32_0_JTAG_TRST (MTK_PIN_NO(134) | 4) +#define PINMUX_GPIO134__FUNC_DBG_MON_A26 (MTK_PIN_NO(134) | 7) + +#define PINMUX_GPIO135__FUNC_GPIO135 (MTK_PIN_NO(135) | 0) +#define PINMUX_GPIO135__FUNC_PWM_0 (MTK_PIN_NO(135) | 1) +#define PINMUX_GPIO135__FUNC_SRCLKENAI1 (MTK_PIN_NO(135) | 2) +#define PINMUX_GPIO135__FUNC_MD_URXD0 (MTK_PIN_NO(135) | 3) +#define PINMUX_GPIO135__FUNC_MD32_0_RXD (MTK_PIN_NO(135) | 4) +#define PINMUX_GPIO135__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(135) | 5) +#define PINMUX_GPIO135__FUNC_DBG_MON_A29 (MTK_PIN_NO(135) | 7) + +#define PINMUX_GPIO136__FUNC_GPIO136 (MTK_PIN_NO(136) | 0) +#define PINMUX_GPIO136__FUNC_CMMCLK3 (MTK_PIN_NO(136) | 1) +#define PINMUX_GPIO136__FUNC_CLKM1 (MTK_PIN_NO(136) | 2) +#define PINMUX_GPIO136__FUNC_MD_UTXD0 (MTK_PIN_NO(136) | 3) +#define PINMUX_GPIO136__FUNC_MD32_0_TXD (MTK_PIN_NO(136) | 4) +#define PINMUX_GPIO136__FUNC_SPI5_B_MI (MTK_PIN_NO(136) | 6) +#define PINMUX_GPIO136__FUNC_DBG_MON_A24 (MTK_PIN_NO(136) | 7) + +#define PINMUX_GPIO137__FUNC_GPIO137 (MTK_PIN_NO(137) | 0) +#define PINMUX_GPIO137__FUNC_CMMCLK4 (MTK_PIN_NO(137) | 1) +#define PINMUX_GPIO137__FUNC_CLKM2 (MTK_PIN_NO(137) | 2) +#define PINMUX_GPIO137__FUNC_MD_URXD1 (MTK_PIN_NO(137) | 3) +#define PINMUX_GPIO137__FUNC_CONN_UART0_RXD (MTK_PIN_NO(137) | 6) +#define PINMUX_GPIO137__FUNC_DBG_MON_A27 (MTK_PIN_NO(137) | 7) + +#define PINMUX_GPIO138__FUNC_GPIO138 (MTK_PIN_NO(138) | 0) +#define PINMUX_GPIO138__FUNC_CMMCLK5 (MTK_PIN_NO(138) | 1) +#define PINMUX_GPIO138__FUNC_CLKM3 (MTK_PIN_NO(138) | 2) +#define PINMUX_GPIO138__FUNC_MD_UTXD1 (MTK_PIN_NO(138) | 3) +#define PINMUX_GPIO138__FUNC_CONN_UART0_TXD (MTK_PIN_NO(138) | 6) +#define PINMUX_GPIO138__FUNC_DBG_MON_A30 (MTK_PIN_NO(138) | 7) + +#define PINMUX_GPIO139__FUNC_GPIO139 (MTK_PIN_NO(139) | 0) +#define PINMUX_GPIO139__FUNC_SCL4 (MTK_PIN_NO(139) | 1) +#define PINMUX_GPIO139__FUNC_DBG_MON_A21 (MTK_PIN_NO(139) | 7) + +#define PINMUX_GPIO140__FUNC_GPIO140 (MTK_PIN_NO(140) | 0) +#define PINMUX_GPIO140__FUNC_SDA4 (MTK_PIN_NO(140) | 1) +#define PINMUX_GPIO140__FUNC_DBG_MON_A20 (MTK_PIN_NO(140) | 7) + +#define PINMUX_GPIO141__FUNC_GPIO141 (MTK_PIN_NO(141) | 0) +#define PINMUX_GPIO141__FUNC_SCL2 (MTK_PIN_NO(141) | 1) +#define PINMUX_GPIO141__FUNC_DBG_MON_A18 (MTK_PIN_NO(141) | 7) + +#define PINMUX_GPIO142__FUNC_GPIO142 (MTK_PIN_NO(142) | 0) +#define PINMUX_GPIO142__FUNC_SDA2 (MTK_PIN_NO(142) | 1) +#define PINMUX_GPIO142__FUNC_DBG_MON_A19 (MTK_PIN_NO(142) | 7) + +#define PINMUX_GPIO143__FUNC_GPIO143 (MTK_PIN_NO(143) | 0) +#define PINMUX_GPIO143__FUNC_CMVREF0 (MTK_PIN_NO(143) | 1) +#define PINMUX_GPIO143__FUNC_SPI3_CLK (MTK_PIN_NO(143) | 2) +#define PINMUX_GPIO143__FUNC_ADSP_JTAG1_TDO (MTK_PIN_NO(143) | 3) +#define PINMUX_GPIO143__FUNC_SCP_JTAG1_TDO (MTK_PIN_NO(143) | 4) +#define PINMUX_GPIO143__FUNC_DBG_MON_A31 (MTK_PIN_NO(143) | 7) + +#define PINMUX_GPIO144__FUNC_GPIO144 (MTK_PIN_NO(144) | 0) +#define PINMUX_GPIO144__FUNC_CMVREF1 (MTK_PIN_NO(144) | 1) +#define PINMUX_GPIO144__FUNC_SPI3_CSB (MTK_PIN_NO(144) | 2) +#define PINMUX_GPIO144__FUNC_ADSP_JTAG1_TDI (MTK_PIN_NO(144) | 3) +#define PINMUX_GPIO144__FUNC_SCP_JTAG1_TDI (MTK_PIN_NO(144) | 4) + +#define PINMUX_GPIO145__FUNC_GPIO145 (MTK_PIN_NO(145) | 0) +#define PINMUX_GPIO145__FUNC_CMVREF2 (MTK_PIN_NO(145) | 1) +#define PINMUX_GPIO145__FUNC_SPI3_MI (MTK_PIN_NO(145) | 2) +#define PINMUX_GPIO145__FUNC_ADSP_JTAG1_TMS (MTK_PIN_NO(145) | 3) +#define PINMUX_GPIO145__FUNC_SCP_JTAG1_TMS (MTK_PIN_NO(145) | 4) + +#define PINMUX_GPIO146__FUNC_GPIO146 (MTK_PIN_NO(146) | 0) +#define PINMUX_GPIO146__FUNC_CMVREF3 (MTK_PIN_NO(146) | 1) +#define PINMUX_GPIO146__FUNC_SPI3_MO (MTK_PIN_NO(146) | 2) +#define PINMUX_GPIO146__FUNC_ADSP_JTAG1_TCK (MTK_PIN_NO(146) | 3) +#define PINMUX_GPIO146__FUNC_SCP_JTAG1_TCK (MTK_PIN_NO(146) | 4) +#define PINMUX_GPIO146__FUNC_DBG_MON_A32 (MTK_PIN_NO(146) | 7) + +#define PINMUX_GPIO147__FUNC_GPIO147 (MTK_PIN_NO(147) | 0) +#define PINMUX_GPIO147__FUNC_CMVREF4 (MTK_PIN_NO(147) | 1) +#define PINMUX_GPIO147__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(147) | 2) +#define PINMUX_GPIO147__FUNC_ADSP_JTAG1_TRSTN (MTK_PIN_NO(147) | 3) +#define PINMUX_GPIO147__FUNC_SCP_JTAG1_TRSTN (MTK_PIN_NO(147) | 4) + +#define PINMUX_GPIO148__FUNC_GPIO148 (MTK_PIN_NO(148) | 0) +#define PINMUX_GPIO148__FUNC_PWM_1 (MTK_PIN_NO(148) | 1) +#define PINMUX_GPIO148__FUNC_AGPS_SYNC (MTK_PIN_NO(148) | 2) +#define PINMUX_GPIO148__FUNC_CMMCLK5 (MTK_PIN_NO(148) | 3) + +#define PINMUX_GPIO149__FUNC_GPIO149 (MTK_PIN_NO(149) | 0) +#define PINMUX_GPIO149__FUNC_CMMCLK0 (MTK_PIN_NO(149) | 1) +#define PINMUX_GPIO149__FUNC_CLKM0 (MTK_PIN_NO(149) | 2) +#define PINMUX_GPIO149__FUNC_MD32_0_GPIO0 (MTK_PIN_NO(149) | 3) + +#define PINMUX_GPIO150__FUNC_GPIO150 (MTK_PIN_NO(150) | 0) +#define PINMUX_GPIO150__FUNC_CMMCLK1 (MTK_PIN_NO(150) | 1) +#define PINMUX_GPIO150__FUNC_CLKM1 (MTK_PIN_NO(150) | 2) +#define PINMUX_GPIO150__FUNC_MD32_0_GPIO1 (MTK_PIN_NO(150) | 3) +#define PINMUX_GPIO150__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(150) | 7) + +#define PINMUX_GPIO151__FUNC_GPIO151 (MTK_PIN_NO(151) | 0) +#define PINMUX_GPIO151__FUNC_CMMCLK2 (MTK_PIN_NO(151) | 1) +#define PINMUX_GPIO151__FUNC_CLKM2 (MTK_PIN_NO(151) | 2) +#define PINMUX_GPIO151__FUNC_MD32_0_GPIO2 (MTK_PIN_NO(151) | 3) +#define PINMUX_GPIO151__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(151) | 7) + +#define PINMUX_GPIO152__FUNC_GPIO152 (MTK_PIN_NO(152) | 0) +#define PINMUX_GPIO152__FUNC_KPROW1 (MTK_PIN_NO(152) | 1) +#define PINMUX_GPIO152__FUNC_PWM_2 (MTK_PIN_NO(152) | 2) +#define PINMUX_GPIO152__FUNC_IDDIG (MTK_PIN_NO(152) | 3) +#define PINMUX_GPIO152__FUNC_MBISTREADEN_TRIGGER (MTK_PIN_NO(152) | 6) +#define PINMUX_GPIO152__FUNC_DBG_MON_B9 (MTK_PIN_NO(152) | 7) + +#define PINMUX_GPIO153__FUNC_GPIO153 (MTK_PIN_NO(153) | 0) +#define PINMUX_GPIO153__FUNC_KPROW0 (MTK_PIN_NO(153) | 1) +#define PINMUX_GPIO153__FUNC_DBG_MON_B8 (MTK_PIN_NO(153) | 7) + +#define PINMUX_GPIO154__FUNC_GPIO154 (MTK_PIN_NO(154) | 0) +#define PINMUX_GPIO154__FUNC_KPCOL0 (MTK_PIN_NO(154) | 1) +#define PINMUX_GPIO154__FUNC_DBG_MON_B6 (MTK_PIN_NO(154) | 7) + +#define PINMUX_GPIO155__FUNC_GPIO155 (MTK_PIN_NO(155) | 0) +#define PINMUX_GPIO155__FUNC_KPCOL1 (MTK_PIN_NO(155) | 1) +#define PINMUX_GPIO155__FUNC_PWM_3 (MTK_PIN_NO(155) | 2) +#define PINMUX_GPIO155__FUNC_USB_DRVVBUS (MTK_PIN_NO(155) | 3) +#define PINMUX_GPIO155__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(155) | 4) +#define PINMUX_GPIO155__FUNC_MBISTWRITEEN_TRIGGER (MTK_PIN_NO(155) | 6) +#define PINMUX_GPIO155__FUNC_DBG_MON_B7 (MTK_PIN_NO(155) | 7) + +#define PINMUX_GPIO156__FUNC_GPIO156 (MTK_PIN_NO(156) | 0) +#define PINMUX_GPIO156__FUNC_SPI1_A_CLK (MTK_PIN_NO(156) | 1) +#define PINMUX_GPIO156__FUNC_SCP_SPI1_A_CK (MTK_PIN_NO(156) | 2) +#define PINMUX_GPIO156__FUNC_MRG_CLK (MTK_PIN_NO(156) | 3) +#define PINMUX_GPIO156__FUNC_AGPS_SYNC (MTK_PIN_NO(156) | 4) +#define PINMUX_GPIO156__FUNC_MD_URXD0 (MTK_PIN_NO(156) | 5) +#define PINMUX_GPIO156__FUNC_UDI_TMS (MTK_PIN_NO(156) | 6) +#define PINMUX_GPIO156__FUNC_DBG_MON_B10 (MTK_PIN_NO(156) | 7) + +#define PINMUX_GPIO157__FUNC_GPIO157 (MTK_PIN_NO(157) | 0) +#define PINMUX_GPIO157__FUNC_SPI1_A_CSB (MTK_PIN_NO(157) | 1) +#define PINMUX_GPIO157__FUNC_SCP_SPI1_A_CS (MTK_PIN_NO(157) | 2) +#define PINMUX_GPIO157__FUNC_MRG_SYNC (MTK_PIN_NO(157) | 3) +#define PINMUX_GPIO157__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(157) | 4) +#define PINMUX_GPIO157__FUNC_MD_UTXD0 (MTK_PIN_NO(157) | 5) +#define PINMUX_GPIO157__FUNC_UDI_TCK (MTK_PIN_NO(157) | 6) +#define PINMUX_GPIO157__FUNC_DBG_MON_B11 (MTK_PIN_NO(157) | 7) + +#define PINMUX_GPIO158__FUNC_GPIO158 (MTK_PIN_NO(158) | 0) +#define PINMUX_GPIO158__FUNC_SPI1_A_MI (MTK_PIN_NO(158) | 1) +#define PINMUX_GPIO158__FUNC_SCP_SPI1_A_MI (MTK_PIN_NO(158) | 2) +#define PINMUX_GPIO158__FUNC_MRG_DI (MTK_PIN_NO(158) | 3) +#define PINMUX_GPIO158__FUNC_PTA_RXD (MTK_PIN_NO(158) | 4) +#define PINMUX_GPIO158__FUNC_MD_URXD1 (MTK_PIN_NO(158) | 5) +#define PINMUX_GPIO158__FUNC_UDI_TDO (MTK_PIN_NO(158) | 6) +#define PINMUX_GPIO158__FUNC_DBG_MON_B12 (MTK_PIN_NO(158) | 7) + +#define PINMUX_GPIO159__FUNC_GPIO159 (MTK_PIN_NO(159) | 0) +#define PINMUX_GPIO159__FUNC_SPI1_A_MO (MTK_PIN_NO(159) | 1) +#define PINMUX_GPIO159__FUNC_SCP_SPI1_A_MO (MTK_PIN_NO(159) | 2) +#define PINMUX_GPIO159__FUNC_MRG_DO (MTK_PIN_NO(159) | 3) +#define PINMUX_GPIO159__FUNC_PTA_TXD (MTK_PIN_NO(159) | 4) +#define PINMUX_GPIO159__FUNC_MD_UTXD1 (MTK_PIN_NO(159) | 5) +#define PINMUX_GPIO159__FUNC_UDI_NTRST (MTK_PIN_NO(159) | 6) +#define PINMUX_GPIO159__FUNC_DBG_MON_B13 (MTK_PIN_NO(159) | 7) + +#define PINMUX_GPIO160__FUNC_GPIO160 (MTK_PIN_NO(160) | 0) +#define PINMUX_GPIO160__FUNC_SCL3 (MTK_PIN_NO(160) | 1) +#define PINMUX_GPIO160__FUNC_SCP_SCL1 (MTK_PIN_NO(160) | 3) +#define PINMUX_GPIO160__FUNC_DBG_MON_B14 (MTK_PIN_NO(160) | 7) + +#define PINMUX_GPIO161__FUNC_GPIO161 (MTK_PIN_NO(161) | 0) +#define PINMUX_GPIO161__FUNC_SDA3 (MTK_PIN_NO(161) | 1) +#define PINMUX_GPIO161__FUNC_SCP_SDA1 (MTK_PIN_NO(161) | 3) +#define PINMUX_GPIO161__FUNC_DBG_MON_B15 (MTK_PIN_NO(161) | 7) + +#define PINMUX_GPIO162__FUNC_GPIO162 (MTK_PIN_NO(162) | 0) +#define PINMUX_GPIO162__FUNC_ANT_SEL0 (MTK_PIN_NO(162) | 1) +#define PINMUX_GPIO162__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(162) | 2) +#define PINMUX_GPIO162__FUNC_UDI_TDI (MTK_PIN_NO(162) | 6) +#define PINMUX_GPIO162__FUNC_DBG_MON_B16 (MTK_PIN_NO(162) | 7) + +#define PINMUX_GPIO163__FUNC_GPIO163 (MTK_PIN_NO(163) | 0) +#define PINMUX_GPIO163__FUNC_ANT_SEL1 (MTK_PIN_NO(163) | 1) +#define PINMUX_GPIO163__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(163) | 2) +#define PINMUX_GPIO163__FUNC_DBG_MON_B17 (MTK_PIN_NO(163) | 7) + +#define PINMUX_GPIO164__FUNC_GPIO164 (MTK_PIN_NO(164) | 0) +#define PINMUX_GPIO164__FUNC_ANT_SEL2 (MTK_PIN_NO(164) | 1) +#define PINMUX_GPIO164__FUNC_SCP_SPI1_B_CK (MTK_PIN_NO(164) | 2) +#define PINMUX_GPIO164__FUNC_TP_URXD1_AO (MTK_PIN_NO(164) | 3) +#define PINMUX_GPIO164__FUNC_UCTS0 (MTK_PIN_NO(164) | 5) +#define PINMUX_GPIO164__FUNC_DBG_MON_B18 (MTK_PIN_NO(164) | 7) + +#define PINMUX_GPIO165__FUNC_GPIO165 (MTK_PIN_NO(165) | 0) +#define PINMUX_GPIO165__FUNC_ANT_SEL3 (MTK_PIN_NO(165) | 1) +#define PINMUX_GPIO165__FUNC_SCP_SPI1_B_CS (MTK_PIN_NO(165) | 2) +#define PINMUX_GPIO165__FUNC_TP_UTXD1_AO (MTK_PIN_NO(165) | 3) +#define PINMUX_GPIO165__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(165) | 4) +#define PINMUX_GPIO165__FUNC_URTS0 (MTK_PIN_NO(165) | 5) +#define PINMUX_GPIO165__FUNC_DBG_MON_B19 (MTK_PIN_NO(165) | 7) + +#define PINMUX_GPIO166__FUNC_GPIO166 (MTK_PIN_NO(166) | 0) +#define PINMUX_GPIO166__FUNC_ANT_SEL4 (MTK_PIN_NO(166) | 1) +#define PINMUX_GPIO166__FUNC_SCP_SPI1_B_MI (MTK_PIN_NO(166) | 2) +#define PINMUX_GPIO166__FUNC_TP_URXD2_AO (MTK_PIN_NO(166) | 3) +#define PINMUX_GPIO166__FUNC_SRCLKENAI1 (MTK_PIN_NO(166) | 4) +#define PINMUX_GPIO166__FUNC_UCTS1 (MTK_PIN_NO(166) | 5) +#define PINMUX_GPIO166__FUNC_DBG_MON_B20 (MTK_PIN_NO(166) | 7) + +#define PINMUX_GPIO167__FUNC_GPIO167 (MTK_PIN_NO(167) | 0) +#define PINMUX_GPIO167__FUNC_ANT_SEL5 (MTK_PIN_NO(167) | 1) +#define PINMUX_GPIO167__FUNC_SCP_SPI1_B_MO (MTK_PIN_NO(167) | 2) +#define PINMUX_GPIO167__FUNC_TP_UTXD2_AO (MTK_PIN_NO(167) | 3) +#define PINMUX_GPIO167__FUNC_SRCLKENAI0 (MTK_PIN_NO(167) | 4) +#define PINMUX_GPIO167__FUNC_URTS1 (MTK_PIN_NO(167) | 5) +#define PINMUX_GPIO167__FUNC_DBG_MON_B21 (MTK_PIN_NO(167) | 7) + +#define PINMUX_GPIO168__FUNC_GPIO168 (MTK_PIN_NO(168) | 0) +#define PINMUX_GPIO168__FUNC_ANT_SEL6 (MTK_PIN_NO(168) | 1) +#define PINMUX_GPIO168__FUNC_SPI0_B_CLK (MTK_PIN_NO(168) | 2) +#define PINMUX_GPIO168__FUNC_TP_UCTS1_AO (MTK_PIN_NO(168) | 3) +#define PINMUX_GPIO168__FUNC_KPCOL2 (MTK_PIN_NO(168) | 4) +#define PINMUX_GPIO168__FUNC_MD_UCTS0 (MTK_PIN_NO(168) | 5) +#define PINMUX_GPIO168__FUNC_SCL11 (MTK_PIN_NO(168) | 6) +#define PINMUX_GPIO168__FUNC_DBG_MON_B22 (MTK_PIN_NO(168) | 7) + +#define PINMUX_GPIO169__FUNC_GPIO169 (MTK_PIN_NO(169) | 0) +#define PINMUX_GPIO169__FUNC_ANT_SEL7 (MTK_PIN_NO(169) | 1) +#define PINMUX_GPIO169__FUNC_SPI0_B_CSB (MTK_PIN_NO(169) | 2) +#define PINMUX_GPIO169__FUNC_TP_URTS1_AO (MTK_PIN_NO(169) | 3) +#define PINMUX_GPIO169__FUNC_KPROW2 (MTK_PIN_NO(169) | 4) +#define PINMUX_GPIO169__FUNC_MD_URTS0 (MTK_PIN_NO(169) | 5) +#define PINMUX_GPIO169__FUNC_SDA11 (MTK_PIN_NO(169) | 6) +#define PINMUX_GPIO169__FUNC_DBG_MON_B23 (MTK_PIN_NO(169) | 7) + +#define PINMUX_GPIO170__FUNC_GPIO170 (MTK_PIN_NO(170) | 0) +#define PINMUX_GPIO170__FUNC_ANT_SEL8 (MTK_PIN_NO(170) | 1) +#define PINMUX_GPIO170__FUNC_SPI0_B_MI (MTK_PIN_NO(170) | 2) +#define PINMUX_GPIO170__FUNC_TP_UCTS2_AO (MTK_PIN_NO(170) | 3) +#define PINMUX_GPIO170__FUNC_SRCLKENAI1 (MTK_PIN_NO(170) | 4) +#define PINMUX_GPIO170__FUNC_MD_UCTS1 (MTK_PIN_NO(170) | 5) +#define PINMUX_GPIO170__FUNC_DBG_MON_B24 (MTK_PIN_NO(170) | 7) + +#define PINMUX_GPIO171__FUNC_GPIO171 (MTK_PIN_NO(171) | 0) +#define PINMUX_GPIO171__FUNC_ANT_SEL9 (MTK_PIN_NO(171) | 1) +#define PINMUX_GPIO171__FUNC_SPI0_B_MO (MTK_PIN_NO(171) | 2) +#define PINMUX_GPIO171__FUNC_TP_URTS2_AO (MTK_PIN_NO(171) | 3) +#define PINMUX_GPIO171__FUNC_SRCLKENAI0 (MTK_PIN_NO(171) | 4) +#define PINMUX_GPIO171__FUNC_MD_URTS1 (MTK_PIN_NO(171) | 5) +#define PINMUX_GPIO171__FUNC_DBG_MON_B25 (MTK_PIN_NO(171) | 7) + +#define PINMUX_GPIO172__FUNC_GPIO172 (MTK_PIN_NO(172) | 0) +#define PINMUX_GPIO172__FUNC_CONN_TOP_CLK (MTK_PIN_NO(172) | 1) +#define PINMUX_GPIO172__FUNC_AUXIF_CLK0 (MTK_PIN_NO(172) | 2) +#define PINMUX_GPIO172__FUNC_DBG_MON_B29 (MTK_PIN_NO(172) | 7) + +#define PINMUX_GPIO173__FUNC_GPIO173 (MTK_PIN_NO(173) | 0) +#define PINMUX_GPIO173__FUNC_CONN_TOP_DATA (MTK_PIN_NO(173) | 1) +#define PINMUX_GPIO173__FUNC_AUXIF_ST0 (MTK_PIN_NO(173) | 2) +#define PINMUX_GPIO173__FUNC_DBG_MON_B30 (MTK_PIN_NO(173) | 7) + +#define PINMUX_GPIO174__FUNC_GPIO174 (MTK_PIN_NO(174) | 0) +#define PINMUX_GPIO174__FUNC_CONN_HRST_B (MTK_PIN_NO(174) | 1) +#define PINMUX_GPIO174__FUNC_DBG_MON_B28 (MTK_PIN_NO(174) | 7) + +#define PINMUX_GPIO175__FUNC_GPIO175 (MTK_PIN_NO(175) | 0) +#define PINMUX_GPIO175__FUNC_CONN_WB_PTA (MTK_PIN_NO(175) | 1) +#define PINMUX_GPIO175__FUNC_DBG_MON_B31 (MTK_PIN_NO(175) | 7) + +#define PINMUX_GPIO176__FUNC_GPIO176 (MTK_PIN_NO(176) | 0) +#define PINMUX_GPIO176__FUNC_CONN_BT_CLK (MTK_PIN_NO(176) | 1) +#define PINMUX_GPIO176__FUNC_AUXIF_CLK1 (MTK_PIN_NO(176) | 2) +#define PINMUX_GPIO176__FUNC_DBG_MON_B26 (MTK_PIN_NO(176) | 7) + +#define PINMUX_GPIO177__FUNC_GPIO177 (MTK_PIN_NO(177) | 0) +#define PINMUX_GPIO177__FUNC_CONN_BT_DATA (MTK_PIN_NO(177) | 1) +#define PINMUX_GPIO177__FUNC_AUXIF_ST1 (MTK_PIN_NO(177) | 2) +#define PINMUX_GPIO177__FUNC_DBG_MON_B27 (MTK_PIN_NO(177) | 7) + +#define PINMUX_GPIO178__FUNC_GPIO178 (MTK_PIN_NO(178) | 0) +#define PINMUX_GPIO178__FUNC_CONN_WF_CTRL0 (MTK_PIN_NO(178) | 1) + +#define PINMUX_GPIO179__FUNC_GPIO179 (MTK_PIN_NO(179) | 0) +#define PINMUX_GPIO179__FUNC_CONN_WF_CTRL1 (MTK_PIN_NO(179) | 1) +#define PINMUX_GPIO179__FUNC_UFS_MPHY_SCL (MTK_PIN_NO(179) | 2) + +#define PINMUX_GPIO180__FUNC_GPIO180 (MTK_PIN_NO(180) | 0) +#define PINMUX_GPIO180__FUNC_CONN_WF_CTRL2 (MTK_PIN_NO(180) | 1) +#define PINMUX_GPIO180__FUNC_UFS_MPHY_SDA (MTK_PIN_NO(180) | 2) + +#define PINMUX_GPIO181__FUNC_GPIO181 (MTK_PIN_NO(181) | 0) +#define PINMUX_GPIO181__FUNC_CONN_WF_CTRL3 (MTK_PIN_NO(181) | 1) + +#define PINMUX_GPIO182__FUNC_GPIO182 (MTK_PIN_NO(182) | 0) +#define PINMUX_GPIO182__FUNC_CONN_WF_CTRL4 (MTK_PIN_NO(182) | 1) + +#define PINMUX_GPIO183__FUNC_GPIO183 (MTK_PIN_NO(183) | 0) +#define PINMUX_GPIO183__FUNC_MSDC0_CMD (MTK_PIN_NO(183) | 1) + +#define PINMUX_GPIO184__FUNC_GPIO184 (MTK_PIN_NO(184) | 0) +#define PINMUX_GPIO184__FUNC_MSDC0_DAT0 (MTK_PIN_NO(184) | 1) + +#define PINMUX_GPIO185__FUNC_GPIO185 (MTK_PIN_NO(185) | 0) +#define PINMUX_GPIO185__FUNC_MSDC0_DAT2 (MTK_PIN_NO(185) | 1) + +#define PINMUX_GPIO186__FUNC_GPIO186 (MTK_PIN_NO(186) | 0) +#define PINMUX_GPIO186__FUNC_MSDC0_DAT4 (MTK_PIN_NO(186) | 1) + +#define PINMUX_GPIO187__FUNC_GPIO187 (MTK_PIN_NO(187) | 0) +#define PINMUX_GPIO187__FUNC_MSDC0_DAT6 (MTK_PIN_NO(187) | 1) + +#define PINMUX_GPIO188__FUNC_GPIO188 (MTK_PIN_NO(188) | 0) +#define PINMUX_GPIO188__FUNC_MSDC0_DAT1 (MTK_PIN_NO(188) | 1) + +#define PINMUX_GPIO189__FUNC_GPIO189 (MTK_PIN_NO(189) | 0) +#define PINMUX_GPIO189__FUNC_MSDC0_DAT5 (MTK_PIN_NO(189) | 1) + +#define PINMUX_GPIO190__FUNC_GPIO190 (MTK_PIN_NO(190) | 0) +#define PINMUX_GPIO190__FUNC_MSDC0_DAT7 (MTK_PIN_NO(190) | 1) + +#define PINMUX_GPIO191__FUNC_GPIO191 (MTK_PIN_NO(191) | 0) +#define PINMUX_GPIO191__FUNC_MSDC0_DSL (MTK_PIN_NO(191) | 1) +#define PINMUX_GPIO191__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(191) | 2) +#define PINMUX_GPIO191__FUNC_IDDIG (MTK_PIN_NO(191) | 3) +#define PINMUX_GPIO191__FUNC_DMIC_CLK (MTK_PIN_NO(191) | 4) + +#define PINMUX_GPIO192__FUNC_GPIO192 (MTK_PIN_NO(192) | 0) +#define PINMUX_GPIO192__FUNC_MSDC0_CLK (MTK_PIN_NO(192) | 1) +#define PINMUX_GPIO192__FUNC_USB_DRVVBUS (MTK_PIN_NO(192) | 3) +#define PINMUX_GPIO192__FUNC_DMIC_DAT (MTK_PIN_NO(192) | 4) + +#define PINMUX_GPIO193__FUNC_GPIO193 (MTK_PIN_NO(193) | 0) +#define PINMUX_GPIO193__FUNC_MSDC0_DAT3 (MTK_PIN_NO(193) | 1) + +#define PINMUX_GPIO194__FUNC_GPIO194 (MTK_PIN_NO(194) | 0) +#define PINMUX_GPIO194__FUNC_MSDC0_RSTB (MTK_PIN_NO(194) | 1) + +#define PINMUX_GPIO195__FUNC_GPIO195 (MTK_PIN_NO(195) | 0) +#define PINMUX_GPIO195__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(195) | 1) +#define PINMUX_GPIO195__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(195) | 2) + +#define PINMUX_GPIO196__FUNC_GPIO196 (MTK_PIN_NO(196) | 0) +#define PINMUX_GPIO196__FUNC_AUD_DAT_MOSI2 (MTK_PIN_NO(196) | 1) + +#define PINMUX_GPIO197__FUNC_GPIO197 (MTK_PIN_NO(197) | 0) +#define PINMUX_GPIO197__FUNC_AUD_NLE_MOSI1 (MTK_PIN_NO(197) | 1) +#define PINMUX_GPIO197__FUNC_AUD_CLK_MISO (MTK_PIN_NO(197) | 2) +#define PINMUX_GPIO197__FUNC_I2S2_MCK (MTK_PIN_NO(197) | 3) +#define PINMUX_GPIO197__FUNC_I2S6_MCK (MTK_PIN_NO(197) | 4) +#define PINMUX_GPIO197__FUNC_I2S8_MCK (MTK_PIN_NO(197) | 5) + +#define PINMUX_GPIO198__FUNC_GPIO198 (MTK_PIN_NO(198) | 0) +#define PINMUX_GPIO198__FUNC_AUD_NLE_MOSI0 (MTK_PIN_NO(198) | 1) +#define PINMUX_GPIO198__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(198) | 2) +#define PINMUX_GPIO198__FUNC_I2S2_BCK (MTK_PIN_NO(198) | 3) +#define PINMUX_GPIO198__FUNC_I2S6_BCK (MTK_PIN_NO(198) | 4) +#define PINMUX_GPIO198__FUNC_I2S8_BCK (MTK_PIN_NO(198) | 5) + +#define PINMUX_GPIO199__FUNC_GPIO199 (MTK_PIN_NO(199) | 0) +#define PINMUX_GPIO199__FUNC_AUD_DAT_MISO2 (MTK_PIN_NO(199) | 1) +#define PINMUX_GPIO199__FUNC_I2S2_DI2 (MTK_PIN_NO(199) | 3) + +#define PINMUX_GPIO200__FUNC_GPIO200 (MTK_PIN_NO(200) | 0) +#define PINMUX_GPIO200__FUNC_SCL6 (MTK_PIN_NO(200) | 1) +#define PINMUX_GPIO200__FUNC_SCP_SCL1 (MTK_PIN_NO(200) | 3) +#define PINMUX_GPIO200__FUNC_SCL_6306 (MTK_PIN_NO(200) | 4) +#define PINMUX_GPIO200__FUNC_DBG_MON_A4 (MTK_PIN_NO(200) | 7) + +#define PINMUX_GPIO201__FUNC_GPIO201 (MTK_PIN_NO(201) | 0) +#define PINMUX_GPIO201__FUNC_SDA6 (MTK_PIN_NO(201) | 1) +#define PINMUX_GPIO201__FUNC_SCP_SDA1 (MTK_PIN_NO(201) | 3) +#define PINMUX_GPIO201__FUNC_SDA_6306 (MTK_PIN_NO(201) | 4) +#define PINMUX_GPIO201__FUNC_DBG_MON_A5 (MTK_PIN_NO(201) | 7) + +#define PINMUX_GPIO202__FUNC_GPIO202 (MTK_PIN_NO(202) | 0) +#define PINMUX_GPIO202__FUNC_SCL5 (MTK_PIN_NO(202) | 1) + +#define PINMUX_GPIO203__FUNC_GPIO203 (MTK_PIN_NO(203) | 0) +#define PINMUX_GPIO203__FUNC_SDA5 (MTK_PIN_NO(203) | 1) + +#define PINMUX_GPIO204__FUNC_GPIO204 (MTK_PIN_NO(204) | 0) +#define PINMUX_GPIO204__FUNC_SCL0 (MTK_PIN_NO(204) | 1) +#define PINMUX_GPIO204__FUNC_SPI7_A_CLK (MTK_PIN_NO(204) | 6) +#define PINMUX_GPIO204__FUNC_DBG_MON_A2 (MTK_PIN_NO(204) | 7) + +#define PINMUX_GPIO205__FUNC_GPIO205 (MTK_PIN_NO(205) | 0) +#define PINMUX_GPIO205__FUNC_SDA0 (MTK_PIN_NO(205) | 1) +#define PINMUX_GPIO205__FUNC_SPI7_A_CSB (MTK_PIN_NO(205) | 6) +#define PINMUX_GPIO205__FUNC_DBG_MON_A3 (MTK_PIN_NO(205) | 7) + +#define PINMUX_GPIO206__FUNC_GPIO206 (MTK_PIN_NO(206) | 0) +#define PINMUX_GPIO206__FUNC_SRCLKENA0 (MTK_PIN_NO(206) | 1) + +#define PINMUX_GPIO207__FUNC_GPIO207 (MTK_PIN_NO(207) | 0) +#define PINMUX_GPIO207__FUNC_SRCLKENA1 (MTK_PIN_NO(207) | 1) + +#define PINMUX_GPIO208__FUNC_GPIO208 (MTK_PIN_NO(208) | 0) +#define PINMUX_GPIO208__FUNC_WATCHDOG (MTK_PIN_NO(208) | 1) + +#define PINMUX_GPIO209__FUNC_GPIO209 (MTK_PIN_NO(209) | 0) +#define PINMUX_GPIO209__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(209) | 1) +#define PINMUX_GPIO209__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(209) | 2) + +#define PINMUX_GPIO210__FUNC_GPIO210 (MTK_PIN_NO(210) | 0) +#define PINMUX_GPIO210__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(210) | 1) + +#define PINMUX_GPIO211__FUNC_GPIO211 (MTK_PIN_NO(211) | 0) +#define PINMUX_GPIO211__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(211) | 1) +#define PINMUX_GPIO211__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(211) | 2) + +#define PINMUX_GPIO212__FUNC_GPIO212 (MTK_PIN_NO(212) | 0) +#define PINMUX_GPIO212__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(212) | 1) + +#define PINMUX_GPIO213__FUNC_GPIO213 (MTK_PIN_NO(213) | 0) +#define PINMUX_GPIO213__FUNC_RTC32K_CK (MTK_PIN_NO(213) | 1) + +#define PINMUX_GPIO214__FUNC_GPIO214 (MTK_PIN_NO(214) | 0) +#define PINMUX_GPIO214__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(214) | 1) +#define PINMUX_GPIO214__FUNC_I2S1_MCK (MTK_PIN_NO(214) | 3) +#define PINMUX_GPIO214__FUNC_I2S7_MCK (MTK_PIN_NO(214) | 4) +#define PINMUX_GPIO214__FUNC_I2S9_MCK (MTK_PIN_NO(214) | 5) + +#define PINMUX_GPIO215__FUNC_GPIO215 (MTK_PIN_NO(215) | 0) +#define PINMUX_GPIO215__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(215) | 1) +#define PINMUX_GPIO215__FUNC_I2S1_BCK (MTK_PIN_NO(215) | 3) +#define PINMUX_GPIO215__FUNC_I2S7_BCK (MTK_PIN_NO(215) | 4) +#define PINMUX_GPIO215__FUNC_I2S9_BCK (MTK_PIN_NO(215) | 5) + +#define PINMUX_GPIO216__FUNC_GPIO216 (MTK_PIN_NO(216) | 0) +#define PINMUX_GPIO216__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(216) | 1) +#define PINMUX_GPIO216__FUNC_I2S1_LRCK (MTK_PIN_NO(216) | 3) +#define PINMUX_GPIO216__FUNC_I2S7_LRCK (MTK_PIN_NO(216) | 4) +#define PINMUX_GPIO216__FUNC_I2S9_LRCK (MTK_PIN_NO(216) | 5) + +#define PINMUX_GPIO217__FUNC_GPIO217 (MTK_PIN_NO(217) | 0) +#define PINMUX_GPIO217__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(217) | 1) +#define PINMUX_GPIO217__FUNC_I2S1_DO (MTK_PIN_NO(217) | 3) +#define PINMUX_GPIO217__FUNC_I2S7_DO (MTK_PIN_NO(217) | 4) +#define PINMUX_GPIO217__FUNC_I2S9_DO (MTK_PIN_NO(217) | 5) + +#define PINMUX_GPIO218__FUNC_GPIO218 (MTK_PIN_NO(218) | 0) +#define PINMUX_GPIO218__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(218) | 1) +#define PINMUX_GPIO218__FUNC_VOW_DAT_MISO (MTK_PIN_NO(218) | 2) +#define PINMUX_GPIO218__FUNC_I2S2_LRCK (MTK_PIN_NO(218) | 3) +#define PINMUX_GPIO218__FUNC_I2S6_LRCK (MTK_PIN_NO(218) | 4) +#define PINMUX_GPIO218__FUNC_I2S8_LRCK (MTK_PIN_NO(218) | 5) + +#define PINMUX_GPIO219__FUNC_GPIO219 (MTK_PIN_NO(219) | 0) +#define PINMUX_GPIO219__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(219) | 1) +#define PINMUX_GPIO219__FUNC_VOW_CLK_MISO (MTK_PIN_NO(219) | 2) +#define PINMUX_GPIO219__FUNC_I2S2_DI (MTK_PIN_NO(219) | 3) +#define PINMUX_GPIO219__FUNC_I2S6_DI (MTK_PIN_NO(219) | 4) +#define PINMUX_GPIO219__FUNC_I2S8_DI (MTK_PIN_NO(219) | 5) + +#endif /* __MT8192_PINFUNC_H */ diff --git a/include/dt-bindings/pinctrl/mt8195-pinfunc.h b/include/dt-bindings/pinctrl/mt8195-pinfunc.h new file mode 100644 index 000000000000..666331bb9b40 --- /dev/null +++ b/include/dt-bindings/pinctrl/mt8195-pinfunc.h @@ -0,0 +1,962 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 MediaTek Inc. + * Author: Zhiyong Tao <zhiyong.tao@mediatek.com> + */ + +#ifndef __MT8195_PINFUNC_H +#define __MT8195_PINFUNC_H + +#include "mt65xx.h" + +#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define PINMUX_GPIO0__FUNC_TP_GPIO0_AO (MTK_PIN_NO(0) | 1) +#define PINMUX_GPIO0__FUNC_MSDC2_CMD (MTK_PIN_NO(0) | 2) +#define PINMUX_GPIO0__FUNC_TDMIN_MCK (MTK_PIN_NO(0) | 3) +#define PINMUX_GPIO0__FUNC_CLKM0 (MTK_PIN_NO(0) | 4) +#define PINMUX_GPIO0__FUNC_PERSTN_1 (MTK_PIN_NO(0) | 5) +#define PINMUX_GPIO0__FUNC_IDDIG_1P (MTK_PIN_NO(0) | 6) +#define PINMUX_GPIO0__FUNC_DMIC4_CLK (MTK_PIN_NO(0) | 7) + +#define PINMUX_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define PINMUX_GPIO1__FUNC_TP_GPIO1_AO (MTK_PIN_NO(1) | 1) +#define PINMUX_GPIO1__FUNC_MSDC2_CLK (MTK_PIN_NO(1) | 2) +#define PINMUX_GPIO1__FUNC_TDMIN_DI (MTK_PIN_NO(1) | 3) +#define PINMUX_GPIO1__FUNC_CLKM1 (MTK_PIN_NO(1) | 4) +#define PINMUX_GPIO1__FUNC_CLKREQN_1 (MTK_PIN_NO(1) | 5) +#define PINMUX_GPIO1__FUNC_USB_DRVVBUS_1P (MTK_PIN_NO(1) | 6) +#define PINMUX_GPIO1__FUNC_DMIC4_DAT (MTK_PIN_NO(1) | 7) + +#define PINMUX_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define PINMUX_GPIO2__FUNC_TP_GPIO2_AO (MTK_PIN_NO(2) | 1) +#define PINMUX_GPIO2__FUNC_MSDC2_DAT3 (MTK_PIN_NO(2) | 2) +#define PINMUX_GPIO2__FUNC_TDMIN_LRCK (MTK_PIN_NO(2) | 3) +#define PINMUX_GPIO2__FUNC_CLKM2 (MTK_PIN_NO(2) | 4) +#define PINMUX_GPIO2__FUNC_WAKEN_1 (MTK_PIN_NO(2) | 5) +#define PINMUX_GPIO2__FUNC_DMIC2_CLK (MTK_PIN_NO(2) | 7) + +#define PINMUX_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define PINMUX_GPIO3__FUNC_TP_GPIO3_AO (MTK_PIN_NO(3) | 1) +#define PINMUX_GPIO3__FUNC_MSDC2_DAT0 (MTK_PIN_NO(3) | 2) +#define PINMUX_GPIO3__FUNC_TDMIN_BCK (MTK_PIN_NO(3) | 3) +#define PINMUX_GPIO3__FUNC_CLKM3 (MTK_PIN_NO(3) | 4) +#define PINMUX_GPIO3__FUNC_DMIC2_DAT (MTK_PIN_NO(3) | 7) + +#define PINMUX_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define PINMUX_GPIO4__FUNC_TP_GPIO4_AO (MTK_PIN_NO(4) | 1) +#define PINMUX_GPIO4__FUNC_MSDC2_DAT2 (MTK_PIN_NO(4) | 2) +#define PINMUX_GPIO4__FUNC_SPDIF_IN1 (MTK_PIN_NO(4) | 3) +#define PINMUX_GPIO4__FUNC_UTXD3 (MTK_PIN_NO(4) | 4) +#define PINMUX_GPIO4__FUNC_SDA2 (MTK_PIN_NO(4) | 5) +#define PINMUX_GPIO4__FUNC_IDDIG_2P (MTK_PIN_NO(4) | 7) + +#define PINMUX_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define PINMUX_GPIO5__FUNC_TP_GPIO5_AO (MTK_PIN_NO(5) | 1) +#define PINMUX_GPIO5__FUNC_MSDC2_DAT1 (MTK_PIN_NO(5) | 2) +#define PINMUX_GPIO5__FUNC_SPDIF_IN0 (MTK_PIN_NO(5) | 3) +#define PINMUX_GPIO5__FUNC_URXD3 (MTK_PIN_NO(5) | 4) +#define PINMUX_GPIO5__FUNC_SCL2 (MTK_PIN_NO(5) | 5) +#define PINMUX_GPIO5__FUNC_USB_DRVVBUS_2P (MTK_PIN_NO(5) | 7) + +#define PINMUX_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define PINMUX_GPIO6__FUNC_TP_GPIO6_AO (MTK_PIN_NO(6) | 1) +#define PINMUX_GPIO6__FUNC_DP_TX_HPD (MTK_PIN_NO(6) | 2) +#define PINMUX_GPIO6__FUNC_I2SO1_D4 (MTK_PIN_NO(6) | 3) +#define PINMUX_GPIO6__FUNC_UTXD4 (MTK_PIN_NO(6) | 4) +#define PINMUX_GPIO6__FUNC_CMVREF3 (MTK_PIN_NO(6) | 5) +#define PINMUX_GPIO6__FUNC_DMIC3_CLK (MTK_PIN_NO(6) | 7) + +#define PINMUX_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +#define PINMUX_GPIO7__FUNC_TP_GPIO7_AO (MTK_PIN_NO(7) | 1) +#define PINMUX_GPIO7__FUNC_EDP_TX_HPD (MTK_PIN_NO(7) | 2) +#define PINMUX_GPIO7__FUNC_I2SO1_D5 (MTK_PIN_NO(7) | 3) +#define PINMUX_GPIO7__FUNC_URXD4 (MTK_PIN_NO(7) | 4) +#define PINMUX_GPIO7__FUNC_CMVREF4 (MTK_PIN_NO(7) | 5) +#define PINMUX_GPIO7__FUNC_DMIC3_DAT (MTK_PIN_NO(7) | 7) + +#define PINMUX_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +#define PINMUX_GPIO8__FUNC_SDA0 (MTK_PIN_NO(8) | 1) +#define PINMUX_GPIO8__FUNC_PWM_0 (MTK_PIN_NO(8) | 2) +#define PINMUX_GPIO8__FUNC_SPDIF_OUT (MTK_PIN_NO(8) | 4) +#define PINMUX_GPIO8__FUNC_LVTS_FOUT (MTK_PIN_NO(8) | 6) +#define PINMUX_GPIO8__FUNC_DBG_MON_A0 (MTK_PIN_NO(8) | 7) + +#define PINMUX_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +#define PINMUX_GPIO9__FUNC_SCL0 (MTK_PIN_NO(9) | 1) +#define PINMUX_GPIO9__FUNC_PWM_1 (MTK_PIN_NO(9) | 2) +#define PINMUX_GPIO9__FUNC_IR_IN (MTK_PIN_NO(9) | 4) +#define PINMUX_GPIO9__FUNC_LVTS_SDO (MTK_PIN_NO(9) | 6) +#define PINMUX_GPIO9__FUNC_DBG_MON_A1 (MTK_PIN_NO(9) | 7) + +#define PINMUX_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +#define PINMUX_GPIO10__FUNC_SDA1 (MTK_PIN_NO(10) | 1) +#define PINMUX_GPIO10__FUNC_PWM_2 (MTK_PIN_NO(10) | 2) +#define PINMUX_GPIO10__FUNC_ADSP_URXD0 (MTK_PIN_NO(10) | 3) +#define PINMUX_GPIO10__FUNC_SPDIF_IN1 (MTK_PIN_NO(10) | 4) +#define PINMUX_GPIO10__FUNC_LVTS_SCF (MTK_PIN_NO(10) | 6) +#define PINMUX_GPIO10__FUNC_DBG_MON_A2 (MTK_PIN_NO(10) | 7) + +#define PINMUX_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +#define PINMUX_GPIO11__FUNC_SCL1 (MTK_PIN_NO(11) | 1) +#define PINMUX_GPIO11__FUNC_PWM_3 (MTK_PIN_NO(11) | 2) +#define PINMUX_GPIO11__FUNC_ADSP_UTXD0 (MTK_PIN_NO(11) | 3) +#define PINMUX_GPIO11__FUNC_SPDIF_IN0 (MTK_PIN_NO(11) | 4) +#define PINMUX_GPIO11__FUNC_LVTS_SCK (MTK_PIN_NO(11) | 6) +#define PINMUX_GPIO11__FUNC_DBG_MON_A3 (MTK_PIN_NO(11) | 7) + +#define PINMUX_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +#define PINMUX_GPIO12__FUNC_SDA2 (MTK_PIN_NO(12) | 1) +#define PINMUX_GPIO12__FUNC_DMIC3_DAT_R (MTK_PIN_NO(12) | 2) +#define PINMUX_GPIO12__FUNC_I2SO1_D6 (MTK_PIN_NO(12) | 3) +#define PINMUX_GPIO12__FUNC_LVTS_SDI (MTK_PIN_NO(12) | 6) +#define PINMUX_GPIO12__FUNC_DBG_MON_A4 (MTK_PIN_NO(12) | 7) + +#define PINMUX_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) +#define PINMUX_GPIO13__FUNC_SCL2 (MTK_PIN_NO(13) | 1) +#define PINMUX_GPIO13__FUNC_DMIC4_DAT_R (MTK_PIN_NO(13) | 2) +#define PINMUX_GPIO13__FUNC_I2SO1_D7 (MTK_PIN_NO(13) | 3) +#define PINMUX_GPIO13__FUNC_DBG_MON_A5 (MTK_PIN_NO(13) | 7) + +#define PINMUX_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) +#define PINMUX_GPIO14__FUNC_SDA3 (MTK_PIN_NO(14) | 1) +#define PINMUX_GPIO14__FUNC_DMIC3_DAT (MTK_PIN_NO(14) | 2) +#define PINMUX_GPIO14__FUNC_TDMIN_MCK (MTK_PIN_NO(14) | 3) +#define PINMUX_GPIO14__FUNC_DBG_MON_A6 (MTK_PIN_NO(14) | 7) + +#define PINMUX_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) +#define PINMUX_GPIO15__FUNC_SCL3 (MTK_PIN_NO(15) | 1) +#define PINMUX_GPIO15__FUNC_DMIC3_CLK (MTK_PIN_NO(15) | 2) +#define PINMUX_GPIO15__FUNC_TDMIN_DI (MTK_PIN_NO(15) | 3) +#define PINMUX_GPIO15__FUNC_DBG_MON_A7 (MTK_PIN_NO(15) | 7) + +#define PINMUX_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) +#define PINMUX_GPIO16__FUNC_SDA4 (MTK_PIN_NO(16) | 1) +#define PINMUX_GPIO16__FUNC_DMIC4_DAT (MTK_PIN_NO(16) | 2) +#define PINMUX_GPIO16__FUNC_TDMIN_LRCK (MTK_PIN_NO(16) | 3) +#define PINMUX_GPIO16__FUNC_DBG_MON_A8 (MTK_PIN_NO(16) | 7) + +#define PINMUX_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) +#define PINMUX_GPIO17__FUNC_SCL4 (MTK_PIN_NO(17) | 1) +#define PINMUX_GPIO17__FUNC_DMIC4_CLK (MTK_PIN_NO(17) | 2) +#define PINMUX_GPIO17__FUNC_TDMIN_BCK (MTK_PIN_NO(17) | 3) +#define PINMUX_GPIO17__FUNC_DBG_MON_A9 (MTK_PIN_NO(17) | 7) + +#define PINMUX_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) +#define PINMUX_GPIO18__FUNC_DP_TX_HPD (MTK_PIN_NO(18) | 1) + +#define PINMUX_GPIO19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) +#define PINMUX_GPIO19__FUNC_WAKEN (MTK_PIN_NO(19) | 1) +#define PINMUX_GPIO19__FUNC_SCP_SDA1 (MTK_PIN_NO(19) | 2) +#define PINMUX_GPIO19__FUNC_MD32_0_JTAG_TCK (MTK_PIN_NO(19) | 3) +#define PINMUX_GPIO19__FUNC_ADSP_JTAG0_TCK (MTK_PIN_NO(19) | 4) +#define PINMUX_GPIO19__FUNC_SDA6 (MTK_PIN_NO(19) | 5) + +#define PINMUX_GPIO20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) +#define PINMUX_GPIO20__FUNC_PERSTN (MTK_PIN_NO(20) | 1) +#define PINMUX_GPIO20__FUNC_SCP_SCL1 (MTK_PIN_NO(20) | 2) +#define PINMUX_GPIO20__FUNC_MD32_0_JTAG_TMS (MTK_PIN_NO(20) | 3) +#define PINMUX_GPIO20__FUNC_ADSP_JTAG0_TMS (MTK_PIN_NO(20) | 4) +#define PINMUX_GPIO20__FUNC_SCL6 (MTK_PIN_NO(20) | 5) + +#define PINMUX_GPIO21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) +#define PINMUX_GPIO21__FUNC_CLKREQN (MTK_PIN_NO(21) | 1) +#define PINMUX_GPIO21__FUNC_MD32_0_JTAG_TDI (MTK_PIN_NO(21) | 3) +#define PINMUX_GPIO21__FUNC_ADSP_JTAG0_TDI (MTK_PIN_NO(21) | 4) +#define PINMUX_GPIO21__FUNC_SCP_SDA1 (MTK_PIN_NO(21) | 5) + +#define PINMUX_GPIO22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) +#define PINMUX_GPIO22__FUNC_CMMCLK0 (MTK_PIN_NO(22) | 1) +#define PINMUX_GPIO22__FUNC_PERSTN_1 (MTK_PIN_NO(22) | 2) +#define PINMUX_GPIO22__FUNC_SCP_SCL1 (MTK_PIN_NO(22) | 5) +#define PINMUX_GPIO22__FUNC_MD32_0_GPIO0 (MTK_PIN_NO(22) | 7) + +#define PINMUX_GPIO23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) +#define PINMUX_GPIO23__FUNC_CMMCLK1 (MTK_PIN_NO(23) | 1) +#define PINMUX_GPIO23__FUNC_CLKREQN_1 (MTK_PIN_NO(23) | 2) +#define PINMUX_GPIO23__FUNC_SDA4 (MTK_PIN_NO(23) | 3) +#define PINMUX_GPIO23__FUNC_DMIC1_CLK (MTK_PIN_NO(23) | 4) +#define PINMUX_GPIO23__FUNC_SCP_SDA0 (MTK_PIN_NO(23) | 5) +#define PINMUX_GPIO23__FUNC_MD32_0_GPIO1 (MTK_PIN_NO(23) | 7) + +#define PINMUX_GPIO24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) +#define PINMUX_GPIO24__FUNC_CMMCLK2 (MTK_PIN_NO(24) | 1) +#define PINMUX_GPIO24__FUNC_WAKEN_1 (MTK_PIN_NO(24) | 2) +#define PINMUX_GPIO24__FUNC_SCL4 (MTK_PIN_NO(24) | 3) +#define PINMUX_GPIO24__FUNC_DMIC1_DAT (MTK_PIN_NO(24) | 4) +#define PINMUX_GPIO24__FUNC_SCP_SCL0 (MTK_PIN_NO(24) | 5) +#define PINMUX_GPIO24__FUNC_LVTS_26M (MTK_PIN_NO(24) | 6) +#define PINMUX_GPIO24__FUNC_MD32_0_GPIO2 (MTK_PIN_NO(24) | 7) + +#define PINMUX_GPIO25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) +#define PINMUX_GPIO25__FUNC_CMMRST (MTK_PIN_NO(25) | 1) +#define PINMUX_GPIO25__FUNC_CMMCLK3 (MTK_PIN_NO(25) | 2) +#define PINMUX_GPIO25__FUNC_SPDIF_OUT (MTK_PIN_NO(25) | 3) +#define PINMUX_GPIO25__FUNC_SDA6 (MTK_PIN_NO(25) | 4) +#define PINMUX_GPIO25__FUNC_ADSP_JTAG0_TRSTN (MTK_PIN_NO(25) | 5) +#define PINMUX_GPIO25__FUNC_MD32_0_JTAG_TRST (MTK_PIN_NO(25) | 6) + +#define PINMUX_GPIO26__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) +#define PINMUX_GPIO26__FUNC_CMMPDN (MTK_PIN_NO(26) | 1) +#define PINMUX_GPIO26__FUNC_CMMCLK4 (MTK_PIN_NO(26) | 2) +#define PINMUX_GPIO26__FUNC_IR_IN (MTK_PIN_NO(26) | 3) +#define PINMUX_GPIO26__FUNC_SCL6 (MTK_PIN_NO(26) | 4) +#define PINMUX_GPIO26__FUNC_ADSP_JTAG0_TDO (MTK_PIN_NO(26) | 5) +#define PINMUX_GPIO26__FUNC_MD32_0_JTAG_TDO (MTK_PIN_NO(26) | 6) + +#define PINMUX_GPIO27__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) +#define PINMUX_GPIO27__FUNC_HDMIRX20_HTPLG (MTK_PIN_NO(27) | 1) +#define PINMUX_GPIO27__FUNC_CMFLASH0 (MTK_PIN_NO(27) | 2) +#define PINMUX_GPIO27__FUNC_MD32_0_TXD (MTK_PIN_NO(27) | 3) +#define PINMUX_GPIO27__FUNC_TP_UTXD2_AO (MTK_PIN_NO(27) | 4) +#define PINMUX_GPIO27__FUNC_SCL7 (MTK_PIN_NO(27) | 5) +#define PINMUX_GPIO27__FUNC_UCTS2 (MTK_PIN_NO(27) | 6) +#define PINMUX_GPIO27__FUNC_DBG_MON_A18 (MTK_PIN_NO(27) | 7) + +#define PINMUX_GPIO28__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) +#define PINMUX_GPIO28__FUNC_HDMIRX20_PWR5V (MTK_PIN_NO(28) | 1) +#define PINMUX_GPIO28__FUNC_CMFLASH1 (MTK_PIN_NO(28) | 2) +#define PINMUX_GPIO28__FUNC_MD32_0_RXD (MTK_PIN_NO(28) | 3) +#define PINMUX_GPIO28__FUNC_TP_URXD2_AO (MTK_PIN_NO(28) | 4) +#define PINMUX_GPIO28__FUNC_SDA7 (MTK_PIN_NO(28) | 5) +#define PINMUX_GPIO28__FUNC_URTS2 (MTK_PIN_NO(28) | 6) +#define PINMUX_GPIO28__FUNC_DBG_MON_A19 (MTK_PIN_NO(28) | 7) + +#define PINMUX_GPIO29__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) +#define PINMUX_GPIO29__FUNC_HDMIRX20_SCL (MTK_PIN_NO(29) | 1) +#define PINMUX_GPIO29__FUNC_CMFLASH2 (MTK_PIN_NO(29) | 2) +#define PINMUX_GPIO29__FUNC_SCL5 (MTK_PIN_NO(29) | 3) +#define PINMUX_GPIO29__FUNC_TP_URTS2_AO (MTK_PIN_NO(29) | 4) +#define PINMUX_GPIO29__FUNC_UTXD2 (MTK_PIN_NO(29) | 6) +#define PINMUX_GPIO29__FUNC_DBG_MON_A20 (MTK_PIN_NO(29) | 7) + +#define PINMUX_GPIO30__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) +#define PINMUX_GPIO30__FUNC_HDMIRX20_SDA (MTK_PIN_NO(30) | 1) +#define PINMUX_GPIO30__FUNC_CMFLASH3 (MTK_PIN_NO(30) | 2) +#define PINMUX_GPIO30__FUNC_SDA5 (MTK_PIN_NO(30) | 3) +#define PINMUX_GPIO30__FUNC_TP_UCTS2_AO (MTK_PIN_NO(30) | 4) +#define PINMUX_GPIO30__FUNC_URXD2 (MTK_PIN_NO(30) | 6) +#define PINMUX_GPIO30__FUNC_DBG_MON_A21 (MTK_PIN_NO(30) | 7) + +#define PINMUX_GPIO31__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) +#define PINMUX_GPIO31__FUNC_HDMITX20_PWR5V (MTK_PIN_NO(31) | 1) +#define PINMUX_GPIO31__FUNC_DMIC1_DAT_R (MTK_PIN_NO(31) | 2) +#define PINMUX_GPIO31__FUNC_PERSTN (MTK_PIN_NO(31) | 3) +#define PINMUX_GPIO31__FUNC_DBG_MON_A22 (MTK_PIN_NO(31) | 7) + +#define PINMUX_GPIO32__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) +#define PINMUX_GPIO32__FUNC_HDMITX20_HTPLG (MTK_PIN_NO(32) | 1) +#define PINMUX_GPIO32__FUNC_CLKREQN (MTK_PIN_NO(32) | 3) +#define PINMUX_GPIO32__FUNC_DBG_MON_A23 (MTK_PIN_NO(32) | 7) + +#define PINMUX_GPIO33__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) +#define PINMUX_GPIO33__FUNC_HDMITX20_CEC (MTK_PIN_NO(33) | 1) +#define PINMUX_GPIO33__FUNC_CMVREF0 (MTK_PIN_NO(33) | 2) +#define PINMUX_GPIO33__FUNC_WAKEN (MTK_PIN_NO(33) | 3) + +#define PINMUX_GPIO34__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) +#define PINMUX_GPIO34__FUNC_HDMITX20_SCL (MTK_PIN_NO(34) | 1) +#define PINMUX_GPIO34__FUNC_CMVREF1 (MTK_PIN_NO(34) | 2) +#define PINMUX_GPIO34__FUNC_SCL7 (MTK_PIN_NO(34) | 3) +#define PINMUX_GPIO34__FUNC_SCL6 (MTK_PIN_NO(34) | 4) +#define PINMUX_GPIO34__FUNC_DBG_MON_A24 (MTK_PIN_NO(34) | 7) + +#define PINMUX_GPIO35__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) +#define PINMUX_GPIO35__FUNC_HDMITX20_SDA (MTK_PIN_NO(35) | 1) +#define PINMUX_GPIO35__FUNC_CMVREF2 (MTK_PIN_NO(35) | 2) +#define PINMUX_GPIO35__FUNC_SDA7 (MTK_PIN_NO(35) | 3) +#define PINMUX_GPIO35__FUNC_SDA6 (MTK_PIN_NO(35) | 4) +#define PINMUX_GPIO35__FUNC_DBG_MON_A25 (MTK_PIN_NO(35) | 7) + +#define PINMUX_GPIO36__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) +#define PINMUX_GPIO36__FUNC_RTC32K_CK (MTK_PIN_NO(36) | 1) +#define PINMUX_GPIO36__FUNC_DBG_MON_A27 (MTK_PIN_NO(36) | 7) + +#define PINMUX_GPIO37__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) +#define PINMUX_GPIO37__FUNC_WATCHDOG (MTK_PIN_NO(37) | 1) +#define PINMUX_GPIO37__FUNC_DBG_MON_A28 (MTK_PIN_NO(37) | 7) + +#define PINMUX_GPIO38__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) +#define PINMUX_GPIO38__FUNC_SRCLKENA0 (MTK_PIN_NO(38) | 1) +#define PINMUX_GPIO38__FUNC_DBG_MON_A29 (MTK_PIN_NO(38) | 7) + +#define PINMUX_GPIO39__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) +#define PINMUX_GPIO39__FUNC_SRCLKENA1 (MTK_PIN_NO(39) | 1) +#define PINMUX_GPIO39__FUNC_DMIC2_DAT_R (MTK_PIN_NO(39) | 2) +#define PINMUX_GPIO39__FUNC_DBG_MON_A30 (MTK_PIN_NO(39) | 7) + +#define PINMUX_GPIO40__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) +#define PINMUX_GPIO40__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(40) | 1) +#define PINMUX_GPIO40__FUNC_SPIM3_CSB (MTK_PIN_NO(40) | 3) +#define PINMUX_GPIO40__FUNC_DBG_MON_A31 (MTK_PIN_NO(40) | 7) + +#define PINMUX_GPIO41__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) +#define PINMUX_GPIO41__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(41) | 1) +#define PINMUX_GPIO41__FUNC_SPIM3_CLK (MTK_PIN_NO(41) | 3) +#define PINMUX_GPIO41__FUNC_DBG_MON_A32 (MTK_PIN_NO(41) | 7) + +#define PINMUX_GPIO42__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) +#define PINMUX_GPIO42__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(42) | 1) +#define PINMUX_GPIO42__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(42) | 2) +#define PINMUX_GPIO42__FUNC_SPIM3_MO (MTK_PIN_NO(42) | 3) +#define PINMUX_GPIO42__FUNC_DBG_MON_B0 (MTK_PIN_NO(42) | 7) + +#define PINMUX_GPIO43__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) +#define PINMUX_GPIO43__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(43) | 1) +#define PINMUX_GPIO43__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(43) | 2) +#define PINMUX_GPIO43__FUNC_SPIM3_MI (MTK_PIN_NO(43) | 3) +#define PINMUX_GPIO43__FUNC_DBG_MON_B1 (MTK_PIN_NO(43) | 7) + +#define PINMUX_GPIO44__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) +#define PINMUX_GPIO44__FUNC_SPMI_M_SCL (MTK_PIN_NO(44) | 1) +#define PINMUX_GPIO44__FUNC_I2SI00_DATA1 (MTK_PIN_NO(44) | 2) +#define PINMUX_GPIO44__FUNC_SCL5 (MTK_PIN_NO(44) | 3) +#define PINMUX_GPIO44__FUNC_UTXD5 (MTK_PIN_NO(44) | 4) +#define PINMUX_GPIO44__FUNC_DBG_MON_B2 (MTK_PIN_NO(44) | 7) + +#define PINMUX_GPIO45__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) +#define PINMUX_GPIO45__FUNC_SPMI_M_SDA (MTK_PIN_NO(45) | 1) +#define PINMUX_GPIO45__FUNC_I2SI00_DATA2 (MTK_PIN_NO(45) | 2) +#define PINMUX_GPIO45__FUNC_SDA5 (MTK_PIN_NO(45) | 3) +#define PINMUX_GPIO45__FUNC_URXD5 (MTK_PIN_NO(45) | 4) +#define PINMUX_GPIO45__FUNC_DBG_MON_B3 (MTK_PIN_NO(45) | 7) + +#define PINMUX_GPIO46__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) +#define PINMUX_GPIO46__FUNC_I2SIN_MCK (MTK_PIN_NO(46) | 1) +#define PINMUX_GPIO46__FUNC_I2SI00_DATA3 (MTK_PIN_NO(46) | 2) +#define PINMUX_GPIO46__FUNC_SPLIN_MCK (MTK_PIN_NO(46) | 3) +#define PINMUX_GPIO46__FUNC_DBG_MON_B4 (MTK_PIN_NO(46) | 7) + +#define PINMUX_GPIO47__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) +#define PINMUX_GPIO47__FUNC_I2SIN_BCK (MTK_PIN_NO(47) | 1) +#define PINMUX_GPIO47__FUNC_I2SIN0_BCK (MTK_PIN_NO(47) | 2) +#define PINMUX_GPIO47__FUNC_SPLIN_LRCK (MTK_PIN_NO(47) | 3) +#define PINMUX_GPIO47__FUNC_DBG_MON_B5 (MTK_PIN_NO(47) | 7) + +#define PINMUX_GPIO48__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) +#define PINMUX_GPIO48__FUNC_I2SIN_WS (MTK_PIN_NO(48) | 1) +#define PINMUX_GPIO48__FUNC_I2SIN0_LRCK (MTK_PIN_NO(48) | 2) +#define PINMUX_GPIO48__FUNC_SPLIN_BCK (MTK_PIN_NO(48) | 3) +#define PINMUX_GPIO48__FUNC_DBG_MON_B6 (MTK_PIN_NO(48) | 7) + +#define PINMUX_GPIO49__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) +#define PINMUX_GPIO49__FUNC_I2SIN_D0 (MTK_PIN_NO(49) | 1) +#define PINMUX_GPIO49__FUNC_I2SI00_DATA0 (MTK_PIN_NO(49) | 2) +#define PINMUX_GPIO49__FUNC_SPLIN_D0 (MTK_PIN_NO(49) | 3) +#define PINMUX_GPIO49__FUNC_DBG_MON_B7 (MTK_PIN_NO(49) | 7) + +#define PINMUX_GPIO50__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) +#define PINMUX_GPIO50__FUNC_I2SO1_MCK (MTK_PIN_NO(50) | 1) +#define PINMUX_GPIO50__FUNC_I2SI5_D0 (MTK_PIN_NO(50) | 2) +#define PINMUX_GPIO50__FUNC_I2SO4_MCK (MTK_PIN_NO(50) | 4) +#define PINMUX_GPIO50__FUNC_DBG_MON_B8 (MTK_PIN_NO(50) | 7) + +#define PINMUX_GPIO51__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) +#define PINMUX_GPIO51__FUNC_I2SO1_BCK (MTK_PIN_NO(51) | 1) +#define PINMUX_GPIO51__FUNC_I2SI5_BCK (MTK_PIN_NO(51) | 2) +#define PINMUX_GPIO51__FUNC_DBG_MON_B9 (MTK_PIN_NO(51) | 7) + +#define PINMUX_GPIO52__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) +#define PINMUX_GPIO52__FUNC_I2SO1_WS (MTK_PIN_NO(52) | 1) +#define PINMUX_GPIO52__FUNC_I2SI5_WS (MTK_PIN_NO(52) | 2) +#define PINMUX_GPIO52__FUNC_DBG_MON_B10 (MTK_PIN_NO(52) | 7) + +#define PINMUX_GPIO53__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) +#define PINMUX_GPIO53__FUNC_I2SO1_D0 (MTK_PIN_NO(53) | 1) +#define PINMUX_GPIO53__FUNC_I2SI5_MCK (MTK_PIN_NO(53) | 2) +#define PINMUX_GPIO53__FUNC_DBG_MON_B11 (MTK_PIN_NO(53) | 7) + +#define PINMUX_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) +#define PINMUX_GPIO54__FUNC_I2SO1_D1 (MTK_PIN_NO(54) | 1) +#define PINMUX_GPIO54__FUNC_I2SI01_DATA1 (MTK_PIN_NO(54) | 2) +#define PINMUX_GPIO54__FUNC_SPLIN_D1 (MTK_PIN_NO(54) | 3) +#define PINMUX_GPIO54__FUNC_I2SO4_BCK (MTK_PIN_NO(54) | 4) +#define PINMUX_GPIO54__FUNC_DBG_MON_B12 (MTK_PIN_NO(54) | 7) + +#define PINMUX_GPIO55__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) +#define PINMUX_GPIO55__FUNC_I2SO1_D2 (MTK_PIN_NO(55) | 1) +#define PINMUX_GPIO55__FUNC_I2SI01_DATA2 (MTK_PIN_NO(55) | 2) +#define PINMUX_GPIO55__FUNC_SPLIN_D2 (MTK_PIN_NO(55) | 3) +#define PINMUX_GPIO55__FUNC_I2SO4_WS (MTK_PIN_NO(55) | 4) +#define PINMUX_GPIO55__FUNC_DBG_MON_B13 (MTK_PIN_NO(55) | 7) + +#define PINMUX_GPIO56__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) +#define PINMUX_GPIO56__FUNC_I2SO1_D3 (MTK_PIN_NO(56) | 1) +#define PINMUX_GPIO56__FUNC_I2SI01_DATA3 (MTK_PIN_NO(56) | 2) +#define PINMUX_GPIO56__FUNC_SPLIN_D3 (MTK_PIN_NO(56) | 3) +#define PINMUX_GPIO56__FUNC_I2SO4_D0 (MTK_PIN_NO(56) | 4) +#define PINMUX_GPIO56__FUNC_DBG_MON_B14 (MTK_PIN_NO(56) | 7) + +#define PINMUX_GPIO57__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) +#define PINMUX_GPIO57__FUNC_I2SO2_MCK (MTK_PIN_NO(57) | 1) +#define PINMUX_GPIO57__FUNC_I2SO1_D12 (MTK_PIN_NO(57) | 2) +#define PINMUX_GPIO57__FUNC_LCM1_RST (MTK_PIN_NO(57) | 3) +#define PINMUX_GPIO57__FUNC_DBG_MON_B15 (MTK_PIN_NO(57) | 7) + +#define PINMUX_GPIO58__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) +#define PINMUX_GPIO58__FUNC_I2SO2_BCK (MTK_PIN_NO(58) | 1) +#define PINMUX_GPIO58__FUNC_I2SO1_D13 (MTK_PIN_NO(58) | 2) +#define PINMUX_GPIO58__FUNC_I2SIN1_BCK (MTK_PIN_NO(58) | 3) +#define PINMUX_GPIO58__FUNC_DBG_MON_B16 (MTK_PIN_NO(58) | 7) + +#define PINMUX_GPIO59__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) +#define PINMUX_GPIO59__FUNC_I2SO2_WS (MTK_PIN_NO(59) | 1) +#define PINMUX_GPIO59__FUNC_I2SO1_D14 (MTK_PIN_NO(59) | 2) +#define PINMUX_GPIO59__FUNC_I2SIN1_LRCK (MTK_PIN_NO(59) | 3) +#define PINMUX_GPIO59__FUNC_DBG_MON_B17 (MTK_PIN_NO(59) | 7) + +#define PINMUX_GPIO60__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) +#define PINMUX_GPIO60__FUNC_I2SO2_D0 (MTK_PIN_NO(60) | 1) +#define PINMUX_GPIO60__FUNC_I2SO1_D15 (MTK_PIN_NO(60) | 2) +#define PINMUX_GPIO60__FUNC_I2SI01_DATA0 (MTK_PIN_NO(60) | 3) +#define PINMUX_GPIO60__FUNC_DBG_MON_B18 (MTK_PIN_NO(60) | 7) + +#define PINMUX_GPIO61__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) +#define PINMUX_GPIO61__FUNC_DMIC1_CLK (MTK_PIN_NO(61) | 1) +#define PINMUX_GPIO61__FUNC_I2SO2_BCK (MTK_PIN_NO(61) | 2) +#define PINMUX_GPIO61__FUNC_SCP_SPI2_CK (MTK_PIN_NO(61) | 3) +#define PINMUX_GPIO61__FUNC_DBG_MON_B19 (MTK_PIN_NO(61) | 7) + +#define PINMUX_GPIO62__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) +#define PINMUX_GPIO62__FUNC_DMIC1_DAT (MTK_PIN_NO(62) | 1) +#define PINMUX_GPIO62__FUNC_I2SO2_WS (MTK_PIN_NO(62) | 2) +#define PINMUX_GPIO62__FUNC_SCP_SPI2_MI (MTK_PIN_NO(62) | 3) +#define PINMUX_GPIO62__FUNC_DBG_MON_B20 (MTK_PIN_NO(62) | 7) + +#define PINMUX_GPIO63__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) +#define PINMUX_GPIO63__FUNC_DMIC2_CLK (MTK_PIN_NO(63) | 1) +#define PINMUX_GPIO63__FUNC_VBUSVALID (MTK_PIN_NO(63) | 2) +#define PINMUX_GPIO63__FUNC_SCP_SPI2_MO (MTK_PIN_NO(63) | 3) +#define PINMUX_GPIO63__FUNC_SCP_SCL2 (MTK_PIN_NO(63) | 4) +#define PINMUX_GPIO63__FUNC_SCP_JTAG1_TDO (MTK_PIN_NO(63) | 5) +#define PINMUX_GPIO63__FUNC_JTDO_SEL1 (MTK_PIN_NO(63) | 6) +#define PINMUX_GPIO63__FUNC_DBG_MON_B21 (MTK_PIN_NO(63) | 7) + +#define PINMUX_GPIO64__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) +#define PINMUX_GPIO64__FUNC_DMIC2_DAT (MTK_PIN_NO(64) | 1) +#define PINMUX_GPIO64__FUNC_VBUSVALID_1P (MTK_PIN_NO(64) | 2) +#define PINMUX_GPIO64__FUNC_SCP_SPI2_CS (MTK_PIN_NO(64) | 3) +#define PINMUX_GPIO64__FUNC_SCP_SDA2 (MTK_PIN_NO(64) | 4) +#define PINMUX_GPIO64__FUNC_DBG_MON_B22 (MTK_PIN_NO(64) | 7) + +#define PINMUX_GPIO65__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) +#define PINMUX_GPIO65__FUNC_PCM_DO (MTK_PIN_NO(65) | 1) +#define PINMUX_GPIO65__FUNC_AUXIF_ST0 (MTK_PIN_NO(65) | 2) +#define PINMUX_GPIO65__FUNC_UCTS2 (MTK_PIN_NO(65) | 3) +#define PINMUX_GPIO65__FUNC_SCP_JTAG1_TMS (MTK_PIN_NO(65) | 5) +#define PINMUX_GPIO65__FUNC_JTMS_SEL1 (MTK_PIN_NO(65) | 6) +#define PINMUX_GPIO65__FUNC_DBG_MON_B23 (MTK_PIN_NO(65) | 7) + +#define PINMUX_GPIO66__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) +#define PINMUX_GPIO66__FUNC_PCM_CLK (MTK_PIN_NO(66) | 1) +#define PINMUX_GPIO66__FUNC_AUXIF_CLK0 (MTK_PIN_NO(66) | 2) +#define PINMUX_GPIO66__FUNC_URTS2 (MTK_PIN_NO(66) | 3) +#define PINMUX_GPIO66__FUNC_SCP_JTAG1_TCK (MTK_PIN_NO(66) | 5) +#define PINMUX_GPIO66__FUNC_JTCK_SEL1 (MTK_PIN_NO(66) | 6) +#define PINMUX_GPIO66__FUNC_DBG_MON_B24 (MTK_PIN_NO(66) | 7) + +#define PINMUX_GPIO67__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) +#define PINMUX_GPIO67__FUNC_PCM_DI (MTK_PIN_NO(67) | 1) +#define PINMUX_GPIO67__FUNC_AUXIF_ST1 (MTK_PIN_NO(67) | 2) +#define PINMUX_GPIO67__FUNC_UTXD2 (MTK_PIN_NO(67) | 3) +#define PINMUX_GPIO67__FUNC_SCP_JTAG1_TRSTN (MTK_PIN_NO(67) | 5) +#define PINMUX_GPIO67__FUNC_JTRSTn_SEL1 (MTK_PIN_NO(67) | 6) +#define PINMUX_GPIO67__FUNC_DBG_MON_B25 (MTK_PIN_NO(67) | 7) + +#define PINMUX_GPIO68__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) +#define PINMUX_GPIO68__FUNC_PCM_SYNC (MTK_PIN_NO(68) | 1) +#define PINMUX_GPIO68__FUNC_AUXIF_CLK1 (MTK_PIN_NO(68) | 2) +#define PINMUX_GPIO68__FUNC_URXD2 (MTK_PIN_NO(68) | 3) +#define PINMUX_GPIO68__FUNC_SCP_JTAG1_TDI (MTK_PIN_NO(68) | 5) +#define PINMUX_GPIO68__FUNC_JTDI_SEL1 (MTK_PIN_NO(68) | 6) +#define PINMUX_GPIO68__FUNC_DBG_MON_B26 (MTK_PIN_NO(68) | 7) + +#define PINMUX_GPIO69__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) +#define PINMUX_GPIO69__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(69) | 1) +#define PINMUX_GPIO69__FUNC_I2SIN2_BCK (MTK_PIN_NO(69) | 2) +#define PINMUX_GPIO69__FUNC_PWM_0 (MTK_PIN_NO(69) | 3) +#define PINMUX_GPIO69__FUNC_WAKEN (MTK_PIN_NO(69) | 4) +#define PINMUX_GPIO69__FUNC_DBG_MON_B27 (MTK_PIN_NO(69) | 7) + +#define PINMUX_GPIO70__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) +#define PINMUX_GPIO70__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(70) | 1) +#define PINMUX_GPIO70__FUNC_I2SIN2_LRCK (MTK_PIN_NO(70) | 2) +#define PINMUX_GPIO70__FUNC_PWM_1 (MTK_PIN_NO(70) | 3) +#define PINMUX_GPIO70__FUNC_PERSTN (MTK_PIN_NO(70) | 4) +#define PINMUX_GPIO70__FUNC_DBG_MON_B28 (MTK_PIN_NO(70) | 7) + +#define PINMUX_GPIO71__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) +#define PINMUX_GPIO71__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(71) | 1) +#define PINMUX_GPIO71__FUNC_IDDIG_2P (MTK_PIN_NO(71) | 2) +#define PINMUX_GPIO71__FUNC_PWM_2 (MTK_PIN_NO(71) | 3) +#define PINMUX_GPIO71__FUNC_CLKREQN (MTK_PIN_NO(71) | 4) +#define PINMUX_GPIO71__FUNC_DBG_MON_B29 (MTK_PIN_NO(71) | 7) + +#define PINMUX_GPIO72__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) +#define PINMUX_GPIO72__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(72) | 1) +#define PINMUX_GPIO72__FUNC_USB_DRVVBUS_2P (MTK_PIN_NO(72) | 2) +#define PINMUX_GPIO72__FUNC_PWM_3 (MTK_PIN_NO(72) | 3) +#define PINMUX_GPIO72__FUNC_PERSTN_1 (MTK_PIN_NO(72) | 4) +#define PINMUX_GPIO72__FUNC_DBG_MON_B30 (MTK_PIN_NO(72) | 7) + +#define PINMUX_GPIO73__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) +#define PINMUX_GPIO73__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(73) | 1) +#define PINMUX_GPIO73__FUNC_I2SI02_DATA0 (MTK_PIN_NO(73) | 2) +#define PINMUX_GPIO73__FUNC_CLKREQN_1 (MTK_PIN_NO(73) | 4) +#define PINMUX_GPIO73__FUNC_VOW_DAT_MISO (MTK_PIN_NO(73) | 5) +#define PINMUX_GPIO73__FUNC_DBG_MON_B31 (MTK_PIN_NO(73) | 7) + +#define PINMUX_GPIO74__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) +#define PINMUX_GPIO74__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(74) | 1) +#define PINMUX_GPIO74__FUNC_I2SI02_DATA1 (MTK_PIN_NO(74) | 2) +#define PINMUX_GPIO74__FUNC_WAKEN_1 (MTK_PIN_NO(74) | 4) +#define PINMUX_GPIO74__FUNC_VOW_CLK_MISO (MTK_PIN_NO(74) | 5) +#define PINMUX_GPIO74__FUNC_DBG_MON_B32 (MTK_PIN_NO(74) | 7) + +#define PINMUX_GPIO75__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) +#define PINMUX_GPIO75__FUNC_AUD_DAT_MISO2 (MTK_PIN_NO(75) | 1) +#define PINMUX_GPIO75__FUNC_I2SI02_DATA2 (MTK_PIN_NO(75) | 2) + +#define PINMUX_GPIO76__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) +#define PINMUX_GPIO76__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(76) | 1) +#define PINMUX_GPIO76__FUNC_I2SI02_DATA3 (MTK_PIN_NO(76) | 2) +#define PINMUX_GPIO76__FUNC_DBG_MON_A26 (MTK_PIN_NO(76) | 7) + +#define PINMUX_GPIO77__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) +#define PINMUX_GPIO77__FUNC_DGI_D0 (MTK_PIN_NO(77) | 1) +#define PINMUX_GPIO77__FUNC_DPI_D0 (MTK_PIN_NO(77) | 2) +#define PINMUX_GPIO77__FUNC_I2SI4_MCK (MTK_PIN_NO(77) | 3) +#define PINMUX_GPIO77__FUNC_SPIM4_CLK (MTK_PIN_NO(77) | 4) +#define PINMUX_GPIO77__FUNC_GBE_TXD3 (MTK_PIN_NO(77) | 5) +#define PINMUX_GPIO77__FUNC_SPM_JTAG_TCK (MTK_PIN_NO(77) | 6) + +#define PINMUX_GPIO78__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) +#define PINMUX_GPIO78__FUNC_DGI_D1 (MTK_PIN_NO(78) | 1) +#define PINMUX_GPIO78__FUNC_DPI_D1 (MTK_PIN_NO(78) | 2) +#define PINMUX_GPIO78__FUNC_I2SI4_BCK (MTK_PIN_NO(78) | 3) +#define PINMUX_GPIO78__FUNC_SPIM4_MO (MTK_PIN_NO(78) | 4) +#define PINMUX_GPIO78__FUNC_GBE_TXD2 (MTK_PIN_NO(78) | 5) +#define PINMUX_GPIO78__FUNC_SPM_JTAG_TMS (MTK_PIN_NO(78) | 6) + +#define PINMUX_GPIO79__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) +#define PINMUX_GPIO79__FUNC_DGI_D2 (MTK_PIN_NO(79) | 1) +#define PINMUX_GPIO79__FUNC_DPI_D2 (MTK_PIN_NO(79) | 2) +#define PINMUX_GPIO79__FUNC_I2SI4_WS (MTK_PIN_NO(79) | 3) +#define PINMUX_GPIO79__FUNC_SPIM4_CSB (MTK_PIN_NO(79) | 4) +#define PINMUX_GPIO79__FUNC_GBE_TXD1 (MTK_PIN_NO(79) | 5) +#define PINMUX_GPIO79__FUNC_SPM_JTAG_TDI (MTK_PIN_NO(79) | 6) + +#define PINMUX_GPIO80__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) +#define PINMUX_GPIO80__FUNC_DGI_D3 (MTK_PIN_NO(80) | 1) +#define PINMUX_GPIO80__FUNC_DPI_D3 (MTK_PIN_NO(80) | 2) +#define PINMUX_GPIO80__FUNC_I2SI4_D0 (MTK_PIN_NO(80) | 3) +#define PINMUX_GPIO80__FUNC_SPIM4_MI (MTK_PIN_NO(80) | 4) +#define PINMUX_GPIO80__FUNC_GBE_TXD0 (MTK_PIN_NO(80) | 5) +#define PINMUX_GPIO80__FUNC_SPM_JTAG_TDO (MTK_PIN_NO(80) | 6) + +#define PINMUX_GPIO81__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) +#define PINMUX_GPIO81__FUNC_DGI_D4 (MTK_PIN_NO(81) | 1) +#define PINMUX_GPIO81__FUNC_DPI_D4 (MTK_PIN_NO(81) | 2) +#define PINMUX_GPIO81__FUNC_I2SI5_MCK (MTK_PIN_NO(81) | 3) +#define PINMUX_GPIO81__FUNC_SPIM5_CLK (MTK_PIN_NO(81) | 4) +#define PINMUX_GPIO81__FUNC_GBE_RXD3 (MTK_PIN_NO(81) | 5) +#define PINMUX_GPIO81__FUNC_SPM_JTAG_TRSTN (MTK_PIN_NO(81) | 6) + +#define PINMUX_GPIO82__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) +#define PINMUX_GPIO82__FUNC_DGI_D5 (MTK_PIN_NO(82) | 1) +#define PINMUX_GPIO82__FUNC_DPI_D5 (MTK_PIN_NO(82) | 2) +#define PINMUX_GPIO82__FUNC_I2SI5_BCK (MTK_PIN_NO(82) | 3) +#define PINMUX_GPIO82__FUNC_SPIM5_MO (MTK_PIN_NO(82) | 4) +#define PINMUX_GPIO82__FUNC_GBE_RXD2 (MTK_PIN_NO(82) | 5) +#define PINMUX_GPIO82__FUNC_MCUPM_JTAG_TDO (MTK_PIN_NO(82) | 6) + +#define PINMUX_GPIO83__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) +#define PINMUX_GPIO83__FUNC_DGI_D6 (MTK_PIN_NO(83) | 1) +#define PINMUX_GPIO83__FUNC_DPI_D6 (MTK_PIN_NO(83) | 2) +#define PINMUX_GPIO83__FUNC_I2SI5_WS (MTK_PIN_NO(83) | 3) +#define PINMUX_GPIO83__FUNC_SPIM5_CSB (MTK_PIN_NO(83) | 4) +#define PINMUX_GPIO83__FUNC_GBE_RXD1 (MTK_PIN_NO(83) | 5) +#define PINMUX_GPIO83__FUNC_MCUPM_JTAG_TMS (MTK_PIN_NO(83) | 6) + +#define PINMUX_GPIO84__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) +#define PINMUX_GPIO84__FUNC_DGI_D7 (MTK_PIN_NO(84) | 1) +#define PINMUX_GPIO84__FUNC_DPI_D7 (MTK_PIN_NO(84) | 2) +#define PINMUX_GPIO84__FUNC_I2SI5_D0 (MTK_PIN_NO(84) | 3) +#define PINMUX_GPIO84__FUNC_SPIM5_MI (MTK_PIN_NO(84) | 4) +#define PINMUX_GPIO84__FUNC_GBE_RXD0 (MTK_PIN_NO(84) | 5) +#define PINMUX_GPIO84__FUNC_MCUPM_JTAG_TCK (MTK_PIN_NO(84) | 6) + +#define PINMUX_GPIO85__FUNC_GPIO85 (MTK_PIN_NO(85) | 0) +#define PINMUX_GPIO85__FUNC_DGI_D8 (MTK_PIN_NO(85) | 1) +#define PINMUX_GPIO85__FUNC_DPI_D8 (MTK_PIN_NO(85) | 2) +#define PINMUX_GPIO85__FUNC_I2SO4_MCK (MTK_PIN_NO(85) | 3) +#define PINMUX_GPIO85__FUNC_SCP_SPI1_B_CK (MTK_PIN_NO(85) | 4) +#define PINMUX_GPIO85__FUNC_GBE_TXC (MTK_PIN_NO(85) | 5) +#define PINMUX_GPIO85__FUNC_MCUPM_JTAG_TDI (MTK_PIN_NO(85) | 6) + +#define PINMUX_GPIO86__FUNC_GPIO86 (MTK_PIN_NO(86) | 0) +#define PINMUX_GPIO86__FUNC_DGI_D9 (MTK_PIN_NO(86) | 1) +#define PINMUX_GPIO86__FUNC_DPI_D9 (MTK_PIN_NO(86) | 2) +#define PINMUX_GPIO86__FUNC_I2SO4_BCK (MTK_PIN_NO(86) | 3) +#define PINMUX_GPIO86__FUNC_SCP_SPI1_B_MI (MTK_PIN_NO(86) | 4) +#define PINMUX_GPIO86__FUNC_GBE_RXC (MTK_PIN_NO(86) | 5) +#define PINMUX_GPIO86__FUNC_MCUPM_JTAG_TRSTN (MTK_PIN_NO(86) | 6) + +#define PINMUX_GPIO87__FUNC_GPIO87 (MTK_PIN_NO(87) | 0) +#define PINMUX_GPIO87__FUNC_DGI_D10 (MTK_PIN_NO(87) | 1) +#define PINMUX_GPIO87__FUNC_DPI_D10 (MTK_PIN_NO(87) | 2) +#define PINMUX_GPIO87__FUNC_I2SO4_WS (MTK_PIN_NO(87) | 3) +#define PINMUX_GPIO87__FUNC_SCP_SPI1_B_CS (MTK_PIN_NO(87) | 4) +#define PINMUX_GPIO87__FUNC_GBE_RXDV (MTK_PIN_NO(87) | 5) +#define PINMUX_GPIO87__FUNC_SSPM_JTAG_TDO (MTK_PIN_NO(87) | 6) + +#define PINMUX_GPIO88__FUNC_GPIO88 (MTK_PIN_NO(88) | 0) +#define PINMUX_GPIO88__FUNC_DGI_D11 (MTK_PIN_NO(88) | 1) +#define PINMUX_GPIO88__FUNC_DPI_D11 (MTK_PIN_NO(88) | 2) +#define PINMUX_GPIO88__FUNC_I2SO4_D0 (MTK_PIN_NO(88) | 3) +#define PINMUX_GPIO88__FUNC_SCP_SPI1_B_MO (MTK_PIN_NO(88) | 4) +#define PINMUX_GPIO88__FUNC_GBE_TXEN (MTK_PIN_NO(88) | 5) +#define PINMUX_GPIO88__FUNC_SSPM_JTAG_TMS (MTK_PIN_NO(88) | 6) + +#define PINMUX_GPIO89__FUNC_GPIO89 (MTK_PIN_NO(89) | 0) +#define PINMUX_GPIO89__FUNC_DGI_D12 (MTK_PIN_NO(89) | 1) +#define PINMUX_GPIO89__FUNC_DPI_D12 (MTK_PIN_NO(89) | 2) +#define PINMUX_GPIO89__FUNC_MSDC2_CMD_A (MTK_PIN_NO(89) | 3) +#define PINMUX_GPIO89__FUNC_I2SO5_BCK (MTK_PIN_NO(89) | 4) +#define PINMUX_GPIO89__FUNC_GBE_MDC (MTK_PIN_NO(89) | 5) +#define PINMUX_GPIO89__FUNC_SSPM_JTAG_TCK (MTK_PIN_NO(89) | 6) + +#define PINMUX_GPIO90__FUNC_GPIO90 (MTK_PIN_NO(90) | 0) +#define PINMUX_GPIO90__FUNC_DGI_D13 (MTK_PIN_NO(90) | 1) +#define PINMUX_GPIO90__FUNC_DPI_D13 (MTK_PIN_NO(90) | 2) +#define PINMUX_GPIO90__FUNC_MSDC2_CLK_A (MTK_PIN_NO(90) | 3) +#define PINMUX_GPIO90__FUNC_I2SO5_WS (MTK_PIN_NO(90) | 4) +#define PINMUX_GPIO90__FUNC_GBE_MDIO (MTK_PIN_NO(90) | 5) +#define PINMUX_GPIO90__FUNC_SSPM_JTAG_TDI (MTK_PIN_NO(90) | 6) + +#define PINMUX_GPIO91__FUNC_GPIO91 (MTK_PIN_NO(91) | 0) +#define PINMUX_GPIO91__FUNC_DGI_D14 (MTK_PIN_NO(91) | 1) +#define PINMUX_GPIO91__FUNC_DPI_D14 (MTK_PIN_NO(91) | 2) +#define PINMUX_GPIO91__FUNC_MSDC2_DAT3_A (MTK_PIN_NO(91) | 3) +#define PINMUX_GPIO91__FUNC_I2SO5_D0 (MTK_PIN_NO(91) | 4) +#define PINMUX_GPIO91__FUNC_GBE_TXER (MTK_PIN_NO(91) | 5) +#define PINMUX_GPIO91__FUNC_SSPM_JTAG_TRSTN (MTK_PIN_NO(91) | 6) + +#define PINMUX_GPIO92__FUNC_GPIO92 (MTK_PIN_NO(92) | 0) +#define PINMUX_GPIO92__FUNC_DGI_D15 (MTK_PIN_NO(92) | 1) +#define PINMUX_GPIO92__FUNC_DPI_D15 (MTK_PIN_NO(92) | 2) +#define PINMUX_GPIO92__FUNC_MSDC2_DAT0_A (MTK_PIN_NO(92) | 3) +#define PINMUX_GPIO92__FUNC_I2SO2_D1 (MTK_PIN_NO(92) | 4) +#define PINMUX_GPIO92__FUNC_GBE_RXER (MTK_PIN_NO(92) | 5) +#define PINMUX_GPIO92__FUNC_CCU0_JTAG_TDO (MTK_PIN_NO(92) | 6) + +#define PINMUX_GPIO93__FUNC_GPIO93 (MTK_PIN_NO(93) | 0) +#define PINMUX_GPIO93__FUNC_DGI_HSYNC (MTK_PIN_NO(93) | 1) +#define PINMUX_GPIO93__FUNC_DPI_HSYNC (MTK_PIN_NO(93) | 2) +#define PINMUX_GPIO93__FUNC_MSDC2_DAT2_A (MTK_PIN_NO(93) | 3) +#define PINMUX_GPIO93__FUNC_I2SO2_D2 (MTK_PIN_NO(93) | 4) +#define PINMUX_GPIO93__FUNC_GBE_COL (MTK_PIN_NO(93) | 5) +#define PINMUX_GPIO93__FUNC_CCU0_JTAG_TMS (MTK_PIN_NO(93) | 6) + +#define PINMUX_GPIO94__FUNC_GPIO94 (MTK_PIN_NO(94) | 0) +#define PINMUX_GPIO94__FUNC_DGI_VSYNC (MTK_PIN_NO(94) | 1) +#define PINMUX_GPIO94__FUNC_DPI_VSYNC (MTK_PIN_NO(94) | 2) +#define PINMUX_GPIO94__FUNC_MSDC2_DAT1_A (MTK_PIN_NO(94) | 3) +#define PINMUX_GPIO94__FUNC_I2SO2_D3 (MTK_PIN_NO(94) | 4) +#define PINMUX_GPIO94__FUNC_GBE_INTR (MTK_PIN_NO(94) | 5) +#define PINMUX_GPIO94__FUNC_CCU0_JTAG_TDI (MTK_PIN_NO(94) | 6) + +#define PINMUX_GPIO95__FUNC_GPIO95 (MTK_PIN_NO(95) | 0) +#define PINMUX_GPIO95__FUNC_DGI_DE (MTK_PIN_NO(95) | 1) +#define PINMUX_GPIO95__FUNC_DPI_DE (MTK_PIN_NO(95) | 2) +#define PINMUX_GPIO95__FUNC_UTXD2 (MTK_PIN_NO(95) | 3) +#define PINMUX_GPIO95__FUNC_I2SIN_D1 (MTK_PIN_NO(95) | 5) +#define PINMUX_GPIO95__FUNC_CCU0_JTAG_TCK (MTK_PIN_NO(95) | 6) + +#define PINMUX_GPIO96__FUNC_GPIO96 (MTK_PIN_NO(96) | 0) +#define PINMUX_GPIO96__FUNC_DGI_CK (MTK_PIN_NO(96) | 1) +#define PINMUX_GPIO96__FUNC_DPI_CK (MTK_PIN_NO(96) | 2) +#define PINMUX_GPIO96__FUNC_URXD2 (MTK_PIN_NO(96) | 3) +#define PINMUX_GPIO96__FUNC_I2SO5_MCK (MTK_PIN_NO(96) | 4) +#define PINMUX_GPIO96__FUNC_I2SIN_D2 (MTK_PIN_NO(96) | 5) +#define PINMUX_GPIO96__FUNC_CCU0_JTAG_TRST (MTK_PIN_NO(96) | 6) + +#define PINMUX_GPIO97__FUNC_GPIO97 (MTK_PIN_NO(97) | 0) +#define PINMUX_GPIO97__FUNC_DISP_PWM0 (MTK_PIN_NO(97) | 1) +#define PINMUX_GPIO97__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(97) | 2) + +#define PINMUX_GPIO98__FUNC_GPIO98 (MTK_PIN_NO(98) | 0) +#define PINMUX_GPIO98__FUNC_UTXD0 (MTK_PIN_NO(98) | 1) + +#define PINMUX_GPIO99__FUNC_GPIO99 (MTK_PIN_NO(99) | 0) +#define PINMUX_GPIO99__FUNC_URXD0 (MTK_PIN_NO(99) | 1) + +#define PINMUX_GPIO100__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) +#define PINMUX_GPIO100__FUNC_URTS1 (MTK_PIN_NO(100) | 1) +#define PINMUX_GPIO100__FUNC_DSI_TE (MTK_PIN_NO(100) | 2) +#define PINMUX_GPIO100__FUNC_I2SO1_D8 (MTK_PIN_NO(100) | 3) +#define PINMUX_GPIO100__FUNC_KPROW2 (MTK_PIN_NO(100) | 4) +#define PINMUX_GPIO100__FUNC_PWM_0 (MTK_PIN_NO(100) | 5) +#define PINMUX_GPIO100__FUNC_TP_URTS1_AO (MTK_PIN_NO(100) | 6) +#define PINMUX_GPIO100__FUNC_I2SIN_D0 (MTK_PIN_NO(100) | 7) + +#define PINMUX_GPIO101__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) +#define PINMUX_GPIO101__FUNC_UCTS1 (MTK_PIN_NO(101) | 1) +#define PINMUX_GPIO101__FUNC_DSI1_TE (MTK_PIN_NO(101) | 2) +#define PINMUX_GPIO101__FUNC_I2SO1_D9 (MTK_PIN_NO(101) | 3) +#define PINMUX_GPIO101__FUNC_KPCOL2 (MTK_PIN_NO(101) | 4) +#define PINMUX_GPIO101__FUNC_PWM_1 (MTK_PIN_NO(101) | 5) +#define PINMUX_GPIO101__FUNC_TP_UCTS1_AO (MTK_PIN_NO(101) | 6) +#define PINMUX_GPIO101__FUNC_I2SIN_D1 (MTK_PIN_NO(101) | 7) + +#define PINMUX_GPIO102__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) +#define PINMUX_GPIO102__FUNC_UTXD1 (MTK_PIN_NO(102) | 1) +#define PINMUX_GPIO102__FUNC_VBUSVALID_2P (MTK_PIN_NO(102) | 2) +#define PINMUX_GPIO102__FUNC_I2SO1_D10 (MTK_PIN_NO(102) | 3) +#define PINMUX_GPIO102__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(102) | 4) +#define PINMUX_GPIO102__FUNC_TP_UTXD1_AO (MTK_PIN_NO(102) | 5) +#define PINMUX_GPIO102__FUNC_MD32_1_TXD (MTK_PIN_NO(102) | 6) +#define PINMUX_GPIO102__FUNC_I2SIN_D2 (MTK_PIN_NO(102) | 7) + +#define PINMUX_GPIO103__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) +#define PINMUX_GPIO103__FUNC_URXD1 (MTK_PIN_NO(103) | 1) +#define PINMUX_GPIO103__FUNC_VBUSVALID_3P (MTK_PIN_NO(103) | 2) +#define PINMUX_GPIO103__FUNC_I2SO1_D11 (MTK_PIN_NO(103) | 3) +#define PINMUX_GPIO103__FUNC_SSPM_URXD_AO (MTK_PIN_NO(103) | 4) +#define PINMUX_GPIO103__FUNC_TP_URXD1_AO (MTK_PIN_NO(103) | 5) +#define PINMUX_GPIO103__FUNC_MD32_1_RXD (MTK_PIN_NO(103) | 6) +#define PINMUX_GPIO103__FUNC_I2SIN_D3 (MTK_PIN_NO(103) | 7) + +#define PINMUX_GPIO104__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) +#define PINMUX_GPIO104__FUNC_KPROW0 (MTK_PIN_NO(104) | 1) +#define PINMUX_GPIO104__FUNC_DISP_PWM1 (MTK_PIN_NO(104) | 2) + +#define PINMUX_GPIO105__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) +#define PINMUX_GPIO105__FUNC_KPROW1 (MTK_PIN_NO(105) | 1) +#define PINMUX_GPIO105__FUNC_EDP_TX_HPD (MTK_PIN_NO(105) | 2) +#define PINMUX_GPIO105__FUNC_PWM_2 (MTK_PIN_NO(105) | 3) + +#define PINMUX_GPIO106__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) +#define PINMUX_GPIO106__FUNC_KPCOL0 (MTK_PIN_NO(106) | 1) + +#define PINMUX_GPIO107__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) +#define PINMUX_GPIO107__FUNC_KPCOL1 (MTK_PIN_NO(107) | 1) +#define PINMUX_GPIO107__FUNC_DSI1_TE (MTK_PIN_NO(107) | 2) +#define PINMUX_GPIO107__FUNC_PWM_3 (MTK_PIN_NO(107) | 3) +#define PINMUX_GPIO107__FUNC_SCP_SCL3 (MTK_PIN_NO(107) | 4) +#define PINMUX_GPIO107__FUNC_I2SIN_MCK (MTK_PIN_NO(107) | 5) + +#define PINMUX_GPIO108__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) +#define PINMUX_GPIO108__FUNC_LCM_RST (MTK_PIN_NO(108) | 1) +#define PINMUX_GPIO108__FUNC_KPCOL1 (MTK_PIN_NO(108) | 2) +#define PINMUX_GPIO108__FUNC_SCP_SDA3 (MTK_PIN_NO(108) | 4) +#define PINMUX_GPIO108__FUNC_I2SIN_BCK (MTK_PIN_NO(108) | 5) + +#define PINMUX_GPIO109__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) +#define PINMUX_GPIO109__FUNC_DSI_TE (MTK_PIN_NO(109) | 1) +#define PINMUX_GPIO109__FUNC_I2SIN_D3 (MTK_PIN_NO(109) | 2) +#define PINMUX_GPIO109__FUNC_I2SIN_WS (MTK_PIN_NO(109) | 5) + +#define PINMUX_GPIO110__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) +#define PINMUX_GPIO110__FUNC_MSDC1_CMD (MTK_PIN_NO(110) | 1) +#define PINMUX_GPIO110__FUNC_JTMS_SEL3 (MTK_PIN_NO(110) | 2) +#define PINMUX_GPIO110__FUNC_UDI_TMS (MTK_PIN_NO(110) | 3) +#define PINMUX_GPIO110__FUNC_CCU1_JTAG_TMS (MTK_PIN_NO(110) | 5) +#define PINMUX_GPIO110__FUNC_IPU_JTAG_TMS (MTK_PIN_NO(110) | 6) + +#define PINMUX_GPIO111__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) +#define PINMUX_GPIO111__FUNC_MSDC1_CLK (MTK_PIN_NO(111) | 1) +#define PINMUX_GPIO111__FUNC_JTCK_SEL3 (MTK_PIN_NO(111) | 2) +#define PINMUX_GPIO111__FUNC_UDI_TCK (MTK_PIN_NO(111) | 3) +#define PINMUX_GPIO111__FUNC_CCU1_JTAG_TCK (MTK_PIN_NO(111) | 5) +#define PINMUX_GPIO111__FUNC_IPU_JTAG_TCK (MTK_PIN_NO(111) | 6) + +#define PINMUX_GPIO112__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) +#define PINMUX_GPIO112__FUNC_MSDC1_DAT0 (MTK_PIN_NO(112) | 1) +#define PINMUX_GPIO112__FUNC_JTDI_SEL3 (MTK_PIN_NO(112) | 2) +#define PINMUX_GPIO112__FUNC_UDI_TDI (MTK_PIN_NO(112) | 3) +#define PINMUX_GPIO112__FUNC_I2SO2_D0 (MTK_PIN_NO(112) | 4) +#define PINMUX_GPIO112__FUNC_CCU1_JTAG_TDI (MTK_PIN_NO(112) | 5) +#define PINMUX_GPIO112__FUNC_IPU_JTAG_TDI (MTK_PIN_NO(112) | 6) + +#define PINMUX_GPIO113__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) +#define PINMUX_GPIO113__FUNC_MSDC1_DAT1 (MTK_PIN_NO(113) | 1) +#define PINMUX_GPIO113__FUNC_JTDO_SEL3 (MTK_PIN_NO(113) | 2) +#define PINMUX_GPIO113__FUNC_UDI_TDO (MTK_PIN_NO(113) | 3) +#define PINMUX_GPIO113__FUNC_I2SO2_D1 (MTK_PIN_NO(113) | 4) +#define PINMUX_GPIO113__FUNC_CCU1_JTAG_TDO (MTK_PIN_NO(113) | 5) +#define PINMUX_GPIO113__FUNC_IPU_JTAG_TDO (MTK_PIN_NO(113) | 6) + +#define PINMUX_GPIO114__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) +#define PINMUX_GPIO114__FUNC_MSDC1_DAT2 (MTK_PIN_NO(114) | 1) +#define PINMUX_GPIO114__FUNC_JTRSTn_SEL3 (MTK_PIN_NO(114) | 2) +#define PINMUX_GPIO114__FUNC_UDI_NTRST (MTK_PIN_NO(114) | 3) +#define PINMUX_GPIO114__FUNC_I2SO2_D2 (MTK_PIN_NO(114) | 4) +#define PINMUX_GPIO114__FUNC_CCU1_JTAG_TRST (MTK_PIN_NO(114) | 5) +#define PINMUX_GPIO114__FUNC_IPU_JTAG_TRST (MTK_PIN_NO(114) | 6) + +#define PINMUX_GPIO115__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) +#define PINMUX_GPIO115__FUNC_MSDC1_DAT3 (MTK_PIN_NO(115) | 1) +#define PINMUX_GPIO115__FUNC_I2SO2_D3 (MTK_PIN_NO(115) | 4) +#define PINMUX_GPIO115__FUNC_MD32_1_GPIO2 (MTK_PIN_NO(115) | 6) + +#define PINMUX_GPIO116__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) +#define PINMUX_GPIO116__FUNC_MSDC0_DAT7 (MTK_PIN_NO(116) | 1) + +#define PINMUX_GPIO117__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) +#define PINMUX_GPIO117__FUNC_MSDC0_DAT6 (MTK_PIN_NO(117) | 1) + +#define PINMUX_GPIO118__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) +#define PINMUX_GPIO118__FUNC_MSDC0_DAT5 (MTK_PIN_NO(118) | 1) + +#define PINMUX_GPIO119__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) +#define PINMUX_GPIO119__FUNC_MSDC0_DAT4 (MTK_PIN_NO(119) | 1) + +#define PINMUX_GPIO120__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) +#define PINMUX_GPIO120__FUNC_MSDC0_RSTB (MTK_PIN_NO(120) | 1) + +#define PINMUX_GPIO121__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) +#define PINMUX_GPIO121__FUNC_MSDC0_CMD (MTK_PIN_NO(121) | 1) + +#define PINMUX_GPIO122__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) +#define PINMUX_GPIO122__FUNC_MSDC0_CLK (MTK_PIN_NO(122) | 1) + +#define PINMUX_GPIO123__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) +#define PINMUX_GPIO123__FUNC_MSDC0_DAT3 (MTK_PIN_NO(123) | 1) + +#define PINMUX_GPIO124__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) +#define PINMUX_GPIO124__FUNC_MSDC0_DAT2 (MTK_PIN_NO(124) | 1) + +#define PINMUX_GPIO125__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) +#define PINMUX_GPIO125__FUNC_MSDC0_DAT1 (MTK_PIN_NO(125) | 1) + +#define PINMUX_GPIO126__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) +#define PINMUX_GPIO126__FUNC_MSDC0_DAT0 (MTK_PIN_NO(126) | 1) + +#define PINMUX_GPIO127__FUNC_GPIO127 (MTK_PIN_NO(127) | 0) +#define PINMUX_GPIO127__FUNC_MSDC0_DSL (MTK_PIN_NO(127) | 1) + +#define PINMUX_GPIO128__FUNC_GPIO128 (MTK_PIN_NO(128) | 0) +#define PINMUX_GPIO128__FUNC_IDDIG (MTK_PIN_NO(128) | 1) +#define PINMUX_GPIO128__FUNC_UCTS2 (MTK_PIN_NO(128) | 2) +#define PINMUX_GPIO128__FUNC_UTXD5 (MTK_PIN_NO(128) | 3) +#define PINMUX_GPIO128__FUNC_UFS_MPHY_SCL (MTK_PIN_NO(128) | 4) +#define PINMUX_GPIO128__FUNC_mbistreaden_trigger (MTK_PIN_NO(128) | 5) +#define PINMUX_GPIO128__FUNC_MD32_1_GPIO0 (MTK_PIN_NO(128) | 6) +#define PINMUX_GPIO128__FUNC_SCP_SCL2 (MTK_PIN_NO(128) | 7) + +#define PINMUX_GPIO129__FUNC_GPIO129 (MTK_PIN_NO(129) | 0) +#define PINMUX_GPIO129__FUNC_USB_DRVVBUS (MTK_PIN_NO(129) | 1) +#define PINMUX_GPIO129__FUNC_URTS2 (MTK_PIN_NO(129) | 2) +#define PINMUX_GPIO129__FUNC_URXD5 (MTK_PIN_NO(129) | 3) +#define PINMUX_GPIO129__FUNC_UFS_MPHY_SDA (MTK_PIN_NO(129) | 4) +#define PINMUX_GPIO129__FUNC_mbistwriteen_trigger (MTK_PIN_NO(129) | 5) +#define PINMUX_GPIO129__FUNC_MD32_1_GPIO1 (MTK_PIN_NO(129) | 6) +#define PINMUX_GPIO129__FUNC_SCP_SDA2 (MTK_PIN_NO(129) | 7) + +#define PINMUX_GPIO130__FUNC_GPIO130 (MTK_PIN_NO(130) | 0) +#define PINMUX_GPIO130__FUNC_IDDIG_1P (MTK_PIN_NO(130) | 1) +#define PINMUX_GPIO130__FUNC_SPINOR_IO2 (MTK_PIN_NO(130) | 2) +#define PINMUX_GPIO130__FUNC_SNFI_WP (MTK_PIN_NO(130) | 3) +#define PINMUX_GPIO130__FUNC_VPU_UDI_NTRST (MTK_PIN_NO(130) | 4) + +#define PINMUX_GPIO131__FUNC_GPIO131 (MTK_PIN_NO(131) | 0) +#define PINMUX_GPIO131__FUNC_USB_DRVVBUS_1P (MTK_PIN_NO(131) | 1) +#define PINMUX_GPIO131__FUNC_SPINOR_IO3 (MTK_PIN_NO(131) | 2) +#define PINMUX_GPIO131__FUNC_SNFI_HOLD (MTK_PIN_NO(131) | 3) +#define PINMUX_GPIO131__FUNC_MD32_1_JTAG_TRST (MTK_PIN_NO(131) | 4) +#define PINMUX_GPIO131__FUNC_SCP_JTAG0_TRSTN (MTK_PIN_NO(131) | 5) +#define PINMUX_GPIO131__FUNC_APU_JTAG_TRST (MTK_PIN_NO(131) | 6) + +#define PINMUX_GPIO132__FUNC_GPIO132 (MTK_PIN_NO(132) | 0) +#define PINMUX_GPIO132__FUNC_SPIM0_CSB (MTK_PIN_NO(132) | 1) +#define PINMUX_GPIO132__FUNC_SCP_SPI0_CS (MTK_PIN_NO(132) | 2) +#define PINMUX_GPIO132__FUNC_SPIS0_CSB (MTK_PIN_NO(132) | 3) +#define PINMUX_GPIO132__FUNC_VPU_UDI_TMS (MTK_PIN_NO(132) | 4) +#define PINMUX_GPIO132__FUNC_I2SO5_D0 (MTK_PIN_NO(132) | 6) + +#define PINMUX_GPIO133__FUNC_GPIO133 (MTK_PIN_NO(133) | 0) +#define PINMUX_GPIO133__FUNC_SPIM0_CLK (MTK_PIN_NO(133) | 1) +#define PINMUX_GPIO133__FUNC_SCP_SPI0_CK (MTK_PIN_NO(133) | 2) +#define PINMUX_GPIO133__FUNC_SPIS0_CLK (MTK_PIN_NO(133) | 3) +#define PINMUX_GPIO133__FUNC_VPU_UDI_TCK (MTK_PIN_NO(133) | 4) +#define PINMUX_GPIO133__FUNC_I2SO5_BCK (MTK_PIN_NO(133) | 6) + +#define PINMUX_GPIO134__FUNC_GPIO134 (MTK_PIN_NO(134) | 0) +#define PINMUX_GPIO134__FUNC_SPIM0_MO (MTK_PIN_NO(134) | 1) +#define PINMUX_GPIO134__FUNC_SCP_SPI0_MO (MTK_PIN_NO(134) | 2) +#define PINMUX_GPIO134__FUNC_SPIS0_SI (MTK_PIN_NO(134) | 3) +#define PINMUX_GPIO134__FUNC_VPU_UDI_TDO (MTK_PIN_NO(134) | 4) +#define PINMUX_GPIO134__FUNC_I2SO5_WS (MTK_PIN_NO(134) | 6) + +#define PINMUX_GPIO135__FUNC_GPIO135 (MTK_PIN_NO(135) | 0) +#define PINMUX_GPIO135__FUNC_SPIM0_MI (MTK_PIN_NO(135) | 1) +#define PINMUX_GPIO135__FUNC_SCP_SPI0_MI (MTK_PIN_NO(135) | 2) +#define PINMUX_GPIO135__FUNC_SPIS0_SO (MTK_PIN_NO(135) | 3) +#define PINMUX_GPIO135__FUNC_VPU_UDI_TDI (MTK_PIN_NO(135) | 4) +#define PINMUX_GPIO135__FUNC_I2SO5_MCK (MTK_PIN_NO(135) | 6) + +#define PINMUX_GPIO136__FUNC_GPIO136 (MTK_PIN_NO(136) | 0) +#define PINMUX_GPIO136__FUNC_SPIM1_CSB (MTK_PIN_NO(136) | 1) +#define PINMUX_GPIO136__FUNC_SCP_SPI1_A_CS (MTK_PIN_NO(136) | 2) +#define PINMUX_GPIO136__FUNC_SPIS1_CSB (MTK_PIN_NO(136) | 3) +#define PINMUX_GPIO136__FUNC_MD32_1_JTAG_TMS (MTK_PIN_NO(136) | 4) +#define PINMUX_GPIO136__FUNC_SCP_JTAG0_TMS (MTK_PIN_NO(136) | 5) +#define PINMUX_GPIO136__FUNC_APU_JTAG_TMS (MTK_PIN_NO(136) | 6) +#define PINMUX_GPIO136__FUNC_DBG_MON_A15 (MTK_PIN_NO(136) | 7) + +#define PINMUX_GPIO137__FUNC_GPIO137 (MTK_PIN_NO(137) | 0) +#define PINMUX_GPIO137__FUNC_SPIM1_CLK (MTK_PIN_NO(137) | 1) +#define PINMUX_GPIO137__FUNC_SCP_SPI1_A_CK (MTK_PIN_NO(137) | 2) +#define PINMUX_GPIO137__FUNC_SPIS1_CLK (MTK_PIN_NO(137) | 3) +#define PINMUX_GPIO137__FUNC_MD32_1_JTAG_TCK (MTK_PIN_NO(137) | 4) +#define PINMUX_GPIO137__FUNC_SCP_JTAG0_TCK (MTK_PIN_NO(137) | 5) +#define PINMUX_GPIO137__FUNC_APU_JTAG_TCK (MTK_PIN_NO(137) | 6) +#define PINMUX_GPIO137__FUNC_DBG_MON_A14 (MTK_PIN_NO(137) | 7) + +#define PINMUX_GPIO138__FUNC_GPIO138 (MTK_PIN_NO(138) | 0) +#define PINMUX_GPIO138__FUNC_SPIM1_MO (MTK_PIN_NO(138) | 1) +#define PINMUX_GPIO138__FUNC_SCP_SPI1_A_MO (MTK_PIN_NO(138) | 2) +#define PINMUX_GPIO138__FUNC_SPIS1_SI (MTK_PIN_NO(138) | 3) +#define PINMUX_GPIO138__FUNC_MD32_1_JTAG_TDO (MTK_PIN_NO(138) | 4) +#define PINMUX_GPIO138__FUNC_SCP_JTAG0_TDO (MTK_PIN_NO(138) | 5) +#define PINMUX_GPIO138__FUNC_APU_JTAG_TDO (MTK_PIN_NO(138) | 6) +#define PINMUX_GPIO138__FUNC_DBG_MON_A16 (MTK_PIN_NO(138) | 7) + +#define PINMUX_GPIO139__FUNC_GPIO139 (MTK_PIN_NO(139) | 0) +#define PINMUX_GPIO139__FUNC_SPIM1_MI (MTK_PIN_NO(139) | 1) +#define PINMUX_GPIO139__FUNC_SCP_SPI1_A_MI (MTK_PIN_NO(139) | 2) +#define PINMUX_GPIO139__FUNC_SPIS1_SO (MTK_PIN_NO(139) | 3) +#define PINMUX_GPIO139__FUNC_MD32_1_JTAG_TDI (MTK_PIN_NO(139) | 4) +#define PINMUX_GPIO139__FUNC_SCP_JTAG0_TDI (MTK_PIN_NO(139) | 5) +#define PINMUX_GPIO139__FUNC_APU_JTAG_TDI (MTK_PIN_NO(139) | 6) +#define PINMUX_GPIO139__FUNC_DBG_MON_A17 (MTK_PIN_NO(139) | 7) + +#define PINMUX_GPIO140__FUNC_GPIO140 (MTK_PIN_NO(140) | 0) +#define PINMUX_GPIO140__FUNC_SPIM2_CSB (MTK_PIN_NO(140) | 1) +#define PINMUX_GPIO140__FUNC_SPINOR_CS (MTK_PIN_NO(140) | 2) +#define PINMUX_GPIO140__FUNC_SNFI_CS (MTK_PIN_NO(140) | 3) +#define PINMUX_GPIO140__FUNC_DMIC3_DAT (MTK_PIN_NO(140) | 4) +#define PINMUX_GPIO140__FUNC_DBG_MON_A11 (MTK_PIN_NO(140) | 7) + +#define PINMUX_GPIO141__FUNC_GPIO141 (MTK_PIN_NO(141) | 0) +#define PINMUX_GPIO141__FUNC_SPIM2_CLK (MTK_PIN_NO(141) | 1) +#define PINMUX_GPIO141__FUNC_SPINOR_CK (MTK_PIN_NO(141) | 2) +#define PINMUX_GPIO141__FUNC_SNFI_CLK (MTK_PIN_NO(141) | 3) +#define PINMUX_GPIO141__FUNC_DMIC3_CLK (MTK_PIN_NO(141) | 4) +#define PINMUX_GPIO141__FUNC_DBG_MON_A10 (MTK_PIN_NO(141) | 7) + +#define PINMUX_GPIO142__FUNC_GPIO142 (MTK_PIN_NO(142) | 0) +#define PINMUX_GPIO142__FUNC_SPIM2_MO (MTK_PIN_NO(142) | 1) +#define PINMUX_GPIO142__FUNC_SPINOR_IO0 (MTK_PIN_NO(142) | 2) +#define PINMUX_GPIO142__FUNC_SNFI_MOSI (MTK_PIN_NO(142) | 3) +#define PINMUX_GPIO142__FUNC_DMIC4_DAT (MTK_PIN_NO(142) | 4) +#define PINMUX_GPIO142__FUNC_DBG_MON_A12 (MTK_PIN_NO(142) | 7) + +#define PINMUX_GPIO143__FUNC_GPIO143 (MTK_PIN_NO(143) | 0) +#define PINMUX_GPIO143__FUNC_SPIM2_MI (MTK_PIN_NO(143) | 1) +#define PINMUX_GPIO143__FUNC_SPINOR_IO1 (MTK_PIN_NO(143) | 2) +#define PINMUX_GPIO143__FUNC_SNFI_MISO (MTK_PIN_NO(143) | 3) +#define PINMUX_GPIO143__FUNC_DMIC4_CLK (MTK_PIN_NO(143) | 4) +#define PINMUX_GPIO143__FUNC_DBG_MON_A13 (MTK_PIN_NO(143) | 7) + +#endif /* __MT8195-PINFUNC_H */ diff --git a/include/dt-bindings/pinctrl/mt8365-pinfunc.h b/include/dt-bindings/pinctrl/mt8365-pinfunc.h new file mode 100644 index 000000000000..e2ec8af57dcf --- /dev/null +++ b/include/dt-bindings/pinctrl/mt8365-pinfunc.h @@ -0,0 +1,858 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021 MediaTek Inc. + */ +#ifndef __MT8365_PINFUNC_H +#define __MT8365_PINFUNC_H + +#include <dt-bindings/pinctrl/mt65xx.h> + +#define MT8365_PIN_0_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define MT8365_PIN_0_GPIO0__FUNC_DPI_D0 (MTK_PIN_NO(0) | 1) +#define MT8365_PIN_0_GPIO0__FUNC_PWM_A (MTK_PIN_NO(0) | 2) +#define MT8365_PIN_0_GPIO0__FUNC_I2S2_BCK (MTK_PIN_NO(0) | 3) +#define MT8365_PIN_0_GPIO0__FUNC_EXT_TXD0 (MTK_PIN_NO(0) | 4) +#define MT8365_PIN_0_GPIO0__FUNC_CONN_MCU_TDO (MTK_PIN_NO(0) | 5) +#define MT8365_PIN_0_GPIO0__FUNC_DBG_MON_A0 (MTK_PIN_NO(0) | 7) + +#define MT8365_PIN_1_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define MT8365_PIN_1_GPIO1__FUNC_DPI_D1 (MTK_PIN_NO(1) | 1) +#define MT8365_PIN_1_GPIO1__FUNC_PWM_B (MTK_PIN_NO(1) | 2) +#define MT8365_PIN_1_GPIO1__FUNC_I2S2_LRCK (MTK_PIN_NO(1) | 3) +#define MT8365_PIN_1_GPIO1__FUNC_EXT_TXD1 (MTK_PIN_NO(1) | 4) +#define MT8365_PIN_1_GPIO1__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(1) | 5) +#define MT8365_PIN_1_GPIO1__FUNC_DBG_MON_A1 (MTK_PIN_NO(1) | 7) + +#define MT8365_PIN_2_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define MT8365_PIN_2_GPIO2__FUNC_DPI_D2 (MTK_PIN_NO(2) | 1) +#define MT8365_PIN_2_GPIO2__FUNC_PWM_C (MTK_PIN_NO(2) | 2) +#define MT8365_PIN_2_GPIO2__FUNC_I2S2_MCK (MTK_PIN_NO(2) | 3) +#define MT8365_PIN_2_GPIO2__FUNC_EXT_TXD2 (MTK_PIN_NO(2) | 4) +#define MT8365_PIN_2_GPIO2__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(2) | 5) +#define MT8365_PIN_2_GPIO2__FUNC_DBG_MON_A2 (MTK_PIN_NO(2) | 7) + +#define MT8365_PIN_3_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define MT8365_PIN_3_GPIO3__FUNC_DPI_D3 (MTK_PIN_NO(3) | 1) +#define MT8365_PIN_3_GPIO3__FUNC_CLKM0 (MTK_PIN_NO(3) | 2) +#define MT8365_PIN_3_GPIO3__FUNC_I2S2_DI (MTK_PIN_NO(3) | 3) +#define MT8365_PIN_3_GPIO3__FUNC_EXT_TXD3 (MTK_PIN_NO(3) | 4) +#define MT8365_PIN_3_GPIO3__FUNC_CONN_MCU_TCK (MTK_PIN_NO(3) | 5) +#define MT8365_PIN_3_GPIO3__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(3) | 6) +#define MT8365_PIN_3_GPIO3__FUNC_DBG_MON_A3 (MTK_PIN_NO(3) | 7) + +#define MT8365_PIN_4_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define MT8365_PIN_4_GPIO4__FUNC_DPI_D4 (MTK_PIN_NO(4) | 1) +#define MT8365_PIN_4_GPIO4__FUNC_CLKM1 (MTK_PIN_NO(4) | 2) +#define MT8365_PIN_4_GPIO4__FUNC_I2S1_BCK (MTK_PIN_NO(4) | 3) +#define MT8365_PIN_4_GPIO4__FUNC_EXT_TXC (MTK_PIN_NO(4) | 4) +#define MT8365_PIN_4_GPIO4__FUNC_CONN_MCU_TDI (MTK_PIN_NO(4) | 5) +#define MT8365_PIN_4_GPIO4__FUNC_VDEC_TEST_CK (MTK_PIN_NO(4) | 6) +#define MT8365_PIN_4_GPIO4__FUNC_DBG_MON_A4 (MTK_PIN_NO(4) | 7) + +#define MT8365_PIN_5_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define MT8365_PIN_5_GPIO5__FUNC_DPI_D5 (MTK_PIN_NO(5) | 1) +#define MT8365_PIN_5_GPIO5__FUNC_CLKM2 (MTK_PIN_NO(5) | 2) +#define MT8365_PIN_5_GPIO5__FUNC_I2S1_LRCK (MTK_PIN_NO(5) | 3) +#define MT8365_PIN_5_GPIO5__FUNC_EXT_RXER (MTK_PIN_NO(5) | 4) +#define MT8365_PIN_5_GPIO5__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(5) | 5) +#define MT8365_PIN_5_GPIO5__FUNC_MM_TEST_CK (MTK_PIN_NO(5) | 6) +#define MT8365_PIN_5_GPIO5__FUNC_DBG_MON_A5 (MTK_PIN_NO(5) | 7) + +#define MT8365_PIN_6_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define MT8365_PIN_6_GPIO6__FUNC_DPI_D6 (MTK_PIN_NO(6) | 1) +#define MT8365_PIN_6_GPIO6__FUNC_CLKM3 (MTK_PIN_NO(6) | 2) +#define MT8365_PIN_6_GPIO6__FUNC_I2S1_MCK (MTK_PIN_NO(6) | 3) +#define MT8365_PIN_6_GPIO6__FUNC_EXT_RXC (MTK_PIN_NO(6) | 4) +#define MT8365_PIN_6_GPIO6__FUNC_CONN_MCU_TMS (MTK_PIN_NO(6) | 5) +#define MT8365_PIN_6_GPIO6__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(6) | 6) +#define MT8365_PIN_6_GPIO6__FUNC_DBG_MON_A6 (MTK_PIN_NO(6) | 7) + +#define MT8365_PIN_7_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +#define MT8365_PIN_7_GPIO7__FUNC_DPI_D7 (MTK_PIN_NO(7) | 1) +#define MT8365_PIN_7_GPIO7__FUNC_I2S1_DO (MTK_PIN_NO(7) | 3) +#define MT8365_PIN_7_GPIO7__FUNC_EXT_RXDV (MTK_PIN_NO(7) | 4) +#define MT8365_PIN_7_GPIO7__FUNC_CONN_DSP_JCK (MTK_PIN_NO(7) | 5) +#define MT8365_PIN_7_GPIO7__FUNC_DBG_MON_A7 (MTK_PIN_NO(7) | 7) + +#define MT8365_PIN_8_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +#define MT8365_PIN_8_GPIO8__FUNC_DPI_D8 (MTK_PIN_NO(8) | 1) +#define MT8365_PIN_8_GPIO8__FUNC_SPI_CLK (MTK_PIN_NO(8) | 2) +#define MT8365_PIN_8_GPIO8__FUNC_I2S0_BCK (MTK_PIN_NO(8) | 3) +#define MT8365_PIN_8_GPIO8__FUNC_EXT_RXD0 (MTK_PIN_NO(8) | 4) +#define MT8365_PIN_8_GPIO8__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(8) | 5) +#define MT8365_PIN_8_GPIO8__FUNC_DBG_MON_A8 (MTK_PIN_NO(8) | 7) + +#define MT8365_PIN_9_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +#define MT8365_PIN_9_GPIO9__FUNC_DPI_D9 (MTK_PIN_NO(9) | 1) +#define MT8365_PIN_9_GPIO9__FUNC_SPI_CSB (MTK_PIN_NO(9) | 2) +#define MT8365_PIN_9_GPIO9__FUNC_I2S0_LRCK (MTK_PIN_NO(9) | 3) +#define MT8365_PIN_9_GPIO9__FUNC_EXT_RXD1 (MTK_PIN_NO(9) | 4) +#define MT8365_PIN_9_GPIO9__FUNC_CONN_DSP_JDI (MTK_PIN_NO(9) | 5) +#define MT8365_PIN_9_GPIO9__FUNC_DBG_MON_A9 (MTK_PIN_NO(9) | 7) + +#define MT8365_PIN_10_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +#define MT8365_PIN_10_GPIO10__FUNC_DPI_D10 (MTK_PIN_NO(10) | 1) +#define MT8365_PIN_10_GPIO10__FUNC_SPI_MI (MTK_PIN_NO(10) | 2) +#define MT8365_PIN_10_GPIO10__FUNC_I2S0_MCK (MTK_PIN_NO(10) | 3) +#define MT8365_PIN_10_GPIO10__FUNC_EXT_RXD2 (MTK_PIN_NO(10) | 4) +#define MT8365_PIN_10_GPIO10__FUNC_CONN_DSP_JMS (MTK_PIN_NO(10) | 5) +#define MT8365_PIN_10_GPIO10__FUNC_DBG_MON_A10 (MTK_PIN_NO(10) | 7) + +#define MT8365_PIN_11_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +#define MT8365_PIN_11_GPIO11__FUNC_DPI_D11 (MTK_PIN_NO(11) | 1) +#define MT8365_PIN_11_GPIO11__FUNC_SPI_MO (MTK_PIN_NO(11) | 2) +#define MT8365_PIN_11_GPIO11__FUNC_I2S0_DI (MTK_PIN_NO(11) | 3) +#define MT8365_PIN_11_GPIO11__FUNC_EXT_RXD3 (MTK_PIN_NO(11) | 4) +#define MT8365_PIN_11_GPIO11__FUNC_CONN_DSP_JDO (MTK_PIN_NO(11) | 5) +#define MT8365_PIN_11_GPIO11__FUNC_DBG_MON_A11 (MTK_PIN_NO(11) | 7) + +#define MT8365_PIN_12_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +#define MT8365_PIN_12_GPIO12__FUNC_DPI_DE (MTK_PIN_NO(12) | 1) +#define MT8365_PIN_12_GPIO12__FUNC_UCTS1 (MTK_PIN_NO(12) | 2) +#define MT8365_PIN_12_GPIO12__FUNC_I2S3_BCK (MTK_PIN_NO(12) | 3) +#define MT8365_PIN_12_GPIO12__FUNC_EXT_TXEN (MTK_PIN_NO(12) | 4) +#define MT8365_PIN_12_GPIO12__FUNC_O_WIFI_TXD (MTK_PIN_NO(12) | 5) +#define MT8365_PIN_12_GPIO12__FUNC_DBG_MON_A12 (MTK_PIN_NO(12) | 7) + +#define MT8365_PIN_13_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) +#define MT8365_PIN_13_GPIO13__FUNC_DPI_VSYNC (MTK_PIN_NO(13) | 1) +#define MT8365_PIN_13_GPIO13__FUNC_URTS1 (MTK_PIN_NO(13) | 2) +#define MT8365_PIN_13_GPIO13__FUNC_I2S3_LRCK (MTK_PIN_NO(13) | 3) +#define MT8365_PIN_13_GPIO13__FUNC_EXT_COL (MTK_PIN_NO(13) | 4) +#define MT8365_PIN_13_GPIO13__FUNC_SPDIF_IN (MTK_PIN_NO(13) | 5) +#define MT8365_PIN_13_GPIO13__FUNC_DBG_MON_A13 (MTK_PIN_NO(13) | 7) + +#define MT8365_PIN_14_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) +#define MT8365_PIN_14_GPIO14__FUNC_DPI_CK (MTK_PIN_NO(14) | 1) +#define MT8365_PIN_14_GPIO14__FUNC_UCTS2 (MTK_PIN_NO(14) | 2) +#define MT8365_PIN_14_GPIO14__FUNC_I2S3_MCK (MTK_PIN_NO(14) | 3) +#define MT8365_PIN_14_GPIO14__FUNC_EXT_MDIO (MTK_PIN_NO(14) | 4) +#define MT8365_PIN_14_GPIO14__FUNC_SPDIF_OUT (MTK_PIN_NO(14) | 5) +#define MT8365_PIN_14_GPIO14__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(14) | 6) +#define MT8365_PIN_14_GPIO14__FUNC_DBG_MON_A14 (MTK_PIN_NO(14) | 7) + +#define MT8365_PIN_15_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) +#define MT8365_PIN_15_GPIO15__FUNC_DPI_HSYNC (MTK_PIN_NO(15) | 1) +#define MT8365_PIN_15_GPIO15__FUNC_URTS2 (MTK_PIN_NO(15) | 2) +#define MT8365_PIN_15_GPIO15__FUNC_I2S3_DO (MTK_PIN_NO(15) | 3) +#define MT8365_PIN_15_GPIO15__FUNC_EXT_MDC (MTK_PIN_NO(15) | 4) +#define MT8365_PIN_15_GPIO15__FUNC_IRRX (MTK_PIN_NO(15) | 5) +#define MT8365_PIN_15_GPIO15__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(15) | 6) +#define MT8365_PIN_15_GPIO15__FUNC_DBG_MON_A15 (MTK_PIN_NO(15) | 7) + +#define MT8365_PIN_16_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) +#define MT8365_PIN_16_GPIO16__FUNC_DPI_D12 (MTK_PIN_NO(16) | 1) +#define MT8365_PIN_16_GPIO16__FUNC_USB_DRVVBUS (MTK_PIN_NO(16) | 2) +#define MT8365_PIN_16_GPIO16__FUNC_PWM_A (MTK_PIN_NO(16) | 3) +#define MT8365_PIN_16_GPIO16__FUNC_CLKM0 (MTK_PIN_NO(16) | 4) +#define MT8365_PIN_16_GPIO16__FUNC_ANT_SEL0 (MTK_PIN_NO(16) | 5) +#define MT8365_PIN_16_GPIO16__FUNC_TSF_IN (MTK_PIN_NO(16) | 6) +#define MT8365_PIN_16_GPIO16__FUNC_DBG_MON_A16 (MTK_PIN_NO(16) | 7) + +#define MT8365_PIN_17_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) +#define MT8365_PIN_17_GPIO17__FUNC_DPI_D13 (MTK_PIN_NO(17) | 1) +#define MT8365_PIN_17_GPIO17__FUNC_IDDIG (MTK_PIN_NO(17) | 2) +#define MT8365_PIN_17_GPIO17__FUNC_PWM_B (MTK_PIN_NO(17) | 3) +#define MT8365_PIN_17_GPIO17__FUNC_CLKM1 (MTK_PIN_NO(17) | 4) +#define MT8365_PIN_17_GPIO17__FUNC_ANT_SEL1 (MTK_PIN_NO(17) | 5) +#define MT8365_PIN_17_GPIO17__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(17) | 6) +#define MT8365_PIN_17_GPIO17__FUNC_DBG_MON_A17 (MTK_PIN_NO(17) | 7) + +#define MT8365_PIN_18_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) +#define MT8365_PIN_18_GPIO18__FUNC_DPI_D14 (MTK_PIN_NO(18) | 1) +#define MT8365_PIN_18_GPIO18__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(18) | 2) +#define MT8365_PIN_18_GPIO18__FUNC_PWM_C (MTK_PIN_NO(18) | 3) +#define MT8365_PIN_18_GPIO18__FUNC_CLKM2 (MTK_PIN_NO(18) | 4) +#define MT8365_PIN_18_GPIO18__FUNC_ANT_SEL2 (MTK_PIN_NO(18) | 5) +#define MT8365_PIN_18_GPIO18__FUNC_MFG_TEST_CK (MTK_PIN_NO(18) | 6) +#define MT8365_PIN_18_GPIO18__FUNC_DBG_MON_A18 (MTK_PIN_NO(18) | 7) + +#define MT8365_PIN_19_DISP_PWM__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) +#define MT8365_PIN_19_DISP_PWM__FUNC_DISP_PWM (MTK_PIN_NO(19) | 1) +#define MT8365_PIN_19_DISP_PWM__FUNC_PWM_A (MTK_PIN_NO(19) | 2) +#define MT8365_PIN_19_DISP_PWM__FUNC_DBG_MON_A19 (MTK_PIN_NO(19) | 7) + +#define MT8365_PIN_20_LCM_RST__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) +#define MT8365_PIN_20_LCM_RST__FUNC_LCM_RST (MTK_PIN_NO(20) | 1) +#define MT8365_PIN_20_LCM_RST__FUNC_PWM_B (MTK_PIN_NO(20) | 2) +#define MT8365_PIN_20_LCM_RST__FUNC_DBG_MON_A20 (MTK_PIN_NO(20) | 7) + +#define MT8365_PIN_21_DSI_TE__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) +#define MT8365_PIN_21_DSI_TE__FUNC_DSI_TE (MTK_PIN_NO(21) | 1) +#define MT8365_PIN_21_DSI_TE__FUNC_PWM_C (MTK_PIN_NO(21) | 2) +#define MT8365_PIN_21_DSI_TE__FUNC_ANT_SEL0 (MTK_PIN_NO(21) | 3) +#define MT8365_PIN_21_DSI_TE__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(21) | 4) +#define MT8365_PIN_21_DSI_TE__FUNC_DBG_MON_A21 (MTK_PIN_NO(21) | 7) + +#define MT8365_PIN_22_KPROW0__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) +#define MT8365_PIN_22_KPROW0__FUNC_KPROW0 (MTK_PIN_NO(22) | 1) +#define MT8365_PIN_22_KPROW0__FUNC_DBG_MON_A22 (MTK_PIN_NO(22) | 7) + +#define MT8365_PIN_23_KPROW1__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) +#define MT8365_PIN_23_KPROW1__FUNC_KPROW1 (MTK_PIN_NO(23) | 1) +#define MT8365_PIN_23_KPROW1__FUNC_IDDIG (MTK_PIN_NO(23) | 2) +#define MT8365_PIN_23_KPROW1__FUNC_WIFI_TXD (MTK_PIN_NO(23) | 3) +#define MT8365_PIN_23_KPROW1__FUNC_CLKM3 (MTK_PIN_NO(23) | 4) +#define MT8365_PIN_23_KPROW1__FUNC_ANT_SEL1 (MTK_PIN_NO(23) | 5) +#define MT8365_PIN_23_KPROW1__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(23) | 6) +#define MT8365_PIN_23_KPROW1__FUNC_DBG_MON_B0 (MTK_PIN_NO(23) | 7) + +#define MT8365_PIN_24_KPCOL0__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) +#define MT8365_PIN_24_KPCOL0__FUNC_KPCOL0 (MTK_PIN_NO(24) | 1) +#define MT8365_PIN_24_KPCOL0__FUNC_DBG_MON_A23 (MTK_PIN_NO(24) | 7) + +#define MT8365_PIN_25_KPCOL1__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) +#define MT8365_PIN_25_KPCOL1__FUNC_KPCOL1 (MTK_PIN_NO(25) | 1) +#define MT8365_PIN_25_KPCOL1__FUNC_USB_DRVVBUS (MTK_PIN_NO(25) | 2) +#define MT8365_PIN_25_KPCOL1__FUNC_APU_JTAG_TRST (MTK_PIN_NO(25) | 3) +#define MT8365_PIN_25_KPCOL1__FUNC_UDI_NTRST_XI (MTK_PIN_NO(25) | 4) +#define MT8365_PIN_25_KPCOL1__FUNC_DFD_NTRST_XI (MTK_PIN_NO(25) | 5) +#define MT8365_PIN_25_KPCOL1__FUNC_CONN_TEST_CK (MTK_PIN_NO(25) | 6) +#define MT8365_PIN_25_KPCOL1__FUNC_DBG_MON_B1 (MTK_PIN_NO(25) | 7) + +#define MT8365_PIN_26_SPI_CS__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) +#define MT8365_PIN_26_SPI_CS__FUNC_SPI_CSB (MTK_PIN_NO(26) | 1) +#define MT8365_PIN_26_SPI_CS__FUNC_APU_JTAG_TMS (MTK_PIN_NO(26) | 3) +#define MT8365_PIN_26_SPI_CS__FUNC_UDI_TMS_XI (MTK_PIN_NO(26) | 4) +#define MT8365_PIN_26_SPI_CS__FUNC_DFD_TMS_XI (MTK_PIN_NO(26) | 5) +#define MT8365_PIN_26_SPI_CS__FUNC_CONN_TEST_CK (MTK_PIN_NO(26) | 6) +#define MT8365_PIN_26_SPI_CS__FUNC_DBG_MON_A24 (MTK_PIN_NO(26) | 7) + +#define MT8365_PIN_27_SPI_CK__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) +#define MT8365_PIN_27_SPI_CK__FUNC_SPI_CLK (MTK_PIN_NO(27) | 1) +#define MT8365_PIN_27_SPI_CK__FUNC_APU_JTAG_TCK (MTK_PIN_NO(27) | 3) +#define MT8365_PIN_27_SPI_CK__FUNC_UDI_TCK_XI (MTK_PIN_NO(27) | 4) +#define MT8365_PIN_27_SPI_CK__FUNC_DFD_TCK_XI (MTK_PIN_NO(27) | 5) +#define MT8365_PIN_27_SPI_CK__FUNC_APU_TEST_CK (MTK_PIN_NO(27) | 6) +#define MT8365_PIN_27_SPI_CK__FUNC_DBG_MON_A25 (MTK_PIN_NO(27) | 7) + +#define MT8365_PIN_28_SPI_MI__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) +#define MT8365_PIN_28_SPI_MI__FUNC_SPI_MI (MTK_PIN_NO(28) | 1) +#define MT8365_PIN_28_SPI_MI__FUNC_SPI_MO (MTK_PIN_NO(28) | 2) +#define MT8365_PIN_28_SPI_MI__FUNC_APU_JTAG_TDI (MTK_PIN_NO(28) | 3) +#define MT8365_PIN_28_SPI_MI__FUNC_UDI_TDI_XI (MTK_PIN_NO(28) | 4) +#define MT8365_PIN_28_SPI_MI__FUNC_DFD_TDI_XI (MTK_PIN_NO(28) | 5) +#define MT8365_PIN_28_SPI_MI__FUNC_DSP_TEST_CK (MTK_PIN_NO(28) | 6) +#define MT8365_PIN_28_SPI_MI__FUNC_DBG_MON_A26 (MTK_PIN_NO(28) | 7) + +#define MT8365_PIN_29_SPI_MO__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) +#define MT8365_PIN_29_SPI_MO__FUNC_SPI_MO (MTK_PIN_NO(29) | 1) +#define MT8365_PIN_29_SPI_MO__FUNC_SPI_MI (MTK_PIN_NO(29) | 2) +#define MT8365_PIN_29_SPI_MO__FUNC_APU_JTAG_TDO (MTK_PIN_NO(29) | 3) +#define MT8365_PIN_29_SPI_MO__FUNC_UDI_TDO (MTK_PIN_NO(29) | 4) +#define MT8365_PIN_29_SPI_MO__FUNC_DFD_TDO (MTK_PIN_NO(29) | 5) +#define MT8365_PIN_29_SPI_MO__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(29) | 6) +#define MT8365_PIN_29_SPI_MO__FUNC_DBG_MON_A27 (MTK_PIN_NO(29) | 7) + +#define MT8365_PIN_30_JTMS__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) +#define MT8365_PIN_30_JTMS__FUNC_JTMS (MTK_PIN_NO(30) | 1) +#define MT8365_PIN_30_JTMS__FUNC_DFD_TMS_XI (MTK_PIN_NO(30) | 2) +#define MT8365_PIN_30_JTMS__FUNC_UDI_TMS_XI (MTK_PIN_NO(30) | 3) +#define MT8365_PIN_30_JTMS__FUNC_MCU_SPM_TMS (MTK_PIN_NO(30) | 4) +#define MT8365_PIN_30_JTMS__FUNC_CONN_MCU_TMS (MTK_PIN_NO(30) | 5) +#define MT8365_PIN_30_JTMS__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(30) | 6) + +#define MT8365_PIN_31_JTCK__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) +#define MT8365_PIN_31_JTCK__FUNC_JTCK (MTK_PIN_NO(31) | 1) +#define MT8365_PIN_31_JTCK__FUNC_DFD_TCK_XI (MTK_PIN_NO(31) | 2) +#define MT8365_PIN_31_JTCK__FUNC_UDI_TCK_XI (MTK_PIN_NO(31) | 3) +#define MT8365_PIN_31_JTCK__FUNC_MCU_SPM_TCK (MTK_PIN_NO(31) | 4) +#define MT8365_PIN_31_JTCK__FUNC_CONN_MCU_TCK (MTK_PIN_NO(31) | 5) +#define MT8365_PIN_31_JTCK__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(31) | 6) + +#define MT8365_PIN_32_JTDI__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) +#define MT8365_PIN_32_JTDI__FUNC_JTDI (MTK_PIN_NO(32) | 1) +#define MT8365_PIN_32_JTDI__FUNC_DFD_TDI_XI (MTK_PIN_NO(32) | 2) +#define MT8365_PIN_32_JTDI__FUNC_UDI_TDI_XI (MTK_PIN_NO(32) | 3) +#define MT8365_PIN_32_JTDI__FUNC_MCU_SPM_TDI (MTK_PIN_NO(32) | 4) +#define MT8365_PIN_32_JTDI__FUNC_CONN_MCU_TDI (MTK_PIN_NO(32) | 5) + +#define MT8365_PIN_33_JTDO__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) +#define MT8365_PIN_33_JTDO__FUNC_JTDO (MTK_PIN_NO(33) | 1) +#define MT8365_PIN_33_JTDO__FUNC_DFD_TDO (MTK_PIN_NO(33) | 2) +#define MT8365_PIN_33_JTDO__FUNC_UDI_TDO (MTK_PIN_NO(33) | 3) +#define MT8365_PIN_33_JTDO__FUNC_MCU_SPM_TDO (MTK_PIN_NO(33) | 4) +#define MT8365_PIN_33_JTDO__FUNC_CONN_MCU_TDO (MTK_PIN_NO(33) | 5) + +#define MT8365_PIN_34_JTRST__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) +#define MT8365_PIN_34_JTRST__FUNC_JTRST (MTK_PIN_NO(34) | 1) +#define MT8365_PIN_34_JTRST__FUNC_DFD_NTRST_XI (MTK_PIN_NO(34) | 2) +#define MT8365_PIN_34_JTRST__FUNC_UDI_NTRST_XI (MTK_PIN_NO(34) | 3) +#define MT8365_PIN_34_JTRST__FUNC_MCU_SPM_NTRST (MTK_PIN_NO(34) | 4) +#define MT8365_PIN_34_JTRST__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(34) | 5) + +#define MT8365_PIN_35_URXD0__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) +#define MT8365_PIN_35_URXD0__FUNC_URXD0 (MTK_PIN_NO(35) | 1) +#define MT8365_PIN_35_URXD0__FUNC_UTXD0 (MTK_PIN_NO(35) | 2) +#define MT8365_PIN_35_URXD0__FUNC_DSP_URXD0 (MTK_PIN_NO(35) | 7) + +#define MT8365_PIN_36_UTXD0__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) +#define MT8365_PIN_36_UTXD0__FUNC_UTXD0 (MTK_PIN_NO(36) | 1) +#define MT8365_PIN_36_UTXD0__FUNC_URXD0 (MTK_PIN_NO(36) | 2) +#define MT8365_PIN_36_UTXD0__FUNC_DSP_UTXD0 (MTK_PIN_NO(36) | 7) + +#define MT8365_PIN_37_URXD1__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) +#define MT8365_PIN_37_URXD1__FUNC_URXD1 (MTK_PIN_NO(37) | 1) +#define MT8365_PIN_37_URXD1__FUNC_UTXD1 (MTK_PIN_NO(37) | 2) +#define MT8365_PIN_37_URXD1__FUNC_UCTS2 (MTK_PIN_NO(37) | 3) +#define MT8365_PIN_37_URXD1__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(37) | 4) +#define MT8365_PIN_37_URXD1__FUNC_CONN_UART0_RXD (MTK_PIN_NO(37) | 5) +#define MT8365_PIN_37_URXD1__FUNC_I2S0_MCK (MTK_PIN_NO(37) | 6) +#define MT8365_PIN_37_URXD1__FUNC_DSP_URXD0 (MTK_PIN_NO(37) | 7) + +#define MT8365_PIN_38_UTXD1__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) +#define MT8365_PIN_38_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(38) | 1) +#define MT8365_PIN_38_UTXD1__FUNC_URXD1 (MTK_PIN_NO(38) | 2) +#define MT8365_PIN_38_UTXD1__FUNC_URTS2 (MTK_PIN_NO(38) | 3) +#define MT8365_PIN_38_UTXD1__FUNC_ANT_SEL2 (MTK_PIN_NO(38) | 4) +#define MT8365_PIN_38_UTXD1__FUNC_CONN_UART0_TXD (MTK_PIN_NO(38) | 5) +#define MT8365_PIN_38_UTXD1__FUNC_I2S1_MCK (MTK_PIN_NO(38) | 6) +#define MT8365_PIN_38_UTXD1__FUNC_DSP_UTXD0 (MTK_PIN_NO(38) | 7) + +#define MT8365_PIN_39_URXD2__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) +#define MT8365_PIN_39_URXD2__FUNC_URXD2 (MTK_PIN_NO(39) | 1) +#define MT8365_PIN_39_URXD2__FUNC_UTXD2 (MTK_PIN_NO(39) | 2) +#define MT8365_PIN_39_URXD2__FUNC_UCTS1 (MTK_PIN_NO(39) | 3) +#define MT8365_PIN_39_URXD2__FUNC_IDDIG (MTK_PIN_NO(39) | 4) +#define MT8365_PIN_39_URXD2__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(39) | 5) +#define MT8365_PIN_39_URXD2__FUNC_I2S2_MCK (MTK_PIN_NO(39) | 6) +#define MT8365_PIN_39_URXD2__FUNC_DSP_URXD0 (MTK_PIN_NO(39) | 7) + +#define MT8365_PIN_40_UTXD2__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) +#define MT8365_PIN_40_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(40) | 1) +#define MT8365_PIN_40_UTXD2__FUNC_URXD2 (MTK_PIN_NO(40) | 2) +#define MT8365_PIN_40_UTXD2__FUNC_URTS1 (MTK_PIN_NO(40) | 3) +#define MT8365_PIN_40_UTXD2__FUNC_USB_DRVVBUS (MTK_PIN_NO(40) | 4) +#define MT8365_PIN_40_UTXD2__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(40) | 5) +#define MT8365_PIN_40_UTXD2__FUNC_I2S3_MCK (MTK_PIN_NO(40) | 6) +#define MT8365_PIN_40_UTXD2__FUNC_DSP_UTXD0 (MTK_PIN_NO(40) | 7) + +#define MT8365_PIN_41_PWRAP_SPI0_MI__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) +#define MT8365_PIN_41_PWRAP_SPI0_MI__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(41) | 1) +#define MT8365_PIN_41_PWRAP_SPI0_MI__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(41) | 2) + +#define MT8365_PIN_42_PWRAP_SPI0_MO__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) +#define MT8365_PIN_42_PWRAP_SPI0_MO__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(42) | 1) +#define MT8365_PIN_42_PWRAP_SPI0_MO__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(42) | 2) + +#define MT8365_PIN_43_PWRAP_SPI0_CK__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) +#define MT8365_PIN_43_PWRAP_SPI0_CK__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(43) | 1) + +#define MT8365_PIN_44_PWRAP_SPI0_CSN__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) +#define MT8365_PIN_44_PWRAP_SPI0_CSN__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(44) | 1) + +#define MT8365_PIN_45_RTC32K_CK__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) +#define MT8365_PIN_45_RTC32K_CK__FUNC_RTC32K_CK (MTK_PIN_NO(45) | 1) + +#define MT8365_PIN_46_WATCHDOG__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) +#define MT8365_PIN_46_WATCHDOG__FUNC_WATCHDOG (MTK_PIN_NO(46) | 1) + +#define MT8365_PIN_47_SRCLKENA0__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) +#define MT8365_PIN_47_SRCLKENA0__FUNC_SRCLKENA0 (MTK_PIN_NO(47) | 1) +#define MT8365_PIN_47_SRCLKENA0__FUNC_SRCLKENA1 (MTK_PIN_NO(47) | 2) + +#define MT8365_PIN_48_SRCLKENA1__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) +#define MT8365_PIN_48_SRCLKENA1__FUNC_SRCLKENA1 (MTK_PIN_NO(48) | 1) + +#define MT8365_PIN_49_AUD_CLK_MOSI__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) +#define MT8365_PIN_49_AUD_CLK_MOSI__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(49) | 1) +#define MT8365_PIN_49_AUD_CLK_MOSI__FUNC_AUD_CLK_MISO (MTK_PIN_NO(49) | 2) +#define MT8365_PIN_49_AUD_CLK_MOSI__FUNC_I2S1_MCK (MTK_PIN_NO(49) | 3) + +#define MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) +#define MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(50) | 1) +#define MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(50) | 2) +#define MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_I2S1_BCK (MTK_PIN_NO(50) | 3) + +#define MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) +#define MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(51) | 1) +#define MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(51) | 2) +#define MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_I2S1_LRCK (MTK_PIN_NO(51) | 3) + +#define MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) +#define MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(52) | 1) +#define MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(52) | 2) +#define MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_I2S1_DO (MTK_PIN_NO(52) | 3) + +#define MT8365_PIN_53_AUD_CLK_MISO__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) +#define MT8365_PIN_53_AUD_CLK_MISO__FUNC_AUD_CLK_MISO (MTK_PIN_NO(53) | 1) +#define MT8365_PIN_53_AUD_CLK_MISO__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(53) | 2) +#define MT8365_PIN_53_AUD_CLK_MISO__FUNC_I2S2_MCK (MTK_PIN_NO(53) | 3) + +#define MT8365_PIN_54_AUD_SYNC_MISO__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) +#define MT8365_PIN_54_AUD_SYNC_MISO__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(54) | 1) +#define MT8365_PIN_54_AUD_SYNC_MISO__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(54) | 2) +#define MT8365_PIN_54_AUD_SYNC_MISO__FUNC_I2S2_BCK (MTK_PIN_NO(54) | 3) + +#define MT8365_PIN_55_AUD_DAT_MISO0__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) +#define MT8365_PIN_55_AUD_DAT_MISO0__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(55) | 1) +#define MT8365_PIN_55_AUD_DAT_MISO0__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(55) | 2) +#define MT8365_PIN_55_AUD_DAT_MISO0__FUNC_I2S2_LRCK (MTK_PIN_NO(55) | 3) + +#define MT8365_PIN_56_AUD_DAT_MISO1__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) +#define MT8365_PIN_56_AUD_DAT_MISO1__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(56) | 1) +#define MT8365_PIN_56_AUD_DAT_MISO1__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(56) | 2) +#define MT8365_PIN_56_AUD_DAT_MISO1__FUNC_I2S2_DI (MTK_PIN_NO(56) | 3) + +#define MT8365_PIN_57_SDA0__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) +#define MT8365_PIN_57_SDA0__FUNC_SDA0_0 (MTK_PIN_NO(57) | 1) + +#define MT8365_PIN_58_SCL0__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) +#define MT8365_PIN_58_SCL0__FUNC_SCL0_0 (MTK_PIN_NO(58) | 1) + +#define MT8365_PIN_59_SDA1__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) +#define MT8365_PIN_59_SDA1__FUNC_SDA1_0 (MTK_PIN_NO(59) | 1) +#define MT8365_PIN_59_SDA1__FUNC_USB_SDA (MTK_PIN_NO(59) | 6) +#define MT8365_PIN_59_SDA1__FUNC_DBG_SDA (MTK_PIN_NO(59) | 7) + +#define MT8365_PIN_60_SCL1__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) +#define MT8365_PIN_60_SCL1__FUNC_SCL1_0 (MTK_PIN_NO(60) | 1) +#define MT8365_PIN_60_SCL1__FUNC_USB_SCL (MTK_PIN_NO(60) | 6) +#define MT8365_PIN_60_SCL1__FUNC_DBG_SCL (MTK_PIN_NO(60) | 7) + +#define MT8365_PIN_61_SDA2__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) +#define MT8365_PIN_61_SDA2__FUNC_SDA2_0 (MTK_PIN_NO(61) | 1) + +#define MT8365_PIN_62_SCL2__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) +#define MT8365_PIN_62_SCL2__FUNC_SCL2_0 (MTK_PIN_NO(62) | 1) + +#define MT8365_PIN_63_SDA3__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) +#define MT8365_PIN_63_SDA3__FUNC_SDA3_0 (MTK_PIN_NO(63) | 1) + +#define MT8365_PIN_64_SCL3__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) +#define MT8365_PIN_64_SCL3__FUNC_SCL3_0 (MTK_PIN_NO(64) | 1) + +#define MT8365_PIN_65_CMMCLK0__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) +#define MT8365_PIN_65_CMMCLK0__FUNC_CMMCLK0 (MTK_PIN_NO(65) | 1) +#define MT8365_PIN_65_CMMCLK0__FUNC_CMMCLK1 (MTK_PIN_NO(65) | 2) +#define MT8365_PIN_65_CMMCLK0__FUNC_DBG_MON_A28 (MTK_PIN_NO(65) | 7) + +#define MT8365_PIN_66_CMMCLK1__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) +#define MT8365_PIN_66_CMMCLK1__FUNC_CMMCLK1 (MTK_PIN_NO(66) | 1) +#define MT8365_PIN_66_CMMCLK1__FUNC_CMMCLK0 (MTK_PIN_NO(66) | 2) +#define MT8365_PIN_66_CMMCLK1__FUNC_DBG_MON_B2 (MTK_PIN_NO(66) | 7) + +#define MT8365_PIN_67_CMPCLK__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) +#define MT8365_PIN_67_CMPCLK__FUNC_CMPCLK (MTK_PIN_NO(67) | 1) +#define MT8365_PIN_67_CMPCLK__FUNC_ANT_SEL0 (MTK_PIN_NO(67) | 2) +#define MT8365_PIN_67_CMPCLK__FUNC_TDM_RX_BCK (MTK_PIN_NO(67) | 4) +#define MT8365_PIN_67_CMPCLK__FUNC_I2S0_BCK (MTK_PIN_NO(67) | 5) +#define MT8365_PIN_67_CMPCLK__FUNC_DBG_MON_B3 (MTK_PIN_NO(67) | 7) + +#define MT8365_PIN_68_CMDAT0__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) +#define MT8365_PIN_68_CMDAT0__FUNC_CMDAT0 (MTK_PIN_NO(68) | 1) +#define MT8365_PIN_68_CMDAT0__FUNC_ANT_SEL1 (MTK_PIN_NO(68) | 2) +#define MT8365_PIN_68_CMDAT0__FUNC_TDM_RX_LRCK (MTK_PIN_NO(68) | 4) +#define MT8365_PIN_68_CMDAT0__FUNC_I2S0_LRCK (MTK_PIN_NO(68) | 5) +#define MT8365_PIN_68_CMDAT0__FUNC_DBG_MON_B4 (MTK_PIN_NO(68) | 7) + +#define MT8365_PIN_69_CMDAT1__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) +#define MT8365_PIN_69_CMDAT1__FUNC_CMDAT1 (MTK_PIN_NO(69) | 1) +#define MT8365_PIN_69_CMDAT1__FUNC_ANT_SEL2 (MTK_PIN_NO(69) | 2) +#define MT8365_PIN_69_CMDAT1__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(69) | 3) +#define MT8365_PIN_69_CMDAT1__FUNC_TDM_RX_MCK (MTK_PIN_NO(69) | 4) +#define MT8365_PIN_69_CMDAT1__FUNC_I2S0_MCK (MTK_PIN_NO(69) | 5) +#define MT8365_PIN_69_CMDAT1__FUNC_DBG_MON_B5 (MTK_PIN_NO(69) | 7) + +#define MT8365_PIN_70_CMDAT2__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) +#define MT8365_PIN_70_CMDAT2__FUNC_CMDAT2 (MTK_PIN_NO(70) | 1) +#define MT8365_PIN_70_CMDAT2__FUNC_ANT_SEL3 (MTK_PIN_NO(70) | 2) +#define MT8365_PIN_70_CMDAT2__FUNC_TDM_RX_DI (MTK_PIN_NO(70) | 4) +#define MT8365_PIN_70_CMDAT2__FUNC_I2S0_DI (MTK_PIN_NO(70) | 5) +#define MT8365_PIN_70_CMDAT2__FUNC_DBG_MON_B6 (MTK_PIN_NO(70) | 7) + +#define MT8365_PIN_71_CMDAT3__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) +#define MT8365_PIN_71_CMDAT3__FUNC_CMDAT3 (MTK_PIN_NO(71) | 1) +#define MT8365_PIN_71_CMDAT3__FUNC_ANT_SEL4 (MTK_PIN_NO(71) | 2) +#define MT8365_PIN_71_CMDAT3__FUNC_DBG_MON_B7 (MTK_PIN_NO(71) | 7) + +#define MT8365_PIN_72_CMDAT4__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) +#define MT8365_PIN_72_CMDAT4__FUNC_CMDAT4 (MTK_PIN_NO(72) | 1) +#define MT8365_PIN_72_CMDAT4__FUNC_ANT_SEL5 (MTK_PIN_NO(72) | 2) +#define MT8365_PIN_72_CMDAT4__FUNC_I2S3_BCK (MTK_PIN_NO(72) | 5) +#define MT8365_PIN_72_CMDAT4__FUNC_DBG_MON_B8 (MTK_PIN_NO(72) | 7) + +#define MT8365_PIN_73_CMDAT5__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) +#define MT8365_PIN_73_CMDAT5__FUNC_CMDAT5 (MTK_PIN_NO(73) | 1) +#define MT8365_PIN_73_CMDAT5__FUNC_ANT_SEL6 (MTK_PIN_NO(73) | 2) +#define MT8365_PIN_73_CMDAT5__FUNC_I2S3_LRCK (MTK_PIN_NO(73) | 5) +#define MT8365_PIN_73_CMDAT5__FUNC_DBG_MON_B9 (MTK_PIN_NO(73) | 7) + +#define MT8365_PIN_74_CMDAT6__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) +#define MT8365_PIN_74_CMDAT6__FUNC_CMDAT6 (MTK_PIN_NO(74) | 1) +#define MT8365_PIN_74_CMDAT6__FUNC_ANT_SEL7 (MTK_PIN_NO(74) | 2) +#define MT8365_PIN_74_CMDAT6__FUNC_I2S3_MCK (MTK_PIN_NO(74) | 5) +#define MT8365_PIN_74_CMDAT6__FUNC_DBG_MON_B10 (MTK_PIN_NO(74) | 7) + +#define MT8365_PIN_75_CMDAT7__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) +#define MT8365_PIN_75_CMDAT7__FUNC_CMDAT7 (MTK_PIN_NO(75) | 1) +#define MT8365_PIN_75_CMDAT7__FUNC_I2S3_DO (MTK_PIN_NO(75) | 5) +#define MT8365_PIN_75_CMDAT7__FUNC_DBG_MON_B11 (MTK_PIN_NO(75) | 7) + +#define MT8365_PIN_76_CMDAT8__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) +#define MT8365_PIN_76_CMDAT8__FUNC_CMDAT8 (MTK_PIN_NO(76) | 1) +#define MT8365_PIN_76_CMDAT8__FUNC_PCM_CLK (MTK_PIN_NO(76) | 5) +#define MT8365_PIN_76_CMDAT8__FUNC_DBG_MON_A29 (MTK_PIN_NO(76) | 7) + +#define MT8365_PIN_77_CMDAT9__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) +#define MT8365_PIN_77_CMDAT9__FUNC_CMDAT9 (MTK_PIN_NO(77) | 1) +#define MT8365_PIN_77_CMDAT9__FUNC_PCM_SYNC (MTK_PIN_NO(77) | 5) +#define MT8365_PIN_77_CMDAT9__FUNC_DBG_MON_A30 (MTK_PIN_NO(77) | 7) + +#define MT8365_PIN_78_CMHSYNC__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) +#define MT8365_PIN_78_CMHSYNC__FUNC_CMHSYNC (MTK_PIN_NO(78) | 1) +#define MT8365_PIN_78_CMHSYNC__FUNC_PCM_RX (MTK_PIN_NO(78) | 5) +#define MT8365_PIN_78_CMHSYNC__FUNC_DBG_MON_A31 (MTK_PIN_NO(78) | 7) + +#define MT8365_PIN_79_CMVSYNC__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) +#define MT8365_PIN_79_CMVSYNC__FUNC_CMVSYNC (MTK_PIN_NO(79) | 1) +#define MT8365_PIN_79_CMVSYNC__FUNC_PCM_TX (MTK_PIN_NO(79) | 5) +#define MT8365_PIN_79_CMVSYNC__FUNC_DBG_MON_A32 (MTK_PIN_NO(79) | 7) + +#define MT8365_PIN_80_MSDC2_CMD__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) +#define MT8365_PIN_80_MSDC2_CMD__FUNC_MSDC2_CMD (MTK_PIN_NO(80) | 1) +#define MT8365_PIN_80_MSDC2_CMD__FUNC_TDM_TX_LRCK (MTK_PIN_NO(80) | 2) +#define MT8365_PIN_80_MSDC2_CMD__FUNC_UTXD1 (MTK_PIN_NO(80) | 3) +#define MT8365_PIN_80_MSDC2_CMD__FUNC_DPI_D19 (MTK_PIN_NO(80) | 4) +#define MT8365_PIN_80_MSDC2_CMD__FUNC_UDI_TMS_XI (MTK_PIN_NO(80) | 5) +#define MT8365_PIN_80_MSDC2_CMD__FUNC_ADSP_JTAG_TMS (MTK_PIN_NO(80) | 6) + +#define MT8365_PIN_81_MSDC2_CLK__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) +#define MT8365_PIN_81_MSDC2_CLK__FUNC_MSDC2_CLK (MTK_PIN_NO(81) | 1) +#define MT8365_PIN_81_MSDC2_CLK__FUNC_TDM_TX_BCK (MTK_PIN_NO(81) | 2) +#define MT8365_PIN_81_MSDC2_CLK__FUNC_URXD1 (MTK_PIN_NO(81) | 3) +#define MT8365_PIN_81_MSDC2_CLK__FUNC_DPI_D20 (MTK_PIN_NO(81) | 4) +#define MT8365_PIN_81_MSDC2_CLK__FUNC_UDI_TCK_XI (MTK_PIN_NO(81) | 5) +#define MT8365_PIN_81_MSDC2_CLK__FUNC_ADSP_JTAG_TCK (MTK_PIN_NO(81) | 6) + +#define MT8365_PIN_82_MSDC2_DAT0__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) +#define MT8365_PIN_82_MSDC2_DAT0__FUNC_MSDC2_DAT0 (MTK_PIN_NO(82) | 1) +#define MT8365_PIN_82_MSDC2_DAT0__FUNC_TDM_TX_DATA0 (MTK_PIN_NO(82) | 2) +#define MT8365_PIN_82_MSDC2_DAT0__FUNC_UTXD2 (MTK_PIN_NO(82) | 3) +#define MT8365_PIN_82_MSDC2_DAT0__FUNC_DPI_D21 (MTK_PIN_NO(82) | 4) +#define MT8365_PIN_82_MSDC2_DAT0__FUNC_UDI_TDI_XI (MTK_PIN_NO(82) | 5) +#define MT8365_PIN_82_MSDC2_DAT0__FUNC_ADSP_JTAG_TDI (MTK_PIN_NO(82) | 6) + +#define MT8365_PIN_83_MSDC2_DAT1__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) +#define MT8365_PIN_83_MSDC2_DAT1__FUNC_MSDC2_DAT1 (MTK_PIN_NO(83) | 1) +#define MT8365_PIN_83_MSDC2_DAT1__FUNC_TDM_TX_DATA1 (MTK_PIN_NO(83) | 2) +#define MT8365_PIN_83_MSDC2_DAT1__FUNC_URXD2 (MTK_PIN_NO(83) | 3) +#define MT8365_PIN_83_MSDC2_DAT1__FUNC_DPI_D22 (MTK_PIN_NO(83) | 4) +#define MT8365_PIN_83_MSDC2_DAT1__FUNC_UDI_TDO (MTK_PIN_NO(83) | 5) +#define MT8365_PIN_83_MSDC2_DAT1__FUNC_ADSP_JTAG_TDO (MTK_PIN_NO(83) | 6) + +#define MT8365_PIN_84_MSDC2_DAT2__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) +#define MT8365_PIN_84_MSDC2_DAT2__FUNC_MSDC2_DAT2 (MTK_PIN_NO(84) | 1) +#define MT8365_PIN_84_MSDC2_DAT2__FUNC_TDM_TX_DATA2 (MTK_PIN_NO(84) | 2) +#define MT8365_PIN_84_MSDC2_DAT2__FUNC_PWM_A (MTK_PIN_NO(84) | 3) +#define MT8365_PIN_84_MSDC2_DAT2__FUNC_DPI_D23 (MTK_PIN_NO(84) | 4) +#define MT8365_PIN_84_MSDC2_DAT2__FUNC_UDI_NTRST_XI (MTK_PIN_NO(84) | 5) +#define MT8365_PIN_84_MSDC2_DAT2__FUNC_ADSP_JTAG_TRST (MTK_PIN_NO(84) | 6) + +#define MT8365_PIN_85_MSDC2_DAT3__FUNC_GPIO85 (MTK_PIN_NO(85) | 0) +#define MT8365_PIN_85_MSDC2_DAT3__FUNC_MSDC2_DAT3 (MTK_PIN_NO(85) | 1) +#define MT8365_PIN_85_MSDC2_DAT3__FUNC_TDM_TX_DATA3 (MTK_PIN_NO(85) | 2) +#define MT8365_PIN_85_MSDC2_DAT3__FUNC_PWM_B (MTK_PIN_NO(85) | 3) +#define MT8365_PIN_85_MSDC2_DAT3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(85) | 5) + +#define MT8365_PIN_86_MSDC2_DSL__FUNC_GPIO86 (MTK_PIN_NO(86) | 0) +#define MT8365_PIN_86_MSDC2_DSL__FUNC_MSDC2_DSL (MTK_PIN_NO(86) | 1) +#define MT8365_PIN_86_MSDC2_DSL__FUNC_TDM_TX_MCK (MTK_PIN_NO(86) | 2) +#define MT8365_PIN_86_MSDC2_DSL__FUNC_PWM_C (MTK_PIN_NO(86) | 3) + +#define MT8365_PIN_87_MSDC1_CMD__FUNC_GPIO87 (MTK_PIN_NO(87) | 0) +#define MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(87) | 1) +#define MT8365_PIN_87_MSDC1_CMD__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(87) | 2) +#define MT8365_PIN_87_MSDC1_CMD__FUNC_DFD_TMS_XI (MTK_PIN_NO(87) | 3) +#define MT8365_PIN_87_MSDC1_CMD__FUNC_APU_JTAG_TMS (MTK_PIN_NO(87) | 4) +#define MT8365_PIN_87_MSDC1_CMD__FUNC_MCU_SPM_TMS (MTK_PIN_NO(87) | 5) +#define MT8365_PIN_87_MSDC1_CMD__FUNC_CONN_DSP_JMS (MTK_PIN_NO(87) | 6) +#define MT8365_PIN_87_MSDC1_CMD__FUNC_ADSP_JTAG_TMS (MTK_PIN_NO(87) | 7) + +#define MT8365_PIN_88_MSDC1_CLK__FUNC_GPIO88 (MTK_PIN_NO(88) | 0) +#define MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(88) | 1) +#define MT8365_PIN_88_MSDC1_CLK__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(88) | 2) +#define MT8365_PIN_88_MSDC1_CLK__FUNC_DFD_TCK_XI (MTK_PIN_NO(88) | 3) +#define MT8365_PIN_88_MSDC1_CLK__FUNC_APU_JTAG_TCK (MTK_PIN_NO(88) | 4) +#define MT8365_PIN_88_MSDC1_CLK__FUNC_MCU_SPM_TCK (MTK_PIN_NO(88) | 5) +#define MT8365_PIN_88_MSDC1_CLK__FUNC_CONN_DSP_JCK (MTK_PIN_NO(88) | 6) +#define MT8365_PIN_88_MSDC1_CLK__FUNC_ADSP_JTAG_TCK (MTK_PIN_NO(88) | 7) + +#define MT8365_PIN_89_MSDC1_DAT0__FUNC_GPIO89 (MTK_PIN_NO(89) | 0) +#define MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(89) | 1) +#define MT8365_PIN_89_MSDC1_DAT0__FUNC_PWM_C (MTK_PIN_NO(89) | 2) +#define MT8365_PIN_89_MSDC1_DAT0__FUNC_DFD_TDI_XI (MTK_PIN_NO(89) | 3) +#define MT8365_PIN_89_MSDC1_DAT0__FUNC_APU_JTAG_TDI (MTK_PIN_NO(89) | 4) +#define MT8365_PIN_89_MSDC1_DAT0__FUNC_MCU_SPM_TDI (MTK_PIN_NO(89) | 5) +#define MT8365_PIN_89_MSDC1_DAT0__FUNC_CONN_DSP_JDI (MTK_PIN_NO(89) | 6) +#define MT8365_PIN_89_MSDC1_DAT0__FUNC_ADSP_JTAG_TDI (MTK_PIN_NO(89) | 7) + +#define MT8365_PIN_90_MSDC1_DAT1__FUNC_GPIO90 (MTK_PIN_NO(90) | 0) +#define MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(90) | 1) +#define MT8365_PIN_90_MSDC1_DAT1__FUNC_SPDIF_IN (MTK_PIN_NO(90) | 2) +#define MT8365_PIN_90_MSDC1_DAT1__FUNC_DFD_TDO (MTK_PIN_NO(90) | 3) +#define MT8365_PIN_90_MSDC1_DAT1__FUNC_APU_JTAG_TDO (MTK_PIN_NO(90) | 4) +#define MT8365_PIN_90_MSDC1_DAT1__FUNC_MCU_SPM_TDO (MTK_PIN_NO(90) | 5) +#define MT8365_PIN_90_MSDC1_DAT1__FUNC_CONN_DSP_JDO (MTK_PIN_NO(90) | 6) +#define MT8365_PIN_90_MSDC1_DAT1__FUNC_ADSP_JTAG_TDO (MTK_PIN_NO(90) | 7) + +#define MT8365_PIN_91_MSDC1_DAT2__FUNC_GPIO91 (MTK_PIN_NO(91) | 0) +#define MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(91) | 1) +#define MT8365_PIN_91_MSDC1_DAT2__FUNC_SPDIF_OUT (MTK_PIN_NO(91) | 2) +#define MT8365_PIN_91_MSDC1_DAT2__FUNC_DFD_NTRST_XI (MTK_PIN_NO(91) | 3) +#define MT8365_PIN_91_MSDC1_DAT2__FUNC_APU_JTAG_TRST (MTK_PIN_NO(91) | 4) +#define MT8365_PIN_91_MSDC1_DAT2__FUNC_MCU_SPM_NTRST (MTK_PIN_NO(91) | 5) +#define MT8365_PIN_91_MSDC1_DAT2__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(91) | 6) +#define MT8365_PIN_91_MSDC1_DAT2__FUNC_ADSP_JTAG_TRST (MTK_PIN_NO(91) | 7) + +#define MT8365_PIN_92_MSDC1_DAT3__FUNC_GPIO92 (MTK_PIN_NO(92) | 0) +#define MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(92) | 1) +#define MT8365_PIN_92_MSDC1_DAT3__FUNC_IRRX (MTK_PIN_NO(92) | 2) +#define MT8365_PIN_92_MSDC1_DAT3__FUNC_PWM_A (MTK_PIN_NO(92) | 3) + +#define MT8365_PIN_93_MSDC0_DAT7__FUNC_GPIO93 (MTK_PIN_NO(93) | 0) +#define MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(93) | 1) +#define MT8365_PIN_93_MSDC0_DAT7__FUNC_NLD7 (MTK_PIN_NO(93) | 2) + +#define MT8365_PIN_94_MSDC0_DAT6__FUNC_GPIO94 (MTK_PIN_NO(94) | 0) +#define MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(94) | 1) +#define MT8365_PIN_94_MSDC0_DAT6__FUNC_NLD6 (MTK_PIN_NO(94) | 2) + +#define MT8365_PIN_95_MSDC0_DAT5__FUNC_GPIO95 (MTK_PIN_NO(95) | 0) +#define MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(95) | 1) +#define MT8365_PIN_95_MSDC0_DAT5__FUNC_NLD4 (MTK_PIN_NO(95) | 2) + +#define MT8365_PIN_96_MSDC0_DAT4__FUNC_GPIO96 (MTK_PIN_NO(96) | 0) +#define MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(96) | 1) +#define MT8365_PIN_96_MSDC0_DAT4__FUNC_NLD3 (MTK_PIN_NO(96) | 2) + +#define MT8365_PIN_97_MSDC0_RSTB__FUNC_GPIO97 (MTK_PIN_NO(97) | 0) +#define MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB (MTK_PIN_NO(97) | 1) +#define MT8365_PIN_97_MSDC0_RSTB__FUNC_NLD0 (MTK_PIN_NO(97) | 2) + +#define MT8365_PIN_98_MSDC0_CMD__FUNC_GPIO98 (MTK_PIN_NO(98) | 0) +#define MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(98) | 1) +#define MT8365_PIN_98_MSDC0_CMD__FUNC_NALE (MTK_PIN_NO(98) | 2) + +#define MT8365_PIN_99_MSDC0_CLK__FUNC_GPIO99 (MTK_PIN_NO(99) | 0) +#define MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(99) | 1) +#define MT8365_PIN_99_MSDC0_CLK__FUNC_NWEB (MTK_PIN_NO(99) | 2) + +#define MT8365_PIN_100_MSDC0_DAT3__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) +#define MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(100) | 1) +#define MT8365_PIN_100_MSDC0_DAT3__FUNC_NLD1 (MTK_PIN_NO(100) | 2) + +#define MT8365_PIN_101_MSDC0_DAT2__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) +#define MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(101) | 1) +#define MT8365_PIN_101_MSDC0_DAT2__FUNC_NLD5 (MTK_PIN_NO(101) | 2) + +#define MT8365_PIN_102_MSDC0_DAT1__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) +#define MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(102) | 1) +#define MT8365_PIN_102_MSDC0_DAT1__FUNC_NDQS (MTK_PIN_NO(102) | 2) + +#define MT8365_PIN_103_MSDC0_DAT0__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) +#define MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(103) | 1) +#define MT8365_PIN_103_MSDC0_DAT0__FUNC_NLD2 (MTK_PIN_NO(103) | 2) + +#define MT8365_PIN_104_MSDC0_DSL__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) +#define MT8365_PIN_104_MSDC0_DSL__FUNC_MSDC0_DSL (MTK_PIN_NO(104) | 1) + +#define MT8365_PIN_105_NCLE__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) +#define MT8365_PIN_105_NCLE__FUNC_NCLE (MTK_PIN_NO(105) | 1) +#define MT8365_PIN_105_NCLE__FUNC_TDM_RX_MCK (MTK_PIN_NO(105) | 2) +#define MT8365_PIN_105_NCLE__FUNC_DBG_MON_B12 (MTK_PIN_NO(105) | 7) + +#define MT8365_PIN_106_NCEB1__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) +#define MT8365_PIN_106_NCEB1__FUNC_NCEB1 (MTK_PIN_NO(106) | 1) +#define MT8365_PIN_106_NCEB1__FUNC_TDM_RX_BCK (MTK_PIN_NO(106) | 2) +#define MT8365_PIN_106_NCEB1__FUNC_DBG_MON_B13 (MTK_PIN_NO(106) | 7) + +#define MT8365_PIN_107_NCEB0__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) +#define MT8365_PIN_107_NCEB0__FUNC_NCEB0 (MTK_PIN_NO(107) | 1) +#define MT8365_PIN_107_NCEB0__FUNC_TDM_RX_LRCK (MTK_PIN_NO(107) | 2) +#define MT8365_PIN_107_NCEB0__FUNC_DBG_MON_B14 (MTK_PIN_NO(107) | 7) + +#define MT8365_PIN_108_NREB__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) +#define MT8365_PIN_108_NREB__FUNC_NREB (MTK_PIN_NO(108) | 1) +#define MT8365_PIN_108_NREB__FUNC_TDM_RX_DI (MTK_PIN_NO(108) | 2) +#define MT8365_PIN_108_NREB__FUNC_DBG_MON_B15 (MTK_PIN_NO(108) | 7) + +#define MT8365_PIN_109_NRNB__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) +#define MT8365_PIN_109_NRNB__FUNC_NRNB (MTK_PIN_NO(109) | 1) +#define MT8365_PIN_109_NRNB__FUNC_TSF_IN (MTK_PIN_NO(109) | 2) +#define MT8365_PIN_109_NRNB__FUNC_DBG_MON_B16 (MTK_PIN_NO(109) | 7) + +#define MT8365_PIN_110_PCM_CLK__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) +#define MT8365_PIN_110_PCM_CLK__FUNC_PCM_CLK (MTK_PIN_NO(110) | 1) +#define MT8365_PIN_110_PCM_CLK__FUNC_I2S0_BCK (MTK_PIN_NO(110) | 2) +#define MT8365_PIN_110_PCM_CLK__FUNC_I2S3_BCK (MTK_PIN_NO(110) | 3) +#define MT8365_PIN_110_PCM_CLK__FUNC_SPDIF_IN (MTK_PIN_NO(110) | 4) +#define MT8365_PIN_110_PCM_CLK__FUNC_DPI_D15 (MTK_PIN_NO(110) | 5) + +#define MT8365_PIN_111_PCM_SYNC__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) +#define MT8365_PIN_111_PCM_SYNC__FUNC_PCM_SYNC (MTK_PIN_NO(111) | 1) +#define MT8365_PIN_111_PCM_SYNC__FUNC_I2S0_LRCK (MTK_PIN_NO(111) | 2) +#define MT8365_PIN_111_PCM_SYNC__FUNC_I2S3_LRCK (MTK_PIN_NO(111) | 3) +#define MT8365_PIN_111_PCM_SYNC__FUNC_SPDIF_OUT (MTK_PIN_NO(111) | 4) +#define MT8365_PIN_111_PCM_SYNC__FUNC_DPI_D16 (MTK_PIN_NO(111) | 5) + +#define MT8365_PIN_112_PCM_RX__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) +#define MT8365_PIN_112_PCM_RX__FUNC_PCM_RX (MTK_PIN_NO(112) | 1) +#define MT8365_PIN_112_PCM_RX__FUNC_I2S0_DI (MTK_PIN_NO(112) | 2) +#define MT8365_PIN_112_PCM_RX__FUNC_I2S3_MCK (MTK_PIN_NO(112) | 3) +#define MT8365_PIN_112_PCM_RX__FUNC_IRRX (MTK_PIN_NO(112) | 4) +#define MT8365_PIN_112_PCM_RX__FUNC_DPI_D17 (MTK_PIN_NO(112) | 5) + +#define MT8365_PIN_113_PCM_TX__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) +#define MT8365_PIN_113_PCM_TX__FUNC_PCM_TX (MTK_PIN_NO(113) | 1) +#define MT8365_PIN_113_PCM_TX__FUNC_I2S0_MCK (MTK_PIN_NO(113) | 2) +#define MT8365_PIN_113_PCM_TX__FUNC_I2S3_DO (MTK_PIN_NO(113) | 3) +#define MT8365_PIN_113_PCM_TX__FUNC_PWM_B (MTK_PIN_NO(113) | 4) +#define MT8365_PIN_113_PCM_TX__FUNC_DPI_D18 (MTK_PIN_NO(113) | 5) + +#define MT8365_PIN_114_I2S_DATA_IN__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) +#define MT8365_PIN_114_I2S_DATA_IN__FUNC_I2S0_DI (MTK_PIN_NO(114) | 1) +#define MT8365_PIN_114_I2S_DATA_IN__FUNC_I2S1_DO (MTK_PIN_NO(114) | 2) +#define MT8365_PIN_114_I2S_DATA_IN__FUNC_I2S2_DI (MTK_PIN_NO(114) | 3) +#define MT8365_PIN_114_I2S_DATA_IN__FUNC_I2S3_DO (MTK_PIN_NO(114) | 4) +#define MT8365_PIN_114_I2S_DATA_IN__FUNC_PWM_A (MTK_PIN_NO(114) | 5) +#define MT8365_PIN_114_I2S_DATA_IN__FUNC_SPDIF_IN (MTK_PIN_NO(114) | 6) +#define MT8365_PIN_114_I2S_DATA_IN__FUNC_DBG_MON_B17 (MTK_PIN_NO(114) | 7) + +#define MT8365_PIN_115_I2S_LRCK__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) +#define MT8365_PIN_115_I2S_LRCK__FUNC_I2S0_LRCK (MTK_PIN_NO(115) | 1) +#define MT8365_PIN_115_I2S_LRCK__FUNC_I2S1_LRCK (MTK_PIN_NO(115) | 2) +#define MT8365_PIN_115_I2S_LRCK__FUNC_I2S2_LRCK (MTK_PIN_NO(115) | 3) +#define MT8365_PIN_115_I2S_LRCK__FUNC_I2S3_LRCK (MTK_PIN_NO(115) | 4) +#define MT8365_PIN_115_I2S_LRCK__FUNC_PWM_B (MTK_PIN_NO(115) | 5) +#define MT8365_PIN_115_I2S_LRCK__FUNC_SPDIF_OUT (MTK_PIN_NO(115) | 6) +#define MT8365_PIN_115_I2S_LRCK__FUNC_DBG_MON_B18 (MTK_PIN_NO(115) | 7) + +#define MT8365_PIN_116_I2S_BCK__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) +#define MT8365_PIN_116_I2S_BCK__FUNC_I2S0_BCK (MTK_PIN_NO(116) | 1) +#define MT8365_PIN_116_I2S_BCK__FUNC_I2S1_BCK (MTK_PIN_NO(116) | 2) +#define MT8365_PIN_116_I2S_BCK__FUNC_I2S2_BCK (MTK_PIN_NO(116) | 3) +#define MT8365_PIN_116_I2S_BCK__FUNC_I2S3_BCK (MTK_PIN_NO(116) | 4) +#define MT8365_PIN_116_I2S_BCK__FUNC_PWM_C (MTK_PIN_NO(116) | 5) +#define MT8365_PIN_116_I2S_BCK__FUNC_IRRX (MTK_PIN_NO(116) | 6) +#define MT8365_PIN_116_I2S_BCK__FUNC_DBG_MON_B19 (MTK_PIN_NO(116) | 7) + +#define MT8365_PIN_117_DMIC0_CLK__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) +#define MT8365_PIN_117_DMIC0_CLK__FUNC_DMIC0_CLK (MTK_PIN_NO(117) | 1) +#define MT8365_PIN_117_DMIC0_CLK__FUNC_I2S2_BCK (MTK_PIN_NO(117) | 2) +#define MT8365_PIN_117_DMIC0_CLK__FUNC_DBG_MON_B20 (MTK_PIN_NO(117) | 7) + +#define MT8365_PIN_118_DMIC0_DAT0__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) +#define MT8365_PIN_118_DMIC0_DAT0__FUNC_DMIC0_DAT0 (MTK_PIN_NO(118) | 1) +#define MT8365_PIN_118_DMIC0_DAT0__FUNC_I2S2_DI (MTK_PIN_NO(118) | 2) +#define MT8365_PIN_118_DMIC0_DAT0__FUNC_DBG_MON_B21 (MTK_PIN_NO(118) | 7) + +#define MT8365_PIN_119_DMIC0_DAT1__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) +#define MT8365_PIN_119_DMIC0_DAT1__FUNC_DMIC0_DAT1 (MTK_PIN_NO(119) | 1) +#define MT8365_PIN_119_DMIC0_DAT1__FUNC_I2S2_LRCK (MTK_PIN_NO(119) | 2) +#define MT8365_PIN_119_DMIC0_DAT1__FUNC_DBG_MON_B22 (MTK_PIN_NO(119) | 7) + +#define MT8365_PIN_120_DMIC1_CLK__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) +#define MT8365_PIN_120_DMIC1_CLK__FUNC_DMIC1_CLK (MTK_PIN_NO(120) | 1) +#define MT8365_PIN_120_DMIC1_CLK__FUNC_I2S2_MCK (MTK_PIN_NO(120) | 2) +#define MT8365_PIN_120_DMIC1_CLK__FUNC_DBG_MON_B23 (MTK_PIN_NO(120) | 7) + +#define MT8365_PIN_121_DMIC1_DAT0__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) +#define MT8365_PIN_121_DMIC1_DAT0__FUNC_DMIC1_DAT0 (MTK_PIN_NO(121) | 1) +#define MT8365_PIN_121_DMIC1_DAT0__FUNC_I2S1_BCK (MTK_PIN_NO(121) | 2) +#define MT8365_PIN_121_DMIC1_DAT0__FUNC_DBG_MON_B24 (MTK_PIN_NO(121) | 7) + +#define MT8365_PIN_122_DMIC1_DAT1__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) +#define MT8365_PIN_122_DMIC1_DAT1__FUNC_DMIC1_DAT1 (MTK_PIN_NO(122) | 1) +#define MT8365_PIN_122_DMIC1_DAT1__FUNC_I2S1_LRCK (MTK_PIN_NO(122) | 2) +#define MT8365_PIN_122_DMIC1_DAT1__FUNC_DBG_MON_B25 (MTK_PIN_NO(122) | 7) + +#define MT8365_PIN_123_DMIC2_CLK__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) +#define MT8365_PIN_123_DMIC2_CLK__FUNC_DMIC2_CLK (MTK_PIN_NO(123) | 1) +#define MT8365_PIN_123_DMIC2_CLK__FUNC_I2S1_MCK (MTK_PIN_NO(123) | 2) +#define MT8365_PIN_123_DMIC2_CLK__FUNC_DBG_MON_B26 (MTK_PIN_NO(123) | 7) + +#define MT8365_PIN_124_DMIC2_DAT0__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) +#define MT8365_PIN_124_DMIC2_DAT0__FUNC_DMIC2_DAT0 (MTK_PIN_NO(124) | 1) +#define MT8365_PIN_124_DMIC2_DAT0__FUNC_I2S1_DO (MTK_PIN_NO(124) | 2) +#define MT8365_PIN_124_DMIC2_DAT0__FUNC_DBG_MON_B27 (MTK_PIN_NO(124) | 7) + +#define MT8365_PIN_125_DMIC2_DAT1__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) +#define MT8365_PIN_125_DMIC2_DAT1__FUNC_DMIC2_DAT1 (MTK_PIN_NO(125) | 1) +#define MT8365_PIN_125_DMIC2_DAT1__FUNC_TDM_RX_BCK (MTK_PIN_NO(125) | 2) +#define MT8365_PIN_125_DMIC2_DAT1__FUNC_DBG_MON_B28 (MTK_PIN_NO(125) | 7) + +#define MT8365_PIN_126_DMIC3_CLK__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) +#define MT8365_PIN_126_DMIC3_CLK__FUNC_DMIC3_CLK (MTK_PIN_NO(126) | 1) +#define MT8365_PIN_126_DMIC3_CLK__FUNC_TDM_RX_LRCK (MTK_PIN_NO(126) | 2) + +#define MT8365_PIN_127_DMIC3_DAT0__FUNC_GPIO127 (MTK_PIN_NO(127) | 0) +#define MT8365_PIN_127_DMIC3_DAT0__FUNC_DMIC3_DAT0 (MTK_PIN_NO(127) | 1) +#define MT8365_PIN_127_DMIC3_DAT0__FUNC_TDM_RX_DI (MTK_PIN_NO(127) | 2) + +#define MT8365_PIN_128_DMIC3_DAT1__FUNC_GPIO128 (MTK_PIN_NO(128) | 0) +#define MT8365_PIN_128_DMIC3_DAT1__FUNC_DMIC3_DAT1 (MTK_PIN_NO(128) | 1) +#define MT8365_PIN_128_DMIC3_DAT1__FUNC_TDM_RX_MCK (MTK_PIN_NO(128) | 2) +#define MT8365_PIN_128_DMIC3_DAT1__FUNC_VAD_CLK (MTK_PIN_NO(128) | 3) + +#define MT8365_PIN_129_TDM_TX_BCK__FUNC_GPIO129 (MTK_PIN_NO(129) | 0) +#define MT8365_PIN_129_TDM_TX_BCK__FUNC_TDM_TX_BCK (MTK_PIN_NO(129) | 1) +#define MT8365_PIN_129_TDM_TX_BCK__FUNC_I2S3_BCK (MTK_PIN_NO(129) | 2) +#define MT8365_PIN_129_TDM_TX_BCK__FUNC_ckmon1_ck (MTK_PIN_NO(129) | 3) + +#define MT8365_PIN_130_TDM_TX_LRCK__FUNC_GPIO130 (MTK_PIN_NO(130) | 0) +#define MT8365_PIN_130_TDM_TX_LRCK__FUNC_TDM_TX_LRCK (MTK_PIN_NO(130) | 1) +#define MT8365_PIN_130_TDM_TX_LRCK__FUNC_I2S3_LRCK (MTK_PIN_NO(130) | 2) +#define MT8365_PIN_130_TDM_TX_LRCK__FUNC_ckmon2_ck (MTK_PIN_NO(130) | 3) + +#define MT8365_PIN_131_TDM_TX_MCK__FUNC_GPIO131 (MTK_PIN_NO(131) | 0) +#define MT8365_PIN_131_TDM_TX_MCK__FUNC_TDM_TX_MCK (MTK_PIN_NO(131) | 1) +#define MT8365_PIN_131_TDM_TX_MCK__FUNC_I2S3_MCK (MTK_PIN_NO(131) | 2) +#define MT8365_PIN_131_TDM_TX_MCK__FUNC_ckmon3_ck (MTK_PIN_NO(131) | 3) + +#define MT8365_PIN_132_TDM_TX_DATA0__FUNC_GPIO132 (MTK_PIN_NO(132) | 0) +#define MT8365_PIN_132_TDM_TX_DATA0__FUNC_TDM_TX_DATA0 (MTK_PIN_NO(132) | 1) +#define MT8365_PIN_132_TDM_TX_DATA0__FUNC_I2S3_DO (MTK_PIN_NO(132) | 2) +#define MT8365_PIN_132_TDM_TX_DATA0__FUNC_ckmon4_ck (MTK_PIN_NO(132) | 3) +#define MT8365_PIN_132_TDM_TX_DATA0__FUNC_DBG_MON_B29 (MTK_PIN_NO(132) | 7) + +#define MT8365_PIN_133_TDM_TX_DATA1__FUNC_GPIO133 (MTK_PIN_NO(133) | 0) +#define MT8365_PIN_133_TDM_TX_DATA1__FUNC_TDM_TX_DATA1 (MTK_PIN_NO(133) | 1) +#define MT8365_PIN_133_TDM_TX_DATA1__FUNC_DBG_MON_B30 (MTK_PIN_NO(133) | 7) + +#define MT8365_PIN_134_TDM_TX_DATA2__FUNC_GPIO134 (MTK_PIN_NO(134) | 0) +#define MT8365_PIN_134_TDM_TX_DATA2__FUNC_TDM_TX_DATA2 (MTK_PIN_NO(134) | 1) +#define MT8365_PIN_134_TDM_TX_DATA2__FUNC_DBG_MON_B31 (MTK_PIN_NO(134) | 7) + +#define MT8365_PIN_135_TDM_TX_DATA3__FUNC_GPIO135 (MTK_PIN_NO(135) | 0) +#define MT8365_PIN_135_TDM_TX_DATA3__FUNC_TDM_TX_DATA3 (MTK_PIN_NO(135) | 1) +#define MT8365_PIN_135_TDM_TX_DATA3__FUNC_DBG_MON_B32 (MTK_PIN_NO(135) | 7) + +#define MT8365_PIN_136_CONN_TOP_CLK__FUNC_GPIO136 (MTK_PIN_NO(136) | 0) +#define MT8365_PIN_136_CONN_TOP_CLK__FUNC_CONN_TOP_CLK (MTK_PIN_NO(136) | 1) + +#define MT8365_PIN_137_CONN_TOP_DATA__FUNC_GPIO137 (MTK_PIN_NO(137) | 0) +#define MT8365_PIN_137_CONN_TOP_DATA__FUNC_CONN_TOP_DATA (MTK_PIN_NO(137) | 1) + +#define MT8365_PIN_138_CONN_HRST_B__FUNC_GPIO138 (MTK_PIN_NO(138) | 0) +#define MT8365_PIN_138_CONN_HRST_B__FUNC_CONN_HRST_B (MTK_PIN_NO(138) | 1) + +#define MT8365_PIN_139_CONN_WB_PTA__FUNC_GPIO139 (MTK_PIN_NO(139) | 0) +#define MT8365_PIN_139_CONN_WB_PTA__FUNC_CONN_WB_PTA (MTK_PIN_NO(139) | 1) + +#define MT8365_PIN_140_CONN_BT_CLK__FUNC_GPIO140 (MTK_PIN_NO(140) | 0) +#define MT8365_PIN_140_CONN_BT_CLK__FUNC_CONN_BT_CLK (MTK_PIN_NO(140) | 1) + +#define MT8365_PIN_141_CONN_BT_DATA__FUNC_GPIO141 (MTK_PIN_NO(141) | 0) +#define MT8365_PIN_141_CONN_BT_DATA__FUNC_CONN_BT_DATA (MTK_PIN_NO(141) | 1) + +#define MT8365_PIN_142_CONN_WF_CTRL0__FUNC_GPIO142 (MTK_PIN_NO(142) | 0) +#define MT8365_PIN_142_CONN_WF_CTRL0__FUNC_CONN_WF_CTRL0 (MTK_PIN_NO(142) | 1) + +#define MT8365_PIN_143_CONN_WF_CTRL1__FUNC_GPIO143 (MTK_PIN_NO(143) | 0) +#define MT8365_PIN_143_CONN_WF_CTRL1__FUNC_CONN_WF_CTRL1 (MTK_PIN_NO(143) | 1) + +#define MT8365_PIN_144_CONN_WF_CTRL2__FUNC_GPIO144 (MTK_PIN_NO(144) | 0) +#define MT8365_PIN_144_CONN_WF_CTRL2__FUNC_CONN_WF_CTRL2 (MTK_PIN_NO(144) | 1) + +#endif /* __MT8365_PINFUNC_H */ diff --git a/include/dt-bindings/pinctrl/omap.h b/include/dt-bindings/pinctrl/omap.h index 625718042413..f48245ff87e5 100644 --- a/include/dt-bindings/pinctrl/omap.h +++ b/include/dt-bindings/pinctrl/omap.h @@ -64,8 +64,8 @@ #define OMAP3_WKUP_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2a00) (val) #define DM814X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) #define DM816X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) -#define AM33XX_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) -#define AM33XX_PADCONF(pa, dir, mux) OMAP_IOPAD_OFFSET((pa), 0x0800) ((dir) | (mux)) +#define AM33XX_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) (0) +#define AM33XX_PADCONF(pa, conf, mux) OMAP_IOPAD_OFFSET((pa), 0x0800) (conf) (mux) /* * Macros to allow using the offset from the padconf physical address diff --git a/include/dt-bindings/pinctrl/pads-imx8dxl.h b/include/dt-bindings/pinctrl/pads-imx8dxl.h new file mode 100644 index 000000000000..b1d7b84c3e0a --- /dev/null +++ b/include/dt-bindings/pinctrl/pads-imx8dxl.h @@ -0,0 +1,639 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019~2020 NXP + */ + +#ifndef _IMX8DXL_PADS_H +#define _IMX8DXL_PADS_H + +/* pin id */ +#define IMX8DXL_PCIE_CTRL0_PERST_B 0 +#define IMX8DXL_PCIE_CTRL0_CLKREQ_B 1 +#define IMX8DXL_PCIE_CTRL0_WAKE_B 2 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_PCIESEP 3 +#define IMX8DXL_USB_SS3_TC0 4 +#define IMX8DXL_USB_SS3_TC1 5 +#define IMX8DXL_USB_SS3_TC2 6 +#define IMX8DXL_USB_SS3_TC3 7 +#define IMX8DXL_COMP_CTL_GPIO_3V3_USB3IO 8 +#define IMX8DXL_EMMC0_CLK 9 +#define IMX8DXL_EMMC0_CMD 10 +#define IMX8DXL_EMMC0_DATA0 11 +#define IMX8DXL_EMMC0_DATA1 12 +#define IMX8DXL_EMMC0_DATA2 13 +#define IMX8DXL_EMMC0_DATA3 14 +#define IMX8DXL_EMMC0_DATA4 15 +#define IMX8DXL_EMMC0_DATA5 16 +#define IMX8DXL_EMMC0_DATA6 17 +#define IMX8DXL_EMMC0_DATA7 18 +#define IMX8DXL_EMMC0_STROBE 19 +#define IMX8DXL_EMMC0_RESET_B 20 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 21 +#define IMX8DXL_USDHC1_RESET_B 22 +#define IMX8DXL_USDHC1_VSELECT 23 +#define IMX8DXL_CTL_NAND_RE_P_N 24 +#define IMX8DXL_USDHC1_WP 25 +#define IMX8DXL_USDHC1_CD_B 26 +#define IMX8DXL_CTL_NAND_DQS_P_N 27 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_VSELSEP 28 +#define IMX8DXL_ENET0_RGMII_TXC 29 +#define IMX8DXL_ENET0_RGMII_TX_CTL 30 +#define IMX8DXL_ENET0_RGMII_TXD0 31 +#define IMX8DXL_ENET0_RGMII_TXD1 32 +#define IMX8DXL_ENET0_RGMII_TXD2 33 +#define IMX8DXL_ENET0_RGMII_TXD3 34 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 35 +#define IMX8DXL_ENET0_RGMII_RXC 36 +#define IMX8DXL_ENET0_RGMII_RX_CTL 37 +#define IMX8DXL_ENET0_RGMII_RXD0 38 +#define IMX8DXL_ENET0_RGMII_RXD1 39 +#define IMX8DXL_ENET0_RGMII_RXD2 40 +#define IMX8DXL_ENET0_RGMII_RXD3 41 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 42 +#define IMX8DXL_ENET0_REFCLK_125M_25M 43 +#define IMX8DXL_ENET0_MDIO 44 +#define IMX8DXL_ENET0_MDC 45 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOCT 46 +#define IMX8DXL_ENET1_RGMII_TXC 47 +#define IMX8DXL_ENET1_RGMII_TXD2 48 +#define IMX8DXL_ENET1_RGMII_TX_CTL 49 +#define IMX8DXL_ENET1_RGMII_TXD3 50 +#define IMX8DXL_ENET1_RGMII_RXC 51 +#define IMX8DXL_ENET1_RGMII_RXD3 52 +#define IMX8DXL_ENET1_RGMII_RXD2 53 +#define IMX8DXL_ENET1_RGMII_RXD1 54 +#define IMX8DXL_ENET1_RGMII_TXD0 55 +#define IMX8DXL_ENET1_RGMII_TXD1 56 +#define IMX8DXL_ENET1_RGMII_RXD0 57 +#define IMX8DXL_ENET1_RGMII_RX_CTL 58 +#define IMX8DXL_ENET1_REFCLK_125M_25M 59 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB 60 +#define IMX8DXL_SPI3_SCK 61 +#define IMX8DXL_SPI3_SDO 62 +#define IMX8DXL_SPI3_SDI 63 +#define IMX8DXL_SPI3_CS0 64 +#define IMX8DXL_SPI3_CS1 65 +#define IMX8DXL_MCLK_IN1 66 +#define IMX8DXL_MCLK_IN0 67 +#define IMX8DXL_MCLK_OUT0 68 +#define IMX8DXL_UART1_TX 69 +#define IMX8DXL_UART1_RX 70 +#define IMX8DXL_UART1_RTS_B 71 +#define IMX8DXL_UART1_CTS_B 72 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK 73 +#define IMX8DXL_SPI0_SCK 74 +#define IMX8DXL_SPI0_SDI 75 +#define IMX8DXL_SPI0_SDO 76 +#define IMX8DXL_SPI0_CS1 77 +#define IMX8DXL_SPI0_CS0 78 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHT 79 +#define IMX8DXL_ADC_IN1 80 +#define IMX8DXL_ADC_IN0 81 +#define IMX8DXL_ADC_IN3 82 +#define IMX8DXL_ADC_IN2 83 +#define IMX8DXL_ADC_IN5 84 +#define IMX8DXL_ADC_IN4 85 +#define IMX8DXL_FLEXCAN0_RX 86 +#define IMX8DXL_FLEXCAN0_TX 87 +#define IMX8DXL_FLEXCAN1_RX 88 +#define IMX8DXL_FLEXCAN1_TX 89 +#define IMX8DXL_FLEXCAN2_RX 90 +#define IMX8DXL_FLEXCAN2_TX 91 +#define IMX8DXL_UART0_RX 92 +#define IMX8DXL_UART0_TX 93 +#define IMX8DXL_UART2_TX 94 +#define IMX8DXL_UART2_RX 95 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOLH 96 +#define IMX8DXL_JTAG_TRST_B 97 +#define IMX8DXL_PMIC_I2C_SCL 98 +#define IMX8DXL_PMIC_I2C_SDA 99 +#define IMX8DXL_PMIC_INT_B 100 +#define IMX8DXL_SCU_GPIO0_00 101 +#define IMX8DXL_SCU_GPIO0_01 102 +#define IMX8DXL_SCU_PMIC_STANDBY 103 +#define IMX8DXL_SCU_BOOT_MODE1 104 +#define IMX8DXL_SCU_BOOT_MODE0 105 +#define IMX8DXL_SCU_BOOT_MODE2 106 +#define IMX8DXL_SNVS_TAMPER_OUT1 107 +#define IMX8DXL_SNVS_TAMPER_OUT2 108 +#define IMX8DXL_SNVS_TAMPER_OUT3 109 +#define IMX8DXL_SNVS_TAMPER_OUT4 110 +#define IMX8DXL_SNVS_TAMPER_IN0 111 +#define IMX8DXL_SNVS_TAMPER_IN1 112 +#define IMX8DXL_SNVS_TAMPER_IN2 113 +#define IMX8DXL_SNVS_TAMPER_IN3 114 +#define IMX8DXL_SPI1_SCK 115 +#define IMX8DXL_SPI1_SDO 116 +#define IMX8DXL_SPI1_SDI 117 +#define IMX8DXL_SPI1_CS0 118 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHD 119 +#define IMX8DXL_QSPI0A_DATA1 120 +#define IMX8DXL_QSPI0A_DATA0 121 +#define IMX8DXL_QSPI0A_DATA3 122 +#define IMX8DXL_QSPI0A_DATA2 123 +#define IMX8DXL_QSPI0A_SS0_B 124 +#define IMX8DXL_QSPI0A_DQS 125 +#define IMX8DXL_QSPI0A_SCLK 126 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_QSPI0A 127 +#define IMX8DXL_QSPI0B_SCLK 128 +#define IMX8DXL_QSPI0B_DQS 129 +#define IMX8DXL_QSPI0B_DATA1 130 +#define IMX8DXL_QSPI0B_DATA0 131 +#define IMX8DXL_QSPI0B_DATA3 132 +#define IMX8DXL_QSPI0B_DATA2 133 +#define IMX8DXL_QSPI0B_SS0_B 134 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_QSPI0B 135 + +/* format: <pin_id mux_mode> */ +#define IMX8DXL_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B IMX8DXL_PCIE_CTRL0_PERST_B 0 +#define IMX8DXL_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 IMX8DXL_PCIE_CTRL0_PERST_B 4 +#define IMX8DXL_PCIE_CTRL0_PERST_B_LSIO_GPIO7_IO00 IMX8DXL_PCIE_CTRL0_PERST_B 5 +#define IMX8DXL_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B IMX8DXL_PCIE_CTRL0_CLKREQ_B 0 +#define IMX8DXL_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 IMX8DXL_PCIE_CTRL0_CLKREQ_B 4 +#define IMX8DXL_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO7_IO01 IMX8DXL_PCIE_CTRL0_CLKREQ_B 5 +#define IMX8DXL_PCIE_CTRL0_WAKE_B_HSIO_PCIE0_WAKE_B IMX8DXL_PCIE_CTRL0_WAKE_B 0 +#define IMX8DXL_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 IMX8DXL_PCIE_CTRL0_WAKE_B 4 +#define IMX8DXL_PCIE_CTRL0_WAKE_B_LSIO_GPIO7_IO02 IMX8DXL_PCIE_CTRL0_WAKE_B 5 +#define IMX8DXL_USB_SS3_TC0_ADMA_I2C1_SCL IMX8DXL_USB_SS3_TC0 0 +#define IMX8DXL_USB_SS3_TC0_CONN_USB_OTG1_PWR IMX8DXL_USB_SS3_TC0 1 +#define IMX8DXL_USB_SS3_TC0_CONN_USB_OTG2_PWR IMX8DXL_USB_SS3_TC0 2 +#define IMX8DXL_USB_SS3_TC0_LSIO_GPIO4_IO03 IMX8DXL_USB_SS3_TC0 4 +#define IMX8DXL_USB_SS3_TC0_LSIO_GPIO7_IO03 IMX8DXL_USB_SS3_TC0 5 +#define IMX8DXL_USB_SS3_TC1_ADMA_I2C1_SCL IMX8DXL_USB_SS3_TC1 0 +#define IMX8DXL_USB_SS3_TC1_CONN_USB_OTG2_PWR IMX8DXL_USB_SS3_TC1 1 +#define IMX8DXL_USB_SS3_TC1_LSIO_GPIO4_IO04 IMX8DXL_USB_SS3_TC1 4 +#define IMX8DXL_USB_SS3_TC1_LSIO_GPIO7_IO04 IMX8DXL_USB_SS3_TC1 5 +#define IMX8DXL_USB_SS3_TC2_ADMA_I2C1_SDA IMX8DXL_USB_SS3_TC2 0 +#define IMX8DXL_USB_SS3_TC2_CONN_USB_OTG1_OC IMX8DXL_USB_SS3_TC2 1 +#define IMX8DXL_USB_SS3_TC2_CONN_USB_OTG2_OC IMX8DXL_USB_SS3_TC2 2 +#define IMX8DXL_USB_SS3_TC2_LSIO_GPIO4_IO05 IMX8DXL_USB_SS3_TC2 4 +#define IMX8DXL_USB_SS3_TC2_LSIO_GPIO7_IO05 IMX8DXL_USB_SS3_TC2 5 +#define IMX8DXL_USB_SS3_TC3_ADMA_I2C1_SDA IMX8DXL_USB_SS3_TC3 0 +#define IMX8DXL_USB_SS3_TC3_CONN_USB_OTG2_OC IMX8DXL_USB_SS3_TC3 1 +#define IMX8DXL_USB_SS3_TC3_LSIO_GPIO4_IO06 IMX8DXL_USB_SS3_TC3 4 +#define IMX8DXL_USB_SS3_TC3_LSIO_GPIO7_IO06 IMX8DXL_USB_SS3_TC3 5 +#define IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK IMX8DXL_EMMC0_CLK 0 +#define IMX8DXL_EMMC0_CLK_CONN_NAND_READY_B IMX8DXL_EMMC0_CLK 1 +#define IMX8DXL_EMMC0_CLK_LSIO_GPIO4_IO07 IMX8DXL_EMMC0_CLK 4 +#define IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD IMX8DXL_EMMC0_CMD 0 +#define IMX8DXL_EMMC0_CMD_CONN_NAND_DQS IMX8DXL_EMMC0_CMD 1 +#define IMX8DXL_EMMC0_CMD_LSIO_GPIO4_IO08 IMX8DXL_EMMC0_CMD 4 +#define IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0 IMX8DXL_EMMC0_DATA0 0 +#define IMX8DXL_EMMC0_DATA0_CONN_NAND_DATA00 IMX8DXL_EMMC0_DATA0 1 +#define IMX8DXL_EMMC0_DATA0_LSIO_GPIO4_IO09 IMX8DXL_EMMC0_DATA0 4 +#define IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1 IMX8DXL_EMMC0_DATA1 0 +#define IMX8DXL_EMMC0_DATA1_CONN_NAND_DATA01 IMX8DXL_EMMC0_DATA1 1 +#define IMX8DXL_EMMC0_DATA1_LSIO_GPIO4_IO10 IMX8DXL_EMMC0_DATA1 4 +#define IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2 IMX8DXL_EMMC0_DATA2 0 +#define IMX8DXL_EMMC0_DATA2_CONN_NAND_DATA02 IMX8DXL_EMMC0_DATA2 1 +#define IMX8DXL_EMMC0_DATA2_LSIO_GPIO4_IO11 IMX8DXL_EMMC0_DATA2 4 +#define IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3 IMX8DXL_EMMC0_DATA3 0 +#define IMX8DXL_EMMC0_DATA3_CONN_NAND_DATA03 IMX8DXL_EMMC0_DATA3 1 +#define IMX8DXL_EMMC0_DATA3_LSIO_GPIO4_IO12 IMX8DXL_EMMC0_DATA3 4 +#define IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4 IMX8DXL_EMMC0_DATA4 0 +#define IMX8DXL_EMMC0_DATA4_CONN_NAND_DATA04 IMX8DXL_EMMC0_DATA4 1 +#define IMX8DXL_EMMC0_DATA4_LSIO_GPIO4_IO13 IMX8DXL_EMMC0_DATA4 4 +#define IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5 IMX8DXL_EMMC0_DATA5 0 +#define IMX8DXL_EMMC0_DATA5_CONN_NAND_DATA05 IMX8DXL_EMMC0_DATA5 1 +#define IMX8DXL_EMMC0_DATA5_LSIO_GPIO4_IO14 IMX8DXL_EMMC0_DATA5 4 +#define IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6 IMX8DXL_EMMC0_DATA6 0 +#define IMX8DXL_EMMC0_DATA6_CONN_NAND_DATA06 IMX8DXL_EMMC0_DATA6 1 +#define IMX8DXL_EMMC0_DATA6_LSIO_GPIO4_IO15 IMX8DXL_EMMC0_DATA6 4 +#define IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7 IMX8DXL_EMMC0_DATA7 0 +#define IMX8DXL_EMMC0_DATA7_CONN_NAND_DATA07 IMX8DXL_EMMC0_DATA7 1 +#define IMX8DXL_EMMC0_DATA7_LSIO_GPIO4_IO16 IMX8DXL_EMMC0_DATA7 4 +#define IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE IMX8DXL_EMMC0_STROBE 0 +#define IMX8DXL_EMMC0_STROBE_CONN_NAND_CLE IMX8DXL_EMMC0_STROBE 1 +#define IMX8DXL_EMMC0_STROBE_LSIO_GPIO4_IO17 IMX8DXL_EMMC0_STROBE 4 +#define IMX8DXL_EMMC0_RESET_B_CONN_EMMC0_RESET_B IMX8DXL_EMMC0_RESET_B 0 +#define IMX8DXL_EMMC0_RESET_B_CONN_NAND_WP_B IMX8DXL_EMMC0_RESET_B 1 +#define IMX8DXL_EMMC0_RESET_B_LSIO_GPIO4_IO18 IMX8DXL_EMMC0_RESET_B 4 +#define IMX8DXL_USDHC1_RESET_B_CONN_USDHC1_RESET_B IMX8DXL_USDHC1_RESET_B 0 +#define IMX8DXL_USDHC1_RESET_B_CONN_NAND_RE_N IMX8DXL_USDHC1_RESET_B 1 +#define IMX8DXL_USDHC1_RESET_B_ADMA_SPI2_SCK IMX8DXL_USDHC1_RESET_B 2 +#define IMX8DXL_USDHC1_RESET_B_CONN_NAND_WE_B IMX8DXL_USDHC1_RESET_B 3 +#define IMX8DXL_USDHC1_RESET_B_LSIO_GPIO4_IO19 IMX8DXL_USDHC1_RESET_B 4 +#define IMX8DXL_USDHC1_RESET_B_LSIO_GPIO7_IO08 IMX8DXL_USDHC1_RESET_B 5 +#define IMX8DXL_USDHC1_VSELECT_CONN_USDHC1_VSELECT IMX8DXL_USDHC1_VSELECT 0 +#define IMX8DXL_USDHC1_VSELECT_CONN_NAND_RE_P IMX8DXL_USDHC1_VSELECT 1 +#define IMX8DXL_USDHC1_VSELECT_ADMA_SPI2_SDO IMX8DXL_USDHC1_VSELECT 2 +#define IMX8DXL_USDHC1_VSELECT_CONN_NAND_RE_B IMX8DXL_USDHC1_VSELECT 3 +#define IMX8DXL_USDHC1_VSELECT_LSIO_GPIO4_IO20 IMX8DXL_USDHC1_VSELECT 4 +#define IMX8DXL_USDHC1_VSELECT_LSIO_GPIO7_IO09 IMX8DXL_USDHC1_VSELECT 5 +#define IMX8DXL_USDHC1_WP_CONN_USDHC1_WP IMX8DXL_USDHC1_WP 0 +#define IMX8DXL_USDHC1_WP_CONN_NAND_DQS_N IMX8DXL_USDHC1_WP 1 +#define IMX8DXL_USDHC1_WP_ADMA_SPI2_SDI IMX8DXL_USDHC1_WP 2 +#define IMX8DXL_USDHC1_WP_CONN_NAND_ALE IMX8DXL_USDHC1_WP 3 +#define IMX8DXL_USDHC1_WP_LSIO_GPIO4_IO21 IMX8DXL_USDHC1_WP 4 +#define IMX8DXL_USDHC1_WP_LSIO_GPIO7_IO10 IMX8DXL_USDHC1_WP 5 +#define IMX8DXL_USDHC1_CD_B_CONN_USDHC1_CD_B IMX8DXL_USDHC1_CD_B 0 +#define IMX8DXL_USDHC1_CD_B_CONN_NAND_DQS_P IMX8DXL_USDHC1_CD_B 1 +#define IMX8DXL_USDHC1_CD_B_ADMA_SPI2_CS0 IMX8DXL_USDHC1_CD_B 2 +#define IMX8DXL_USDHC1_CD_B_CONN_NAND_DQS IMX8DXL_USDHC1_CD_B 3 +#define IMX8DXL_USDHC1_CD_B_LSIO_GPIO4_IO22 IMX8DXL_USDHC1_CD_B 4 +#define IMX8DXL_USDHC1_CD_B_LSIO_GPIO7_IO11 IMX8DXL_USDHC1_CD_B 5 +#define IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC IMX8DXL_ENET0_RGMII_TXC 0 +#define IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT IMX8DXL_ENET0_RGMII_TXC 1 +#define IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_IN IMX8DXL_ENET0_RGMII_TXC 2 +#define IMX8DXL_ENET0_RGMII_TXC_CONN_NAND_CE1_B IMX8DXL_ENET0_RGMII_TXC 3 +#define IMX8DXL_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 IMX8DXL_ENET0_RGMII_TXC 4 +#define IMX8DXL_ENET0_RGMII_TXC_CONN_USDHC2_CLK IMX8DXL_ENET0_RGMII_TXC 5 +#define IMX8DXL_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL IMX8DXL_ENET0_RGMII_TX_CTL 0 +#define IMX8DXL_ENET0_RGMII_TX_CTL_CONN_USDHC1_RESET_B IMX8DXL_ENET0_RGMII_TX_CTL 3 +#define IMX8DXL_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 IMX8DXL_ENET0_RGMII_TX_CTL 4 +#define IMX8DXL_ENET0_RGMII_TX_CTL_CONN_USDHC2_CMD IMX8DXL_ENET0_RGMII_TX_CTL 5 +#define IMX8DXL_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 IMX8DXL_ENET0_RGMII_TXD0 0 +#define IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT IMX8DXL_ENET0_RGMII_TXD0 3 +#define IMX8DXL_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31 IMX8DXL_ENET0_RGMII_TXD0 4 +#define IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC2_DATA0 IMX8DXL_ENET0_RGMII_TXD0 5 +#define IMX8DXL_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 IMX8DXL_ENET0_RGMII_TXD1 0 +#define IMX8DXL_ENET0_RGMII_TXD1_CONN_USDHC1_WP IMX8DXL_ENET0_RGMII_TXD1 3 +#define IMX8DXL_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 IMX8DXL_ENET0_RGMII_TXD1 4 +#define IMX8DXL_ENET0_RGMII_TXD1_CONN_USDHC2_DATA1 IMX8DXL_ENET0_RGMII_TXD1 5 +#define IMX8DXL_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 IMX8DXL_ENET0_RGMII_TXD2 0 +#define IMX8DXL_ENET0_RGMII_TXD2_CONN_NAND_CE0_B IMX8DXL_ENET0_RGMII_TXD2 2 +#define IMX8DXL_ENET0_RGMII_TXD2_CONN_USDHC1_CD_B IMX8DXL_ENET0_RGMII_TXD2 3 +#define IMX8DXL_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 IMX8DXL_ENET0_RGMII_TXD2 4 +#define IMX8DXL_ENET0_RGMII_TXD2_CONN_USDHC2_DATA2 IMX8DXL_ENET0_RGMII_TXD2 5 +#define IMX8DXL_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 IMX8DXL_ENET0_RGMII_TXD3 0 +#define IMX8DXL_ENET0_RGMII_TXD3_CONN_NAND_RE_B IMX8DXL_ENET0_RGMII_TXD3 2 +#define IMX8DXL_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 IMX8DXL_ENET0_RGMII_TXD3 4 +#define IMX8DXL_ENET0_RGMII_TXD3_CONN_USDHC2_DATA3 IMX8DXL_ENET0_RGMII_TXD3 5 +#define IMX8DXL_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC IMX8DXL_ENET0_RGMII_RXC 0 +#define IMX8DXL_ENET0_RGMII_RXC_CONN_NAND_WE_B IMX8DXL_ENET0_RGMII_RXC 2 +#define IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK IMX8DXL_ENET0_RGMII_RXC 3 +#define IMX8DXL_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 IMX8DXL_ENET0_RGMII_RXC 4 +#define IMX8DXL_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL IMX8DXL_ENET0_RGMII_RX_CTL 0 +#define IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD IMX8DXL_ENET0_RGMII_RX_CTL 3 +#define IMX8DXL_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04 IMX8DXL_ENET0_RGMII_RX_CTL 4 +#define IMX8DXL_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 IMX8DXL_ENET0_RGMII_RXD0 0 +#define IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 IMX8DXL_ENET0_RGMII_RXD0 3 +#define IMX8DXL_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05 IMX8DXL_ENET0_RGMII_RXD0 4 +#define IMX8DXL_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 IMX8DXL_ENET0_RGMII_RXD1 0 +#define IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 IMX8DXL_ENET0_RGMII_RXD1 3 +#define IMX8DXL_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06 IMX8DXL_ENET0_RGMII_RXD1 4 +#define IMX8DXL_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 IMX8DXL_ENET0_RGMII_RXD2 0 +#define IMX8DXL_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER IMX8DXL_ENET0_RGMII_RXD2 1 +#define IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 IMX8DXL_ENET0_RGMII_RXD2 3 +#define IMX8DXL_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07 IMX8DXL_ENET0_RGMII_RXD2 4 +#define IMX8DXL_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 IMX8DXL_ENET0_RGMII_RXD3 0 +#define IMX8DXL_ENET0_RGMII_RXD3_CONN_NAND_ALE IMX8DXL_ENET0_RGMII_RXD3 2 +#define IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 IMX8DXL_ENET0_RGMII_RXD3 3 +#define IMX8DXL_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 IMX8DXL_ENET0_RGMII_RXD3 4 +#define IMX8DXL_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M IMX8DXL_ENET0_REFCLK_125M_25M 0 +#define IMX8DXL_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS IMX8DXL_ENET0_REFCLK_125M_25M 1 +#define IMX8DXL_ENET0_REFCLK_125M_25M_CONN_EQOS_PPS_IN IMX8DXL_ENET0_REFCLK_125M_25M 2 +#define IMX8DXL_ENET0_REFCLK_125M_25M_CONN_EQOS_PPS_OUT IMX8DXL_ENET0_REFCLK_125M_25M 3 +#define IMX8DXL_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 IMX8DXL_ENET0_REFCLK_125M_25M 4 +#define IMX8DXL_ENET0_MDIO_CONN_ENET0_MDIO IMX8DXL_ENET0_MDIO 0 +#define IMX8DXL_ENET0_MDIO_ADMA_I2C3_SDA IMX8DXL_ENET0_MDIO 1 +#define IMX8DXL_ENET0_MDIO_CONN_EQOS_MDIO IMX8DXL_ENET0_MDIO 2 +#define IMX8DXL_ENET0_MDIO_LSIO_GPIO5_IO10 IMX8DXL_ENET0_MDIO 4 +#define IMX8DXL_ENET0_MDIO_LSIO_GPIO7_IO16 IMX8DXL_ENET0_MDIO 5 +#define IMX8DXL_ENET0_MDC_CONN_ENET0_MDC IMX8DXL_ENET0_MDC 0 +#define IMX8DXL_ENET0_MDC_ADMA_I2C3_SCL IMX8DXL_ENET0_MDC 1 +#define IMX8DXL_ENET0_MDC_CONN_EQOS_MDC IMX8DXL_ENET0_MDC 2 +#define IMX8DXL_ENET0_MDC_LSIO_GPIO5_IO11 IMX8DXL_ENET0_MDC 4 +#define IMX8DXL_ENET0_MDC_LSIO_GPIO7_IO17 IMX8DXL_ENET0_MDC 5 +#define IMX8DXL_ENET1_RGMII_TXC_LSIO_GPIO0_IO00 IMX8DXL_ENET1_RGMII_TXC 0 +#define IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RCLK50M_OUT IMX8DXL_ENET1_RGMII_TXC 1 +#define IMX8DXL_ENET1_RGMII_TXC_ADMA_LCDIF_D00 IMX8DXL_ENET1_RGMII_TXC 2 +#define IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RGMII_TXC IMX8DXL_ENET1_RGMII_TXC 3 +#define IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RCLK50M_IN IMX8DXL_ENET1_RGMII_TXC 4 +#define IMX8DXL_ENET1_RGMII_TXD2_ADMA_LCDIF_D01 IMX8DXL_ENET1_RGMII_TXD2 2 +#define IMX8DXL_ENET1_RGMII_TXD2_CONN_EQOS_RGMII_TXD2 IMX8DXL_ENET1_RGMII_TXD2 3 +#define IMX8DXL_ENET1_RGMII_TXD2_LSIO_GPIO0_IO01 IMX8DXL_ENET1_RGMII_TXD2 4 +#define IMX8DXL_ENET1_RGMII_TX_CTL_ADMA_LCDIF_D02 IMX8DXL_ENET1_RGMII_TX_CTL 2 +#define IMX8DXL_ENET1_RGMII_TX_CTL_CONN_EQOS_RGMII_TX_CTL IMX8DXL_ENET1_RGMII_TX_CTL 3 +#define IMX8DXL_ENET1_RGMII_TX_CTL_LSIO_GPIO0_IO02 IMX8DXL_ENET1_RGMII_TX_CTL 4 +#define IMX8DXL_ENET1_RGMII_TXD3_ADMA_LCDIF_D03 IMX8DXL_ENET1_RGMII_TXD3 2 +#define IMX8DXL_ENET1_RGMII_TXD3_CONN_EQOS_RGMII_TXD3 IMX8DXL_ENET1_RGMII_TXD3 3 +#define IMX8DXL_ENET1_RGMII_TXD3_LSIO_GPIO0_IO03 IMX8DXL_ENET1_RGMII_TXD3 4 +#define IMX8DXL_ENET1_RGMII_RXC_ADMA_LCDIF_D04 IMX8DXL_ENET1_RGMII_RXC 2 +#define IMX8DXL_ENET1_RGMII_RXC_CONN_EQOS_RGMII_RXC IMX8DXL_ENET1_RGMII_RXC 3 +#define IMX8DXL_ENET1_RGMII_RXC_LSIO_GPIO0_IO04 IMX8DXL_ENET1_RGMII_RXC 4 +#define IMX8DXL_ENET1_RGMII_RXD3_ADMA_LCDIF_D05 IMX8DXL_ENET1_RGMII_RXD3 2 +#define IMX8DXL_ENET1_RGMII_RXD3_CONN_EQOS_RGMII_RXD3 IMX8DXL_ENET1_RGMII_RXD3 3 +#define IMX8DXL_ENET1_RGMII_RXD3_LSIO_GPIO0_IO05 IMX8DXL_ENET1_RGMII_RXD3 4 +#define IMX8DXL_ENET1_RGMII_RXD2_ADMA_LCDIF_D06 IMX8DXL_ENET1_RGMII_RXD2 2 +#define IMX8DXL_ENET1_RGMII_RXD2_CONN_EQOS_RGMII_RXD2 IMX8DXL_ENET1_RGMII_RXD2 3 +#define IMX8DXL_ENET1_RGMII_RXD2_LSIO_GPIO0_IO06 IMX8DXL_ENET1_RGMII_RXD2 4 +#define IMX8DXL_ENET1_RGMII_RXD2_LSIO_GPIO6_IO00 IMX8DXL_ENET1_RGMII_RXD2 5 +#define IMX8DXL_ENET1_RGMII_RXD1_ADMA_LCDIF_D07 IMX8DXL_ENET1_RGMII_RXD1 2 +#define IMX8DXL_ENET1_RGMII_RXD1_CONN_EQOS_RGMII_RXD1 IMX8DXL_ENET1_RGMII_RXD1 3 +#define IMX8DXL_ENET1_RGMII_RXD1_LSIO_GPIO0_IO07 IMX8DXL_ENET1_RGMII_RXD1 4 +#define IMX8DXL_ENET1_RGMII_RXD1_LSIO_GPIO6_IO01 IMX8DXL_ENET1_RGMII_RXD1 5 +#define IMX8DXL_ENET1_RGMII_TXD0_ADMA_LCDIF_D08 IMX8DXL_ENET1_RGMII_TXD0 2 +#define IMX8DXL_ENET1_RGMII_TXD0_CONN_EQOS_RGMII_TXD0 IMX8DXL_ENET1_RGMII_TXD0 3 +#define IMX8DXL_ENET1_RGMII_TXD0_LSIO_GPIO0_IO08 IMX8DXL_ENET1_RGMII_TXD0 4 +#define IMX8DXL_ENET1_RGMII_TXD0_LSIO_GPIO6_IO02 IMX8DXL_ENET1_RGMII_TXD0 5 +#define IMX8DXL_ENET1_RGMII_TXD1_ADMA_LCDIF_D09 IMX8DXL_ENET1_RGMII_TXD1 2 +#define IMX8DXL_ENET1_RGMII_TXD1_CONN_EQOS_RGMII_TXD1 IMX8DXL_ENET1_RGMII_TXD1 3 +#define IMX8DXL_ENET1_RGMII_TXD1_LSIO_GPIO0_IO09 IMX8DXL_ENET1_RGMII_TXD1 4 +#define IMX8DXL_ENET1_RGMII_TXD1_LSIO_GPIO6_IO03 IMX8DXL_ENET1_RGMII_TXD1 5 +#define IMX8DXL_ENET1_RGMII_RXD0_ADMA_SPDIF0_RX IMX8DXL_ENET1_RGMII_RXD0 0 +#define IMX8DXL_ENET1_RGMII_RXD0_ADMA_MQS_R IMX8DXL_ENET1_RGMII_RXD0 1 +#define IMX8DXL_ENET1_RGMII_RXD0_ADMA_LCDIF_D10 IMX8DXL_ENET1_RGMII_RXD0 2 +#define IMX8DXL_ENET1_RGMII_RXD0_CONN_EQOS_RGMII_RXD0 IMX8DXL_ENET1_RGMII_RXD0 3 +#define IMX8DXL_ENET1_RGMII_RXD0_LSIO_GPIO0_IO10 IMX8DXL_ENET1_RGMII_RXD0 4 +#define IMX8DXL_ENET1_RGMII_RXD0_LSIO_GPIO6_IO04 IMX8DXL_ENET1_RGMII_RXD0 5 +#define IMX8DXL_ENET1_RGMII_RX_CTL_ADMA_SPDIF0_TX IMX8DXL_ENET1_RGMII_RX_CTL 0 +#define IMX8DXL_ENET1_RGMII_RX_CTL_ADMA_MQS_L IMX8DXL_ENET1_RGMII_RX_CTL 1 +#define IMX8DXL_ENET1_RGMII_RX_CTL_ADMA_LCDIF_D11 IMX8DXL_ENET1_RGMII_RX_CTL 2 +#define IMX8DXL_ENET1_RGMII_RX_CTL_CONN_EQOS_RGMII_RX_CTL IMX8DXL_ENET1_RGMII_RX_CTL 3 +#define IMX8DXL_ENET1_RGMII_RX_CTL_LSIO_GPIO0_IO11 IMX8DXL_ENET1_RGMII_RX_CTL 4 +#define IMX8DXL_ENET1_RGMII_RX_CTL_LSIO_GPIO6_IO05 IMX8DXL_ENET1_RGMII_RX_CTL 5 +#define IMX8DXL_ENET1_REFCLK_125M_25M_ADMA_SPDIF0_EXT_CLK IMX8DXL_ENET1_REFCLK_125M_25M 0 +#define IMX8DXL_ENET1_REFCLK_125M_25M_ADMA_LCDIF_D12 IMX8DXL_ENET1_REFCLK_125M_25M 2 +#define IMX8DXL_ENET1_REFCLK_125M_25M_CONN_EQOS_REFCLK_125M_25M IMX8DXL_ENET1_REFCLK_125M_25M 3 +#define IMX8DXL_ENET1_REFCLK_125M_25M_LSIO_GPIO0_IO12 IMX8DXL_ENET1_REFCLK_125M_25M 4 +#define IMX8DXL_ENET1_REFCLK_125M_25M_LSIO_GPIO6_IO06 IMX8DXL_ENET1_REFCLK_125M_25M 5 +#define IMX8DXL_SPI3_SCK_ADMA_SPI3_SCK IMX8DXL_SPI3_SCK 0 +#define IMX8DXL_SPI3_SCK_ADMA_LCDIF_D13 IMX8DXL_SPI3_SCK 2 +#define IMX8DXL_SPI3_SCK_LSIO_GPIO0_IO13 IMX8DXL_SPI3_SCK 4 +#define IMX8DXL_SPI3_SCK_ADMA_LCDIF_D00 IMX8DXL_SPI3_SCK 5 +#define IMX8DXL_SPI3_SDO_ADMA_SPI3_SDO IMX8DXL_SPI3_SDO 0 +#define IMX8DXL_SPI3_SDO_ADMA_LCDIF_D14 IMX8DXL_SPI3_SDO 2 +#define IMX8DXL_SPI3_SDO_LSIO_GPIO0_IO14 IMX8DXL_SPI3_SDO 4 +#define IMX8DXL_SPI3_SDO_ADMA_LCDIF_D01 IMX8DXL_SPI3_SDO 5 +#define IMX8DXL_SPI3_SDI_ADMA_SPI3_SDI IMX8DXL_SPI3_SDI 0 +#define IMX8DXL_SPI3_SDI_ADMA_LCDIF_D15 IMX8DXL_SPI3_SDI 2 +#define IMX8DXL_SPI3_SDI_LSIO_GPIO0_IO15 IMX8DXL_SPI3_SDI 4 +#define IMX8DXL_SPI3_SDI_ADMA_LCDIF_D02 IMX8DXL_SPI3_SDI 5 +#define IMX8DXL_SPI3_CS0_ADMA_SPI3_CS0 IMX8DXL_SPI3_CS0 0 +#define IMX8DXL_SPI3_CS0_ADMA_ACM_MCLK_OUT1 IMX8DXL_SPI3_CS0 1 +#define IMX8DXL_SPI3_CS0_ADMA_LCDIF_HSYNC IMX8DXL_SPI3_CS0 2 +#define IMX8DXL_SPI3_CS0_LSIO_GPIO0_IO16 IMX8DXL_SPI3_CS0 4 +#define IMX8DXL_SPI3_CS0_ADMA_LCDIF_CS IMX8DXL_SPI3_CS0 5 +#define IMX8DXL_SPI3_CS1_ADMA_SPI3_CS1 IMX8DXL_SPI3_CS1 0 +#define IMX8DXL_SPI3_CS1_ADMA_I2C3_SCL IMX8DXL_SPI3_CS1 1 +#define IMX8DXL_SPI3_CS1_ADMA_LCDIF_RESET IMX8DXL_SPI3_CS1 2 +#define IMX8DXL_SPI3_CS1_ADMA_SPI2_CS0 IMX8DXL_SPI3_CS1 3 +#define IMX8DXL_SPI3_CS1_ADMA_LCDIF_D16 IMX8DXL_SPI3_CS1 4 +#define IMX8DXL_SPI3_CS1_ADMA_LCDIF_RD_E IMX8DXL_SPI3_CS1 5 +#define IMX8DXL_MCLK_IN1_ADMA_ACM_MCLK_IN1 IMX8DXL_MCLK_IN1 0 +#define IMX8DXL_MCLK_IN1_ADMA_I2C3_SDA IMX8DXL_MCLK_IN1 1 +#define IMX8DXL_MCLK_IN1_ADMA_LCDIF_EN IMX8DXL_MCLK_IN1 2 +#define IMX8DXL_MCLK_IN1_ADMA_SPI2_SCK IMX8DXL_MCLK_IN1 3 +#define IMX8DXL_MCLK_IN1_ADMA_LCDIF_D17 IMX8DXL_MCLK_IN1 4 +#define IMX8DXL_MCLK_IN1_ADMA_LCDIF_D03 IMX8DXL_MCLK_IN1 5 +#define IMX8DXL_MCLK_IN0_ADMA_ACM_MCLK_IN0 IMX8DXL_MCLK_IN0 0 +#define IMX8DXL_MCLK_IN0_ADMA_LCDIF_VSYNC IMX8DXL_MCLK_IN0 2 +#define IMX8DXL_MCLK_IN0_ADMA_SPI2_SDI IMX8DXL_MCLK_IN0 3 +#define IMX8DXL_MCLK_IN0_LSIO_GPIO0_IO19 IMX8DXL_MCLK_IN0 4 +#define IMX8DXL_MCLK_IN0_ADMA_LCDIF_RS IMX8DXL_MCLK_IN0 5 +#define IMX8DXL_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 IMX8DXL_MCLK_OUT0 0 +#define IMX8DXL_MCLK_OUT0_ADMA_LCDIF_CLK IMX8DXL_MCLK_OUT0 2 +#define IMX8DXL_MCLK_OUT0_ADMA_SPI2_SDO IMX8DXL_MCLK_OUT0 3 +#define IMX8DXL_MCLK_OUT0_LSIO_GPIO0_IO20 IMX8DXL_MCLK_OUT0 4 +#define IMX8DXL_MCLK_OUT0_ADMA_LCDIF_WR_RWN IMX8DXL_MCLK_OUT0 5 +#define IMX8DXL_UART1_TX_ADMA_UART1_TX IMX8DXL_UART1_TX 0 +#define IMX8DXL_UART1_TX_LSIO_PWM0_OUT IMX8DXL_UART1_TX 1 +#define IMX8DXL_UART1_TX_LSIO_GPT0_CAPTURE IMX8DXL_UART1_TX 2 +#define IMX8DXL_UART1_TX_LSIO_GPIO0_IO21 IMX8DXL_UART1_TX 4 +#define IMX8DXL_UART1_TX_ADMA_LCDIF_D04 IMX8DXL_UART1_TX 5 +#define IMX8DXL_UART1_RX_ADMA_UART1_RX IMX8DXL_UART1_RX 0 +#define IMX8DXL_UART1_RX_LSIO_PWM1_OUT IMX8DXL_UART1_RX 1 +#define IMX8DXL_UART1_RX_LSIO_GPT0_COMPARE IMX8DXL_UART1_RX 2 +#define IMX8DXL_UART1_RX_LSIO_GPT1_CLK IMX8DXL_UART1_RX 3 +#define IMX8DXL_UART1_RX_LSIO_GPIO0_IO22 IMX8DXL_UART1_RX 4 +#define IMX8DXL_UART1_RX_ADMA_LCDIF_D05 IMX8DXL_UART1_RX 5 +#define IMX8DXL_UART1_RTS_B_ADMA_UART1_RTS_B IMX8DXL_UART1_RTS_B 0 +#define IMX8DXL_UART1_RTS_B_LSIO_PWM2_OUT IMX8DXL_UART1_RTS_B 1 +#define IMX8DXL_UART1_RTS_B_ADMA_LCDIF_D16 IMX8DXL_UART1_RTS_B 2 +#define IMX8DXL_UART1_RTS_B_LSIO_GPT1_CAPTURE IMX8DXL_UART1_RTS_B 3 +#define IMX8DXL_UART1_RTS_B_LSIO_GPT0_CLK IMX8DXL_UART1_RTS_B 4 +#define IMX8DXL_UART1_RTS_B_ADMA_LCDIF_D06 IMX8DXL_UART1_RTS_B 5 +#define IMX8DXL_UART1_CTS_B_ADMA_UART1_CTS_B IMX8DXL_UART1_CTS_B 0 +#define IMX8DXL_UART1_CTS_B_LSIO_PWM3_OUT IMX8DXL_UART1_CTS_B 1 +#define IMX8DXL_UART1_CTS_B_ADMA_LCDIF_D17 IMX8DXL_UART1_CTS_B 2 +#define IMX8DXL_UART1_CTS_B_LSIO_GPT1_COMPARE IMX8DXL_UART1_CTS_B 3 +#define IMX8DXL_UART1_CTS_B_LSIO_GPIO0_IO24 IMX8DXL_UART1_CTS_B 4 +#define IMX8DXL_UART1_CTS_B_ADMA_LCDIF_D07 IMX8DXL_UART1_CTS_B 5 +#define IMX8DXL_SPI0_SCK_ADMA_SPI0_SCK IMX8DXL_SPI0_SCK 0 +#define IMX8DXL_SPI0_SCK_ADMA_SAI0_TXC IMX8DXL_SPI0_SCK 1 +#define IMX8DXL_SPI0_SCK_M40_I2C0_SCL IMX8DXL_SPI0_SCK 2 +#define IMX8DXL_SPI0_SCK_M40_GPIO0_IO00 IMX8DXL_SPI0_SCK 3 +#define IMX8DXL_SPI0_SCK_LSIO_GPIO1_IO04 IMX8DXL_SPI0_SCK 4 +#define IMX8DXL_SPI0_SCK_ADMA_LCDIF_D08 IMX8DXL_SPI0_SCK 5 +#define IMX8DXL_SPI0_SDI_ADMA_SPI0_SDI IMX8DXL_SPI0_SDI 0 +#define IMX8DXL_SPI0_SDI_ADMA_SAI0_TXD IMX8DXL_SPI0_SDI 1 +#define IMX8DXL_SPI0_SDI_M40_TPM0_CH0 IMX8DXL_SPI0_SDI 2 +#define IMX8DXL_SPI0_SDI_M40_GPIO0_IO02 IMX8DXL_SPI0_SDI 3 +#define IMX8DXL_SPI0_SDI_LSIO_GPIO1_IO05 IMX8DXL_SPI0_SDI 4 +#define IMX8DXL_SPI0_SDI_ADMA_LCDIF_D09 IMX8DXL_SPI0_SDI 5 +#define IMX8DXL_SPI0_SDO_ADMA_SPI0_SDO IMX8DXL_SPI0_SDO 0 +#define IMX8DXL_SPI0_SDO_ADMA_SAI0_TXFS IMX8DXL_SPI0_SDO 1 +#define IMX8DXL_SPI0_SDO_M40_I2C0_SDA IMX8DXL_SPI0_SDO 2 +#define IMX8DXL_SPI0_SDO_M40_GPIO0_IO01 IMX8DXL_SPI0_SDO 3 +#define IMX8DXL_SPI0_SDO_LSIO_GPIO1_IO06 IMX8DXL_SPI0_SDO 4 +#define IMX8DXL_SPI0_SDO_ADMA_LCDIF_D10 IMX8DXL_SPI0_SDO 5 +#define IMX8DXL_SPI0_CS1_ADMA_SPI0_CS1 IMX8DXL_SPI0_CS1 0 +#define IMX8DXL_SPI0_CS1_ADMA_SAI0_RXC IMX8DXL_SPI0_CS1 1 +#define IMX8DXL_SPI0_CS1_ADMA_SAI1_TXD IMX8DXL_SPI0_CS1 2 +#define IMX8DXL_SPI0_CS1_ADMA_LCD_PWM0_OUT IMX8DXL_SPI0_CS1 3 +#define IMX8DXL_SPI0_CS1_LSIO_GPIO1_IO07 IMX8DXL_SPI0_CS1 4 +#define IMX8DXL_SPI0_CS1_ADMA_LCDIF_D11 IMX8DXL_SPI0_CS1 5 +#define IMX8DXL_SPI0_CS0_ADMA_SPI0_CS0 IMX8DXL_SPI0_CS0 0 +#define IMX8DXL_SPI0_CS0_ADMA_SAI0_RXD IMX8DXL_SPI0_CS0 1 +#define IMX8DXL_SPI0_CS0_M40_TPM0_CH1 IMX8DXL_SPI0_CS0 2 +#define IMX8DXL_SPI0_CS0_M40_GPIO0_IO03 IMX8DXL_SPI0_CS0 3 +#define IMX8DXL_SPI0_CS0_LSIO_GPIO1_IO08 IMX8DXL_SPI0_CS0 4 +#define IMX8DXL_SPI0_CS0_ADMA_LCDIF_D12 IMX8DXL_SPI0_CS0 5 +#define IMX8DXL_ADC_IN1_ADMA_ADC_IN1 IMX8DXL_ADC_IN1 0 +#define IMX8DXL_ADC_IN1_M40_I2C0_SDA IMX8DXL_ADC_IN1 1 +#define IMX8DXL_ADC_IN1_M40_GPIO0_IO01 IMX8DXL_ADC_IN1 2 +#define IMX8DXL_ADC_IN1_ADMA_I2C0_SDA IMX8DXL_ADC_IN1 3 +#define IMX8DXL_ADC_IN1_LSIO_GPIO1_IO09 IMX8DXL_ADC_IN1 4 +#define IMX8DXL_ADC_IN1_ADMA_LCDIF_D13 IMX8DXL_ADC_IN1 5 +#define IMX8DXL_ADC_IN0_ADMA_ADC_IN0 IMX8DXL_ADC_IN0 0 +#define IMX8DXL_ADC_IN0_M40_I2C0_SCL IMX8DXL_ADC_IN0 1 +#define IMX8DXL_ADC_IN0_M40_GPIO0_IO00 IMX8DXL_ADC_IN0 2 +#define IMX8DXL_ADC_IN0_ADMA_I2C0_SCL IMX8DXL_ADC_IN0 3 +#define IMX8DXL_ADC_IN0_LSIO_GPIO1_IO10 IMX8DXL_ADC_IN0 4 +#define IMX8DXL_ADC_IN0_ADMA_LCDIF_D14 IMX8DXL_ADC_IN0 5 +#define IMX8DXL_ADC_IN3_ADMA_ADC_IN3 IMX8DXL_ADC_IN3 0 +#define IMX8DXL_ADC_IN3_M40_UART0_TX IMX8DXL_ADC_IN3 1 +#define IMX8DXL_ADC_IN3_M40_GPIO0_IO03 IMX8DXL_ADC_IN3 2 +#define IMX8DXL_ADC_IN3_ADMA_ACM_MCLK_OUT0 IMX8DXL_ADC_IN3 3 +#define IMX8DXL_ADC_IN3_LSIO_GPIO1_IO11 IMX8DXL_ADC_IN3 4 +#define IMX8DXL_ADC_IN3_ADMA_LCDIF_D15 IMX8DXL_ADC_IN3 5 +#define IMX8DXL_ADC_IN2_ADMA_ADC_IN2 IMX8DXL_ADC_IN2 0 +#define IMX8DXL_ADC_IN2_M40_UART0_RX IMX8DXL_ADC_IN2 1 +#define IMX8DXL_ADC_IN2_M40_GPIO0_IO02 IMX8DXL_ADC_IN2 2 +#define IMX8DXL_ADC_IN2_ADMA_ACM_MCLK_IN0 IMX8DXL_ADC_IN2 3 +#define IMX8DXL_ADC_IN2_LSIO_GPIO1_IO12 IMX8DXL_ADC_IN2 4 +#define IMX8DXL_ADC_IN2_ADMA_LCDIF_D16 IMX8DXL_ADC_IN2 5 +#define IMX8DXL_ADC_IN5_ADMA_ADC_IN5 IMX8DXL_ADC_IN5 0 +#define IMX8DXL_ADC_IN5_M40_TPM0_CH1 IMX8DXL_ADC_IN5 1 +#define IMX8DXL_ADC_IN5_M40_GPIO0_IO05 IMX8DXL_ADC_IN5 2 +#define IMX8DXL_ADC_IN5_ADMA_LCDIF_LCDBUSY IMX8DXL_ADC_IN5 3 +#define IMX8DXL_ADC_IN5_LSIO_GPIO1_IO13 IMX8DXL_ADC_IN5 4 +#define IMX8DXL_ADC_IN5_ADMA_LCDIF_D17 IMX8DXL_ADC_IN5 5 +#define IMX8DXL_ADC_IN4_ADMA_ADC_IN4 IMX8DXL_ADC_IN4 0 +#define IMX8DXL_ADC_IN4_M40_TPM0_CH0 IMX8DXL_ADC_IN4 1 +#define IMX8DXL_ADC_IN4_M40_GPIO0_IO04 IMX8DXL_ADC_IN4 2 +#define IMX8DXL_ADC_IN4_ADMA_LCDIF_LCDRESET IMX8DXL_ADC_IN4 3 +#define IMX8DXL_ADC_IN4_LSIO_GPIO1_IO14 IMX8DXL_ADC_IN4 4 +#define IMX8DXL_FLEXCAN0_RX_ADMA_FLEXCAN0_RX IMX8DXL_FLEXCAN0_RX 0 +#define IMX8DXL_FLEXCAN0_RX_ADMA_SAI2_RXC IMX8DXL_FLEXCAN0_RX 1 +#define IMX8DXL_FLEXCAN0_RX_ADMA_UART0_RTS_B IMX8DXL_FLEXCAN0_RX 2 +#define IMX8DXL_FLEXCAN0_RX_ADMA_SAI1_TXC IMX8DXL_FLEXCAN0_RX 3 +#define IMX8DXL_FLEXCAN0_RX_LSIO_GPIO1_IO15 IMX8DXL_FLEXCAN0_RX 4 +#define IMX8DXL_FLEXCAN0_RX_LSIO_GPIO6_IO08 IMX8DXL_FLEXCAN0_RX 5 +#define IMX8DXL_FLEXCAN0_TX_ADMA_FLEXCAN0_TX IMX8DXL_FLEXCAN0_TX 0 +#define IMX8DXL_FLEXCAN0_TX_ADMA_SAI2_RXD IMX8DXL_FLEXCAN0_TX 1 +#define IMX8DXL_FLEXCAN0_TX_ADMA_UART0_CTS_B IMX8DXL_FLEXCAN0_TX 2 +#define IMX8DXL_FLEXCAN0_TX_ADMA_SAI1_TXFS IMX8DXL_FLEXCAN0_TX 3 +#define IMX8DXL_FLEXCAN0_TX_LSIO_GPIO1_IO16 IMX8DXL_FLEXCAN0_TX 4 +#define IMX8DXL_FLEXCAN0_TX_LSIO_GPIO6_IO09 IMX8DXL_FLEXCAN0_TX 5 +#define IMX8DXL_FLEXCAN1_RX_ADMA_FLEXCAN1_RX IMX8DXL_FLEXCAN1_RX 0 +#define IMX8DXL_FLEXCAN1_RX_ADMA_SAI2_RXFS IMX8DXL_FLEXCAN1_RX 1 +#define IMX8DXL_FLEXCAN1_RX_ADMA_FTM_CH2 IMX8DXL_FLEXCAN1_RX 2 +#define IMX8DXL_FLEXCAN1_RX_ADMA_SAI1_TXD IMX8DXL_FLEXCAN1_RX 3 +#define IMX8DXL_FLEXCAN1_RX_LSIO_GPIO1_IO17 IMX8DXL_FLEXCAN1_RX 4 +#define IMX8DXL_FLEXCAN1_RX_LSIO_GPIO6_IO10 IMX8DXL_FLEXCAN1_RX 5 +#define IMX8DXL_FLEXCAN1_TX_ADMA_FLEXCAN1_TX IMX8DXL_FLEXCAN1_TX 0 +#define IMX8DXL_FLEXCAN1_TX_ADMA_SAI3_RXC IMX8DXL_FLEXCAN1_TX 1 +#define IMX8DXL_FLEXCAN1_TX_ADMA_DMA0_REQ_IN0 IMX8DXL_FLEXCAN1_TX 2 +#define IMX8DXL_FLEXCAN1_TX_ADMA_SAI1_RXD IMX8DXL_FLEXCAN1_TX 3 +#define IMX8DXL_FLEXCAN1_TX_LSIO_GPIO1_IO18 IMX8DXL_FLEXCAN1_TX 4 +#define IMX8DXL_FLEXCAN1_TX_LSIO_GPIO6_IO11 IMX8DXL_FLEXCAN1_TX 5 +#define IMX8DXL_FLEXCAN2_RX_ADMA_FLEXCAN2_RX IMX8DXL_FLEXCAN2_RX 0 +#define IMX8DXL_FLEXCAN2_RX_ADMA_SAI3_RXD IMX8DXL_FLEXCAN2_RX 1 +#define IMX8DXL_FLEXCAN2_RX_ADMA_UART3_RX IMX8DXL_FLEXCAN2_RX 2 +#define IMX8DXL_FLEXCAN2_RX_ADMA_SAI1_RXFS IMX8DXL_FLEXCAN2_RX 3 +#define IMX8DXL_FLEXCAN2_RX_LSIO_GPIO1_IO19 IMX8DXL_FLEXCAN2_RX 4 +#define IMX8DXL_FLEXCAN2_RX_LSIO_GPIO6_IO12 IMX8DXL_FLEXCAN2_RX 5 +#define IMX8DXL_FLEXCAN2_TX_ADMA_FLEXCAN2_TX IMX8DXL_FLEXCAN2_TX 0 +#define IMX8DXL_FLEXCAN2_TX_ADMA_SAI3_RXFS IMX8DXL_FLEXCAN2_TX 1 +#define IMX8DXL_FLEXCAN2_TX_ADMA_UART3_TX IMX8DXL_FLEXCAN2_TX 2 +#define IMX8DXL_FLEXCAN2_TX_ADMA_SAI1_RXC IMX8DXL_FLEXCAN2_TX 3 +#define IMX8DXL_FLEXCAN2_TX_LSIO_GPIO1_IO20 IMX8DXL_FLEXCAN2_TX 4 +#define IMX8DXL_FLEXCAN2_TX_LSIO_GPIO6_IO13 IMX8DXL_FLEXCAN2_TX 5 +#define IMX8DXL_UART0_RX_ADMA_UART0_RX IMX8DXL_UART0_RX 0 +#define IMX8DXL_UART0_RX_ADMA_MQS_R IMX8DXL_UART0_RX 1 +#define IMX8DXL_UART0_RX_ADMA_FLEXCAN0_RX IMX8DXL_UART0_RX 2 +#define IMX8DXL_UART0_RX_SCU_UART0_RX IMX8DXL_UART0_RX 3 +#define IMX8DXL_UART0_RX_LSIO_GPIO1_IO21 IMX8DXL_UART0_RX 4 +#define IMX8DXL_UART0_RX_LSIO_GPIO6_IO14 IMX8DXL_UART0_RX 5 +#define IMX8DXL_UART0_TX_ADMA_UART0_TX IMX8DXL_UART0_TX 0 +#define IMX8DXL_UART0_TX_ADMA_MQS_L IMX8DXL_UART0_TX 1 +#define IMX8DXL_UART0_TX_ADMA_FLEXCAN0_TX IMX8DXL_UART0_TX 2 +#define IMX8DXL_UART0_TX_SCU_UART0_TX IMX8DXL_UART0_TX 3 +#define IMX8DXL_UART0_TX_LSIO_GPIO1_IO22 IMX8DXL_UART0_TX 4 +#define IMX8DXL_UART0_TX_LSIO_GPIO6_IO15 IMX8DXL_UART0_TX 5 +#define IMX8DXL_UART2_TX_ADMA_UART2_TX IMX8DXL_UART2_TX 0 +#define IMX8DXL_UART2_TX_ADMA_FTM_CH1 IMX8DXL_UART2_TX 1 +#define IMX8DXL_UART2_TX_ADMA_FLEXCAN1_TX IMX8DXL_UART2_TX 2 +#define IMX8DXL_UART2_TX_LSIO_GPIO1_IO23 IMX8DXL_UART2_TX 4 +#define IMX8DXL_UART2_TX_LSIO_GPIO6_IO16 IMX8DXL_UART2_TX 5 +#define IMX8DXL_UART2_RX_ADMA_UART2_RX IMX8DXL_UART2_RX 0 +#define IMX8DXL_UART2_RX_ADMA_FTM_CH0 IMX8DXL_UART2_RX 1 +#define IMX8DXL_UART2_RX_ADMA_FLEXCAN1_RX IMX8DXL_UART2_RX 2 +#define IMX8DXL_UART2_RX_LSIO_GPIO1_IO24 IMX8DXL_UART2_RX 4 +#define IMX8DXL_UART2_RX_LSIO_GPIO6_IO17 IMX8DXL_UART2_RX 5 +#define IMX8DXL_JTAG_TRST_B_SCU_JTAG_TRST_B IMX8DXL_JTAG_TRST_B 0 +#define IMX8DXL_JTAG_TRST_B_SCU_WDOG0_WDOG_OUT IMX8DXL_JTAG_TRST_B 1 +#define IMX8DXL_PMIC_I2C_SCL_SCU_PMIC_I2C_SCL IMX8DXL_PMIC_I2C_SCL 0 +#define IMX8DXL_PMIC_I2C_SCL_SCU_GPIO0_IOXX_PMIC_A35_ON IMX8DXL_PMIC_I2C_SCL 1 +#define IMX8DXL_PMIC_I2C_SCL_LSIO_GPIO2_IO01 IMX8DXL_PMIC_I2C_SCL 4 +#define IMX8DXL_PMIC_I2C_SDA_SCU_PMIC_I2C_SDA IMX8DXL_PMIC_I2C_SDA 0 +#define IMX8DXL_PMIC_I2C_SDA_SCU_GPIO0_IOXX_PMIC_GPU_ON IMX8DXL_PMIC_I2C_SDA 1 +#define IMX8DXL_PMIC_I2C_SDA_LSIO_GPIO2_IO02 IMX8DXL_PMIC_I2C_SDA 4 +#define IMX8DXL_PMIC_INT_B_SCU_DSC_PMIC_INT_B IMX8DXL_PMIC_INT_B 0 +#define IMX8DXL_SCU_GPIO0_00_SCU_GPIO0_IO00 IMX8DXL_SCU_GPIO0_00 0 +#define IMX8DXL_SCU_GPIO0_00_SCU_UART0_RX IMX8DXL_SCU_GPIO0_00 1 +#define IMX8DXL_SCU_GPIO0_00_M40_UART0_RX IMX8DXL_SCU_GPIO0_00 2 +#define IMX8DXL_SCU_GPIO0_00_ADMA_UART3_RX IMX8DXL_SCU_GPIO0_00 3 +#define IMX8DXL_SCU_GPIO0_00_LSIO_GPIO2_IO03 IMX8DXL_SCU_GPIO0_00 4 +#define IMX8DXL_SCU_GPIO0_01_SCU_GPIO0_IO01 IMX8DXL_SCU_GPIO0_01 0 +#define IMX8DXL_SCU_GPIO0_01_SCU_UART0_TX IMX8DXL_SCU_GPIO0_01 1 +#define IMX8DXL_SCU_GPIO0_01_M40_UART0_TX IMX8DXL_SCU_GPIO0_01 2 +#define IMX8DXL_SCU_GPIO0_01_ADMA_UART3_TX IMX8DXL_SCU_GPIO0_01 3 +#define IMX8DXL_SCU_GPIO0_01_SCU_WDOG0_WDOG_OUT IMX8DXL_SCU_GPIO0_01 4 +#define IMX8DXL_SCU_PMIC_STANDBY_SCU_DSC_PMIC_STANDBY IMX8DXL_SCU_PMIC_STANDBY 0 +#define IMX8DXL_SCU_BOOT_MODE1_SCU_DSC_BOOT_MODE1 IMX8DXL_SCU_BOOT_MODE1 0 +#define IMX8DXL_SCU_BOOT_MODE0_SCU_DSC_BOOT_MODE0 IMX8DXL_SCU_BOOT_MODE0 0 +#define IMX8DXL_SCU_BOOT_MODE2_SCU_DSC_BOOT_MODE2 IMX8DXL_SCU_BOOT_MODE2 0 +#define IMX8DXL_SCU_BOOT_MODE2_SCU_DSC_RTC_CLOCK_OUTPUT_32K IMX8DXL_SCU_BOOT_MODE2 1 +#define IMX8DXL_SNVS_TAMPER_OUT1_LSIO_GPIO2_IO05_IN IMX8DXL_SNVS_TAMPER_OUT1 4 +#define IMX8DXL_SNVS_TAMPER_OUT1_LSIO_GPIO6_IO19_IN IMX8DXL_SNVS_TAMPER_OUT1 5 +#define IMX8DXL_SNVS_TAMPER_OUT2_LSIO_GPIO2_IO06_IN IMX8DXL_SNVS_TAMPER_OUT2 4 +#define IMX8DXL_SNVS_TAMPER_OUT2_LSIO_GPIO6_IO20_IN IMX8DXL_SNVS_TAMPER_OUT2 5 +#define IMX8DXL_SNVS_TAMPER_OUT3_ADMA_SAI2_RXC IMX8DXL_SNVS_TAMPER_OUT3 2 +#define IMX8DXL_SNVS_TAMPER_OUT3_LSIO_GPIO2_IO07_IN IMX8DXL_SNVS_TAMPER_OUT3 4 +#define IMX8DXL_SNVS_TAMPER_OUT3_LSIO_GPIO6_IO21_IN IMX8DXL_SNVS_TAMPER_OUT3 5 +#define IMX8DXL_SNVS_TAMPER_OUT4_ADMA_SAI2_RXD IMX8DXL_SNVS_TAMPER_OUT4 2 +#define IMX8DXL_SNVS_TAMPER_OUT4_LSIO_GPIO2_IO08_IN IMX8DXL_SNVS_TAMPER_OUT4 4 +#define IMX8DXL_SNVS_TAMPER_OUT4_LSIO_GPIO6_IO22_IN IMX8DXL_SNVS_TAMPER_OUT4 5 +#define IMX8DXL_SNVS_TAMPER_IN0_ADMA_SAI2_RXFS IMX8DXL_SNVS_TAMPER_IN0 2 +#define IMX8DXL_SNVS_TAMPER_IN0_LSIO_GPIO2_IO09_IN IMX8DXL_SNVS_TAMPER_IN0 4 +#define IMX8DXL_SNVS_TAMPER_IN0_LSIO_GPIO6_IO23_IN IMX8DXL_SNVS_TAMPER_IN0 5 +#define IMX8DXL_SNVS_TAMPER_IN1_ADMA_SAI3_RXC IMX8DXL_SNVS_TAMPER_IN1 2 +#define IMX8DXL_SNVS_TAMPER_IN1_LSIO_GPIO2_IO10_IN IMX8DXL_SNVS_TAMPER_IN1 4 +#define IMX8DXL_SNVS_TAMPER_IN1_LSIO_GPIO6_IO24_IN IMX8DXL_SNVS_TAMPER_IN1 5 +#define IMX8DXL_SNVS_TAMPER_IN2_ADMA_SAI3_RXD IMX8DXL_SNVS_TAMPER_IN2 2 +#define IMX8DXL_SNVS_TAMPER_IN2_LSIO_GPIO2_IO11_IN IMX8DXL_SNVS_TAMPER_IN2 4 +#define IMX8DXL_SNVS_TAMPER_IN2_LSIO_GPIO6_IO25_IN IMX8DXL_SNVS_TAMPER_IN2 5 +#define IMX8DXL_SNVS_TAMPER_IN3_ADMA_SAI3_RXFS IMX8DXL_SNVS_TAMPER_IN3 2 +#define IMX8DXL_SNVS_TAMPER_IN3_LSIO_GPIO2_IO12_IN IMX8DXL_SNVS_TAMPER_IN3 4 +#define IMX8DXL_SNVS_TAMPER_IN3_LSIO_GPIO6_IO26_IN IMX8DXL_SNVS_TAMPER_IN3 5 +#define IMX8DXL_SPI1_SCK_ADMA_I2C2_SDA IMX8DXL_SPI1_SCK 2 +#define IMX8DXL_SPI1_SCK_ADMA_SPI1_SCK IMX8DXL_SPI1_SCK 3 +#define IMX8DXL_SPI1_SCK_LSIO_GPIO3_IO00 IMX8DXL_SPI1_SCK 4 +#define IMX8DXL_SPI1_SDO_ADMA_I2C2_SCL IMX8DXL_SPI1_SDO 2 +#define IMX8DXL_SPI1_SDO_ADMA_SPI1_SDO IMX8DXL_SPI1_SDO 3 +#define IMX8DXL_SPI1_SDO_LSIO_GPIO3_IO01 IMX8DXL_SPI1_SDO 4 +#define IMX8DXL_SPI1_SDI_ADMA_I2C3_SCL IMX8DXL_SPI1_SDI 2 +#define IMX8DXL_SPI1_SDI_ADMA_SPI1_SDI IMX8DXL_SPI1_SDI 3 +#define IMX8DXL_SPI1_SDI_LSIO_GPIO3_IO02 IMX8DXL_SPI1_SDI 4 +#define IMX8DXL_SPI1_CS0_ADMA_I2C3_SDA IMX8DXL_SPI1_CS0 2 +#define IMX8DXL_SPI1_CS0_ADMA_SPI1_CS0 IMX8DXL_SPI1_CS0 3 +#define IMX8DXL_SPI1_CS0_LSIO_GPIO3_IO03 IMX8DXL_SPI1_CS0 4 +#define IMX8DXL_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 IMX8DXL_QSPI0A_DATA1 0 +#define IMX8DXL_QSPI0A_DATA1_LSIO_GPIO3_IO10 IMX8DXL_QSPI0A_DATA1 4 +#define IMX8DXL_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 IMX8DXL_QSPI0A_DATA0 0 +#define IMX8DXL_QSPI0A_DATA0_LSIO_GPIO3_IO09 IMX8DXL_QSPI0A_DATA0 4 +#define IMX8DXL_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 IMX8DXL_QSPI0A_DATA3 0 +#define IMX8DXL_QSPI0A_DATA3_LSIO_GPIO3_IO12 IMX8DXL_QSPI0A_DATA3 4 +#define IMX8DXL_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 IMX8DXL_QSPI0A_DATA2 0 +#define IMX8DXL_QSPI0A_DATA2_LSIO_GPIO3_IO11 IMX8DXL_QSPI0A_DATA2 4 +#define IMX8DXL_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B IMX8DXL_QSPI0A_SS0_B 0 +#define IMX8DXL_QSPI0A_SS0_B_LSIO_GPIO3_IO14 IMX8DXL_QSPI0A_SS0_B 4 +#define IMX8DXL_QSPI0A_DQS_LSIO_QSPI0A_DQS IMX8DXL_QSPI0A_DQS 0 +#define IMX8DXL_QSPI0A_DQS_LSIO_GPIO3_IO13 IMX8DXL_QSPI0A_DQS 4 +#define IMX8DXL_QSPI0A_SCLK_LSIO_QSPI0A_SCLK IMX8DXL_QSPI0A_SCLK 0 +#define IMX8DXL_QSPI0A_SCLK_LSIO_GPIO3_IO16 IMX8DXL_QSPI0A_SCLK 4 +#define IMX8DXL_QSPI0B_SCLK_LSIO_QSPI0B_SCLK IMX8DXL_QSPI0B_SCLK 0 +#define IMX8DXL_QSPI0B_SCLK_LSIO_GPIO3_IO17 IMX8DXL_QSPI0B_SCLK 4 +#define IMX8DXL_QSPI0B_DQS_LSIO_QSPI0B_DQS IMX8DXL_QSPI0B_DQS 0 +#define IMX8DXL_QSPI0B_DQS_LSIO_GPIO3_IO22 IMX8DXL_QSPI0B_DQS 4 +#define IMX8DXL_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 IMX8DXL_QSPI0B_DATA1 0 +#define IMX8DXL_QSPI0B_DATA1_LSIO_GPIO3_IO19 IMX8DXL_QSPI0B_DATA1 4 +#define IMX8DXL_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 IMX8DXL_QSPI0B_DATA0 0 +#define IMX8DXL_QSPI0B_DATA0_LSIO_GPIO3_IO18 IMX8DXL_QSPI0B_DATA0 4 +#define IMX8DXL_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 IMX8DXL_QSPI0B_DATA3 0 +#define IMX8DXL_QSPI0B_DATA3_LSIO_GPIO3_IO21 IMX8DXL_QSPI0B_DATA3 4 +#define IMX8DXL_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 IMX8DXL_QSPI0B_DATA2 0 +#define IMX8DXL_QSPI0B_DATA2_LSIO_GPIO3_IO20 IMX8DXL_QSPI0B_DATA2 4 +#define IMX8DXL_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B IMX8DXL_QSPI0B_SS0_B 0 +#define IMX8DXL_QSPI0B_SS0_B_LSIO_GPIO3_IO23 IMX8DXL_QSPI0B_SS0_B 4 +#define IMX8DXL_QSPI0B_SS0_B_LSIO_QSPI0A_SS1_B IMX8DXL_QSPI0B_SS0_B 5 + +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_PCIESEP_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_PCIESEP 0 +#define IMX8DXL_COMP_CTL_GPIO_3V3_USB3IO_PAD IMX8DXL_COMP_CTL_GPIO_3V3_USB3IO 0 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 0 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_VSELSEP_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_VSELSEP 0 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 0 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 0 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOCT_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOCT 0 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB 0 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK 0 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHT_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHT 0 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOLH_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOLH 0 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHD_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHD 0 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_QSPI0A_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_QSPI0A 0 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_QSPI0B_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_QSPI0B 0 + +#endif diff --git a/include/dt-bindings/pinctrl/pinctrl-starfive-jh7100.h b/include/dt-bindings/pinctrl/pinctrl-starfive-jh7100.h new file mode 100644 index 000000000000..a200f546d078 --- /dev/null +++ b/include/dt-bindings/pinctrl/pinctrl-starfive-jh7100.h @@ -0,0 +1,275 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk> + */ + +#ifndef __DT_BINDINGS_PINCTRL_STARFIVE_JH7100_H__ +#define __DT_BINDINGS_PINCTRL_STARFIVE_JH7100_H__ + +#define PAD_GPIO_OFFSET 0 +#define PAD_FUNC_SHARE_OFFSET 64 +#define PAD_GPIO(x) (PAD_GPIO_OFFSET + (x)) +#define PAD_FUNC_SHARE(x) (PAD_FUNC_SHARE_OFFSET + (x)) + +/* + * GPIOMUX bits: + * | 31 - 24 | 23 - 16 | 15 - 8 | 7 | 6 | 5 - 0 | + * | dout | doen | din | dout rev | doen rev | gpio nr | + * + * dout: output signal + * doen: output enable signal + * din: optional input signal, 0xff = none + * dout rev: output signal reverse bit + * doen rev: output enable signal reverse bit + * gpio nr: gpio number, 0 - 63 + */ +#define GPIOMUX(n, dout, doen, din) ( \ + (((dout) & 0x80000000) >> (31 - 7)) | (((dout) & 0xff) << 24) | \ + (((doen) & 0x80000000) >> (31 - 6)) | (((doen) & 0xff) << 16) | \ + (((din) & 0xff) << 8) | \ + ((n) & 0x3f)) + +#define GPO_REVERSE 0x80000000 + +#define GPO_LOW 0 +#define GPO_HIGH 1 +#define GPO_ENABLE 0 +#define GPO_DISABLE 1 +#define GPO_CLK_GMAC_PAPHYREF 2 +#define GPO_JTAG_TDO 3 +#define GPO_JTAG_TDO_OEN 4 +#define GPO_DMIC_CLK_OUT 5 +#define GPO_DSP_JTDOEN_PAD 6 +#define GPO_DSP_JTDO_PAD 7 +#define GPO_I2C0_PAD_SCK_OE 8 +#define GPO_I2C0_PAD_SCK_OEN (GPO_I2C0_PAD_SCK_OE | GPO_REVERSE) +#define GPO_I2C0_PAD_SDA_OE 9 +#define GPO_I2C0_PAD_SDA_OEN (GPO_I2C0_PAD_SDA_OE | GPO_REVERSE) +#define GPO_I2C1_PAD_SCK_OE 10 +#define GPO_I2C1_PAD_SCK_OEN (GPO_I2C1_PAD_SCK_OE | GPO_REVERSE) +#define GPO_I2C1_PAD_SDA_OE 11 +#define GPO_I2C1_PAD_SDA_OEN (GPO_I2C1_PAD_SDA_OE | GPO_REVERSE) +#define GPO_I2C2_PAD_SCK_OE 12 +#define GPO_I2C2_PAD_SCK_OEN (GPO_I2C2_PAD_SCK_OE | GPO_REVERSE) +#define GPO_I2C2_PAD_SDA_OE 13 +#define GPO_I2C2_PAD_SDA_OEN (GPO_I2C2_PAD_SDA_OE | GPO_REVERSE) +#define GPO_I2C3_PAD_SCK_OE 14 +#define GPO_I2C3_PAD_SCK_OEN (GPO_I2C3_PAD_SCK_OE | GPO_REVERSE) +#define GPO_I2C3_PAD_SDA_OE 15 +#define GPO_I2C3_PAD_SDA_OEN (GPO_I2C3_PAD_SDA_OE | GPO_REVERSE) +#define GPO_I2SRX_BCLK_OUT 16 +#define GPO_I2SRX_BCLK_OUT_OEN 17 +#define GPO_I2SRX_LRCK_OUT 18 +#define GPO_I2SRX_LRCK_OUT_OEN 19 +#define GPO_I2SRX_MCLK_OUT 20 +#define GPO_I2STX_BCLK_OUT 21 +#define GPO_I2STX_BCLK_OUT_OEN 22 +#define GPO_I2STX_LRCK_OUT 23 +#define GPO_I2STX_LRCK_OUT_OEN 24 +#define GPO_I2STX_MCLK_OUT 25 +#define GPO_I2STX_SDOUT0 26 +#define GPO_I2STX_SDOUT1 27 +#define GPO_LCD_PAD_CSM_N 28 +#define GPO_PWM_PAD_OE_N_BIT0 29 +#define GPO_PWM_PAD_OE_N_BIT1 30 +#define GPO_PWM_PAD_OE_N_BIT2 31 +#define GPO_PWM_PAD_OE_N_BIT3 32 +#define GPO_PWM_PAD_OE_N_BIT4 33 +#define GPO_PWM_PAD_OE_N_BIT5 34 +#define GPO_PWM_PAD_OE_N_BIT6 35 +#define GPO_PWM_PAD_OE_N_BIT7 36 +#define GPO_PWM_PAD_OUT_BIT0 37 +#define GPO_PWM_PAD_OUT_BIT1 38 +#define GPO_PWM_PAD_OUT_BIT2 39 +#define GPO_PWM_PAD_OUT_BIT3 40 +#define GPO_PWM_PAD_OUT_BIT4 41 +#define GPO_PWM_PAD_OUT_BIT5 42 +#define GPO_PWM_PAD_OUT_BIT6 43 +#define GPO_PWM_PAD_OUT_BIT7 44 +#define GPO_PWMDAC_LEFT_OUT 45 +#define GPO_PWMDAC_RIGHT_OUT 46 +#define GPO_QSPI_CSN1_OUT 47 +#define GPO_QSPI_CSN2_OUT 48 +#define GPO_QSPI_CSN3_OUT 49 +#define GPO_REGISTER23_SCFG_CMSENSOR_RST0 50 +#define GPO_REGISTER23_SCFG_CMSENSOR_RST1 51 +#define GPO_REGISTER32_SCFG_GMAC_PHY_RSTN 52 +#define GPO_SDIO0_PAD_CARD_POWER_EN 53 +#define GPO_SDIO0_PAD_CCLK_OUT 54 +#define GPO_SDIO0_PAD_CCMD_OE 55 +#define GPO_SDIO0_PAD_CCMD_OEN (GPO_SDIO0_PAD_CCMD_OE | GPO_REVERSE) +#define GPO_SDIO0_PAD_CCMD_OUT 56 +#define GPO_SDIO0_PAD_CDATA_OE_BIT0 57 +#define GPO_SDIO0_PAD_CDATA_OEN_BIT0 (GPO_SDIO0_PAD_CDATA_OE_BIT0 | GPO_REVERSE) +#define GPO_SDIO0_PAD_CDATA_OE_BIT1 58 +#define GPO_SDIO0_PAD_CDATA_OEN_BIT1 (GPO_SDIO0_PAD_CDATA_OE_BIT1 | GPO_REVERSE) +#define GPO_SDIO0_PAD_CDATA_OE_BIT2 59 +#define GPO_SDIO0_PAD_CDATA_OEN_BIT2 (GPO_SDIO0_PAD_CDATA_OE_BIT2 | GPO_REVERSE) +#define GPO_SDIO0_PAD_CDATA_OE_BIT3 60 +#define GPO_SDIO0_PAD_CDATA_OEN_BIT3 (GPO_SDIO0_PAD_CDATA_OE_BIT3 | GPO_REVERSE) +#define GPO_SDIO0_PAD_CDATA_OE_BIT4 61 +#define GPO_SDIO0_PAD_CDATA_OEN_BIT4 (GPO_SDIO0_PAD_CDATA_OE_BIT4 | GPO_REVERSE) +#define GPO_SDIO0_PAD_CDATA_OE_BIT5 62 +#define GPO_SDIO0_PAD_CDATA_OEN_BIT5 (GPO_SDIO0_PAD_CDATA_OE_BIT5 | GPO_REVERSE) +#define GPO_SDIO0_PAD_CDATA_OE_BIT6 63 +#define GPO_SDIO0_PAD_CDATA_OEN_BIT6 (GPO_SDIO0_PAD_CDATA_OE_BIT6 | GPO_REVERSE) +#define GPO_SDIO0_PAD_CDATA_OE_BIT7 64 +#define GPO_SDIO0_PAD_CDATA_OEN_BIT7 (GPO_SDIO0_PAD_CDATA_OE_BIT7 | GPO_REVERSE) +#define GPO_SDIO0_PAD_CDATA_OUT_BIT0 65 +#define GPO_SDIO0_PAD_CDATA_OUT_BIT1 66 +#define GPO_SDIO0_PAD_CDATA_OUT_BIT2 67 +#define GPO_SDIO0_PAD_CDATA_OUT_BIT3 68 +#define GPO_SDIO0_PAD_CDATA_OUT_BIT4 69 +#define GPO_SDIO0_PAD_CDATA_OUT_BIT5 70 +#define GPO_SDIO0_PAD_CDATA_OUT_BIT6 71 +#define GPO_SDIO0_PAD_CDATA_OUT_BIT7 72 +#define GPO_SDIO0_PAD_RST_N 73 +#define GPO_SDIO1_PAD_CARD_POWER_EN 74 +#define GPO_SDIO1_PAD_CCLK_OUT 75 +#define GPO_SDIO1_PAD_CCMD_OE 76 +#define GPO_SDIO1_PAD_CCMD_OEN (GPO_SDIO1_PAD_CCMD_OE | GPO_REVERSE) +#define GPO_SDIO1_PAD_CCMD_OUT 77 +#define GPO_SDIO1_PAD_CDATA_OE_BIT0 78 +#define GPO_SDIO1_PAD_CDATA_OEN_BIT0 (GPO_SDIO1_PAD_CDATA_OE_BIT0 | GPO_REVERSE) +#define GPO_SDIO1_PAD_CDATA_OE_BIT1 79 +#define GPO_SDIO1_PAD_CDATA_OEN_BIT1 (GPO_SDIO1_PAD_CDATA_OE_BIT1 | GPO_REVERSE) +#define GPO_SDIO1_PAD_CDATA_OE_BIT2 80 +#define GPO_SDIO1_PAD_CDATA_OEN_BIT2 (GPO_SDIO1_PAD_CDATA_OE_BIT2 | GPO_REVERSE) +#define GPO_SDIO1_PAD_CDATA_OE_BIT3 81 +#define GPO_SDIO1_PAD_CDATA_OEN_BIT3 (GPO_SDIO1_PAD_CDATA_OE_BIT3 | GPO_REVERSE) +#define GPO_SDIO1_PAD_CDATA_OE_BIT4 82 +#define GPO_SDIO1_PAD_CDATA_OEN_BIT4 (GPO_SDIO1_PAD_CDATA_OE_BIT4 | GPO_REVERSE) +#define GPO_SDIO1_PAD_CDATA_OE_BIT5 83 +#define GPO_SDIO1_PAD_CDATA_OEN_BIT5 (GPO_SDIO1_PAD_CDATA_OE_BIT5 | GPO_REVERSE) +#define GPO_SDIO1_PAD_CDATA_OE_BIT6 84 +#define GPO_SDIO1_PAD_CDATA_OEN_BIT6 (GPO_SDIO1_PAD_CDATA_OE_BIT6 | GPO_REVERSE) +#define GPO_SDIO1_PAD_CDATA_OE_BIT7 85 +#define GPO_SDIO1_PAD_CDATA_OEN_BIT7 (GPO_SDIO1_PAD_CDATA_OE_BIT7 | GPO_REVERSE) +#define GPO_SDIO1_PAD_CDATA_OUT_BIT0 86 +#define GPO_SDIO1_PAD_CDATA_OUT_BIT1 87 +#define GPO_SDIO1_PAD_CDATA_OUT_BIT2 88 +#define GPO_SDIO1_PAD_CDATA_OUT_BIT3 89 +#define GPO_SDIO1_PAD_CDATA_OUT_BIT4 90 +#define GPO_SDIO1_PAD_CDATA_OUT_BIT5 91 +#define GPO_SDIO1_PAD_CDATA_OUT_BIT6 92 +#define GPO_SDIO1_PAD_CDATA_OUT_BIT7 93 +#define GPO_SDIO1_PAD_RST_N 94 +#define GPO_SPDIF_TX_SDOUT 95 +#define GPO_SPDIF_TX_SDOUT_OEN 96 +#define GPO_SPI0_PAD_OE_N 97 +#define GPO_SPI0_PAD_SCK_OUT 98 +#define GPO_SPI0_PAD_SS_0_N 99 +#define GPO_SPI0_PAD_SS_1_N 100 +#define GPO_SPI0_PAD_TXD 101 +#define GPO_SPI1_PAD_OE_N 102 +#define GPO_SPI1_PAD_SCK_OUT 103 +#define GPO_SPI1_PAD_SS_0_N 104 +#define GPO_SPI1_PAD_SS_1_N 105 +#define GPO_SPI1_PAD_TXD 106 +#define GPO_SPI2_PAD_OE_N 107 +#define GPO_SPI2_PAD_SCK_OUT 108 +#define GPO_SPI2_PAD_SS_0_N 109 +#define GPO_SPI2_PAD_SS_1_N 110 +#define GPO_SPI2_PAD_TXD 111 +#define GPO_SPI2AHB_PAD_OE_N_BIT0 112 +#define GPO_SPI2AHB_PAD_OE_N_BIT1 113 +#define GPO_SPI2AHB_PAD_OE_N_BIT2 114 +#define GPO_SPI2AHB_PAD_OE_N_BIT3 115 +#define GPO_SPI2AHB_PAD_TXD_BIT0 116 +#define GPO_SPI2AHB_PAD_TXD_BIT1 117 +#define GPO_SPI2AHB_PAD_TXD_BIT2 118 +#define GPO_SPI2AHB_PAD_TXD_BIT3 119 +#define GPO_SPI3_PAD_OE_N 120 +#define GPO_SPI3_PAD_SCK_OUT 121 +#define GPO_SPI3_PAD_SS_0_N 122 +#define GPO_SPI3_PAD_SS_1_N 123 +#define GPO_SPI3_PAD_TXD 124 +#define GPO_UART0_PAD_DTRN 125 +#define GPO_UART0_PAD_RTSN 126 +#define GPO_UART0_PAD_SOUT 127 +#define GPO_UART1_PAD_SOUT 128 +#define GPO_UART2_PAD_DTR_N 129 +#define GPO_UART2_PAD_RTS_N 130 +#define GPO_UART2_PAD_SOUT 131 +#define GPO_UART3_PAD_SOUT 132 +#define GPO_USB_DRV_BUS 133 + +#define GPI_CPU_JTAG_TCK 0 +#define GPI_CPU_JTAG_TDI 1 +#define GPI_CPU_JTAG_TMS 2 +#define GPI_CPU_JTAG_TRST 3 +#define GPI_DMIC_SDIN_BIT0 4 +#define GPI_DMIC_SDIN_BIT1 5 +#define GPI_DSP_JTCK_PAD 6 +#define GPI_DSP_JTDI_PAD 7 +#define GPI_DSP_JTMS_PAD 8 +#define GPI_DSP_TRST_PAD 9 +#define GPI_I2C0_PAD_SCK_IN 10 +#define GPI_I2C0_PAD_SDA_IN 11 +#define GPI_I2C1_PAD_SCK_IN 12 +#define GPI_I2C1_PAD_SDA_IN 13 +#define GPI_I2C2_PAD_SCK_IN 14 +#define GPI_I2C2_PAD_SDA_IN 15 +#define GPI_I2C3_PAD_SCK_IN 16 +#define GPI_I2C3_PAD_SDA_IN 17 +#define GPI_I2SRX_BCLK_IN 18 +#define GPI_I2SRX_LRCK_IN 19 +#define GPI_I2SRX_SDIN_BIT0 20 +#define GPI_I2SRX_SDIN_BIT1 21 +#define GPI_I2SRX_SDIN_BIT2 22 +#define GPI_I2STX_BCLK_IN 23 +#define GPI_I2STX_LRCK_IN 24 +#define GPI_SDIO0_PAD_CARD_DETECT_N 25 +#define GPI_SDIO0_PAD_CARD_WRITE_PRT 26 +#define GPI_SDIO0_PAD_CCMD_IN 27 +#define GPI_SDIO0_PAD_CDATA_IN_BIT0 28 +#define GPI_SDIO0_PAD_CDATA_IN_BIT1 29 +#define GPI_SDIO0_PAD_CDATA_IN_BIT2 30 +#define GPI_SDIO0_PAD_CDATA_IN_BIT3 31 +#define GPI_SDIO0_PAD_CDATA_IN_BIT4 32 +#define GPI_SDIO0_PAD_CDATA_IN_BIT5 33 +#define GPI_SDIO0_PAD_CDATA_IN_BIT6 34 +#define GPI_SDIO0_PAD_CDATA_IN_BIT7 35 +#define GPI_SDIO1_PAD_CARD_DETECT_N 36 +#define GPI_SDIO1_PAD_CARD_WRITE_PRT 37 +#define GPI_SDIO1_PAD_CCMD_IN 38 +#define GPI_SDIO1_PAD_CDATA_IN_BIT0 39 +#define GPI_SDIO1_PAD_CDATA_IN_BIT1 40 +#define GPI_SDIO1_PAD_CDATA_IN_BIT2 41 +#define GPI_SDIO1_PAD_CDATA_IN_BIT3 42 +#define GPI_SDIO1_PAD_CDATA_IN_BIT4 43 +#define GPI_SDIO1_PAD_CDATA_IN_BIT5 44 +#define GPI_SDIO1_PAD_CDATA_IN_BIT6 45 +#define GPI_SDIO1_PAD_CDATA_IN_BIT7 46 +#define GPI_SPDIF_RX_SDIN 47 +#define GPI_SPI0_PAD_RXD 48 +#define GPI_SPI0_PAD_SS_IN_N 49 +#define GPI_SPI1_PAD_RXD 50 +#define GPI_SPI1_PAD_SS_IN_N 51 +#define GPI_SPI2_PAD_RXD 52 +#define GPI_SPI2_PAD_SS_IN_N 53 +#define GPI_SPI2AHB_PAD_RXD_BIT0 54 +#define GPI_SPI2AHB_PAD_RXD_BIT1 55 +#define GPI_SPI2AHB_PAD_RXD_BIT2 56 +#define GPI_SPI2AHB_PAD_RXD_BIT3 57 +#define GPI_SPI2AHB_PAD_SS_N 58 +#define GPI_SPI2AHB_SLV_SCLKIN 59 +#define GPI_SPI3_PAD_RXD 60 +#define GPI_SPI3_PAD_SS_IN_N 61 +#define GPI_UART0_PAD_CTSN 62 +#define GPI_UART0_PAD_DCDN 63 +#define GPI_UART0_PAD_DSRN 64 +#define GPI_UART0_PAD_RIN 65 +#define GPI_UART0_PAD_SIN 66 +#define GPI_UART1_PAD_SIN 67 +#define GPI_UART2_PAD_CTS_N 68 +#define GPI_UART2_PAD_DCD_N 69 +#define GPI_UART2_PAD_DSR_N 70 +#define GPI_UART2_PAD_RI_N 71 +#define GPI_UART2_PAD_SIN 72 +#define GPI_UART3_PAD_SIN 73 +#define GPI_USB_OVER_CURRENT 74 + +#define GPI_NONE 0xff + +#endif /* __DT_BINDINGS_PINCTRL_STARFIVE_JH7100_H__ */ diff --git a/include/dt-bindings/pinctrl/pinctrl-zynq.h b/include/dt-bindings/pinctrl/pinctrl-zynq.h new file mode 100644 index 000000000000..bbfc345f017d --- /dev/null +++ b/include/dt-bindings/pinctrl/pinctrl-zynq.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * MIO pin configuration defines for Xilinx Zynq + * + * Copyright (C) 2021 Xilinx, Inc. + */ + +#ifndef _DT_BINDINGS_PINCTRL_ZYNQ_H +#define _DT_BINDINGS_PINCTRL_ZYNQ_H + +/* Configuration options for different power supplies */ +#define IO_STANDARD_LVCMOS18 1 +#define IO_STANDARD_LVCMOS25 2 +#define IO_STANDARD_LVCMOS33 3 +#define IO_STANDARD_HSTL 4 + +#endif /* _DT_BINDINGS_PINCTRL_ZYNQ_H */ diff --git a/include/dt-bindings/pinctrl/pinctrl-zynqmp.h b/include/dt-bindings/pinctrl/pinctrl-zynqmp.h new file mode 100644 index 000000000000..cdb215734bdf --- /dev/null +++ b/include/dt-bindings/pinctrl/pinctrl-zynqmp.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * MIO pin configuration defines for Xilinx ZynqMP + * + * Copyright (C) 2020 Xilinx, Inc. + */ + +#ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H +#define _DT_BINDINGS_PINCTRL_ZYNQMP_H + +/* Bit value for different voltage levels */ +#define IO_STANDARD_LVCMOS33 0 +#define IO_STANDARD_LVCMOS18 1 + +/* Bit values for Slew Rates */ +#define SLEW_RATE_FAST 0 +#define SLEW_RATE_SLOW 1 + +#endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */ diff --git a/include/dt-bindings/pinctrl/r7s9210-pinctrl.h b/include/dt-bindings/pinctrl/r7s9210-pinctrl.h index 2d0c23e5d3a7..8736ce038eca 100644 --- a/include/dt-bindings/pinctrl/r7s9210-pinctrl.h +++ b/include/dt-bindings/pinctrl/r7s9210-pinctrl.h @@ -42,6 +42,6 @@ /* * Convert a port and pin label to its global pin index */ - #define RZA2_PIN(port, pin) ((port) * RZA2_PINS_PER_PORT + (pin)) +#define RZA2_PIN(port, pin) ((port) * RZA2_PINS_PER_PORT + (pin)) #endif /* __DT_BINDINGS_PINCTRL_RENESAS_RZA2_H */ diff --git a/include/dt-bindings/pinctrl/rockchip.h b/include/dt-bindings/pinctrl/rockchip.h index 6d6bac1c26d7..5f291045e8fd 100644 --- a/include/dt-bindings/pinctrl/rockchip.h +++ b/include/dt-bindings/pinctrl/rockchip.h @@ -9,13 +9,6 @@ #ifndef __DT_BINDINGS_ROCKCHIP_PINCTRL_H__ #define __DT_BINDINGS_ROCKCHIP_PINCTRL_H__ -#define RK_GPIO0 0 -#define RK_GPIO1 1 -#define RK_GPIO2 2 -#define RK_GPIO3 3 -#define RK_GPIO4 4 -#define RK_GPIO6 6 - #define RK_PA0 0 #define RK_PA1 1 #define RK_PA2 2 @@ -50,9 +43,5 @@ #define RK_PD7 31 #define RK_FUNC_GPIO 0 -#define RK_FUNC_1 1 /* deprecated */ -#define RK_FUNC_2 2 /* deprecated */ -#define RK_FUNC_3 3 /* deprecated */ -#define RK_FUNC_4 4 /* deprecated */ #endif diff --git a/include/dt-bindings/pinctrl/rzg2l-pinctrl.h b/include/dt-bindings/pinctrl/rzg2l-pinctrl.h new file mode 100644 index 000000000000..c78ed5e5efb7 --- /dev/null +++ b/include/dt-bindings/pinctrl/rzg2l-pinctrl.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * This header provides constants for Renesas RZ/G2L family pinctrl bindings. + * + * Copyright (C) 2021 Renesas Electronics Corp. + * + */ + +#ifndef __DT_BINDINGS_RZG2L_PINCTRL_H +#define __DT_BINDINGS_RZG2L_PINCTRL_H + +#define RZG2L_PINS_PER_PORT 8 + +/* + * Create the pin index from its bank and position numbers and store in + * the upper 16 bits the alternate function identifier + */ +#define RZG2L_PORT_PINMUX(b, p, f) ((b) * RZG2L_PINS_PER_PORT + (p) | ((f) << 16)) + +/* Convert a port and pin label to its global pin index */ +#define RZG2L_GPIO(port, pin) ((port) * RZG2L_PINS_PER_PORT + (pin)) + +#endif /* __DT_BINDINGS_RZG2L_PINCTRL_H */ diff --git a/include/dt-bindings/pinctrl/rzv2m-pinctrl.h b/include/dt-bindings/pinctrl/rzv2m-pinctrl.h new file mode 100644 index 000000000000..525532cd15da --- /dev/null +++ b/include/dt-bindings/pinctrl/rzv2m-pinctrl.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * This header provides constants for Renesas RZ/V2M pinctrl bindings. + * + * Copyright (C) 2022 Renesas Electronics Corp. + * + */ + +#ifndef __DT_BINDINGS_RZV2M_PINCTRL_H +#define __DT_BINDINGS_RZV2M_PINCTRL_H + +#define RZV2M_PINS_PER_PORT 16 + +/* + * Create the pin index from its bank and position numbers and store in + * the upper 16 bits the alternate function identifier + */ +#define RZV2M_PORT_PINMUX(b, p, f) ((b) * RZV2M_PINS_PER_PORT + (p) | ((f) << 16)) + +/* Convert a port and pin label to its global pin index */ +#define RZV2M_GPIO(port, pin) ((port) * RZV2M_PINS_PER_PORT + (pin)) + +#endif /* __DT_BINDINGS_RZV2M_PINCTRL_H */ diff --git a/include/dt-bindings/pinctrl/samsung.h b/include/dt-bindings/pinctrl/samsung.h index b1832506b923..d1da5ff68d0c 100644 --- a/include/dt-bindings/pinctrl/samsung.h +++ b/include/dt-bindings/pinctrl/samsung.h @@ -10,6 +10,13 @@ #ifndef __DT_BINDINGS_PINCTRL_SAMSUNG_H__ #define __DT_BINDINGS_PINCTRL_SAMSUNG_H__ +/* + * These bindings are deprecated, because they do not match the actual + * concept of bindings but rather contain pure register values. + * Instead include the header in the DTS source directory. + */ +#warning "These bindings are deprecated. Instead use the header in the DTS source directory." + #define EXYNOS_PIN_PULL_NONE 0 #define EXYNOS_PIN_PULL_DOWN 1 #define EXYNOS_PIN_PULL_UP 3 @@ -36,7 +43,10 @@ #define EXYNOS5260_PIN_DRV_LV4 2 #define EXYNOS5260_PIN_DRV_LV6 3 -/* Drive strengths for Exynos5410, Exynos542x and Exynos5800 */ +/* + * Drive strengths for Exynos5410, Exynos542x, Exynos5800 and Exynos850 (except + * GPIO_HSI block) + */ #define EXYNOS5420_PIN_DRV_LV1 0 #define EXYNOS5420_PIN_DRV_LV2 1 #define EXYNOS5420_PIN_DRV_LV3 2 @@ -56,6 +66,14 @@ #define EXYNOS5433_PIN_DRV_SLOW_SR5 0xc #define EXYNOS5433_PIN_DRV_SLOW_SR6 0xf +/* Drive strengths for Exynos850 GPIO_HSI block */ +#define EXYNOS850_HSI_PIN_DRV_LV1 0 /* 1x */ +#define EXYNOS850_HSI_PIN_DRV_LV1_5 1 /* 1.5x */ +#define EXYNOS850_HSI_PIN_DRV_LV2 2 /* 2x */ +#define EXYNOS850_HSI_PIN_DRV_LV2_5 3 /* 2.5x */ +#define EXYNOS850_HSI_PIN_DRV_LV3 4 /* 3x */ +#define EXYNOS850_HSI_PIN_DRV_LV4 5 /* 4x */ + #define EXYNOS_PIN_FUNC_INPUT 0 #define EXYNOS_PIN_FUNC_OUTPUT 1 #define EXYNOS_PIN_FUNC_2 2 diff --git a/include/dt-bindings/pinctrl/sppctl-sp7021.h b/include/dt-bindings/pinctrl/sppctl-sp7021.h new file mode 100644 index 000000000000..629aa9b5ffbc --- /dev/null +++ b/include/dt-bindings/pinctrl/sppctl-sp7021.h @@ -0,0 +1,179 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Sunplus SP7021 dt-bindings Pinctrl header file + * Copyright (C) Sunplus Tech/Tibbo Tech. + * Author: Dvorkin Dmitry <dvorkin@tibbo.com> + */ + +#ifndef __DT_BINDINGS_PINCTRL_SPPCTL_SP7021_H__ +#define __DT_BINDINGS_PINCTRL_SPPCTL_SP7021_H__ + +#include <dt-bindings/pinctrl/sppctl.h> + +/* + * Please don't change the order of the following defines. + * They are based on order of 'hardware' control register + * defined in MOON2 ~ MOON3 registers. + */ +#define MUXF_GPIO 0 +#define MUXF_IOP 1 +#define MUXF_L2SW_CLK_OUT 2 +#define MUXF_L2SW_MAC_SMI_MDC 3 +#define MUXF_L2SW_LED_FLASH0 4 +#define MUXF_L2SW_LED_FLASH1 5 +#define MUXF_L2SW_LED_ON0 6 +#define MUXF_L2SW_LED_ON1 7 +#define MUXF_L2SW_MAC_SMI_MDIO 8 +#define MUXF_L2SW_P0_MAC_RMII_TXEN 9 +#define MUXF_L2SW_P0_MAC_RMII_TXD0 10 +#define MUXF_L2SW_P0_MAC_RMII_TXD1 11 +#define MUXF_L2SW_P0_MAC_RMII_CRSDV 12 +#define MUXF_L2SW_P0_MAC_RMII_RXD0 13 +#define MUXF_L2SW_P0_MAC_RMII_RXD1 14 +#define MUXF_L2SW_P0_MAC_RMII_RXER 15 +#define MUXF_L2SW_P1_MAC_RMII_TXEN 16 +#define MUXF_L2SW_P1_MAC_RMII_TXD0 17 +#define MUXF_L2SW_P1_MAC_RMII_TXD1 18 +#define MUXF_L2SW_P1_MAC_RMII_CRSDV 19 +#define MUXF_L2SW_P1_MAC_RMII_RXD0 20 +#define MUXF_L2SW_P1_MAC_RMII_RXD1 21 +#define MUXF_L2SW_P1_MAC_RMII_RXER 22 +#define MUXF_DAISY_MODE 23 +#define MUXF_SDIO_CLK 24 +#define MUXF_SDIO_CMD 25 +#define MUXF_SDIO_D0 26 +#define MUXF_SDIO_D1 27 +#define MUXF_SDIO_D2 28 +#define MUXF_SDIO_D3 29 +#define MUXF_PWM0 30 +#define MUXF_PWM1 31 +#define MUXF_PWM2 32 +#define MUXF_PWM3 33 +#define MUXF_PWM4 34 +#define MUXF_PWM5 35 +#define MUXF_PWM6 36 +#define MUXF_PWM7 37 +#define MUXF_ICM0_D 38 +#define MUXF_ICM1_D 39 +#define MUXF_ICM2_D 40 +#define MUXF_ICM3_D 41 +#define MUXF_ICM0_CLK 42 +#define MUXF_ICM1_CLK 43 +#define MUXF_ICM2_CLK 44 +#define MUXF_ICM3_CLK 45 +#define MUXF_SPIM0_INT 46 +#define MUXF_SPIM0_CLK 47 +#define MUXF_SPIM0_EN 48 +#define MUXF_SPIM0_DO 49 +#define MUXF_SPIM0_DI 50 +#define MUXF_SPIM1_INT 51 +#define MUXF_SPIM1_CLK 52 +#define MUXF_SPIM1_EN 53 +#define MUXF_SPIM1_DO 54 +#define MUXF_SPIM1_DI 55 +#define MUXF_SPIM2_INT 56 +#define MUXF_SPIM2_CLK 57 +#define MUXF_SPIM2_EN 58 +#define MUXF_SPIM2_DO 59 +#define MUXF_SPIM2_DI 60 +#define MUXF_SPIM3_INT 61 +#define MUXF_SPIM3_CLK 62 +#define MUXF_SPIM3_EN 63 +#define MUXF_SPIM3_DO 64 +#define MUXF_SPIM3_DI 65 +#define MUXF_SPI0S_INT 66 +#define MUXF_SPI0S_CLK 67 +#define MUXF_SPI0S_EN 68 +#define MUXF_SPI0S_DO 69 +#define MUXF_SPI0S_DI 70 +#define MUXF_SPI1S_INT 71 +#define MUXF_SPI1S_CLK 72 +#define MUXF_SPI1S_EN 73 +#define MUXF_SPI1S_DO 74 +#define MUXF_SPI1S_DI 75 +#define MUXF_SPI2S_INT 76 +#define MUXF_SPI2S_CLK 77 +#define MUXF_SPI2S_EN 78 +#define MUXF_SPI2S_DO 79 +#define MUXF_SPI2S_DI 80 +#define MUXF_SPI3S_INT 81 +#define MUXF_SPI3S_CLK 82 +#define MUXF_SPI3S_EN 83 +#define MUXF_SPI3S_DO 84 +#define MUXF_SPI3S_DI 85 +#define MUXF_I2CM0_CLK 86 +#define MUXF_I2CM0_DAT 87 +#define MUXF_I2CM1_CLK 88 +#define MUXF_I2CM1_DAT 89 +#define MUXF_I2CM2_CLK 90 +#define MUXF_I2CM2_DAT 91 +#define MUXF_I2CM3_CLK 92 +#define MUXF_I2CM3_DAT 93 +#define MUXF_UA1_TX 94 +#define MUXF_UA1_RX 95 +#define MUXF_UA1_CTS 96 +#define MUXF_UA1_RTS 97 +#define MUXF_UA2_TX 98 +#define MUXF_UA2_RX 99 +#define MUXF_UA2_CTS 100 +#define MUXF_UA2_RTS 101 +#define MUXF_UA3_TX 102 +#define MUXF_UA3_RX 103 +#define MUXF_UA3_CTS 104 +#define MUXF_UA3_RTS 105 +#define MUXF_UA4_TX 106 +#define MUXF_UA4_RX 107 +#define MUXF_UA4_CTS 108 +#define MUXF_UA4_RTS 109 +#define MUXF_TIMER0_INT 110 +#define MUXF_TIMER1_INT 111 +#define MUXF_TIMER2_INT 112 +#define MUXF_TIMER3_INT 113 +#define MUXF_GPIO_INT0 114 +#define MUXF_GPIO_INT1 115 +#define MUXF_GPIO_INT2 116 +#define MUXF_GPIO_INT3 117 +#define MUXF_GPIO_INT4 118 +#define MUXF_GPIO_INT5 119 +#define MUXF_GPIO_INT6 120 +#define MUXF_GPIO_INT7 121 + +/* + * Please don't change the order of the following defines. + * They are based on order of items in array 'sppctl_list_funcs' + * in Sunplus pinctrl driver. + */ +#define GROP_SPI_FLASH 122 +#define GROP_SPI_FLASH_4BIT 123 +#define GROP_SPI_NAND 124 +#define GROP_CARD0_EMMC 125 +#define GROP_SD_CARD 126 +#define GROP_UA0 127 +#define GROP_ACHIP_DEBUG 128 +#define GROP_ACHIP_UA2AXI 129 +#define GROP_FPGA_IFX 130 +#define GROP_HDMI_TX 131 +#define GROP_AUD_EXT_ADC_IFX0 132 +#define GROP_AUD_EXT_DAC_IFX0 133 +#define GROP_SPDIF_RX 134 +#define GROP_SPDIF_TX 135 +#define GROP_TDMTX_IFX0 136 +#define GROP_TDMRX_IFX0 137 +#define GROP_PDMRX_IFX0 138 +#define GROP_PCM_IEC_TX 139 +#define GROP_LCDIF 140 +#define GROP_DVD_DSP_DEBUG 141 +#define GROP_I2C_DEBUG 142 +#define GROP_I2C_SLAVE 143 +#define GROP_WAKEUP 144 +#define GROP_UART2AXI 145 +#define GROP_USB0_I2C 146 +#define GROP_USB1_I2C 147 +#define GROP_USB0_OTG 148 +#define GROP_USB1_OTG 149 +#define GROP_UPHY0_DEBUG 150 +#define GROP_UPHY1_DEBUG 151 +#define GROP_UPHY0_EXT 152 +#define GROP_PROBE_PORT 153 + +#endif diff --git a/include/dt-bindings/pinctrl/sppctl.h b/include/dt-bindings/pinctrl/sppctl.h new file mode 100644 index 000000000000..50557265dbfc --- /dev/null +++ b/include/dt-bindings/pinctrl/sppctl.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Sunplus dt-bindings Pinctrl header file + * Copyright (C) Sunplus Tech / Tibbo Tech. + * Author: Dvorkin Dmitry <dvorkin@tibbo.com> + */ + +#ifndef __DT_BINDINGS_PINCTRL_SPPCTL_H__ +#define __DT_BINDINGS_PINCTRL_SPPCTL_H__ + +#define IOP_G_MASTE (0x01 << 0) +#define IOP_G_FIRST (0x01 << 1) + +#define SPPCTL_PCTL_G_PMUX (0x00 | IOP_G_MASTE) +#define SPPCTL_PCTL_G_GPIO (IOP_G_FIRST | IOP_G_MASTE) +#define SPPCTL_PCTL_G_IOPP (IOP_G_FIRST | 0x00) + +#define SPPCTL_PCTL_L_OUT (0x01 << 0) /* Output LOW */ +#define SPPCTL_PCTL_L_OU1 (0x01 << 1) /* Output HIGH */ +#define SPPCTL_PCTL_L_INV (0x01 << 2) /* Input Invert */ +#define SPPCTL_PCTL_L_ONV (0x01 << 3) /* Output Invert */ +#define SPPCTL_PCTL_L_ODR (0x01 << 4) /* Output Open Drain */ + +/* + * pack into 32-bit value: + * pin# (8bit), typ (8bit), function (8bit), flag (8bit) + */ +#define SPPCTL_IOPAD(pin, typ, fun, flg) (((pin) << 24) | ((typ) << 16) | \ + ((fun) << 8) | (flg)) + +#endif diff --git a/include/dt-bindings/power/fsl,imx93-power.h b/include/dt-bindings/power/fsl,imx93-power.h new file mode 100644 index 000000000000..17f9f015bf7d --- /dev/null +++ b/include/dt-bindings/power/fsl,imx93-power.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright 2022 NXP + */ + +#ifndef __DT_BINDINGS_IMX93_POWER_H__ +#define __DT_BINDINGS_IMX93_POWER_H__ + +#define IMX93_MEDIABLK_PD_MIPI_DSI 0 +#define IMX93_MEDIABLK_PD_MIPI_CSI 1 +#define IMX93_MEDIABLK_PD_PXP 2 +#define IMX93_MEDIABLK_PD_LCDIF 3 +#define IMX93_MEDIABLK_PD_ISI 4 + +#endif diff --git a/include/dt-bindings/power/imx8mm-power.h b/include/dt-bindings/power/imx8mm-power.h new file mode 100644 index 000000000000..648938f24c8e --- /dev/null +++ b/include/dt-bindings/power/imx8mm-power.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (C) 2020 Pengutronix, Lucas Stach <kernel@pengutronix.de> + */ + +#ifndef __DT_BINDINGS_IMX8MM_POWER_H__ +#define __DT_BINDINGS_IMX8MM_POWER_H__ + +#define IMX8MM_POWER_DOMAIN_HSIOMIX 0 +#define IMX8MM_POWER_DOMAIN_PCIE 1 +#define IMX8MM_POWER_DOMAIN_OTG1 2 +#define IMX8MM_POWER_DOMAIN_OTG2 3 +#define IMX8MM_POWER_DOMAIN_GPUMIX 4 +#define IMX8MM_POWER_DOMAIN_GPU 5 +#define IMX8MM_POWER_DOMAIN_VPUMIX 6 +#define IMX8MM_POWER_DOMAIN_VPUG1 7 +#define IMX8MM_POWER_DOMAIN_VPUG2 8 +#define IMX8MM_POWER_DOMAIN_VPUH1 9 +#define IMX8MM_POWER_DOMAIN_DISPMIX 10 +#define IMX8MM_POWER_DOMAIN_MIPI 11 + +#define IMX8MM_VPUBLK_PD_G1 0 +#define IMX8MM_VPUBLK_PD_G2 1 +#define IMX8MM_VPUBLK_PD_H1 2 + +#define IMX8MM_DISPBLK_PD_CSI_BRIDGE 0 +#define IMX8MM_DISPBLK_PD_LCDIF 1 +#define IMX8MM_DISPBLK_PD_MIPI_DSI 2 +#define IMX8MM_DISPBLK_PD_MIPI_CSI 3 + +#endif diff --git a/include/dt-bindings/power/imx8mn-power.h b/include/dt-bindings/power/imx8mn-power.h new file mode 100644 index 000000000000..eedd0e581939 --- /dev/null +++ b/include/dt-bindings/power/imx8mn-power.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (C) 2020 Compass Electronics Group, LLC + */ + +#ifndef __DT_BINDINGS_IMX8MN_POWER_H__ +#define __DT_BINDINGS_IMX8MN_POWER_H__ + +#define IMX8MN_POWER_DOMAIN_HSIOMIX 0 +#define IMX8MN_POWER_DOMAIN_OTG1 1 +#define IMX8MN_POWER_DOMAIN_GPUMIX 2 +#define IMX8MN_POWER_DOMAIN_DISPMIX 3 +#define IMX8MN_POWER_DOMAIN_MIPI 4 + +#define IMX8MN_DISPBLK_PD_MIPI_DSI 0 +#define IMX8MN_DISPBLK_PD_MIPI_CSI 1 +#define IMX8MN_DISPBLK_PD_LCDIF 2 +#define IMX8MN_DISPBLK_PD_ISI 3 + +#endif diff --git a/include/dt-bindings/power/imx8mp-power.h b/include/dt-bindings/power/imx8mp-power.h new file mode 100644 index 000000000000..2fe3c2abad13 --- /dev/null +++ b/include/dt-bindings/power/imx8mp-power.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (C) 2020 Pengutronix, Sascha Hauer <kernel@pengutronix.de> + */ + +#ifndef __DT_BINDINGS_IMX8MP_POWER_DOMAIN_POWER_H__ +#define __DT_BINDINGS_IMX8MP_POWER_DOMAIN_POWER_H__ + +#define IMX8MP_POWER_DOMAIN_MIPI_PHY1 0 +#define IMX8MP_POWER_DOMAIN_PCIE_PHY 1 +#define IMX8MP_POWER_DOMAIN_USB1_PHY 2 +#define IMX8MP_POWER_DOMAIN_USB2_PHY 3 +#define IMX8MP_POWER_DOMAIN_MLMIX 4 +#define IMX8MP_POWER_DOMAIN_AUDIOMIX 5 +#define IMX8MP_POWER_DOMAIN_GPU2D 6 +#define IMX8MP_POWER_DOMAIN_GPUMIX 7 +#define IMX8MP_POWER_DOMAIN_VPUMIX 8 +#define IMX8MP_POWER_DOMAIN_GPU3D 9 +#define IMX8MP_POWER_DOMAIN_MEDIAMIX 10 +#define IMX8MP_POWER_DOMAIN_VPU_G1 11 +#define IMX8MP_POWER_DOMAIN_VPU_G2 12 +#define IMX8MP_POWER_DOMAIN_VPU_VC8000E 13 +#define IMX8MP_POWER_DOMAIN_HDMIMIX 14 +#define IMX8MP_POWER_DOMAIN_HDMI_PHY 15 +#define IMX8MP_POWER_DOMAIN_MIPI_PHY2 16 +#define IMX8MP_POWER_DOMAIN_HSIOMIX 17 +#define IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP 18 + +#define IMX8MP_HSIOBLK_PD_USB 0 +#define IMX8MP_HSIOBLK_PD_USB_PHY1 1 +#define IMX8MP_HSIOBLK_PD_USB_PHY2 2 +#define IMX8MP_HSIOBLK_PD_PCIE 3 +#define IMX8MP_HSIOBLK_PD_PCIE_PHY 4 + +#define IMX8MP_MEDIABLK_PD_MIPI_DSI_1 0 +#define IMX8MP_MEDIABLK_PD_MIPI_CSI2_1 1 +#define IMX8MP_MEDIABLK_PD_LCDIF_1 2 +#define IMX8MP_MEDIABLK_PD_ISI 3 +#define IMX8MP_MEDIABLK_PD_MIPI_CSI2_2 4 +#define IMX8MP_MEDIABLK_PD_LCDIF_2 5 +#define IMX8MP_MEDIABLK_PD_ISP 6 +#define IMX8MP_MEDIABLK_PD_DWE 7 +#define IMX8MP_MEDIABLK_PD_MIPI_DSI_2 8 + +#define IMX8MP_HDMIBLK_PD_IRQSTEER 0 +#define IMX8MP_HDMIBLK_PD_LCDIF 1 +#define IMX8MP_HDMIBLK_PD_PAI 2 +#define IMX8MP_HDMIBLK_PD_PVI 3 +#define IMX8MP_HDMIBLK_PD_TRNG 4 +#define IMX8MP_HDMIBLK_PD_HDMI_TX 5 +#define IMX8MP_HDMIBLK_PD_HDMI_TX_PHY 6 +#define IMX8MP_HDMIBLK_PD_HDCP 7 +#define IMX8MP_HDMIBLK_PD_HRV 8 + +#define IMX8MP_VPUBLK_PD_G1 0 +#define IMX8MP_VPUBLK_PD_G2 1 +#define IMX8MP_VPUBLK_PD_VC8000E 2 + +#endif diff --git a/include/dt-bindings/power/imx8mq-power.h b/include/dt-bindings/power/imx8mq-power.h index 8a513bd9166e..9f7d0f1e7c32 100644 --- a/include/dt-bindings/power/imx8mq-power.h +++ b/include/dt-bindings/power/imx8mq-power.h @@ -18,4 +18,7 @@ #define IMX8M_POWER_DOMAIN_MIPI_CSI2 9 #define IMX8M_POWER_DOMAIN_PCIE2 10 +#define IMX8MQ_VPUBLK_PD_G1 0 +#define IMX8MQ_VPUBLK_PD_G2 1 + #endif diff --git a/include/dt-bindings/power/imx8ulp-power.h b/include/dt-bindings/power/imx8ulp-power.h new file mode 100644 index 000000000000..a556b2e96df1 --- /dev/null +++ b/include/dt-bindings/power/imx8ulp-power.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright 2021 NXP + */ + +#ifndef __DT_BINDINGS_IMX8ULP_POWER_H__ +#define __DT_BINDINGS_IMX8ULP_POWER_H__ + +#define IMX8ULP_PD_DMA1 0 +#define IMX8ULP_PD_FLEXSPI2 1 +#define IMX8ULP_PD_USB0 2 +#define IMX8ULP_PD_USDHC0 3 +#define IMX8ULP_PD_USDHC1 4 +#define IMX8ULP_PD_USDHC2_USB1 5 +#define IMX8ULP_PD_DCNANO 6 +#define IMX8ULP_PD_EPDC 7 +#define IMX8ULP_PD_DMA2 8 +#define IMX8ULP_PD_GPU2D 9 +#define IMX8ULP_PD_GPU3D 10 +#define IMX8ULP_PD_HIFI4 11 +#define IMX8ULP_PD_ISI 12 +#define IMX8ULP_PD_MIPI_CSI 13 +#define IMX8ULP_PD_MIPI_DSI 14 +#define IMX8ULP_PD_PXP 15 + +#endif diff --git a/include/dt-bindings/power/marvell,mmp2.h b/include/dt-bindings/power/marvell,mmp2.h new file mode 100644 index 000000000000..c53d2b3e1057 --- /dev/null +++ b/include/dt-bindings/power/marvell,mmp2.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DTS_MARVELL_MMP2_POWER_H +#define __DTS_MARVELL_MMP2_POWER_H + +#define MMP2_POWER_DOMAIN_GPU 0 +#define MMP2_POWER_DOMAIN_AUDIO 1 +#define MMP3_POWER_DOMAIN_CAMERA 2 + +#define MMP2_NR_POWER_DOMAINS 3 + +#endif diff --git a/include/dt-bindings/power/meson-a1-power.h b/include/dt-bindings/power/meson-a1-power.h new file mode 100644 index 000000000000..6cf50bfb8ccf --- /dev/null +++ b/include/dt-bindings/power/meson-a1-power.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. + * Author: Jianxin Pan <jianxin.pan@amlogic.com> + */ + +#ifndef _DT_BINDINGS_MESON_A1_POWER_H +#define _DT_BINDINGS_MESON_A1_POWER_H + +#define PWRC_DSPA_ID 8 +#define PWRC_DSPB_ID 9 +#define PWRC_UART_ID 10 +#define PWRC_DMC_ID 11 +#define PWRC_I2C_ID 12 +#define PWRC_PSRAM_ID 13 +#define PWRC_ACODEC_ID 14 +#define PWRC_AUDIO_ID 15 +#define PWRC_OTP_ID 16 +#define PWRC_DMA_ID 17 +#define PWRC_SD_EMMC_ID 18 +#define PWRC_RAMA_ID 19 +#define PWRC_RAMB_ID 20 +#define PWRC_IR_ID 21 +#define PWRC_SPICC_ID 22 +#define PWRC_SPIFC_ID 23 +#define PWRC_USB_ID 24 +#define PWRC_NIC_ID 25 +#define PWRC_PDMIN_ID 26 +#define PWRC_RSA_ID 27 +#define PWRC_MAX_ID 28 + +#endif diff --git a/include/dt-bindings/power/meson-axg-power.h b/include/dt-bindings/power/meson-axg-power.h new file mode 100644 index 000000000000..e5243884b249 --- /dev/null +++ b/include/dt-bindings/power/meson-axg-power.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* + * Copyright (c) 2020 BayLibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +#ifndef _DT_BINDINGS_MESON_AXG_POWER_H +#define _DT_BINDINGS_MESON_AXG_POWER_H + +#define PWRC_AXG_VPU_ID 0 +#define PWRC_AXG_ETHERNET_MEM_ID 1 +#define PWRC_AXG_AUDIO_ID 2 + +#endif diff --git a/include/dt-bindings/power/meson-gxbb-power.h b/include/dt-bindings/power/meson-gxbb-power.h new file mode 100644 index 000000000000..1262dac696c0 --- /dev/null +++ b/include/dt-bindings/power/meson-gxbb-power.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* + * Copyright (c) 2019 BayLibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +#ifndef _DT_BINDINGS_MESON_GXBB_POWER_H +#define _DT_BINDINGS_MESON_GXBB_POWER_H + +#define PWRC_GXBB_VPU_ID 0 +#define PWRC_GXBB_ETHERNET_MEM_ID 1 + +#endif diff --git a/include/dt-bindings/power/meson-s4-power.h b/include/dt-bindings/power/meson-s4-power.h new file mode 100644 index 000000000000..462dd2cb938b --- /dev/null +++ b/include/dt-bindings/power/meson-s4-power.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* + * Copyright (c) 2021 Amlogic, Inc. + * Author: Shunzhou Jiang <shunzhou.jiang@amlogic.com> + */ + +#ifndef _DT_BINDINGS_MESON_S4_POWER_H +#define _DT_BINDINGS_MESON_S4_POWER_H + +#define PWRC_S4_DOS_HEVC_ID 0 +#define PWRC_S4_DOS_VDEC_ID 1 +#define PWRC_S4_VPU_HDMI_ID 2 +#define PWRC_S4_USB_COMB_ID 3 +#define PWRC_S4_GE2D_ID 4 +#define PWRC_S4_ETH_ID 5 +#define PWRC_S4_DEMOD_ID 6 +#define PWRC_S4_AUDIO_ID 7 + +#endif diff --git a/include/dt-bindings/power/meson8-power.h b/include/dt-bindings/power/meson8-power.h new file mode 100644 index 000000000000..dd8b2ddb82a7 --- /dev/null +++ b/include/dt-bindings/power/meson8-power.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* + * Copyright (c) 2019 Martin Blumenstingl <martin.blumenstingl@googlemail.com> + */ + +#ifndef _DT_BINDINGS_MESON8_POWER_H +#define _DT_BINDINGS_MESON8_POWER_H + +#define PWRC_MESON8_VPU_ID 0 +#define PWRC_MESON8_ETHERNET_MEM_ID 1 +#define PWRC_MESON8_AUDIO_DSP_MEM_ID 2 + +#endif /* _DT_BINDINGS_MESON8_POWER_H */ diff --git a/include/dt-bindings/power/mt6795-power.h b/include/dt-bindings/power/mt6795-power.h new file mode 100644 index 000000000000..b0fc26cb1da4 --- /dev/null +++ b/include/dt-bindings/power/mt6795-power.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +#ifndef _DT_BINDINGS_POWER_MT6795_POWER_H +#define _DT_BINDINGS_POWER_MT6795_POWER_H + +#define MT6795_POWER_DOMAIN_MM 0 +#define MT6795_POWER_DOMAIN_VDEC 1 +#define MT6795_POWER_DOMAIN_VENC 2 +#define MT6795_POWER_DOMAIN_ISP 3 +#define MT6795_POWER_DOMAIN_MJC 4 +#define MT6795_POWER_DOMAIN_AUDIO 5 +#define MT6795_POWER_DOMAIN_MFG_ASYNC 6 +#define MT6795_POWER_DOMAIN_MFG_2D 7 +#define MT6795_POWER_DOMAIN_MFG 8 +#define MT6795_POWER_DOMAIN_MODEM 9 + +#endif /* _DT_BINDINGS_POWER_MT6795_POWER_H */ diff --git a/include/dt-bindings/power/mt6797-power.h b/include/dt-bindings/power/mt6797-power.h index a60c1d81cf75..bd451d860e6a 100644 --- a/include/dt-bindings/power/mt6797-power.h +++ b/include/dt-bindings/power/mt6797-power.h @@ -1,14 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2017 MediaTek Inc. * Author: Mars.C <mars.cheng@mediatek.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #ifndef _DT_BINDINGS_POWER_MT6797_POWER_H diff --git a/include/dt-bindings/power/mt8167-power.h b/include/dt-bindings/power/mt8167-power.h new file mode 100644 index 000000000000..c8ec9983a4bc --- /dev/null +++ b/include/dt-bindings/power/mt8167-power.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (c) 2020 MediaTek Inc. + */ + +#ifndef _DT_BINDINGS_POWER_MT8167_POWER_H +#define _DT_BINDINGS_POWER_MT8167_POWER_H + +#define MT8167_POWER_DOMAIN_MM 0 +#define MT8167_POWER_DOMAIN_VDEC 1 +#define MT8167_POWER_DOMAIN_ISP 2 +#define MT8167_POWER_DOMAIN_CONN 3 +#define MT8167_POWER_DOMAIN_MFG_ASYNC 4 +#define MT8167_POWER_DOMAIN_MFG_2D 5 +#define MT8167_POWER_DOMAIN_MFG 6 + +#endif /* _DT_BINDINGS_POWER_MT8167_POWER_H */ diff --git a/include/dt-bindings/power/mt8183-power.h b/include/dt-bindings/power/mt8183-power.h new file mode 100644 index 000000000000..d1ab387ba8c7 --- /dev/null +++ b/include/dt-bindings/power/mt8183-power.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 MediaTek Inc. + * Author: Weiyi Lu <weiyi.lu@mediatek.com> + */ + +#ifndef _DT_BINDINGS_POWER_MT8183_POWER_H +#define _DT_BINDINGS_POWER_MT8183_POWER_H + +#define MT8183_POWER_DOMAIN_AUDIO 0 +#define MT8183_POWER_DOMAIN_CONN 1 +#define MT8183_POWER_DOMAIN_MFG_ASYNC 2 +#define MT8183_POWER_DOMAIN_MFG 3 +#define MT8183_POWER_DOMAIN_MFG_CORE0 4 +#define MT8183_POWER_DOMAIN_MFG_CORE1 5 +#define MT8183_POWER_DOMAIN_MFG_2D 6 +#define MT8183_POWER_DOMAIN_DISP 7 +#define MT8183_POWER_DOMAIN_CAM 8 +#define MT8183_POWER_DOMAIN_ISP 9 +#define MT8183_POWER_DOMAIN_VDEC 10 +#define MT8183_POWER_DOMAIN_VENC 11 +#define MT8183_POWER_DOMAIN_VPU_TOP 12 +#define MT8183_POWER_DOMAIN_VPU_CORE0 13 +#define MT8183_POWER_DOMAIN_VPU_CORE1 14 + +#endif /* _DT_BINDINGS_POWER_MT8183_POWER_H */ diff --git a/include/dt-bindings/power/mt8186-power.h b/include/dt-bindings/power/mt8186-power.h new file mode 100644 index 000000000000..429f7197f6b6 --- /dev/null +++ b/include/dt-bindings/power/mt8186-power.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> + */ + +#ifndef _DT_BINDINGS_POWER_MT8186_POWER_H +#define _DT_BINDINGS_POWER_MT8186_POWER_H + +#define MT8186_POWER_DOMAIN_MFG0 0 +#define MT8186_POWER_DOMAIN_MFG1 1 +#define MT8186_POWER_DOMAIN_MFG2 2 +#define MT8186_POWER_DOMAIN_MFG3 3 +#define MT8186_POWER_DOMAIN_SSUSB 4 +#define MT8186_POWER_DOMAIN_SSUSB_P1 5 +#define MT8186_POWER_DOMAIN_DIS 6 +#define MT8186_POWER_DOMAIN_IMG 7 +#define MT8186_POWER_DOMAIN_IMG2 8 +#define MT8186_POWER_DOMAIN_IPE 9 +#define MT8186_POWER_DOMAIN_CAM 10 +#define MT8186_POWER_DOMAIN_CAM_RAWA 11 +#define MT8186_POWER_DOMAIN_CAM_RAWB 12 +#define MT8186_POWER_DOMAIN_VENC 13 +#define MT8186_POWER_DOMAIN_VDEC 14 +#define MT8186_POWER_DOMAIN_WPE 15 +#define MT8186_POWER_DOMAIN_CONN_ON 16 +#define MT8186_POWER_DOMAIN_CSIRX_TOP 17 +#define MT8186_POWER_DOMAIN_ADSP_AO 18 +#define MT8186_POWER_DOMAIN_ADSP_INFRA 19 +#define MT8186_POWER_DOMAIN_ADSP_TOP 20 + +#endif /* _DT_BINDINGS_POWER_MT8186_POWER_H */ diff --git a/include/dt-bindings/power/mt8192-power.h b/include/dt-bindings/power/mt8192-power.h new file mode 100644 index 000000000000..4eaa53d7270a --- /dev/null +++ b/include/dt-bindings/power/mt8192-power.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (c) 2020 MediaTek Inc. + * Author: Weiyi Lu <weiyi.lu@mediatek.com> + */ + +#ifndef _DT_BINDINGS_POWER_MT8192_POWER_H +#define _DT_BINDINGS_POWER_MT8192_POWER_H + +#define MT8192_POWER_DOMAIN_AUDIO 0 +#define MT8192_POWER_DOMAIN_CONN 1 +#define MT8192_POWER_DOMAIN_MFG0 2 +#define MT8192_POWER_DOMAIN_MFG1 3 +#define MT8192_POWER_DOMAIN_MFG2 4 +#define MT8192_POWER_DOMAIN_MFG3 5 +#define MT8192_POWER_DOMAIN_MFG4 6 +#define MT8192_POWER_DOMAIN_MFG5 7 +#define MT8192_POWER_DOMAIN_MFG6 8 +#define MT8192_POWER_DOMAIN_DISP 9 +#define MT8192_POWER_DOMAIN_IPE 10 +#define MT8192_POWER_DOMAIN_ISP 11 +#define MT8192_POWER_DOMAIN_ISP2 12 +#define MT8192_POWER_DOMAIN_MDP 13 +#define MT8192_POWER_DOMAIN_VENC 14 +#define MT8192_POWER_DOMAIN_VDEC 15 +#define MT8192_POWER_DOMAIN_VDEC2 16 +#define MT8192_POWER_DOMAIN_CAM 17 +#define MT8192_POWER_DOMAIN_CAM_RAWA 18 +#define MT8192_POWER_DOMAIN_CAM_RAWB 19 +#define MT8192_POWER_DOMAIN_CAM_RAWC 20 + +#endif /* _DT_BINDINGS_POWER_MT8192_POWER_H */ diff --git a/include/dt-bindings/power/mt8195-power.h b/include/dt-bindings/power/mt8195-power.h new file mode 100644 index 000000000000..b20ca4b3e3a8 --- /dev/null +++ b/include/dt-bindings/power/mt8195-power.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (c) 2021 MediaTek Inc. + * Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> + */ + +#ifndef _DT_BINDINGS_POWER_MT8195_POWER_H +#define _DT_BINDINGS_POWER_MT8195_POWER_H + +#define MT8195_POWER_DOMAIN_PCIE_MAC_P0 0 +#define MT8195_POWER_DOMAIN_PCIE_MAC_P1 1 +#define MT8195_POWER_DOMAIN_PCIE_PHY 2 +#define MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY 3 +#define MT8195_POWER_DOMAIN_CSI_RX_TOP 4 +#define MT8195_POWER_DOMAIN_ETHER 5 +#define MT8195_POWER_DOMAIN_ADSP 6 +#define MT8195_POWER_DOMAIN_AUDIO 7 +#define MT8195_POWER_DOMAIN_MFG0 8 +#define MT8195_POWER_DOMAIN_MFG1 9 +#define MT8195_POWER_DOMAIN_MFG2 10 +#define MT8195_POWER_DOMAIN_MFG3 11 +#define MT8195_POWER_DOMAIN_MFG4 12 +#define MT8195_POWER_DOMAIN_MFG5 13 +#define MT8195_POWER_DOMAIN_MFG6 14 +#define MT8195_POWER_DOMAIN_VPPSYS0 15 +#define MT8195_POWER_DOMAIN_VDOSYS0 16 +#define MT8195_POWER_DOMAIN_VPPSYS1 17 +#define MT8195_POWER_DOMAIN_VDOSYS1 18 +#define MT8195_POWER_DOMAIN_DP_TX 19 +#define MT8195_POWER_DOMAIN_EPD_TX 20 +#define MT8195_POWER_DOMAIN_HDMI_TX 21 +#define MT8195_POWER_DOMAIN_WPESYS 22 +#define MT8195_POWER_DOMAIN_VDEC0 23 +#define MT8195_POWER_DOMAIN_VDEC1 24 +#define MT8195_POWER_DOMAIN_VDEC2 25 +#define MT8195_POWER_DOMAIN_VENC 26 +#define MT8195_POWER_DOMAIN_VENC_CORE1 27 +#define MT8195_POWER_DOMAIN_IMG 28 +#define MT8195_POWER_DOMAIN_DIP 29 +#define MT8195_POWER_DOMAIN_IPE 30 +#define MT8195_POWER_DOMAIN_CAM 31 +#define MT8195_POWER_DOMAIN_CAM_RAWA 32 +#define MT8195_POWER_DOMAIN_CAM_RAWB 33 +#define MT8195_POWER_DOMAIN_CAM_MRAW 34 + +#endif /* _DT_BINDINGS_POWER_MT8195_POWER_H */ diff --git a/include/dt-bindings/power/qcom-aoss-qmp.h b/include/dt-bindings/power/qcom-aoss-qmp.h deleted file mode 100644 index ec336d31dee4..000000000000 --- a/include/dt-bindings/power/qcom-aoss-qmp.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Copyright (c) 2018, Linaro Ltd. */ - -#ifndef __DT_BINDINGS_POWER_QCOM_AOSS_QMP_H -#define __DT_BINDINGS_POWER_QCOM_AOSS_QMP_H - -#define AOSS_QMP_LS_CDSP 0 -#define AOSS_QMP_LS_LPASS 1 -#define AOSS_QMP_LS_MODEM 2 -#define AOSS_QMP_LS_SLPI 3 -#define AOSS_QMP_LS_SPSS 4 -#define AOSS_QMP_LS_VENUS 5 - -#endif diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h index 3f74096d5a7c..f5f82dde7399 100644 --- a/include/dt-bindings/power/qcom-rpmpd.h +++ b/include/dt-bindings/power/qcom-rpmpd.h @@ -15,6 +15,39 @@ #define SDM845_GFX 7 #define SDM845_MSS 8 +/* SDX55 Power Domain Indexes */ +#define SDX55_MSS 0 +#define SDX55_MX 1 +#define SDX55_CX 2 + +/* SDX65 Power Domain Indexes */ +#define SDX65_MSS 0 +#define SDX65_MX 1 +#define SDX65_MX_AO 2 +#define SDX65_CX 3 +#define SDX65_CX_AO 4 +#define SDX65_MXC 5 + +/* SM6350 Power Domain Indexes */ +#define SM6350_CX 0 +#define SM6350_GFX 1 +#define SM6350_LCX 2 +#define SM6350_LMX 3 +#define SM6350_MSS 4 +#define SM6350_MX 5 + +/* SM6350 Power Domain Indexes */ +#define SM6375_VDDCX 0 +#define SM6375_VDDCX_AO 1 +#define SM6375_VDDCX_VFL 2 +#define SM6375_VDDMX 3 +#define SM6375_VDDMX_AO 4 +#define SM6375_VDDMX_VFL 5 +#define SM6375_VDDGX 6 +#define SM6375_VDDGX_AO 7 +#define SM6375_VDD_LPI_CX 8 +#define SM6375_VDD_LPI_MX 9 + /* SM8150 Power Domain Indexes */ #define SM8150_MSS 0 #define SM8150_EBI 1 @@ -28,6 +61,48 @@ #define SM8150_MMCX 9 #define SM8150_MMCX_AO 10 +/* SM8250 Power Domain Indexes */ +#define SM8250_CX 0 +#define SM8250_CX_AO 1 +#define SM8250_EBI 2 +#define SM8250_GFX 3 +#define SM8250_LCX 4 +#define SM8250_LMX 5 +#define SM8250_MMCX 6 +#define SM8250_MMCX_AO 7 +#define SM8250_MX 8 +#define SM8250_MX_AO 9 + +/* SM8350 Power Domain Indexes */ +#define SM8350_CX 0 +#define SM8350_CX_AO 1 +#define SM8350_EBI 2 +#define SM8350_GFX 3 +#define SM8350_LCX 4 +#define SM8350_LMX 5 +#define SM8350_MMCX 6 +#define SM8350_MMCX_AO 7 +#define SM8350_MX 8 +#define SM8350_MX_AO 9 +#define SM8350_MXC 10 +#define SM8350_MXC_AO 11 +#define SM8350_MSS 12 + +/* SM8450 Power Domain Indexes */ +#define SM8450_CX 0 +#define SM8450_CX_AO 1 +#define SM8450_EBI 2 +#define SM8450_GFX 3 +#define SM8450_LCX 4 +#define SM8450_LMX 5 +#define SM8450_MMCX 6 +#define SM8450_MMCX_AO 7 +#define SM8450_MX 8 +#define SM8450_MX_AO 9 +#define SM8450_MXC 10 +#define SM8450_MXC_AO 11 +#define SM8450_MSS 12 + /* SC7180 Power Domain Indexes */ #define SC7180_CX 0 #define SC7180_CX_AO 1 @@ -38,11 +113,54 @@ #define SC7180_LCX 6 #define SC7180_MSS 7 +/* SC7280 Power Domain Indexes */ +#define SC7280_CX 0 +#define SC7280_CX_AO 1 +#define SC7280_EBI 2 +#define SC7280_GFX 3 +#define SC7280_MX 4 +#define SC7280_MX_AO 5 +#define SC7280_LMX 6 +#define SC7280_LCX 7 +#define SC7280_MSS 8 + +/* SC8180X Power Domain Indexes */ +#define SC8180X_CX 0 +#define SC8180X_CX_AO 1 +#define SC8180X_EBI 2 +#define SC8180X_GFX 3 +#define SC8180X_LCX 4 +#define SC8180X_LMX 5 +#define SC8180X_MMCX 6 +#define SC8180X_MMCX_AO 7 +#define SC8180X_MSS 8 +#define SC8180X_MX 9 +#define SC8180X_MX_AO 10 + +/* SC8280XP Power Domain Indexes */ +#define SC8280XP_CX 0 +#define SC8280XP_CX_AO 1 +#define SC8280XP_DDR 2 +#define SC8280XP_EBI 3 +#define SC8280XP_GFX 4 +#define SC8280XP_LCX 5 +#define SC8280XP_LMX 6 +#define SC8280XP_MMCX 7 +#define SC8280XP_MMCX_AO 8 +#define SC8280XP_MSS 9 +#define SC8280XP_MX 10 +#define SC8280XP_MXC 12 +#define SC8280XP_MX_AO 11 +#define SC8280XP_NSP 13 +#define SC8280XP_QPHY 14 +#define SC8280XP_XO 15 + /* SDM845 Power Domain performance levels */ #define RPMH_REGULATOR_LEVEL_RETENTION 16 #define RPMH_REGULATOR_LEVEL_MIN_SVS 48 #define RPMH_REGULATOR_LEVEL_LOW_SVS 64 #define RPMH_REGULATOR_LEVEL_SVS 128 +#define RPMH_REGULATOR_LEVEL_SVS_L0 144 #define RPMH_REGULATOR_LEVEL_SVS_L1 192 #define RPMH_REGULATOR_LEVEL_SVS_L2 224 #define RPMH_REGULATOR_LEVEL_NOM 256 @@ -51,6 +169,52 @@ #define RPMH_REGULATOR_LEVEL_TURBO 384 #define RPMH_REGULATOR_LEVEL_TURBO_L1 416 +/* MDM9607 Power Domains */ +#define MDM9607_VDDCX 0 +#define MDM9607_VDDCX_AO 1 +#define MDM9607_VDDCX_VFL 2 +#define MDM9607_VDDMX 3 +#define MDM9607_VDDMX_AO 4 +#define MDM9607_VDDMX_VFL 5 + +/* MSM8226 Power Domain Indexes */ +#define MSM8226_VDDCX 0 +#define MSM8226_VDDCX_AO 1 +#define MSM8226_VDDCX_VFC 2 + +/* MSM8939 Power Domains */ +#define MSM8939_VDDMDCX 0 +#define MSM8939_VDDMDCX_AO 1 +#define MSM8939_VDDMDCX_VFC 2 +#define MSM8939_VDDCX 3 +#define MSM8939_VDDCX_AO 4 +#define MSM8939_VDDCX_VFC 5 +#define MSM8939_VDDMX 6 +#define MSM8939_VDDMX_AO 7 + +/* MSM8916 Power Domain Indexes */ +#define MSM8916_VDDCX 0 +#define MSM8916_VDDCX_AO 1 +#define MSM8916_VDDCX_VFC 2 +#define MSM8916_VDDMX 3 +#define MSM8916_VDDMX_AO 4 + +/* MSM8909 Power Domain Indexes */ +#define MSM8909_VDDCX MSM8916_VDDCX +#define MSM8909_VDDCX_AO MSM8916_VDDCX_AO +#define MSM8909_VDDCX_VFC MSM8916_VDDCX_VFC +#define MSM8909_VDDMX MSM8916_VDDMX +#define MSM8909_VDDMX_AO MSM8916_VDDMX_AO + +/* MSM8953 Power Domain Indexes */ +#define MSM8953_VDDMD 0 +#define MSM8953_VDDMD_AO 1 +#define MSM8953_VDDCX 2 +#define MSM8953_VDDCX_AO 3 +#define MSM8953_VDDCX_VFL 4 +#define MSM8953_VDDMX 5 +#define MSM8953_VDDMX_AO 6 + /* MSM8976 Power Domain Indexes */ #define MSM8976_VDDCX 0 #define MSM8976_VDDCX_AO 1 @@ -59,6 +223,15 @@ #define MSM8976_VDDMX_AO 4 #define MSM8976_VDDMX_VFL 5 +/* MSM8994 Power Domain Indexes */ +#define MSM8994_VDDCX 0 +#define MSM8994_VDDCX_AO 1 +#define MSM8994_VDDCX_VFC 2 +#define MSM8994_VDDMX 3 +#define MSM8994_VDDMX_AO 4 +#define MSM8994_VDDGFX 5 +#define MSM8994_VDDGFX_VFC 6 + /* MSM8996 Power Domain Indexes */ #define MSM8996_VDDCX 0 #define MSM8996_VDDCX_AO 1 @@ -89,6 +262,46 @@ #define QCS404_LPIMX 5 #define QCS404_LPIMX_VFL 6 +/* SDM660 Power Domains */ +#define SDM660_VDDCX 0 +#define SDM660_VDDCX_AO 1 +#define SDM660_VDDCX_VFL 2 +#define SDM660_VDDMX 3 +#define SDM660_VDDMX_AO 4 +#define SDM660_VDDMX_VFL 5 +#define SDM660_SSCCX 6 +#define SDM660_SSCCX_VFL 7 +#define SDM660_SSCMX 8 +#define SDM660_SSCMX_VFL 9 + +/* SM6115 Power Domains */ +#define SM6115_VDDCX 0 +#define SM6115_VDDCX_AO 1 +#define SM6115_VDDCX_VFL 2 +#define SM6115_VDDMX 3 +#define SM6115_VDDMX_AO 4 +#define SM6115_VDDMX_VFL 5 +#define SM6115_VDD_LPI_CX 6 +#define SM6115_VDD_LPI_MX 7 + +/* SM6125 Power Domains */ +#define SM6125_VDDCX 0 +#define SM6125_VDDCX_AO 1 +#define SM6125_VDDCX_VFL 2 +#define SM6125_VDDMX 3 +#define SM6125_VDDMX_AO 4 +#define SM6125_VDDMX_VFL 5 + +/* QCM2290 Power Domains */ +#define QCM2290_VDDCX 0 +#define QCM2290_VDDCX_AO 1 +#define QCM2290_VDDCX_VFL 2 +#define QCM2290_VDDMX 3 +#define QCM2290_VDDMX_AO 4 +#define QCM2290_VDDMX_VFL 5 +#define QCM2290_VDD_LPI_CX 6 +#define QCM2290_VDD_LPI_MX 7 + /* RPM SMD Power Domain performance levels */ #define RPM_SMD_LEVEL_RETENTION 16 #define RPM_SMD_LEVEL_RETENTION_PLUS 32 diff --git a/include/dt-bindings/power/r8a7742-sysc.h b/include/dt-bindings/power/r8a7742-sysc.h new file mode 100644 index 000000000000..1b1bd3cf95db --- /dev/null +++ b/include/dt-bindings/power/r8a7742-sysc.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_POWER_R8A7742_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A7742_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A7742_PD_CA15_CPU0 0 +#define R8A7742_PD_CA15_CPU1 1 +#define R8A7742_PD_CA15_CPU2 2 +#define R8A7742_PD_CA15_CPU3 3 +#define R8A7742_PD_CA7_CPU0 5 +#define R8A7742_PD_CA7_CPU1 6 +#define R8A7742_PD_CA7_CPU2 7 +#define R8A7742_PD_CA7_CPU3 8 +#define R8A7742_PD_CA15_SCU 12 +#define R8A7742_PD_RGX 20 +#define R8A7742_PD_CA7_SCU 21 + +/* Always-on power area */ +#define R8A7742_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A7742_SYSC_H__ */ diff --git a/include/dt-bindings/power/r8a774e1-sysc.h b/include/dt-bindings/power/r8a774e1-sysc.h new file mode 100644 index 000000000000..7edb8161db36 --- /dev/null +++ b/include/dt-bindings/power/r8a774e1-sysc.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_POWER_R8A774E1_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A774E1_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A774E1_PD_CA57_CPU0 0 +#define R8A774E1_PD_CA57_CPU1 1 +#define R8A774E1_PD_CA57_CPU2 2 +#define R8A774E1_PD_CA57_CPU3 3 +#define R8A774E1_PD_CA53_CPU0 5 +#define R8A774E1_PD_CA53_CPU1 6 +#define R8A774E1_PD_CA53_CPU2 7 +#define R8A774E1_PD_CA53_CPU3 8 +#define R8A774E1_PD_A3VP 9 +#define R8A774E1_PD_CA57_SCU 12 +#define R8A774E1_PD_A3VC 14 +#define R8A774E1_PD_3DG_A 17 +#define R8A774E1_PD_3DG_B 18 +#define R8A774E1_PD_3DG_C 19 +#define R8A774E1_PD_3DG_D 20 +#define R8A774E1_PD_CA53_SCU 21 +#define R8A774E1_PD_3DG_E 22 +#define R8A774E1_PD_A2VC1 26 + +/* Always-on power area */ +#define R8A774E1_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A774E1_SYSC_H__ */ diff --git a/include/dt-bindings/power/r8a779a0-sysc.h b/include/dt-bindings/power/r8a779a0-sysc.h new file mode 100644 index 000000000000..57929e459a67 --- /dev/null +++ b/include/dt-bindings/power/r8a779a0-sysc.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2020 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_POWER_R8A779A0_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A779A0_SYSC_H__ + +/* + * These power domain indices match the Power Domain Register Numbers (PDR) + */ + +#define R8A779A0_PD_A1E0D0C0 0 +#define R8A779A0_PD_A1E0D0C1 1 +#define R8A779A0_PD_A1E0D1C0 2 +#define R8A779A0_PD_A1E0D1C1 3 +#define R8A779A0_PD_A1E1D0C0 4 +#define R8A779A0_PD_A1E1D0C1 5 +#define R8A779A0_PD_A1E1D1C0 6 +#define R8A779A0_PD_A1E1D1C1 7 +#define R8A779A0_PD_A2E0D0 16 +#define R8A779A0_PD_A2E0D1 17 +#define R8A779A0_PD_A2E1D0 18 +#define R8A779A0_PD_A2E1D1 19 +#define R8A779A0_PD_A3E0 20 +#define R8A779A0_PD_A3E1 21 +#define R8A779A0_PD_3DG_A 24 +#define R8A779A0_PD_3DG_B 25 +#define R8A779A0_PD_A1CNN2 32 +#define R8A779A0_PD_A1DSP0 33 +#define R8A779A0_PD_A2IMP01 34 +#define R8A779A0_PD_A2DP0 35 +#define R8A779A0_PD_A2CV0 36 +#define R8A779A0_PD_A2CV1 37 +#define R8A779A0_PD_A2CV4 38 +#define R8A779A0_PD_A2CV6 39 +#define R8A779A0_PD_A2CN2 40 +#define R8A779A0_PD_A1CNN0 41 +#define R8A779A0_PD_A2CN0 42 +#define R8A779A0_PD_A3IR 43 +#define R8A779A0_PD_A1CNN1 44 +#define R8A779A0_PD_A1DSP1 45 +#define R8A779A0_PD_A2IMP23 46 +#define R8A779A0_PD_A2DP1 47 +#define R8A779A0_PD_A2CV2 48 +#define R8A779A0_PD_A2CV3 49 +#define R8A779A0_PD_A2CV5 50 +#define R8A779A0_PD_A2CV7 51 +#define R8A779A0_PD_A2CN1 52 +#define R8A779A0_PD_A3VIP0 56 +#define R8A779A0_PD_A3VIP1 57 +#define R8A779A0_PD_A3VIP2 58 +#define R8A779A0_PD_A3VIP3 59 +#define R8A779A0_PD_A3ISP01 60 +#define R8A779A0_PD_A3ISP23 61 + +/* Always-on power area */ +#define R8A779A0_PD_ALWAYS_ON 64 + +#endif /* __DT_BINDINGS_POWER_R8A779A0_SYSC_H__ */ diff --git a/include/dt-bindings/power/r8a779f0-sysc.h b/include/dt-bindings/power/r8a779f0-sysc.h new file mode 100644 index 000000000000..0ec8ad727ed9 --- /dev/null +++ b/include/dt-bindings/power/r8a779f0-sysc.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: (GPL-2.0 or MIT) */ +/* + * Copyright (C) 2021 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_POWER_R8A779F0_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A779F0_SYSC_H__ + +/* + * These power domain indices match the Power Domain Register Numbers (PDR) + */ + +#define R8A779F0_PD_A1E0D0C0 0 +#define R8A779F0_PD_A1E0D0C1 1 +#define R8A779F0_PD_A1E0D1C0 2 +#define R8A779F0_PD_A1E0D1C1 3 +#define R8A779F0_PD_A1E1D0C0 4 +#define R8A779F0_PD_A1E1D0C1 5 +#define R8A779F0_PD_A1E1D1C0 6 +#define R8A779F0_PD_A1E1D1C1 7 +#define R8A779F0_PD_A2E0D0 16 +#define R8A779F0_PD_A2E0D1 17 +#define R8A779F0_PD_A2E1D0 18 +#define R8A779F0_PD_A2E1D1 19 +#define R8A779F0_PD_A3E0 20 +#define R8A779F0_PD_A3E1 21 + +/* Always-on power area */ +#define R8A779F0_PD_ALWAYS_ON 64 + +#endif /* __DT_BINDINGS_POWER_R8A779A0_SYSC_H__*/ diff --git a/include/dt-bindings/power/r8a779g0-sysc.h b/include/dt-bindings/power/r8a779g0-sysc.h new file mode 100644 index 000000000000..7daa70f1814e --- /dev/null +++ b/include/dt-bindings/power/r8a779g0-sysc.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2022 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_POWER_R8A779G0_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A779G0_SYSC_H__ + +/* + * These power domain indices match the Power Domain Register Numbers (PDR) + */ + +#define R8A779G0_PD_A1E0D0C0 0 +#define R8A779G0_PD_A1E0D0C1 1 +#define R8A779G0_PD_A1E0D1C0 2 +#define R8A779G0_PD_A1E0D1C1 3 +#define R8A779G0_PD_A2E0D0 16 +#define R8A779G0_PD_A2E0D1 17 +#define R8A779G0_PD_A3E0 20 +#define R8A779G0_PD_A33DGA 24 +#define R8A779G0_PD_A23DGB 25 +#define R8A779G0_PD_A1DSP0 33 +#define R8A779G0_PD_A2IMP01 34 +#define R8A779G0_PD_A2PSC 35 +#define R8A779G0_PD_A2CV0 36 +#define R8A779G0_PD_A2CV1 37 +#define R8A779G0_PD_A1CNN0 41 +#define R8A779G0_PD_A2CN0 42 +#define R8A779G0_PD_A3IR 43 +#define R8A779G0_PD_A1DSP1 45 +#define R8A779G0_PD_A2IMP23 46 +#define R8A779G0_PD_A2DMA 47 +#define R8A779G0_PD_A2CV2 48 +#define R8A779G0_PD_A2CV3 49 +#define R8A779G0_PD_A1DSP2 53 +#define R8A779G0_PD_A1DSP3 54 +#define R8A779G0_PD_A3VIP0 56 +#define R8A779G0_PD_A3VIP1 57 +#define R8A779G0_PD_A3VIP2 58 +#define R8A779G0_PD_A3ISP0 60 +#define R8A779G0_PD_A3ISP1 61 + +/* Always-on power area */ +#define R8A779G0_PD_ALWAYS_ON 64 + +#endif /* __DT_BINDINGS_POWER_R8A779G0_SYSC_H__*/ diff --git a/include/dt-bindings/power/rk3568-power.h b/include/dt-bindings/power/rk3568-power.h new file mode 100644 index 000000000000..6cc1af1a9d26 --- /dev/null +++ b/include/dt-bindings/power/rk3568-power.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_POWER_RK3568_POWER_H__ +#define __DT_BINDINGS_POWER_RK3568_POWER_H__ + +/* VD_CORE */ +#define RK3568_PD_CPU_0 0 +#define RK3568_PD_CPU_1 1 +#define RK3568_PD_CPU_2 2 +#define RK3568_PD_CPU_3 3 +#define RK3568_PD_CORE_ALIVE 4 + +/* VD_PMU */ +#define RK3568_PD_PMU 5 + +/* VD_NPU */ +#define RK3568_PD_NPU 6 + +/* VD_GPU */ +#define RK3568_PD_GPU 7 + +/* VD_LOGIC */ +#define RK3568_PD_VI 8 +#define RK3568_PD_VO 9 +#define RK3568_PD_RGA 10 +#define RK3568_PD_VPU 11 +#define RK3568_PD_CENTER 12 +#define RK3568_PD_RKVDEC 13 +#define RK3568_PD_RKVENC 14 +#define RK3568_PD_PIPE 15 +#define RK3568_PD_LOGIC_ALIVE 16 + +#endif diff --git a/include/dt-bindings/power/rk3588-power.h b/include/dt-bindings/power/rk3588-power.h new file mode 100644 index 000000000000..1b92fec013cb --- /dev/null +++ b/include/dt-bindings/power/rk3588-power.h @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: (GPL-2.0 or MIT) */ +#ifndef __DT_BINDINGS_POWER_RK3588_POWER_H__ +#define __DT_BINDINGS_POWER_RK3588_POWER_H__ + +/* VD_LITDSU */ +#define RK3588_PD_CPU_0 0 +#define RK3588_PD_CPU_1 1 +#define RK3588_PD_CPU_2 2 +#define RK3588_PD_CPU_3 3 + +/* VD_BIGCORE0 */ +#define RK3588_PD_CPU_4 4 +#define RK3588_PD_CPU_5 5 + +/* VD_BIGCORE1 */ +#define RK3588_PD_CPU_6 6 +#define RK3588_PD_CPU_7 7 + +/* VD_NPU */ +#define RK3588_PD_NPU 8 +#define RK3588_PD_NPUTOP 9 +#define RK3588_PD_NPU1 10 +#define RK3588_PD_NPU2 11 + +/* VD_GPU */ +#define RK3588_PD_GPU 12 + +/* VD_VCODEC */ +#define RK3588_PD_VCODEC 13 +#define RK3588_PD_RKVDEC0 14 +#define RK3588_PD_RKVDEC1 15 +#define RK3588_PD_VENC0 16 +#define RK3588_PD_VENC1 17 + +/* VD_DD01 */ +#define RK3588_PD_DDR01 18 + +/* VD_DD23 */ +#define RK3588_PD_DDR23 19 + +/* VD_LOGIC */ +#define RK3588_PD_CENTER 20 +#define RK3588_PD_VDPU 21 +#define RK3588_PD_RGA30 22 +#define RK3588_PD_AV1 23 +#define RK3588_PD_VOP 24 +#define RK3588_PD_VO0 25 +#define RK3588_PD_VO1 26 +#define RK3588_PD_VI 27 +#define RK3588_PD_ISP1 28 +#define RK3588_PD_FEC 29 +#define RK3588_PD_RGA31 30 +#define RK3588_PD_USB 31 +#define RK3588_PD_PHP 32 +#define RK3588_PD_GMAC 33 +#define RK3588_PD_PCIE 34 +#define RK3588_PD_NVM 35 +#define RK3588_PD_NVM0 36 +#define RK3588_PD_SDIO 37 +#define RK3588_PD_AUDIO 38 +#define RK3588_PD_SECURE 39 +#define RK3588_PD_SDMMC 40 +#define RK3588_PD_CRYPTO 41 +#define RK3588_PD_BUS 42 + +/* VD_PMU */ +#define RK3588_PD_PMU1 43 + +#endif diff --git a/include/dt-bindings/power/rockchip,rv1126-power.h b/include/dt-bindings/power/rockchip,rv1126-power.h new file mode 100644 index 000000000000..38a68e000d38 --- /dev/null +++ b/include/dt-bindings/power/rockchip,rv1126-power.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef __DT_BINDINGS_POWER_RV1126_POWER_H__ +#define __DT_BINDINGS_POWER_RV1126_POWER_H__ + +/* VD_CORE */ +#define RV1126_PD_CPU_0 0 +#define RV1126_PD_CPU_1 1 +#define RV1126_PD_CPU_2 2 +#define RV1126_PD_CPU_3 3 +#define RV1126_PD_CORE_ALIVE 4 + +/* VD_PMU */ +#define RV1126_PD_PMU 5 +#define RV1126_PD_PMU_ALIVE 6 + +/* VD_NPU */ +#define RV1126_PD_NPU 7 + +/* VD_VEPU */ +#define RV1126_PD_VEPU 8 + +/* VD_LOGIC */ +#define RV1126_PD_VI 9 +#define RV1126_PD_VO 10 +#define RV1126_PD_ISPP 11 +#define RV1126_PD_VDPU 12 +#define RV1126_PD_CRYPTO 13 +#define RV1126_PD_DDR 14 +#define RV1126_PD_NVM 15 +#define RV1126_PD_SDIO 16 +#define RV1126_PD_USB 17 +#define RV1126_PD_LOGIC_ALIVE 18 + +#endif diff --git a/include/dt-bindings/power/summit,smb347-charger.h b/include/dt-bindings/power/summit,smb347-charger.h new file mode 100644 index 000000000000..3205699b5e41 --- /dev/null +++ b/include/dt-bindings/power/summit,smb347-charger.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: (GPL-2.0-or-later or MIT) */ +/* + * Author: David Heidelberg <david@ixit.cz> + */ + +#ifndef _DT_BINDINGS_SMB347_CHARGER_H +#define _DT_BINDINGS_SMB347_CHARGER_H + +/* Charging compensation method */ +#define SMB3XX_SOFT_TEMP_COMPENSATE_NONE 0 +#define SMB3XX_SOFT_TEMP_COMPENSATE_CURRENT 1 +#define SMB3XX_SOFT_TEMP_COMPENSATE_VOLTAGE 2 + +/* Charging enable control */ +#define SMB3XX_CHG_ENABLE_SW 0 +#define SMB3XX_CHG_ENABLE_PIN_ACTIVE_LOW 1 +#define SMB3XX_CHG_ENABLE_PIN_ACTIVE_HIGH 2 + +/* Polarity of INOK signal */ +#define SMB3XX_SYSOK_INOK_ACTIVE_LOW 0 +#define SMB3XX_SYSOK_INOK_ACTIVE_HIGH 1 + +#endif diff --git a/include/dt-bindings/power/tegra234-powergate.h b/include/dt-bindings/power/tegra234-powergate.h new file mode 100644 index 000000000000..ae9286cef85c --- /dev/null +++ b/include/dt-bindings/power/tegra234-powergate.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */ + +#ifndef __ABI_MACH_T234_POWERGATE_T234_H_ +#define __ABI_MACH_T234_POWERGATE_T234_H_ + +#define TEGRA234_POWER_DOMAIN_AUD 2U +#define TEGRA234_POWER_DOMAIN_DISP 3U +#define TEGRA234_POWER_DOMAIN_PCIEX8A 5U +#define TEGRA234_POWER_DOMAIN_PCIEX4A 6U +#define TEGRA234_POWER_DOMAIN_PCIEX4BA 7U +#define TEGRA234_POWER_DOMAIN_PCIEX4BB 8U +#define TEGRA234_POWER_DOMAIN_PCIEX1A 9U +#define TEGRA234_POWER_DOMAIN_PCIEX4CA 13U +#define TEGRA234_POWER_DOMAIN_PCIEX4CB 14U +#define TEGRA234_POWER_DOMAIN_PCIEX4CC 15U +#define TEGRA234_POWER_DOMAIN_PCIEX8B 16U +#define TEGRA234_POWER_DOMAIN_MGBEA 17U +#define TEGRA234_POWER_DOMAIN_MGBEB 18U +#define TEGRA234_POWER_DOMAIN_MGBEC 19U +#define TEGRA234_POWER_DOMAIN_MGBED 20U +#define TEGRA234_POWER_DOMAIN_VIC 29U + +#endif diff --git a/include/dt-bindings/pwm/raspberrypi,firmware-poe-pwm.h b/include/dt-bindings/pwm/raspberrypi,firmware-poe-pwm.h new file mode 100644 index 000000000000..27c5ce68847b --- /dev/null +++ b/include/dt-bindings/pwm/raspberrypi,firmware-poe-pwm.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 Nicolas Saenz Julienne + * Author: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> + */ + +#ifndef _DT_BINDINGS_RASPBERRYPI_FIRMWARE_PWM_H +#define _DT_BINDINGS_RASPBERRYPI_FIRMWARE_PWM_H + +#define RASPBERRYPI_FIRMWARE_PWM_POE 0 +#define RASPBERRYPI_FIRMWARE_PWM_NUM 1 + +#endif diff --git a/include/dt-bindings/regulator/dlg,da9121-regulator.h b/include/dt-bindings/regulator/dlg,da9121-regulator.h new file mode 100644 index 000000000000..954edf633ce7 --- /dev/null +++ b/include/dt-bindings/regulator/dlg,da9121-regulator.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef _DT_BINDINGS_REGULATOR_DLG_DA9121_H +#define _DT_BINDINGS_REGULATOR_DLG_DA9121_H + +/* + * These buck mode constants may be used to specify values in device tree + * properties (e.g. regulator-initial-mode). + * A description of the following modes is in the manufacturers datasheet. + */ + +#define DA9121_BUCK_MODE_FORCE_PFM 0 +#define DA9121_BUCK_MODE_FORCE_PWM 1 +#define DA9121_BUCK_MODE_FORCE_PWM_SHEDDING 2 +#define DA9121_BUCK_MODE_AUTO 3 + +#define DA9121_BUCK_RIPPLE_CANCEL_NONE 0 +#define DA9121_BUCK_RIPPLE_CANCEL_SMALL 1 +#define DA9121_BUCK_RIPPLE_CANCEL_MID 2 +#define DA9121_BUCK_RIPPLE_CANCEL_LARGE 3 + +#endif diff --git a/include/dt-bindings/regulator/dlg,da9211-regulator.h b/include/dt-bindings/regulator/dlg,da9211-regulator.h new file mode 100644 index 000000000000..cdce2d54c8ba --- /dev/null +++ b/include/dt-bindings/regulator/dlg,da9211-regulator.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef _DT_BINDINGS_REGULATOR_DLG_DA9211_H +#define _DT_BINDINGS_REGULATOR_DLG_DA9211_H + +/* + * These buck mode constants may be used to specify values in device tree + * properties (e.g. regulator-initial-mode, regulator-allowed-modes). + * A description of the following modes is in the manufacturers datasheet. + */ + +#define DA9211_BUCK_MODE_SLEEP 1 +#define DA9211_BUCK_MODE_SYNC 2 +#define DA9211_BUCK_MODE_AUTO 3 + +#endif diff --git a/include/dt-bindings/regulator/mediatek,mt6360-regulator.h b/include/dt-bindings/regulator/mediatek,mt6360-regulator.h new file mode 100644 index 000000000000..21c75de700c0 --- /dev/null +++ b/include/dt-bindings/regulator/mediatek,mt6360-regulator.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef __DT_BINDINGS_MEDIATEK_MT6360_REGULATOR_H__ +#define __DT_BINDINGS_MEDIATEK_MT6360_REGULATOR_H__ + +/* + * BUCK/LDO mode constants which may be used in devicetree properties + * (eg. regulator-allowed-modes). + * See the manufacturer's datasheet for more information on these modes. + */ + +#define MT6360_OPMODE_LP 2 +#define MT6360_OPMODE_ULP 3 +#define MT6360_OPMODE_NORMAL 0 + +#endif diff --git a/include/dt-bindings/regulator/mediatek,mt6397-regulator.h b/include/dt-bindings/regulator/mediatek,mt6397-regulator.h new file mode 100644 index 000000000000..99869a8665cf --- /dev/null +++ b/include/dt-bindings/regulator/mediatek,mt6397-regulator.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef _DT_BINDINGS_REGULATOR_MEDIATEK_MT6397_H_ +#define _DT_BINDINGS_REGULATOR_MEDIATEK_MT6397_H_ + +/* + * Buck mode constants which may be used in devicetree properties (eg. + * regulator-initial-mode, regulator-allowed-modes). + * See the manufacturer's datasheet for more information on these modes. + */ + +#define MT6397_BUCK_MODE_AUTO 0 +#define MT6397_BUCK_MODE_FORCE_PWM 1 + +#endif diff --git a/include/dt-bindings/regulator/richtek,rt5190a-regulator.h b/include/dt-bindings/regulator/richtek,rt5190a-regulator.h new file mode 100644 index 000000000000..63f99d4c1cb3 --- /dev/null +++ b/include/dt-bindings/regulator/richtek,rt5190a-regulator.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef __DT_BINDINGS_RICHTEK_RT5190A_REGULATOR_H__ +#define __DT_BINDINGS_RICHTEK_RT5190A_REGULATOR_H__ + +/* + * BUCK/LDO mode constants which may be used in devicetree properties + * (eg. regulator-allowed-modes). + * See the manufacturer's datasheet for more information on these modes. + */ + +#define RT5190A_OPMODE_AUTO 0 +#define RT5190A_OPMODE_FPWM 1 + +#endif diff --git a/include/dt-bindings/regulator/ti,tps62864.h b/include/dt-bindings/regulator/ti,tps62864.h new file mode 100644 index 000000000000..8db31f23d956 --- /dev/null +++ b/include/dt-bindings/regulator/ti,tps62864.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_REGULATOR_TI_TPS62864_H +#define _DT_BINDINGS_REGULATOR_TI_TPS62864_H + +#define TPS62864_MODE_NORMAL 0 +#define TPS62864_MODE_FPWM 1 + +#endif diff --git a/include/dt-bindings/reset/actions,s500-reset.h b/include/dt-bindings/reset/actions,s500-reset.h new file mode 100644 index 000000000000..f5d94176d10b --- /dev/null +++ b/include/dt-bindings/reset/actions,s500-reset.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Device Tree binding constants for Actions Semi S500 Reset Management Unit + * + * Copyright (c) 2014 Actions Semi Inc. + * Copyright (c) 2020 Cristian Ciocaltea <cristian.ciocaltea@gmail.com> + */ + +#ifndef __DT_BINDINGS_ACTIONS_S500_RESET_H +#define __DT_BINDINGS_ACTIONS_S500_RESET_H + +#define RESET_DMAC 0 +#define RESET_NORIF 1 +#define RESET_DDR 2 +#define RESET_NANDC 3 +#define RESET_SD0 4 +#define RESET_SD1 5 +#define RESET_PCM1 6 +#define RESET_DE 7 +#define RESET_LCD 8 +#define RESET_SD2 9 +#define RESET_DSI 10 +#define RESET_CSI 11 +#define RESET_BISP 12 +#define RESET_KEY 13 +#define RESET_GPIO 14 +#define RESET_AUDIO 15 +#define RESET_PCM0 16 +#define RESET_VDE 17 +#define RESET_VCE 18 +#define RESET_GPU3D 19 +#define RESET_NIC301 20 +#define RESET_LENS 21 +#define RESET_PERIPHRESET 22 +#define RESET_USB2_0 23 +#define RESET_TVOUT 24 +#define RESET_HDMI 25 +#define RESET_HDCP2TX 26 +#define RESET_UART6 27 +#define RESET_UART0 28 +#define RESET_UART1 29 +#define RESET_UART2 30 +#define RESET_SPI0 31 +#define RESET_SPI1 32 +#define RESET_SPI2 33 +#define RESET_SPI3 34 +#define RESET_I2C0 35 +#define RESET_I2C1 36 +#define RESET_USB3 37 +#define RESET_UART3 38 +#define RESET_UART4 39 +#define RESET_UART5 40 +#define RESET_I2C2 41 +#define RESET_I2C3 42 +#define RESET_ETHERNET 43 +#define RESET_CHIPID 44 +#define RESET_USB2_1 45 +#define RESET_WD0RESET 46 +#define RESET_WD1RESET 47 +#define RESET_WD2RESET 48 +#define RESET_WD3RESET 49 +#define RESET_DBG0RESET 50 +#define RESET_DBG1RESET 51 +#define RESET_DBG2RESET 52 +#define RESET_DBG3RESET 53 + +#endif /* __DT_BINDINGS_ACTIONS_S500_RESET_H */ diff --git a/include/dt-bindings/reset/amlogic,meson-gxbb-reset.h b/include/dt-bindings/reset/amlogic,meson-gxbb-reset.h index ea5058618863..883bfd3bcbad 100644 --- a/include/dt-bindings/reset/amlogic,meson-gxbb-reset.h +++ b/include/dt-bindings/reset/amlogic,meson-gxbb-reset.h @@ -69,7 +69,7 @@ #define RESET_SYS_CPU_L2 58 #define RESET_SYS_CPU_P 59 #define RESET_SYS_CPU_MBIST 60 -/* 61 */ +#define RESET_ACODEC 61 /* 62 */ /* 63 */ /* RESET2 */ diff --git a/include/dt-bindings/reset/amlogic,meson-s4-reset.h b/include/dt-bindings/reset/amlogic,meson-s4-reset.h new file mode 100644 index 000000000000..eab428eb8ad6 --- /dev/null +++ b/include/dt-bindings/reset/amlogic,meson-s4-reset.h @@ -0,0 +1,125 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2021 Amlogic, Inc. All rights reserved. + * Author: Zelong Dong <zelong.dong@amlogic.com> + * + */ + +#ifndef _DT_BINDINGS_AMLOGIC_MESON_S4_RESET_H +#define _DT_BINDINGS_AMLOGIC_MESON_S4_RESET_H + +/* RESET0 */ +#define RESET_USB_DDR0 0 +#define RESET_USB_DDR1 1 +#define RESET_USB_DDR2 2 +#define RESET_USB_DDR3 3 +#define RESET_USBCTRL 4 +/* 5-7 */ +#define RESET_USBPHY20 8 +#define RESET_USBPHY21 9 +/* 10-15 */ +#define RESET_HDMITX_APB 16 +#define RESET_BRG_VCBUS_DEC 17 +#define RESET_VCBUS 18 +#define RESET_VID_PLL_DIV 19 +#define RESET_VDI6 20 +#define RESET_GE2D 21 +#define RESET_HDMITXPHY 22 +#define RESET_VID_LOCK 23 +#define RESET_VENCL 24 +#define RESET_VDAC 25 +#define RESET_VENCP 26 +#define RESET_VENCI 27 +#define RESET_RDMA 28 +#define RESET_HDMI_TX 29 +#define RESET_VIU 30 +#define RESET_VENC 31 + +/* RESET1 */ +#define RESET_AUDIO 32 +#define RESET_MALI_APB 33 +#define RESET_MALI 34 +#define RESET_DDR_APB 35 +#define RESET_DDR 36 +#define RESET_DOS_APB 37 +#define RESET_DOS 38 +/* 39-47 */ +#define RESET_ETH 48 +/* 49-51 */ +#define RESET_DEMOD 52 +/* 53-63 */ + +/* RESET2 */ +#define RESET_ABUS_ARB 64 +#define RESET_IR_CTRL 65 +#define RESET_TEMPSENSOR_DDR 66 +#define RESET_TEMPSENSOR_PLL 67 +/* 68-71 */ +#define RESET_SMART_CARD 72 +#define RESET_SPICC0 73 +/* 74 */ +#define RESET_RSA 75 +/* 76-79 */ +#define RESET_MSR_CLK 80 +#define RESET_SPIFC 81 +#define RESET_SARADC 82 +/* 83-87 */ +#define RESET_ACODEC 88 +#define RESET_CEC 89 +#define RESET_AFIFO 90 +#define RESET_WATCHDOG 91 +/* 92-95 */ + +/* RESET3 */ +/* 96-127 */ + +/* RESET4 */ +/* 128-131 */ +#define RESET_PWM_AB 132 +#define RESET_PWM_CD 133 +#define RESET_PWM_EF 134 +#define RESET_PWM_GH 135 +#define RESET_PWM_IJ 136 +/* 137 */ +#define RESET_UART_A 138 +#define RESET_UART_B 139 +#define RESET_UART_C 140 +#define RESET_UART_D 141 +#define RESET_UART_E 142 +/* 143 */ +#define RESET_I2C_S_A 144 +#define RESET_I2C_M_A 145 +#define RESET_I2C_M_B 146 +#define RESET_I2C_M_C 147 +#define RESET_I2C_M_D 148 +#define RESET_I2C_M_E 149 +/* 150-151 */ +#define RESET_SD_EMMC_A 152 +#define RESET_SD_EMMC_B 153 +#define RESET_NAND_EMMC 154 +/* 155-159 */ + +/* RESET5 */ +#define RESET_BRG_VDEC_PIPL0 160 +#define RESET_BRG_HEVCF_PIPL0 161 +/* 162 */ +#define RESET_BRG_HCODEC_PIPL0 163 +#define RESET_BRG_GE2D_PIPL0 164 +#define RESET_BRG_VPU_PIPL0 165 +#define RESET_BRG_CPU_PIPL0 166 +#define RESET_BRG_MALI_PIPL0 167 +/* 168 */ +#define RESET_BRG_MALI_PIPL1 169 +/* 170-171 */ +#define RESET_BRG_HEVCF_PIPL1 172 +#define RESET_BRG_HEVCB_PIPL1 173 +/* 174-183 */ +#define RESET_RAMA 184 +/* 185-186 */ +#define RESET_BRG_NIC_VAPB 187 +#define RESET_BRG_NIC_DSU 188 +#define RESET_BRG_NIC_SYSCLK 189 +#define RESET_BRG_NIC_MAIN 190 +#define RESET_BRG_NIC_ALL 191 + +#endif diff --git a/include/dt-bindings/reset/bcm6318-reset.h b/include/dt-bindings/reset/bcm6318-reset.h new file mode 100644 index 000000000000..f882662505ea --- /dev/null +++ b/include/dt-bindings/reset/bcm6318-reset.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __DT_BINDINGS_RESET_BCM6318_H +#define __DT_BINDINGS_RESET_BCM6318_H + +#define BCM6318_RST_SPI 0 +#define BCM6318_RST_EPHY 1 +#define BCM6318_RST_SAR 2 +#define BCM6318_RST_ENETSW 3 +#define BCM6318_RST_USBD 4 +#define BCM6318_RST_USBH 5 +#define BCM6318_RST_PCIE_CORE 6 +#define BCM6318_RST_PCIE 7 +#define BCM6318_RST_PCIE_EXT 8 +#define BCM6318_RST_PCIE_HARD 9 +#define BCM6318_RST_ADSL 10 +#define BCM6318_RST_PHYMIPS 11 +#define BCM6318_RST_HOSTMIPS 12 + +#endif /* __DT_BINDINGS_RESET_BCM6318_H */ diff --git a/include/dt-bindings/reset/bcm63268-reset.h b/include/dt-bindings/reset/bcm63268-reset.h new file mode 100644 index 000000000000..6a6403a4c2d5 --- /dev/null +++ b/include/dt-bindings/reset/bcm63268-reset.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __DT_BINDINGS_RESET_BCM63268_H +#define __DT_BINDINGS_RESET_BCM63268_H + +#define BCM63268_RST_SPI 0 +#define BCM63268_RST_IPSEC 1 +#define BCM63268_RST_EPHY 2 +#define BCM63268_RST_SAR 3 +#define BCM63268_RST_ENETSW 4 +#define BCM63268_RST_USBS 5 +#define BCM63268_RST_USBH 6 +#define BCM63268_RST_PCM 7 +#define BCM63268_RST_PCIE_CORE 8 +#define BCM63268_RST_PCIE 9 +#define BCM63268_RST_PCIE_EXT 10 +#define BCM63268_RST_WLAN_SHIM 11 +#define BCM63268_RST_DDR_PHY 12 +#define BCM63268_RST_FAP0 13 +#define BCM63268_RST_WLAN_UBUS 14 +#define BCM63268_RST_DECT 15 +#define BCM63268_RST_FAP1 16 +#define BCM63268_RST_PCIE_HARD 17 +#define BCM63268_RST_GPHY 18 + +#endif /* __DT_BINDINGS_RESET_BCM63268_H */ diff --git a/include/dt-bindings/reset/bcm6328-reset.h b/include/dt-bindings/reset/bcm6328-reset.h new file mode 100644 index 000000000000..0f3df87d47af --- /dev/null +++ b/include/dt-bindings/reset/bcm6328-reset.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __DT_BINDINGS_RESET_BCM6328_H +#define __DT_BINDINGS_RESET_BCM6328_H + +#define BCM6328_RST_SPI 0 +#define BCM6328_RST_EPHY 1 +#define BCM6328_RST_SAR 2 +#define BCM6328_RST_ENETSW 3 +#define BCM6328_RST_USBS 4 +#define BCM6328_RST_USBH 5 +#define BCM6328_RST_PCM 6 +#define BCM6328_RST_PCIE_CORE 7 +#define BCM6328_RST_PCIE 8 +#define BCM6328_RST_PCIE_EXT 9 +#define BCM6328_RST_PCIE_HARD 10 + +#endif /* __DT_BINDINGS_RESET_BCM6328_H */ diff --git a/include/dt-bindings/reset/bcm6358-reset.h b/include/dt-bindings/reset/bcm6358-reset.h new file mode 100644 index 000000000000..bda62ef84f5a --- /dev/null +++ b/include/dt-bindings/reset/bcm6358-reset.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __DT_BINDINGS_RESET_BCM6358_H +#define __DT_BINDINGS_RESET_BCM6358_H + +#define BCM6358_RST_SPI 0 +#define BCM6358_RST_ENET 2 +#define BCM6358_RST_MPI 3 +#define BCM6358_RST_EPHY 6 +#define BCM6358_RST_SAR 7 +#define BCM6358_RST_USBH 12 +#define BCM6358_RST_PCM 13 +#define BCM6358_RST_ADSL 14 + +#endif /* __DT_BINDINGS_RESET_BCM6358_H */ diff --git a/include/dt-bindings/reset/bcm6362-reset.h b/include/dt-bindings/reset/bcm6362-reset.h new file mode 100644 index 000000000000..7ebb0546e0ab --- /dev/null +++ b/include/dt-bindings/reset/bcm6362-reset.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __DT_BINDINGS_RESET_BCM6362_H +#define __DT_BINDINGS_RESET_BCM6362_H + +#define BCM6362_RST_SPI 0 +#define BCM6362_RST_IPSEC 1 +#define BCM6362_RST_EPHY 2 +#define BCM6362_RST_SAR 3 +#define BCM6362_RST_ENETSW 4 +#define BCM6362_RST_USBD 5 +#define BCM6362_RST_USBH 6 +#define BCM6362_RST_PCM 7 +#define BCM6362_RST_PCIE_CORE 8 +#define BCM6362_RST_PCIE 9 +#define BCM6362_RST_PCIE_EXT 10 +#define BCM6362_RST_WLAN_SHIM 11 +#define BCM6362_RST_DDR_PHY 12 +#define BCM6362_RST_FAP 13 +#define BCM6362_RST_WLAN_UBUS 14 + +#endif /* __DT_BINDINGS_RESET_BCM6362_H */ diff --git a/include/dt-bindings/reset/bcm6368-reset.h b/include/dt-bindings/reset/bcm6368-reset.h new file mode 100644 index 000000000000..c81d8eb6d173 --- /dev/null +++ b/include/dt-bindings/reset/bcm6368-reset.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __DT_BINDINGS_RESET_BCM6368_H +#define __DT_BINDINGS_RESET_BCM6368_H + +#define BCM6368_RST_SPI 0 +#define BCM6368_RST_MPI 3 +#define BCM6368_RST_IPSEC 4 +#define BCM6368_RST_EPHY 6 +#define BCM6368_RST_SAR 7 +#define BCM6368_RST_SWITCH 10 +#define BCM6368_RST_USBD 11 +#define BCM6368_RST_USBH 12 +#define BCM6368_RST_PCM 13 + +#endif /* __DT_BINDINGS_RESET_BCM6368_H */ diff --git a/include/dt-bindings/reset/bt1-ccu.h b/include/dt-bindings/reset/bt1-ccu.h new file mode 100644 index 000000000000..c691efaa678f --- /dev/null +++ b/include/dt-bindings/reset/bt1-ccu.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC + * + * Baikal-T1 CCU reset indices + */ +#ifndef __DT_BINDINGS_RESET_BT1_CCU_H +#define __DT_BINDINGS_RESET_BT1_CCU_H + +#define CCU_AXI_MAIN_RST 0 +#define CCU_AXI_DDR_RST 1 +#define CCU_AXI_SATA_RST 2 +#define CCU_AXI_GMAC0_RST 3 +#define CCU_AXI_GMAC1_RST 4 +#define CCU_AXI_XGMAC_RST 5 +#define CCU_AXI_PCIE_M_RST 6 +#define CCU_AXI_PCIE_S_RST 7 +#define CCU_AXI_USB_RST 8 +#define CCU_AXI_HWA_RST 9 +#define CCU_AXI_SRAM_RST 10 + +#define CCU_SYS_SATA_REF_RST 0 +#define CCU_SYS_APB_RST 1 +#define CCU_SYS_DDR_FULL_RST 2 +#define CCU_SYS_DDR_INIT_RST 3 +#define CCU_SYS_PCIE_PCS_PHY_RST 4 +#define CCU_SYS_PCIE_PIPE0_RST 5 +#define CCU_SYS_PCIE_CORE_RST 6 +#define CCU_SYS_PCIE_PWR_RST 7 +#define CCU_SYS_PCIE_STICKY_RST 8 +#define CCU_SYS_PCIE_NSTICKY_RST 9 +#define CCU_SYS_PCIE_HOT_RST 10 + +#endif /* __DT_BINDINGS_RESET_BT1_CCU_H */ diff --git a/include/dt-bindings/reset/delta,tn48m-reset.h b/include/dt-bindings/reset/delta,tn48m-reset.h new file mode 100644 index 000000000000..d4e9ed12de3e --- /dev/null +++ b/include/dt-bindings/reset/delta,tn48m-reset.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Delta TN48M CPLD GPIO driver + * + * Copyright (C) 2021 Sartura Ltd. + * + * Author: Robert Marko <robert.marko@sartura.hr> + */ + +#ifndef _DT_BINDINGS_RESET_TN48M_H +#define _DT_BINDINGS_RESET_TN48M_H + +#define CPU_88F7040_RESET 0 +#define CPU_88F6820_RESET 1 +#define MAC_98DX3265_RESET 2 +#define PHY_88E1680_RESET 3 +#define PHY_88E1512_RESET 4 +#define POE_RESET 5 + +#endif /* _DT_BINDINGS_RESET_TN48M_H */ diff --git a/include/dt-bindings/reset/imx8mp-reset.h b/include/dt-bindings/reset/imx8mp-reset.h new file mode 100644 index 000000000000..2e8c9104b666 --- /dev/null +++ b/include/dt-bindings/reset/imx8mp-reset.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2020 NXP + */ + +#ifndef DT_BINDING_RESET_IMX8MP_H +#define DT_BINDING_RESET_IMX8MP_H + +#define IMX8MP_RESET_A53_CORE_POR_RESET0 0 +#define IMX8MP_RESET_A53_CORE_POR_RESET1 1 +#define IMX8MP_RESET_A53_CORE_POR_RESET2 2 +#define IMX8MP_RESET_A53_CORE_POR_RESET3 3 +#define IMX8MP_RESET_A53_CORE_RESET0 4 +#define IMX8MP_RESET_A53_CORE_RESET1 5 +#define IMX8MP_RESET_A53_CORE_RESET2 6 +#define IMX8MP_RESET_A53_CORE_RESET3 7 +#define IMX8MP_RESET_A53_DBG_RESET0 8 +#define IMX8MP_RESET_A53_DBG_RESET1 9 +#define IMX8MP_RESET_A53_DBG_RESET2 10 +#define IMX8MP_RESET_A53_DBG_RESET3 11 +#define IMX8MP_RESET_A53_ETM_RESET0 12 +#define IMX8MP_RESET_A53_ETM_RESET1 13 +#define IMX8MP_RESET_A53_ETM_RESET2 14 +#define IMX8MP_RESET_A53_ETM_RESET3 15 +#define IMX8MP_RESET_A53_SOC_DBG_RESET 16 +#define IMX8MP_RESET_A53_L2RESET 17 +#define IMX8MP_RESET_SW_NON_SCLR_M7C_RST 18 +#define IMX8MP_RESET_OTG1_PHY_RESET 19 +#define IMX8MP_RESET_OTG2_PHY_RESET 20 +#define IMX8MP_RESET_SUPERMIX_RESET 21 +#define IMX8MP_RESET_AUDIOMIX_RESET 22 +#define IMX8MP_RESET_MLMIX_RESET 23 +#define IMX8MP_RESET_PCIEPHY 24 +#define IMX8MP_RESET_PCIEPHY_PERST 25 +#define IMX8MP_RESET_PCIE_CTRL_APPS_EN 26 +#define IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF 27 +#define IMX8MP_RESET_HDMI_PHY_APB_RESET 28 +#define IMX8MP_RESET_MEDIA_RESET 29 +#define IMX8MP_RESET_GPU2D_RESET 30 +#define IMX8MP_RESET_GPU3D_RESET 31 +#define IMX8MP_RESET_GPU_RESET 32 +#define IMX8MP_RESET_VPU_RESET 33 +#define IMX8MP_RESET_VPU_G1_RESET 34 +#define IMX8MP_RESET_VPU_G2_RESET 35 +#define IMX8MP_RESET_VPUVC8KE_RESET 36 +#define IMX8MP_RESET_NOC_RESET 37 + +#define IMX8MP_RESET_NUM 38 + +#endif diff --git a/include/dt-bindings/reset/imx8mq-reset.h b/include/dt-bindings/reset/imx8mq-reset.h index 9a301082d361..705870693ec2 100644 --- a/include/dt-bindings/reset/imx8mq-reset.h +++ b/include/dt-bindings/reset/imx8mq-reset.h @@ -28,37 +28,40 @@ #define IMX8MQ_RESET_A53_L2RESET 17 #define IMX8MQ_RESET_SW_NON_SCLR_M4C_RST 18 #define IMX8MQ_RESET_OTG1_PHY_RESET 19 -#define IMX8MQ_RESET_OTG2_PHY_RESET 20 -#define IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N 21 -#define IMX8MQ_RESET_MIPI_DSI_RESET_N 22 -#define IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N 23 -#define IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N 24 -#define IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N 25 -#define IMX8MQ_RESET_PCIEPHY 26 -#define IMX8MQ_RESET_PCIEPHY_PERST 27 -#define IMX8MQ_RESET_PCIE_CTRL_APPS_EN 28 -#define IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF 29 -#define IMX8MQ_RESET_HDMI_PHY_APB_RESET 30 /* i.MX8MM does NOT support */ +#define IMX8MQ_RESET_OTG2_PHY_RESET 20 /* i.MX8MN does NOT support */ +#define IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N 21 /* i.MX8MN does NOT support */ +#define IMX8MQ_RESET_MIPI_DSI_RESET_N 22 /* i.MX8MN does NOT support */ +#define IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N 23 /* i.MX8MN does NOT support */ +#define IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N 24 /* i.MX8MN does NOT support */ +#define IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N 25 /* i.MX8MN does NOT support */ +#define IMX8MQ_RESET_PCIEPHY 26 /* i.MX8MN does NOT support */ +#define IMX8MQ_RESET_PCIEPHY_PERST 27 /* i.MX8MN does NOT support */ +#define IMX8MQ_RESET_PCIE_CTRL_APPS_EN 28 /* i.MX8MN does NOT support */ +#define IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF 29 /* i.MX8MN does NOT support */ +#define IMX8MQ_RESET_HDMI_PHY_APB_RESET 30 /* i.MX8MM/i.MX8MN does NOT support */ #define IMX8MQ_RESET_DISP_RESET 31 #define IMX8MQ_RESET_GPU_RESET 32 -#define IMX8MQ_RESET_VPU_RESET 33 -#define IMX8MQ_RESET_PCIEPHY2 34 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_PCIEPHY2_PERST 35 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_PCIE2_CTRL_APPS_EN 36 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF 37 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_MIPI_CSI1_CORE_RESET 38 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET 39 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_MIPI_CSI1_ESC_RESET 40 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_MIPI_CSI2_CORE_RESET 41 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET 42 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_MIPI_CSI2_ESC_RESET 43 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_DDRC1_PRST 44 -#define IMX8MQ_RESET_DDRC1_CORE_RESET 45 -#define IMX8MQ_RESET_DDRC1_PHY_RESET 46 -#define IMX8MQ_RESET_DDRC2_PRST 47 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_DDRC2_CORE_RESET 48 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_DDRC2_PHY_RESET 49 /* i.MX8MM does NOT support */ +#define IMX8MQ_RESET_VPU_RESET 33 /* i.MX8MN does NOT support */ +#define IMX8MQ_RESET_PCIEPHY2 34 /* i.MX8MM/i.MX8MN does NOT support */ +#define IMX8MQ_RESET_PCIEPHY2_PERST 35 /* i.MX8MM/i.MX8MN does NOT support */ +#define IMX8MQ_RESET_PCIE2_CTRL_APPS_EN 36 /* i.MX8MM/i.MX8MN does NOT support */ +#define IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF 37 /* i.MX8MM/i.MX8MN does NOT support */ +#define IMX8MQ_RESET_MIPI_CSI1_CORE_RESET 38 /* i.MX8MM/i.MX8MN does NOT support */ +#define IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET 39 /* i.MX8MM/i.MX8MN does NOT support */ +#define IMX8MQ_RESET_MIPI_CSI1_ESC_RESET 40 /* i.MX8MM/i.MX8MN does NOT support */ +#define IMX8MQ_RESET_MIPI_CSI2_CORE_RESET 41 /* i.MX8MM/i.MX8MN does NOT support */ +#define IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET 42 /* i.MX8MM/i.MX8MN does NOT support */ +#define IMX8MQ_RESET_MIPI_CSI2_ESC_RESET 43 /* i.MX8MM/i.MX8MN does NOT support */ +#define IMX8MQ_RESET_DDRC1_PRST 44 /* i.MX8MN does NOT support */ +#define IMX8MQ_RESET_DDRC1_CORE_RESET 45 /* i.MX8MN does NOT support */ +#define IMX8MQ_RESET_DDRC1_PHY_RESET 46 /* i.MX8MN does NOT support */ +#define IMX8MQ_RESET_DDRC2_PRST 47 /* i.MX8MM/i.MX8MN does NOT support */ +#define IMX8MQ_RESET_DDRC2_CORE_RESET 48 /* i.MX8MM/i.MX8MN does NOT support */ +#define IMX8MQ_RESET_DDRC2_PHY_RESET 49 /* i.MX8MM/i.MX8MN does NOT support */ +#define IMX8MQ_RESET_SW_M4C_RST 50 +#define IMX8MQ_RESET_SW_M4P_RST 51 +#define IMX8MQ_RESET_M4_ENABLE 52 -#define IMX8MQ_RESET_NUM 50 +#define IMX8MQ_RESET_NUM 53 #endif diff --git a/include/dt-bindings/reset/imx8ulp-pcc-reset.h b/include/dt-bindings/reset/imx8ulp-pcc-reset.h new file mode 100644 index 000000000000..e99a4735c3c4 --- /dev/null +++ b/include/dt-bindings/reset/imx8ulp-pcc-reset.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2021 NXP + */ + +#ifndef DT_BINDING_PCC_RESET_IMX8ULP_H +#define DT_BINDING_PCC_RESET_IMX8ULP_H + +/* PCC3 */ +#define PCC3_WDOG3_SWRST 0 +#define PCC3_WDOG4_SWRST 1 +#define PCC3_LPIT1_SWRST 2 +#define PCC3_TPM4_SWRST 3 +#define PCC3_TPM5_SWRST 4 +#define PCC3_FLEXIO1_SWRST 5 +#define PCC3_I3C2_SWRST 6 +#define PCC3_LPI2C4_SWRST 7 +#define PCC3_LPI2C5_SWRST 8 +#define PCC3_LPUART4_SWRST 9 +#define PCC3_LPUART5_SWRST 10 +#define PCC3_LPSPI4_SWRST 11 +#define PCC3_LPSPI5_SWRST 12 + +/* PCC4 */ +#define PCC4_FLEXSPI2_SWRST 0 +#define PCC4_TPM6_SWRST 1 +#define PCC4_TPM7_SWRST 2 +#define PCC4_LPI2C6_SWRST 3 +#define PCC4_LPI2C7_SWRST 4 +#define PCC4_LPUART6_SWRST 5 +#define PCC4_LPUART7_SWRST 6 +#define PCC4_SAI4_SWRST 7 +#define PCC4_SAI5_SWRST 8 +#define PCC4_USDHC0_SWRST 9 +#define PCC4_USDHC1_SWRST 10 +#define PCC4_USDHC2_SWRST 11 +#define PCC4_USB0_SWRST 12 +#define PCC4_USB0_PHY_SWRST 13 +#define PCC4_USB1_SWRST 14 +#define PCC4_USB1_PHY_SWRST 15 +#define PCC4_ENET_SWRST 16 + +/* PCC5 */ +#define PCC5_TPM8_SWRST 0 +#define PCC5_SAI6_SWRST 1 +#define PCC5_SAI7_SWRST 2 +#define PCC5_SPDIF_SWRST 3 +#define PCC5_ISI_SWRST 4 +#define PCC5_CSI_REGS_SWRST 5 +#define PCC5_CSI_SWRST 6 +#define PCC5_DSI_SWRST 7 +#define PCC5_WDOG5_SWRST 8 +#define PCC5_EPDC_SWRST 9 +#define PCC5_PXP_SWRST 10 +#define PCC5_GPU2D_SWRST 11 +#define PCC5_GPU3D_SWRST 12 +#define PCC5_DC_NANO_SWRST 13 + +#endif /*DT_BINDING_RESET_IMX8ULP_H */ diff --git a/include/dt-bindings/reset/k210-rst.h b/include/dt-bindings/reset/k210-rst.h new file mode 100644 index 000000000000..883c1aed50e8 --- /dev/null +++ b/include/dt-bindings/reset/k210-rst.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 Sean Anderson <seanga2@gmail.com> + * Copyright (c) 2020 Western Digital Corporation or its affiliates. + */ +#ifndef RESET_K210_SYSCTL_H +#define RESET_K210_SYSCTL_H + +/* + * Kendryte K210 SoC system controller K210_SYSCTL_SOFT_RESET register bits. + * Taken from Kendryte SDK (kendryte-standalone-sdk). + */ +#define K210_RST_ROM 0 +#define K210_RST_DMA 1 +#define K210_RST_AI 2 +#define K210_RST_DVP 3 +#define K210_RST_FFT 4 +#define K210_RST_GPIO 5 +#define K210_RST_SPI0 6 +#define K210_RST_SPI1 7 +#define K210_RST_SPI2 8 +#define K210_RST_SPI3 9 +#define K210_RST_I2S0 10 +#define K210_RST_I2S1 11 +#define K210_RST_I2S2 12 +#define K210_RST_I2C0 13 +#define K210_RST_I2C1 14 +#define K210_RST_I2C2 15 +#define K210_RST_UART1 16 +#define K210_RST_UART2 17 +#define K210_RST_UART3 18 +#define K210_RST_AES 19 +#define K210_RST_FPIOA 20 +#define K210_RST_TIMER0 21 +#define K210_RST_TIMER1 22 +#define K210_RST_TIMER2 23 +#define K210_RST_WDT0 24 +#define K210_RST_WDT1 25 +#define K210_RST_SHA 26 +#define K210_RST_RTC 29 + +#endif /* RESET_K210_SYSCTL_H */ diff --git a/include/dt-bindings/reset/mediatek,mt6795-resets.h b/include/dt-bindings/reset/mediatek,mt6795-resets.h new file mode 100644 index 000000000000..5464a4a79a70 --- /dev/null +++ b/include/dt-bindings/reset/mediatek,mt6795-resets.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) */ +/* + * Copyright (c) 2022 Collabora Ltd. + * Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> + */ + +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT6795 +#define _DT_BINDINGS_RESET_CONTROLLER_MT6795 + +/* INFRACFG resets */ +#define MT6795_INFRA_RST0_SCPSYS_RST 0 +#define MT6795_INFRA_RST0_PMIC_WRAP_RST 1 +#define MT6795_INFRA_RST1_MIPI_DSI_RST 2 +#define MT6795_INFRA_RST1_MIPI_CSI_RST 3 +#define MT6795_INFRA_RST1_MM_IOMMU_RST 4 + +/* MMSYS resets */ +#define MT6795_MMSYS_SW0_RST_B_SMI_COMMON 0 +#define MT6795_MMSYS_SW0_RST_B_SMI_LARB 1 +#define MT6795_MMSYS_SW0_RST_B_CAM_MDP 2 +#define MT6795_MMSYS_SW0_RST_B_MDP_RDMA0 3 +#define MT6795_MMSYS_SW0_RST_B_MDP_RDMA1 4 +#define MT6795_MMSYS_SW0_RST_B_MDP_RSZ0 5 +#define MT6795_MMSYS_SW0_RST_B_MDP_RSZ1 6 +#define MT6795_MMSYS_SW0_RST_B_MDP_RSZ2 7 +#define MT6795_MMSYS_SW0_RST_B_MDP_TDSHP0 8 +#define MT6795_MMSYS_SW0_RST_B_MDP_TDSHP1 9 +#define MT6795_MMSYS_SW0_RST_B_MDP_WDMA 10 +#define MT6795_MMSYS_SW0_RST_B_MDP_WROT0 11 +#define MT6795_MMSYS_SW0_RST_B_MDP_WROT1 12 +#define MT6795_MMSYS_SW0_RST_B_MDP_CROP 13 + +/* PERICFG resets */ +#define MT6795_PERI_NFI_SW_RST 0 +#define MT6795_PERI_THERM_SW_RST 1 +#define MT6795_PERI_MSDC1_SW_RST 2 + +/* TOPRGU resets */ +#define MT6795_TOPRGU_INFRA_SW_RST 0 +#define MT6795_TOPRGU_MM_SW_RST 1 +#define MT6795_TOPRGU_MFG_SW_RST 2 +#define MT6795_TOPRGU_VENC_SW_RST 3 +#define MT6795_TOPRGU_VDEC_SW_RST 4 +#define MT6795_TOPRGU_IMG_SW_RST 5 +#define MT6795_TOPRGU_DDRPHY_SW_RST 6 +#define MT6795_TOPRGU_MD_SW_RST 7 +#define MT6795_TOPRGU_INFRA_AO_SW_RST 8 +#define MT6795_TOPRGU_MD_LITE_SW_RST 9 +#define MT6795_TOPRGU_APMIXED_SW_RST 10 +#define MT6795_TOPRGU_PWRAP_SPI_CTL_RST 11 +#define MT6795_TOPRGU_SW_RST_NUM 12 + +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT6795 */ diff --git a/include/dt-bindings/reset-controller/mt2712-resets.h b/include/dt-bindings/reset/mt2712-resets.h index 9e7ee762f076..9e7ee762f076 100644 --- a/include/dt-bindings/reset-controller/mt2712-resets.h +++ b/include/dt-bindings/reset/mt2712-resets.h diff --git a/include/dt-bindings/reset/mt7621-reset.h b/include/dt-bindings/reset/mt7621-reset.h new file mode 100644 index 000000000000..7572c6b41453 --- /dev/null +++ b/include/dt-bindings/reset/mt7621-reset.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2021 Sergio Paracuellos + * Author: Sergio Paracuellos <sergio.paracuellos@gmail.com> + */ + +#ifndef DT_BINDING_MT7621_RESET_H +#define DT_BINDING_MT7621_RESET_H + +#define MT7621_RST_SYS 0 +#define MT7621_RST_MCM 2 +#define MT7621_RST_HSDMA 5 +#define MT7621_RST_FE 6 +#define MT7621_RST_SPDIFTX 7 +#define MT7621_RST_TIMER 8 +#define MT7621_RST_INT 9 +#define MT7621_RST_MC 10 +#define MT7621_RST_PCM 11 +#define MT7621_RST_PIO 13 +#define MT7621_RST_GDMA 14 +#define MT7621_RST_NFI 15 +#define MT7621_RST_I2C 16 +#define MT7621_RST_I2S 17 +#define MT7621_RST_SPI 18 +#define MT7621_RST_UART1 19 +#define MT7621_RST_UART2 20 +#define MT7621_RST_UART3 21 +#define MT7621_RST_ETH 23 +#define MT7621_RST_PCIE0 24 +#define MT7621_RST_PCIE1 25 +#define MT7621_RST_PCIE2 26 +#define MT7621_RST_AUX_STCK 28 +#define MT7621_RST_CRYPTO 29 +#define MT7621_RST_SDXC 30 +#define MT7621_RST_PPE 31 + +#endif /* DT_BINDING_MT7621_RESET_H */ diff --git a/include/dt-bindings/reset/mt7986-resets.h b/include/dt-bindings/reset/mt7986-resets.h new file mode 100644 index 000000000000..af3d16c81192 --- /dev/null +++ b/include/dt-bindings/reset/mt7986-resets.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Sam Shih <sam.shih@mediatek.com> + */ + +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7986 +#define _DT_BINDINGS_RESET_CONTROLLER_MT7986 + +/* INFRACFG resets */ +#define MT7986_INFRACFG_PEXTP_MAC_SW_RST 6 +#define MT7986_INFRACFG_SSUSB_SW_RST 7 +#define MT7986_INFRACFG_EIP97_SW_RST 8 +#define MT7986_INFRACFG_AUDIO_SW_RST 13 +#define MT7986_INFRACFG_CQ_DMA_SW_RST 14 + +#define MT7986_INFRACFG_TRNG_SW_RST 17 +#define MT7986_INFRACFG_AP_DMA_SW_RST 32 +#define MT7986_INFRACFG_I2C_SW_RST 33 +#define MT7986_INFRACFG_NFI_SW_RST 34 +#define MT7986_INFRACFG_SPI0_SW_RST 35 +#define MT7986_INFRACFG_SPI1_SW_RST 36 +#define MT7986_INFRACFG_UART0_SW_RST 37 +#define MT7986_INFRACFG_UART1_SW_RST 38 +#define MT7986_INFRACFG_UART2_SW_RST 39 +#define MT7986_INFRACFG_AUXADC_SW_RST 43 + +#define MT7986_INFRACFG_APXGPT_SW_RST 66 +#define MT7986_INFRACFG_PWM_SW_RST 68 + +#define MT7986_INFRACFG_SW_RST_NUM 69 + +/* TOPRGU resets */ +#define MT7986_TOPRGU_APMIXEDSYS_SW_RST 0 +#define MT7986_TOPRGU_SGMII0_SW_RST 1 +#define MT7986_TOPRGU_SGMII1_SW_RST 2 +#define MT7986_TOPRGU_INFRA_SW_RST 3 +#define MT7986_TOPRGU_U2PHY_SW_RST 5 +#define MT7986_TOPRGU_PCIE_SW_RST 6 +#define MT7986_TOPRGU_SSUSB_SW_RST 7 +#define MT7986_TOPRGU_ETHDMA_SW_RST 20 +#define MT7986_TOPRGU_CONSYS_SW_RST 23 + +#define MT7986_TOPRGU_SW_RST_NUM 24 + +/* ETHSYS Subsystem resets */ +#define MT7986_ETHSYS_FE_SW_RST 6 +#define MT7986_ETHSYS_PMTR_SW_RST 8 +#define MT7986_ETHSYS_GMAC_SW_RST 23 +#define MT7986_ETHSYS_PPE0_SW_RST 30 +#define MT7986_ETHSYS_PPE1_SW_RST 31 + +#define MT7986_ETHSYS_SW_RST_NUM 32 + +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7986 */ diff --git a/include/dt-bindings/reset/mt8173-resets.h b/include/dt-bindings/reset/mt8173-resets.h index ba8636eda5ae..6a60c7cecc4c 100644 --- a/include/dt-bindings/reset/mt8173-resets.h +++ b/include/dt-bindings/reset/mt8173-resets.h @@ -27,6 +27,8 @@ #define MT8173_INFRA_GCE_FAXI_RST 40 #define MT8173_INFRA_MMIOMMURST 47 +/* MMSYS resets */ +#define MT8173_MMSYS_SW0_RST_B_DISP_DSI0 25 /* PERICFG resets */ #define MT8173_PERI_UART0_SW_RST 0 diff --git a/include/dt-bindings/reset-controller/mt8183-resets.h b/include/dt-bindings/reset/mt8183-resets.h index a1bbd41e0d12..48c5d2de0a38 100644 --- a/include/dt-bindings/reset-controller/mt8183-resets.h +++ b/include/dt-bindings/reset/mt8183-resets.h @@ -80,6 +80,9 @@ #define MT8183_INFRACFG_SW_RST_NUM 128 +/* MMSYS resets */ +#define MT8183_MMSYS_SW0_RST_B_DISP_DSI0 25 + #define MT8183_TOPRGU_MM_SW_RST 1 #define MT8183_TOPRGU_MFG_SW_RST 2 #define MT8183_TOPRGU_VENC_SW_RST 3 diff --git a/include/dt-bindings/reset/mt8186-resets.h b/include/dt-bindings/reset/mt8186-resets.h new file mode 100644 index 000000000000..2e9029c22f38 --- /dev/null +++ b/include/dt-bindings/reset/mt8186-resets.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Runyang Chen <runyang.chen@mediatek.com> + */ + +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8186 +#define _DT_BINDINGS_RESET_CONTROLLER_MT8186 + +/* TOPRGU resets */ +#define MT8186_TOPRGU_INFRA_SW_RST 0 +#define MT8186_TOPRGU_MM_SW_RST 1 +#define MT8186_TOPRGU_MFG_SW_RST 2 +#define MT8186_TOPRGU_VENC_SW_RST 3 +#define MT8186_TOPRGU_VDEC_SW_RST 4 +#define MT8186_TOPRGU_IMG_SW_RST 5 +#define MT8186_TOPRGU_DDR_SW_RST 6 +#define MT8186_TOPRGU_INFRA_AO_SW_RST 8 +#define MT8186_TOPRGU_CONNSYS_SW_RST 9 +#define MT8186_TOPRGU_APMIXED_SW_RST 10 +#define MT8186_TOPRGU_PWRAP_SW_RST 11 +#define MT8186_TOPRGU_CONN_MCU_SW_RST 12 +#define MT8186_TOPRGU_IPNNA_SW_RST 13 +#define MT8186_TOPRGU_WPE_SW_RST 14 +#define MT8186_TOPRGU_ADSP_SW_RST 15 +#define MT8186_TOPRGU_AUDIO_SW_RST 17 +#define MT8186_TOPRGU_CAM_MAIN_SW_RST 18 +#define MT8186_TOPRGU_CAM_RAWA_SW_RST 19 +#define MT8186_TOPRGU_CAM_RAWB_SW_RST 20 +#define MT8186_TOPRGU_IPE_SW_RST 21 +#define MT8186_TOPRGU_IMG2_SW_RST 22 +#define MT8186_TOPRGU_SW_RST_NUM 23 + +/* MMSYS resets */ +#define MT8186_MMSYS_SW0_RST_B_DISP_DSI0 19 + +/* INFRA resets */ +#define MT8186_INFRA_THERMAL_CTRL_RST 0 +#define MT8186_INFRA_PTP_CTRL_RST 1 + +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8186 */ diff --git a/include/dt-bindings/reset/mt8192-resets.h b/include/dt-bindings/reset/mt8192-resets.h new file mode 100644 index 000000000000..12e2087c90a3 --- /dev/null +++ b/include/dt-bindings/reset/mt8192-resets.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 MediaTek Inc. + * Author: Yong Liang <yong.liang@mediatek.com> + */ + +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8192 +#define _DT_BINDINGS_RESET_CONTROLLER_MT8192 + +/* TOPRGU resets */ +#define MT8192_TOPRGU_MM_SW_RST 1 +#define MT8192_TOPRGU_MFG_SW_RST 2 +#define MT8192_TOPRGU_VENC_SW_RST 3 +#define MT8192_TOPRGU_VDEC_SW_RST 4 +#define MT8192_TOPRGU_IMG_SW_RST 5 +#define MT8192_TOPRGU_MD_SW_RST 7 +#define MT8192_TOPRGU_CONN_SW_RST 9 +#define MT8192_TOPRGU_CONN_MCU_SW_RST 12 +#define MT8192_TOPRGU_IPU0_SW_RST 14 +#define MT8192_TOPRGU_IPU1_SW_RST 15 +#define MT8192_TOPRGU_AUDIO_SW_RST 17 +#define MT8192_TOPRGU_CAMSYS_SW_RST 18 +#define MT8192_TOPRGU_MJC_SW_RST 19 +#define MT8192_TOPRGU_C2K_S2_SW_RST 20 +#define MT8192_TOPRGU_C2K_SW_RST 21 +#define MT8192_TOPRGU_PERI_SW_RST 22 +#define MT8192_TOPRGU_PERI_AO_SW_RST 23 + +#define MT8192_TOPRGU_SW_RST_NUM 23 + +/* MMSYS resets */ +#define MT8192_MMSYS_SW0_RST_B_DISP_DSI0 15 + +/* INFRA resets */ +#define MT8192_INFRA_RST0_THERM_CTRL_SWRST 0 +#define MT8192_INFRA_RST2_PEXTP_PHY_SWRST 1 +#define MT8192_INFRA_RST3_THERM_CTRL_PTP_SWRST 2 +#define MT8192_INFRA_RST4_PCIE_TOP_SWRST 3 +#define MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST 4 + +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */ diff --git a/include/dt-bindings/reset/mt8195-resets.h b/include/dt-bindings/reset/mt8195-resets.h new file mode 100644 index 000000000000..24ab3631dcea --- /dev/null +++ b/include/dt-bindings/reset/mt8195-resets.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)*/ +/* + * Copyright (c) 2021 MediaTek Inc. + * Author: Christine Zhu <christine.zhu@mediatek.com> + */ + +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8195 +#define _DT_BINDINGS_RESET_CONTROLLER_MT8195 + +/* TOPRGU resets */ +#define MT8195_TOPRGU_CONN_MCU_SW_RST 0 +#define MT8195_TOPRGU_INFRA_GRST_SW_RST 1 +#define MT8195_TOPRGU_APU_SW_RST 2 +#define MT8195_TOPRGU_INFRA_AO_GRST_SW_RST 6 +#define MT8195_TOPRGU_MMSYS_SW_RST 7 +#define MT8195_TOPRGU_MFG_SW_RST 8 +#define MT8195_TOPRGU_VENC_SW_RST 9 +#define MT8195_TOPRGU_VDEC_SW_RST 10 +#define MT8195_TOPRGU_IMG_SW_RST 11 +#define MT8195_TOPRGU_APMIXEDSYS_SW_RST 13 +#define MT8195_TOPRGU_AUDIO_SW_RST 14 +#define MT8195_TOPRGU_CAMSYS_SW_RST 15 +#define MT8195_TOPRGU_EDPTX_SW_RST 16 +#define MT8195_TOPRGU_ADSPSYS_SW_RST 21 +#define MT8195_TOPRGU_DPTX_SW_RST 22 +#define MT8195_TOPRGU_SPMI_MST_SW_RST 23 + +#define MT8195_TOPRGU_SW_RST_NUM 16 + +/* INFRA resets */ +#define MT8195_INFRA_RST0_THERM_CTRL_SWRST 0 +#define MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST 1 +#define MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST 2 +#define MT8195_INFRA_RST2_PCIE_P0_SWRST 3 +#define MT8195_INFRA_RST2_PCIE_P1_SWRST 4 +#define MT8195_INFRA_RST2_USBSIF_P1_SWRST 5 + +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */ diff --git a/include/dt-bindings/reset/qcom,gcc-ipq806x.h b/include/dt-bindings/reset/qcom,gcc-ipq806x.h index 26b6f9200620..020c9cf18751 100644 --- a/include/dt-bindings/reset/qcom,gcc-ipq806x.h +++ b/include/dt-bindings/reset/qcom,gcc-ipq806x.h @@ -163,5 +163,10 @@ #define NSS_CAL_PRBS_RST_N_RESET 154 #define NSS_LCKDT_RST_N_RESET 155 #define NSS_SRDS_N_RESET 156 +#define CRYPTO_ENG1_RESET 157 +#define CRYPTO_ENG2_RESET 158 +#define CRYPTO_ENG3_RESET 159 +#define CRYPTO_ENG4_RESET 160 +#define CRYPTO_AHB_RESET 161 #endif diff --git a/include/dt-bindings/reset/qcom,gcc-msm8939.h b/include/dt-bindings/reset/qcom,gcc-msm8939.h new file mode 100644 index 000000000000..fa41ffeae7a2 --- /dev/null +++ b/include/dt-bindings/reset/qcom,gcc-msm8939.h @@ -0,0 +1,110 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2020 Linaro Limited + */ + +#ifndef _DT_BINDINGS_RESET_MSM_GCC_8939_H +#define _DT_BINDINGS_RESET_MSM_GCC_8939_H + +#define GCC_BLSP1_BCR 0 +#define GCC_BLSP1_QUP1_BCR 1 +#define GCC_BLSP1_UART1_BCR 2 +#define GCC_BLSP1_QUP2_BCR 3 +#define GCC_BLSP1_UART2_BCR 4 +#define GCC_BLSP1_QUP3_BCR 5 +#define GCC_BLSP1_QUP4_BCR 6 +#define GCC_BLSP1_QUP5_BCR 7 +#define GCC_BLSP1_QUP6_BCR 8 +#define GCC_IMEM_BCR 9 +#define GCC_SMMU_BCR 10 +#define GCC_APSS_TCU_BCR 11 +#define GCC_SMMU_XPU_BCR 12 +#define GCC_PCNOC_TBU_BCR 13 +#define GCC_PRNG_BCR 14 +#define GCC_BOOT_ROM_BCR 15 +#define GCC_CRYPTO_BCR 16 +#define GCC_SEC_CTRL_BCR 17 +#define GCC_AUDIO_CORE_BCR 18 +#define GCC_ULT_AUDIO_BCR 19 +#define GCC_DEHR_BCR 20 +#define GCC_SYSTEM_NOC_BCR 21 +#define GCC_PCNOC_BCR 22 +#define GCC_TCSR_BCR 23 +#define GCC_QDSS_BCR 24 +#define GCC_DCD_BCR 25 +#define GCC_MSG_RAM_BCR 26 +#define GCC_MPM_BCR 27 +#define GCC_SPMI_BCR 28 +#define GCC_SPDM_BCR 29 +#define GCC_MM_SPDM_BCR 30 +#define GCC_BIMC_BCR 31 +#define GCC_RBCPR_BCR 32 +#define GCC_TLMM_BCR 33 +#define GCC_USB_HS_BCR 34 +#define GCC_USB2A_PHY_BCR 35 +#define GCC_SDCC1_BCR 36 +#define GCC_SDCC2_BCR 37 +#define GCC_PDM_BCR 38 +#define GCC_SNOC_BUS_TIMEOUT0_BCR 39 +#define GCC_PCNOC_BUS_TIMEOUT0_BCR 40 +#define GCC_PCNOC_BUS_TIMEOUT1_BCR 41 +#define GCC_PCNOC_BUS_TIMEOUT2_BCR 42 +#define GCC_PCNOC_BUS_TIMEOUT3_BCR 43 +#define GCC_PCNOC_BUS_TIMEOUT4_BCR 44 +#define GCC_PCNOC_BUS_TIMEOUT5_BCR 45 +#define GCC_PCNOC_BUS_TIMEOUT6_BCR 46 +#define GCC_PCNOC_BUS_TIMEOUT7_BCR 47 +#define GCC_PCNOC_BUS_TIMEOUT8_BCR 48 +#define GCC_PCNOC_BUS_TIMEOUT9_BCR 49 +#define GCC_MMSS_BCR 50 +#define GCC_VENUS0_BCR 51 +#define GCC_MDSS_BCR 52 +#define GCC_CAMSS_PHY0_BCR 53 +#define GCC_CAMSS_CSI0_BCR 54 +#define GCC_CAMSS_CSI0PHY_BCR 55 +#define GCC_CAMSS_CSI0RDI_BCR 56 +#define GCC_CAMSS_CSI0PIX_BCR 57 +#define GCC_CAMSS_PHY1_BCR 58 +#define GCC_CAMSS_CSI1_BCR 59 +#define GCC_CAMSS_CSI1PHY_BCR 60 +#define GCC_CAMSS_CSI1RDI_BCR 61 +#define GCC_CAMSS_CSI1PIX_BCR 62 +#define GCC_CAMSS_ISPIF_BCR 63 +#define GCC_CAMSS_CCI_BCR 64 +#define GCC_CAMSS_MCLK0_BCR 65 +#define GCC_CAMSS_MCLK1_BCR 66 +#define GCC_CAMSS_GP0_BCR 67 +#define GCC_CAMSS_GP1_BCR 68 +#define GCC_CAMSS_TOP_BCR 69 +#define GCC_CAMSS_MICRO_BCR 70 +#define GCC_CAMSS_JPEG_BCR 71 +#define GCC_CAMSS_VFE_BCR 72 +#define GCC_CAMSS_CSI_VFE0_BCR 73 +#define GCC_OXILI_BCR 74 +#define GCC_GMEM_BCR 75 +#define GCC_CAMSS_AHB_BCR 76 +#define GCC_MDP_TBU_BCR 77 +#define GCC_GFX_TBU_BCR 78 +#define GCC_GFX_TCU_BCR 79 +#define GCC_MSS_TBU_AXI_BCR 80 +#define GCC_MSS_TBU_GSS_AXI_BCR 81 +#define GCC_MSS_TBU_Q6_AXI_BCR 82 +#define GCC_GTCU_AHB_BCR 83 +#define GCC_SMMU_CFG_BCR 84 +#define GCC_VFE_TBU_BCR 85 +#define GCC_VENUS_TBU_BCR 86 +#define GCC_JPEG_TBU_BCR 87 +#define GCC_PRONTO_TBU_BCR 88 +#define GCC_SMMU_CATS_BCR 89 +#define GCC_BLSP1_UART3_BCR 90 +#define GCC_CAMSS_CSI2_BCR 91 +#define GCC_CAMSS_CSI2PHY_BCR 92 +#define GCC_CAMSS_CSI2RDI_BCR 93 +#define GCC_CAMSS_CSI2PIX_BCR 94 +#define GCC_USB_FS_BCR 95 +#define GCC_BLSP1_QUP4_SPI_APPS_CBCR 96 +#define GCC_CAMSS_MCLK2_BCR 97 +#define GCC_CPP_TBU_BCR 98 +#define GCC_MDP_RT_TBU_BCR 99 + +#endif diff --git a/include/dt-bindings/reset/qcom,sdm845-pdc.h b/include/dt-bindings/reset/qcom,sdm845-pdc.h index 53c37f9c319a..03a0c0eb8147 100644 --- a/include/dt-bindings/reset/qcom,sdm845-pdc.h +++ b/include/dt-bindings/reset/qcom,sdm845-pdc.h @@ -16,5 +16,7 @@ #define PDC_DISPLAY_SYNC_RESET 7 #define PDC_COMPUTE_SYNC_RESET 8 #define PDC_MODEM_SYNC_RESET 9 +#define PDC_WLAN_RF_SYNC_RESET 10 +#define PDC_WPSS_SYNC_RESET 11 #endif diff --git a/include/dt-bindings/reset/raspberrypi,firmware-reset.h b/include/dt-bindings/reset/raspberrypi,firmware-reset.h new file mode 100644 index 000000000000..1a4f4c792723 --- /dev/null +++ b/include/dt-bindings/reset/raspberrypi,firmware-reset.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 Nicolas Saenz Julienne + * Author: Nicolas Saenz Julienne <nsaenzjulienne@suse.com> + */ + +#ifndef _DT_BINDINGS_RASPBERRYPI_FIRMWARE_RESET_H +#define _DT_BINDINGS_RASPBERRYPI_FIRMWARE_RESET_H + +#define RASPBERRYPI_FIRMWARE_RESET_ID_USB 0 +#define RASPBERRYPI_FIRMWARE_RESET_NUM_IDS 1 + +#endif diff --git a/include/dt-bindings/reset/realtek,rtd1195.h b/include/dt-bindings/reset/realtek,rtd1195.h new file mode 100644 index 000000000000..27902abf935b --- /dev/null +++ b/include/dt-bindings/reset/realtek,rtd1195.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */ +/* + * Realtek RTD1195 reset controllers + * + * Copyright (c) 2017 Andreas Färber + */ +#ifndef DT_BINDINGS_RESET_RTD1195_H +#define DT_BINDINGS_RESET_RTD1195_H + +/* soft reset 1 */ +#define RTD1195_RSTN_MISC 0 +#define RTD1195_RSTN_RNG 1 +#define RTD1195_RSTN_USB3_POW 2 +#define RTD1195_RSTN_GSPI 3 +#define RTD1195_RSTN_USB3_P0_MDIO 4 +#define RTD1195_RSTN_VE_H265 5 +#define RTD1195_RSTN_USB 6 +#define RTD1195_RSTN_USB_PHY0 8 +#define RTD1195_RSTN_USB_PHY1 9 +#define RTD1195_RSTN_HDMIRX 11 +#define RTD1195_RSTN_HDMI 12 +#define RTD1195_RSTN_ETN 14 +#define RTD1195_RSTN_AIO 15 +#define RTD1195_RSTN_GPU 16 +#define RTD1195_RSTN_VE_H264 17 +#define RTD1195_RSTN_VE_JPEG 18 +#define RTD1195_RSTN_TVE 19 +#define RTD1195_RSTN_VO 20 +#define RTD1195_RSTN_LVDS 21 +#define RTD1195_RSTN_SE 22 +#define RTD1195_RSTN_DCU 23 +#define RTD1195_RSTN_DC_PHY 24 +#define RTD1195_RSTN_CP 25 +#define RTD1195_RSTN_MD 26 +#define RTD1195_RSTN_TP 27 +#define RTD1195_RSTN_AE 28 +#define RTD1195_RSTN_NF 29 +#define RTD1195_RSTN_MIPI 30 + +/* soft reset 2 */ +#define RTD1195_RSTN_ACPU 0 +#define RTD1195_RSTN_VCPU 1 +#define RTD1195_RSTN_PCR 9 +#define RTD1195_RSTN_CR 10 +#define RTD1195_RSTN_EMMC 11 +#define RTD1195_RSTN_SDIO 12 +#define RTD1195_RSTN_I2C_5 18 +#define RTD1195_RSTN_RTC 20 +#define RTD1195_RSTN_I2C_4 23 +#define RTD1195_RSTN_I2C_3 24 +#define RTD1195_RSTN_I2C_2 25 +#define RTD1195_RSTN_I2C_1 26 +#define RTD1195_RSTN_UR1 28 + +/* soft reset 3 */ +#define RTD1195_RSTN_SB2 0 + +/* iso soft reset */ +#define RTD1195_ISO_RSTN_VFD 0 +#define RTD1195_ISO_RSTN_IR 1 +#define RTD1195_ISO_RSTN_CEC0 2 +#define RTD1195_ISO_RSTN_CEC1 3 +#define RTD1195_ISO_RSTN_DP 4 +#define RTD1195_ISO_RSTN_CBUSTX 5 +#define RTD1195_ISO_RSTN_CBUSRX 6 +#define RTD1195_ISO_RSTN_EFUSE 7 +#define RTD1195_ISO_RSTN_UR0 8 +#define RTD1195_ISO_RSTN_GMAC 9 +#define RTD1195_ISO_RSTN_GPHY 10 +#define RTD1195_ISO_RSTN_I2C_0 11 +#define RTD1195_ISO_RSTN_I2C_6 12 +#define RTD1195_ISO_RSTN_CBUS 13 + +#endif diff --git a/include/dt-bindings/reset/realtek,rtd1295.h b/include/dt-bindings/reset/realtek,rtd1295.h index 2c0cb6afe816..dd89e4c80264 100644 --- a/include/dt-bindings/reset/realtek,rtd1295.h +++ b/include/dt-bindings/reset/realtek,rtd1295.h @@ -75,6 +75,9 @@ #define RTD1295_RSTN_CBUS_TX 30 #define RTD1295_RSTN_SDS_PHY 31 +/* soft reset 3 */ +#define RTD1295_RSTN_SB2 0 + /* soft reset 4 */ #define RTD1295_RSTN_DCPHY_CRT 0 #define RTD1295_RSTN_DCPHY_ALERT_RX 1 diff --git a/include/dt-bindings/reset/sama7g5-reset.h b/include/dt-bindings/reset/sama7g5-reset.h new file mode 100644 index 000000000000..2116f41d04e0 --- /dev/null +++ b/include/dt-bindings/reset/sama7g5-reset.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef __DT_BINDINGS_RESET_SAMA7G5_H +#define __DT_BINDINGS_RESET_SAMA7G5_H + +#define SAMA7G5_RESET_USB_PHY1 4 +#define SAMA7G5_RESET_USB_PHY2 5 +#define SAMA7G5_RESET_USB_PHY3 6 + +#endif /* __DT_BINDINGS_RESET_SAMA7G5_H */ diff --git a/include/dt-bindings/reset/starfive-jh7100.h b/include/dt-bindings/reset/starfive-jh7100.h new file mode 100644 index 000000000000..540e19254f39 --- /dev/null +++ b/include/dt-bindings/reset/starfive-jh7100.h @@ -0,0 +1,126 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Copyright (C) 2021 Ahmad Fatoum, Pengutronix + */ + +#ifndef __DT_BINDINGS_RESET_STARFIVE_JH7100_H__ +#define __DT_BINDINGS_RESET_STARFIVE_JH7100_H__ + +#define JH7100_RSTN_DOM3AHB_BUS 0 +#define JH7100_RSTN_DOM7AHB_BUS 1 +#define JH7100_RST_U74 2 +#define JH7100_RSTN_U74_AXI 3 +#define JH7100_RSTN_SGDMA2P_AHB 4 +#define JH7100_RSTN_SGDMA2P_AXI 5 +#define JH7100_RSTN_DMA2PNOC_AXI 6 +#define JH7100_RSTN_DLA_AXI 7 +#define JH7100_RSTN_DLANOC_AXI 8 +#define JH7100_RSTN_DLA_APB 9 +#define JH7100_RST_VP6_DRESET 10 +#define JH7100_RST_VP6_BRESET 11 +#define JH7100_RSTN_VP6_AXI 12 +#define JH7100_RSTN_VDECBRG_MAIN 13 +#define JH7100_RSTN_VDEC_AXI 14 +#define JH7100_RSTN_VDEC_BCLK 15 +#define JH7100_RSTN_VDEC_CCLK 16 +#define JH7100_RSTN_VDEC_APB 17 +#define JH7100_RSTN_JPEG_AXI 18 +#define JH7100_RSTN_JPEG_CCLK 19 +#define JH7100_RSTN_JPEG_APB 20 +#define JH7100_RSTN_JPCGC300_MAIN 21 +#define JH7100_RSTN_GC300_2X 22 +#define JH7100_RSTN_GC300_AXI 23 +#define JH7100_RSTN_GC300_AHB 24 +#define JH7100_RSTN_VENC_AXI 25 +#define JH7100_RSTN_VENCBRG_MAIN 26 +#define JH7100_RSTN_VENC_BCLK 27 +#define JH7100_RSTN_VENC_CCLK 28 +#define JH7100_RSTN_VENC_APB 29 +#define JH7100_RSTN_DDRPHY_APB 30 +#define JH7100_RSTN_NOC_ROB 31 +#define JH7100_RSTN_NOC_COG 32 +#define JH7100_RSTN_HIFI4_AXI 33 +#define JH7100_RSTN_HIFI4NOC_AXI 34 +#define JH7100_RST_HIFI4_DRESET 35 +#define JH7100_RST_HIFI4_BRESET 36 +#define JH7100_RSTN_USB_AXI 37 +#define JH7100_RSTN_USBNOC_AXI 38 +#define JH7100_RSTN_SGDMA1P_AXI 39 +#define JH7100_RSTN_DMA1P_AXI 40 +#define JH7100_RSTN_X2C_AXI 41 +#define JH7100_RSTN_NNE_AHB 42 +#define JH7100_RSTN_NNE_AXI 43 +#define JH7100_RSTN_NNENOC_AXI 44 +#define JH7100_RSTN_DLASLV_AXI 45 +#define JH7100_RSTN_DSPX2C_AXI 46 +#define JH7100_RSTN_VIN_SRC 47 +#define JH7100_RSTN_ISPSLV_AXI 48 +#define JH7100_RSTN_VIN_AXI 49 +#define JH7100_RSTN_VINNOC_AXI 50 +#define JH7100_RSTN_ISP0_AXI 51 +#define JH7100_RSTN_ISP0NOC_AXI 52 +#define JH7100_RSTN_ISP1_AXI 53 +#define JH7100_RSTN_ISP1NOC_AXI 54 +#define JH7100_RSTN_VOUT_SRC 55 +#define JH7100_RSTN_DISP_AXI 56 +#define JH7100_RSTN_DISPNOC_AXI 57 +#define JH7100_RSTN_SDIO0_AHB 58 +#define JH7100_RSTN_SDIO1_AHB 59 +#define JH7100_RSTN_GMAC_AHB 60 +#define JH7100_RSTN_SPI2AHB_AHB 61 +#define JH7100_RSTN_SPI2AHB_CORE 62 +#define JH7100_RSTN_EZMASTER_AHB 63 +#define JH7100_RST_E24 64 +#define JH7100_RSTN_QSPI_AHB 65 +#define JH7100_RSTN_QSPI_CORE 66 +#define JH7100_RSTN_QSPI_APB 67 +#define JH7100_RSTN_SEC_AHB 68 +#define JH7100_RSTN_AES 69 +#define JH7100_RSTN_PKA 70 +#define JH7100_RSTN_SHA 71 +#define JH7100_RSTN_TRNG_APB 72 +#define JH7100_RSTN_OTP_APB 73 +#define JH7100_RSTN_UART0_APB 74 +#define JH7100_RSTN_UART0_CORE 75 +#define JH7100_RSTN_UART1_APB 76 +#define JH7100_RSTN_UART1_CORE 77 +#define JH7100_RSTN_SPI0_APB 78 +#define JH7100_RSTN_SPI0_CORE 79 +#define JH7100_RSTN_SPI1_APB 80 +#define JH7100_RSTN_SPI1_CORE 81 +#define JH7100_RSTN_I2C0_APB 82 +#define JH7100_RSTN_I2C0_CORE 83 +#define JH7100_RSTN_I2C1_APB 84 +#define JH7100_RSTN_I2C1_CORE 85 +#define JH7100_RSTN_GPIO_APB 86 +#define JH7100_RSTN_UART2_APB 87 +#define JH7100_RSTN_UART2_CORE 88 +#define JH7100_RSTN_UART3_APB 89 +#define JH7100_RSTN_UART3_CORE 90 +#define JH7100_RSTN_SPI2_APB 91 +#define JH7100_RSTN_SPI2_CORE 92 +#define JH7100_RSTN_SPI3_APB 93 +#define JH7100_RSTN_SPI3_CORE 94 +#define JH7100_RSTN_I2C2_APB 95 +#define JH7100_RSTN_I2C2_CORE 96 +#define JH7100_RSTN_I2C3_APB 97 +#define JH7100_RSTN_I2C3_CORE 98 +#define JH7100_RSTN_WDTIMER_APB 99 +#define JH7100_RSTN_WDT 100 +#define JH7100_RSTN_TIMER0 101 +#define JH7100_RSTN_TIMER1 102 +#define JH7100_RSTN_TIMER2 103 +#define JH7100_RSTN_TIMER3 104 +#define JH7100_RSTN_TIMER4 105 +#define JH7100_RSTN_TIMER5 106 +#define JH7100_RSTN_TIMER6 107 +#define JH7100_RSTN_VP6INTC_APB 108 +#define JH7100_RSTN_PWM_APB 109 +#define JH7100_RSTN_MSI_APB 110 +#define JH7100_RSTN_TEMP_APB 111 +#define JH7100_RSTN_TEMP_SENSE 112 +#define JH7100_RSTN_SYSERR_APB 113 + +#define JH7100_RSTN_END 114 + +#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7100_H__ */ diff --git a/include/dt-bindings/reset/stericsson,db8500-prcc-reset.h b/include/dt-bindings/reset/stericsson,db8500-prcc-reset.h new file mode 100644 index 000000000000..ea906896c70f --- /dev/null +++ b/include/dt-bindings/reset/stericsson,db8500-prcc-reset.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef _DT_BINDINGS_STE_PRCC_RESET +#define _DT_BINDINGS_STE_PRCC_RESET + +#define DB8500_PRCC_1 1 +#define DB8500_PRCC_2 2 +#define DB8500_PRCC_3 3 +#define DB8500_PRCC_6 6 + +/* Reset lines on PRCC 1 */ +#define DB8500_PRCC_1_RESET_UART0 0 +#define DB8500_PRCC_1_RESET_UART1 1 +#define DB8500_PRCC_1_RESET_I2C1 2 +#define DB8500_PRCC_1_RESET_MSP0 3 +#define DB8500_PRCC_1_RESET_MSP1 4 +#define DB8500_PRCC_1_RESET_SDI0 5 +#define DB8500_PRCC_1_RESET_I2C2 6 +#define DB8500_PRCC_1_RESET_SPI3 7 +#define DB8500_PRCC_1_RESET_SLIMBUS0 8 +#define DB8500_PRCC_1_RESET_I2C4 9 +#define DB8500_PRCC_1_RESET_MSP3 10 +#define DB8500_PRCC_1_RESET_PER_MSP3 11 +#define DB8500_PRCC_1_RESET_PER_MSP1 12 +#define DB8500_PRCC_1_RESET_PER_MSP0 13 +#define DB8500_PRCC_1_RESET_PER_SLIMBUS 14 + +/* Reset lines on PRCC 2 */ +#define DB8500_PRCC_2_RESET_I2C3 0 +#define DB8500_PRCC_2_RESET_PWL 1 +#define DB8500_PRCC_2_RESET_SDI4 2 +#define DB8500_PRCC_2_RESET_MSP2 3 +#define DB8500_PRCC_2_RESET_SDI1 4 +#define DB8500_PRCC_2_RESET_SDI3 5 +#define DB8500_PRCC_2_RESET_HSIRX 6 +#define DB8500_PRCC_2_RESET_HSITX 7 +#define DB8500_PRCC_1_RESET_PER_MSP2 8 + +/* Reset lines on PRCC 3 */ +#define DB8500_PRCC_3_RESET_SSP0 1 +#define DB8500_PRCC_3_RESET_SSP1 2 +#define DB8500_PRCC_3_RESET_I2C0 3 +#define DB8500_PRCC_3_RESET_SDI2 4 +#define DB8500_PRCC_3_RESET_SKE 5 +#define DB8500_PRCC_3_RESET_UART2 6 +#define DB8500_PRCC_3_RESET_SDI5 7 + +/* Reset lines on PRCC 6 */ +#define DB8500_PRCC_3_RESET_RNG 0 + +#endif diff --git a/include/dt-bindings/reset/stm32mp1-resets.h b/include/dt-bindings/reset/stm32mp1-resets.h index f0c3aaef67a0..4ffa7c3612e6 100644 --- a/include/dt-bindings/reset/stm32mp1-resets.h +++ b/include/dt-bindings/reset/stm32mp1-resets.h @@ -7,6 +7,7 @@ #ifndef _DT_BINDINGS_STM32MP1_RESET_H_ #define _DT_BINDINGS_STM32MP1_RESET_H_ +#define MCU_HOLD_BOOT_R 2144 #define LTDC_R 3072 #define DSI_R 3076 #define DDRPERFM_R 3080 @@ -105,4 +106,18 @@ #define GPIOJ_R 19785 #define GPIOK_R 19786 +/* SCMI reset domain identifiers */ +#define RST_SCMI_SPI6 0 +#define RST_SCMI_I2C4 1 +#define RST_SCMI_I2C6 2 +#define RST_SCMI_USART1 3 +#define RST_SCMI_STGEN 4 +#define RST_SCMI_GPIOZ 5 +#define RST_SCMI_CRYP1 6 +#define RST_SCMI_HASH1 7 +#define RST_SCMI_RNG1 8 +#define RST_SCMI_MDMA 9 +#define RST_SCMI_MCU 10 +#define RST_SCMI_MCU_HOLD_BOOT 11 + #endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */ diff --git a/include/dt-bindings/reset/stm32mp13-resets.h b/include/dt-bindings/reset/stm32mp13-resets.h new file mode 100644 index 000000000000..934864e90da6 --- /dev/null +++ b/include/dt-bindings/reset/stm32mp13-resets.h @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ +/* + * Copyright (C) STMicroelectronics 2018 - All Rights Reserved + * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics. + */ + +#ifndef _DT_BINDINGS_STM32MP13_RESET_H_ +#define _DT_BINDINGS_STM32MP13_RESET_H_ + +#define TIM2_R 13568 +#define TIM3_R 13569 +#define TIM4_R 13570 +#define TIM5_R 13571 +#define TIM6_R 13572 +#define TIM7_R 13573 +#define LPTIM1_R 13577 +#define SPI2_R 13579 +#define SPI3_R 13580 +#define USART3_R 13583 +#define UART4_R 13584 +#define UART5_R 13585 +#define UART7_R 13586 +#define UART8_R 13587 +#define I2C1_R 13589 +#define I2C2_R 13590 +#define SPDIF_R 13594 +#define TIM1_R 13632 +#define TIM8_R 13633 +#define SPI1_R 13640 +#define USART6_R 13645 +#define SAI1_R 13648 +#define SAI2_R 13649 +#define DFSDM_R 13652 +#define FDCAN_R 13656 +#define LPTIM2_R 13696 +#define LPTIM3_R 13697 +#define LPTIM4_R 13698 +#define LPTIM5_R 13699 +#define SYSCFG_R 13707 +#define VREF_R 13709 +#define DTS_R 13712 +#define PMBCTRL_R 13713 +#define LTDC_R 13760 +#define DCMIPP_R 13761 +#define DDRPERFM_R 13768 +#define USBPHY_R 13776 +#define STGEN_R 13844 +#define USART1_R 13888 +#define USART2_R 13889 +#define SPI4_R 13890 +#define SPI5_R 13891 +#define I2C3_R 13892 +#define I2C4_R 13893 +#define I2C5_R 13894 +#define TIM12_R 13895 +#define TIM13_R 13896 +#define TIM14_R 13897 +#define TIM15_R 13898 +#define TIM16_R 13899 +#define TIM17_R 13900 +#define DMA1_R 13952 +#define DMA2_R 13953 +#define DMAMUX1_R 13954 +#define DMA3_R 13955 +#define DMAMUX2_R 13956 +#define ADC1_R 13957 +#define ADC2_R 13958 +#define USBO_R 13960 +#define GPIOA_R 14080 +#define GPIOB_R 14081 +#define GPIOC_R 14082 +#define GPIOD_R 14083 +#define GPIOE_R 14084 +#define GPIOF_R 14085 +#define GPIOG_R 14086 +#define GPIOH_R 14087 +#define GPIOI_R 14088 +#define TSC_R 14095 +#define PKA_R 14146 +#define SAES_R 14147 +#define CRYP1_R 14148 +#define HASH1_R 14149 +#define RNG1_R 14150 +#define AXIMC_R 14160 +#define MDMA_R 14208 +#define MCE_R 14209 +#define ETH1MAC_R 14218 +#define FMC_R 14220 +#define QSPI_R 14222 +#define SDMMC1_R 14224 +#define SDMMC2_R 14225 +#define CRC1_R 14228 +#define USBH_R 14232 +#define ETH2MAC_R 14238 + +/* SCMI reset domain identifiers */ +#define RST_SCMI_LTDC 0 +#define RST_SCMI_MDMA 1 + +#endif /* _DT_BINDINGS_STM32MP13_RESET_H_ */ diff --git a/include/dt-bindings/reset/sun20i-d1-ccu.h b/include/dt-bindings/reset/sun20i-d1-ccu.h new file mode 100644 index 000000000000..de9ff5203239 --- /dev/null +++ b/include/dt-bindings/reset/sun20i-d1-ccu.h @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* + * Copyright (c) 2020 huangzhenwei@allwinnertech.com + * Copyright (C) 2021 Samuel Holland <samuel@sholland.org> + */ + +#ifndef _DT_BINDINGS_RST_SUN20I_D1_CCU_H_ +#define _DT_BINDINGS_RST_SUN20I_D1_CCU_H_ + +#define RST_MBUS 0 +#define RST_BUS_DE 1 +#define RST_BUS_DI 2 +#define RST_BUS_G2D 3 +#define RST_BUS_CE 4 +#define RST_BUS_VE 5 +#define RST_BUS_DMA 6 +#define RST_BUS_MSGBOX0 7 +#define RST_BUS_MSGBOX1 8 +#define RST_BUS_MSGBOX2 9 +#define RST_BUS_SPINLOCK 10 +#define RST_BUS_HSTIMER 11 +#define RST_BUS_DBG 12 +#define RST_BUS_PWM 13 +#define RST_BUS_DRAM 14 +#define RST_BUS_MMC0 15 +#define RST_BUS_MMC1 16 +#define RST_BUS_MMC2 17 +#define RST_BUS_UART0 18 +#define RST_BUS_UART1 19 +#define RST_BUS_UART2 20 +#define RST_BUS_UART3 21 +#define RST_BUS_UART4 22 +#define RST_BUS_UART5 23 +#define RST_BUS_I2C0 24 +#define RST_BUS_I2C1 25 +#define RST_BUS_I2C2 26 +#define RST_BUS_I2C3 27 +#define RST_BUS_SPI0 28 +#define RST_BUS_SPI1 29 +#define RST_BUS_EMAC 30 +#define RST_BUS_IR_TX 31 +#define RST_BUS_GPADC 32 +#define RST_BUS_THS 33 +#define RST_BUS_I2S0 34 +#define RST_BUS_I2S1 35 +#define RST_BUS_I2S2 36 +#define RST_BUS_SPDIF 37 +#define RST_BUS_DMIC 38 +#define RST_BUS_AUDIO 39 +#define RST_USB_PHY0 40 +#define RST_USB_PHY1 41 +#define RST_BUS_OHCI0 42 +#define RST_BUS_OHCI1 43 +#define RST_BUS_EHCI0 44 +#define RST_BUS_EHCI1 45 +#define RST_BUS_OTG 46 +#define RST_BUS_LRADC 47 +#define RST_BUS_DPSS_TOP 48 +#define RST_BUS_HDMI_SUB 49 +#define RST_BUS_HDMI_MAIN 50 +#define RST_BUS_MIPI_DSI 51 +#define RST_BUS_TCON_LCD0 52 +#define RST_BUS_TCON_TV 53 +#define RST_BUS_LVDS0 54 +#define RST_BUS_TVE 55 +#define RST_BUS_TVE_TOP 56 +#define RST_BUS_TVD 57 +#define RST_BUS_TVD_TOP 58 +#define RST_BUS_LEDC 59 +#define RST_BUS_CSI 60 +#define RST_BUS_TPADC 61 +#define RST_DSP 62 +#define RST_BUS_DSP_CFG 63 +#define RST_BUS_DSP_DBG 64 +#define RST_BUS_RISCV_CFG 65 + +#endif /* _DT_BINDINGS_RST_SUN20I_D1_CCU_H_ */ diff --git a/include/dt-bindings/reset/sun20i-d1-r-ccu.h b/include/dt-bindings/reset/sun20i-d1-r-ccu.h new file mode 100644 index 000000000000..d93d6423d283 --- /dev/null +++ b/include/dt-bindings/reset/sun20i-d1-r-ccu.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* + * Copyright (C) 2021 Samuel Holland <samuel@sholland.org> + */ + +#ifndef _DT_BINDINGS_RST_SUN20I_D1_R_CCU_H_ +#define _DT_BINDINGS_RST_SUN20I_D1_R_CCU_H_ + +#define RST_BUS_R_TIMER 0 +#define RST_BUS_R_TWD 1 +#define RST_BUS_R_PPU 2 +#define RST_BUS_R_IR_RX 3 +#define RST_BUS_R_RTC 4 +#define RST_BUS_R_CPUCFG 5 + +#endif /* _DT_BINDINGS_RST_SUN20I_D1_R_CCU_H_ */ diff --git a/include/dt-bindings/reset/sun50i-a100-ccu.h b/include/dt-bindings/reset/sun50i-a100-ccu.h new file mode 100644 index 000000000000..55c0ada99885 --- /dev/null +++ b/include/dt-bindings/reset/sun50i-a100-ccu.h @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* + * Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com> + */ + +#ifndef _DT_BINDINGS_RESET_SUN50I_A100_H_ +#define _DT_BINDINGS_RESET_SUN50I_A100_H_ + +#define RST_MBUS 0 +#define RST_BUS_DE 1 +#define RST_BUS_G2D 2 +#define RST_BUS_GPU 3 +#define RST_BUS_CE 4 +#define RST_BUS_VE 5 +#define RST_BUS_DMA 6 +#define RST_BUS_MSGBOX 7 +#define RST_BUS_SPINLOCK 8 +#define RST_BUS_HSTIMER 9 +#define RST_BUS_DBG 10 +#define RST_BUS_PSI 11 +#define RST_BUS_PWM 12 +#define RST_BUS_DRAM 13 +#define RST_BUS_NAND 14 +#define RST_BUS_MMC0 15 +#define RST_BUS_MMC1 16 +#define RST_BUS_MMC2 17 +#define RST_BUS_UART0 18 +#define RST_BUS_UART1 19 +#define RST_BUS_UART2 20 +#define RST_BUS_UART3 21 +#define RST_BUS_UART4 22 +#define RST_BUS_I2C0 23 +#define RST_BUS_I2C1 24 +#define RST_BUS_I2C2 25 +#define RST_BUS_I2C3 26 +#define RST_BUS_SPI0 27 +#define RST_BUS_SPI1 28 +#define RST_BUS_SPI2 29 +#define RST_BUS_EMAC 30 +#define RST_BUS_IR_RX 31 +#define RST_BUS_IR_TX 32 +#define RST_BUS_GPADC 33 +#define RST_BUS_THS 34 +#define RST_BUS_I2S0 35 +#define RST_BUS_I2S1 36 +#define RST_BUS_I2S2 37 +#define RST_BUS_I2S3 38 +#define RST_BUS_SPDIF 39 +#define RST_BUS_DMIC 40 +#define RST_BUS_AUDIO_CODEC 41 +#define RST_USB_PHY0 42 +#define RST_USB_PHY1 43 +#define RST_BUS_OHCI0 44 +#define RST_BUS_OHCI1 45 +#define RST_BUS_EHCI0 46 +#define RST_BUS_EHCI1 47 +#define RST_BUS_OTG 48 +#define RST_BUS_LRADC 49 +#define RST_BUS_DPSS_TOP0 50 +#define RST_BUS_DPSS_TOP1 51 +#define RST_BUS_MIPI_DSI 52 +#define RST_BUS_TCON_LCD 53 +#define RST_BUS_LVDS 54 +#define RST_BUS_LEDC 55 +#define RST_BUS_CSI 56 +#define RST_BUS_CSI_ISP 57 + +#endif /* _DT_BINDINGS_RESET_SUN50I_A100_H_ */ diff --git a/include/dt-bindings/reset/sun50i-a100-r-ccu.h b/include/dt-bindings/reset/sun50i-a100-r-ccu.h new file mode 100644 index 000000000000..737bf6f66626 --- /dev/null +++ b/include/dt-bindings/reset/sun50i-a100-r-ccu.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* + * Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com> + */ + +#ifndef _DT_BINDINGS_RST_SUN50I_A100_R_CCU_H_ +#define _DT_BINDINGS_RST_SUN50I_A100_R_CCU_H_ + +#define RST_R_APB1_TIMER 0 +#define RST_R_APB1_BUS_PWM 1 +#define RST_R_APB1_PPU 2 +#define RST_R_APB2_UART 3 +#define RST_R_APB2_I2C0 4 +#define RST_R_APB2_I2C1 5 +#define RST_R_APB1_BUS_IR 6 +#define RST_R_AHB_BUS_RTC 7 + +#endif /* _DT_BINDINGS_RST_SUN50I_A100_R_CCU_H_ */ diff --git a/include/dt-bindings/reset/sun50i-h6-r-ccu.h b/include/dt-bindings/reset/sun50i-h6-r-ccu.h index 01c84dba49a4..7950e799c76d 100644 --- a/include/dt-bindings/reset/sun50i-h6-r-ccu.h +++ b/include/dt-bindings/reset/sun50i-h6-r-ccu.h @@ -13,5 +13,6 @@ #define RST_R_APB2_I2C 4 #define RST_R_APB1_IR 5 #define RST_R_APB1_W1 6 +#define RST_R_APB2_RSB 7 #endif /* _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_ */ diff --git a/include/dt-bindings/reset/sun50i-h616-ccu.h b/include/dt-bindings/reset/sun50i-h616-ccu.h new file mode 100644 index 000000000000..cb6285a8d128 --- /dev/null +++ b/include/dt-bindings/reset/sun50i-h616-ccu.h @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* + * Copyright (C) 2020 Arm Ltd. + */ + +#ifndef _DT_BINDINGS_RESET_SUN50I_H616_H_ +#define _DT_BINDINGS_RESET_SUN50I_H616_H_ + +#define RST_MBUS 0 +#define RST_BUS_DE 1 +#define RST_BUS_DEINTERLACE 2 +#define RST_BUS_GPU 3 +#define RST_BUS_CE 4 +#define RST_BUS_VE 5 +#define RST_BUS_DMA 6 +#define RST_BUS_HSTIMER 7 +#define RST_BUS_DBG 8 +#define RST_BUS_PSI 9 +#define RST_BUS_PWM 10 +#define RST_BUS_IOMMU 11 +#define RST_BUS_DRAM 12 +#define RST_BUS_NAND 13 +#define RST_BUS_MMC0 14 +#define RST_BUS_MMC1 15 +#define RST_BUS_MMC2 16 +#define RST_BUS_UART0 17 +#define RST_BUS_UART1 18 +#define RST_BUS_UART2 19 +#define RST_BUS_UART3 20 +#define RST_BUS_UART4 21 +#define RST_BUS_UART5 22 +#define RST_BUS_I2C0 23 +#define RST_BUS_I2C1 24 +#define RST_BUS_I2C2 25 +#define RST_BUS_I2C3 26 +#define RST_BUS_I2C4 27 +#define RST_BUS_SPI0 28 +#define RST_BUS_SPI1 29 +#define RST_BUS_EMAC0 30 +#define RST_BUS_EMAC1 31 +#define RST_BUS_TS 32 +#define RST_BUS_THS 33 +#define RST_BUS_SPDIF 34 +#define RST_BUS_DMIC 35 +#define RST_BUS_AUDIO_CODEC 36 +#define RST_BUS_AUDIO_HUB 37 +#define RST_USB_PHY0 38 +#define RST_USB_PHY1 39 +#define RST_USB_PHY2 40 +#define RST_USB_PHY3 41 +#define RST_BUS_OHCI0 42 +#define RST_BUS_OHCI1 43 +#define RST_BUS_OHCI2 44 +#define RST_BUS_OHCI3 45 +#define RST_BUS_EHCI0 46 +#define RST_BUS_EHCI1 47 +#define RST_BUS_EHCI2 48 +#define RST_BUS_EHCI3 49 +#define RST_BUS_OTG 50 +#define RST_BUS_HDMI 51 +#define RST_BUS_HDMI_SUB 52 +#define RST_BUS_TCON_TOP 53 +#define RST_BUS_TCON_TV0 54 +#define RST_BUS_TCON_TV1 55 +#define RST_BUS_TVE_TOP 56 +#define RST_BUS_TVE0 57 +#define RST_BUS_HDCP 58 +#define RST_BUS_KEYADC 59 + +#endif /* _DT_BINDINGS_RESET_SUN50I_H616_H_ */ diff --git a/include/dt-bindings/reset/sunplus,sp7021-reset.h b/include/dt-bindings/reset/sunplus,sp7021-reset.h new file mode 100644 index 000000000000..ab486707387f --- /dev/null +++ b/include/dt-bindings/reset/sunplus,sp7021-reset.h @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) Sunplus Technology Co., Ltd. + * All rights reserved. + */ +#ifndef _DT_BINDINGS_RST_SUNPLUS_SP7021_H +#define _DT_BINDINGS_RST_SUNPLUS_SP7021_H + +#define RST_SYSTEM 0 +#define RST_RTC 1 +#define RST_IOCTL 2 +#define RST_IOP 3 +#define RST_OTPRX 4 +#define RST_NOC 5 +#define RST_BR 6 +#define RST_RBUS_L00 7 +#define RST_SPIFL 8 +#define RST_SDCTRL0 9 +#define RST_PERI0 10 +#define RST_A926 11 +#define RST_UMCTL2 12 +#define RST_PERI1 13 +#define RST_DDR_PHY0 14 +#define RST_ACHIP 15 +#define RST_STC0 16 +#define RST_STC_AV0 17 +#define RST_STC_AV1 18 +#define RST_STC_AV2 19 +#define RST_UA0 20 +#define RST_UA1 21 +#define RST_UA2 22 +#define RST_UA3 23 +#define RST_UA4 24 +#define RST_HWUA 25 +#define RST_DDC0 26 +#define RST_UADMA 27 +#define RST_CBDMA0 28 +#define RST_CBDMA1 29 +#define RST_SPI_COMBO_0 30 +#define RST_SPI_COMBO_1 31 +#define RST_SPI_COMBO_2 32 +#define RST_SPI_COMBO_3 33 +#define RST_AUD 34 +#define RST_USBC0 35 +#define RST_USBC1 36 +#define RST_UPHY0 37 +#define RST_UPHY1 38 +#define RST_I2CM0 39 +#define RST_I2CM1 40 +#define RST_I2CM2 41 +#define RST_I2CM3 42 +#define RST_PMC 43 +#define RST_CARD_CTL0 44 +#define RST_CARD_CTL1 45 +#define RST_CARD_CTL4 46 +#define RST_BCH 47 +#define RST_DDFCH 48 +#define RST_CSIIW0 49 +#define RST_CSIIW1 50 +#define RST_MIPICSI0 51 +#define RST_MIPICSI1 52 +#define RST_HDMI_TX 53 +#define RST_VPOST 54 +#define RST_TGEN 55 +#define RST_DMIX 56 +#define RST_TCON 57 +#define RST_INTERRUPT 58 +#define RST_RGST 59 +#define RST_GPIO 60 +#define RST_RBUS_TOP 61 +#define RST_MAILBOX 62 +#define RST_SPIND 63 +#define RST_I2C2CBUS 64 +#define RST_SEC 65 +#define RST_DVE 66 +#define RST_GPOST0 67 +#define RST_OSD0 68 +#define RST_DISP_PWM 69 +#define RST_UADBG 70 +#define RST_DUMMY_MASTER 71 +#define RST_FIO_CTL 72 +#define RST_FPGA 73 +#define RST_L2SW 74 +#define RST_ICM 75 +#define RST_AXI_GLOBAL 76 + +#endif diff --git a/include/dt-bindings/reset/tegra234-reset.h b/include/dt-bindings/reset/tegra234-reset.h new file mode 100644 index 000000000000..d48d22b2bc7f --- /dev/null +++ b/include/dt-bindings/reset/tegra234-reset.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */ + +#ifndef DT_BINDINGS_RESET_TEGRA234_RESET_H +#define DT_BINDINGS_RESET_TEGRA234_RESET_H + +/** + * @file + * @defgroup bpmp_reset_ids Reset ID's + * @brief Identifiers for Resets controllable by firmware + * @{ + */ +#define TEGRA234_RESET_PEX1_CORE_6 11U +#define TEGRA234_RESET_PEX1_CORE_6_APB 12U +#define TEGRA234_RESET_PEX1_COMMON_APB 13U +#define TEGRA234_RESET_PEX2_CORE_7 14U +#define TEGRA234_RESET_PEX2_CORE_7_APB 15U +#define TEGRA234_RESET_GPCDMA 18U +#define TEGRA234_RESET_HDA 20U +#define TEGRA234_RESET_HDACODEC 21U +#define TEGRA234_RESET_I2C1 24U +#define TEGRA234_RESET_PEX2_CORE_8 25U +#define TEGRA234_RESET_PEX2_CORE_8_APB 26U +#define TEGRA234_RESET_PEX2_CORE_9 27U +#define TEGRA234_RESET_PEX2_CORE_9_APB 28U +#define TEGRA234_RESET_I2C2 29U +#define TEGRA234_RESET_I2C3 30U +#define TEGRA234_RESET_I2C4 31U +#define TEGRA234_RESET_I2C6 32U +#define TEGRA234_RESET_I2C7 33U +#define TEGRA234_RESET_I2C8 34U +#define TEGRA234_RESET_I2C9 35U +#define TEGRA234_RESET_MGBE0_PCS 45U +#define TEGRA234_RESET_MGBE0_MAC 46U +#define TEGRA234_RESET_MGBE1_PCS 49U +#define TEGRA234_RESET_MGBE1_MAC 50U +#define TEGRA234_RESET_MGBE2_PCS 53U +#define TEGRA234_RESET_MGBE2_MAC 54U +#define TEGRA234_RESET_PEX2_CORE_10 56U +#define TEGRA234_RESET_PEX2_CORE_10_APB 57U +#define TEGRA234_RESET_PEX2_COMMON_APB 58U +#define TEGRA234_RESET_PWM1 68U +#define TEGRA234_RESET_PWM2 69U +#define TEGRA234_RESET_PWM3 70U +#define TEGRA234_RESET_PWM4 71U +#define TEGRA234_RESET_PWM5 72U +#define TEGRA234_RESET_PWM6 73U +#define TEGRA234_RESET_PWM7 74U +#define TEGRA234_RESET_PWM8 75U +#define TEGRA234_RESET_QSPI0 76U +#define TEGRA234_RESET_QSPI1 77U +#define TEGRA234_RESET_SDMMC4 85U +#define TEGRA234_RESET_MGBE3_PCS 87U +#define TEGRA234_RESET_MGBE3_MAC 88U +#define TEGRA234_RESET_UARTA 100U +#define TEGRA234_RESET_VIC 113U +#define TEGRA234_RESET_PEX0_CORE_0 116U +#define TEGRA234_RESET_PEX0_CORE_1 117U +#define TEGRA234_RESET_PEX0_CORE_2 118U +#define TEGRA234_RESET_PEX0_CORE_3 119U +#define TEGRA234_RESET_PEX0_CORE_4 120U +#define TEGRA234_RESET_PEX0_CORE_0_APB 121U +#define TEGRA234_RESET_PEX0_CORE_1_APB 122U +#define TEGRA234_RESET_PEX0_CORE_2_APB 123U +#define TEGRA234_RESET_PEX0_CORE_3_APB 124U +#define TEGRA234_RESET_PEX0_CORE_4_APB 125U +#define TEGRA234_RESET_PEX0_COMMON_APB 126U +#define TEGRA234_RESET_PEX1_CORE_5 129U +#define TEGRA234_RESET_PEX1_CORE_5_APB 130U + +/** @} */ + +#endif diff --git a/include/dt-bindings/reset/ti-syscon.h b/include/dt-bindings/reset/ti-syscon.h index 6d696d2d1508..eacc0f18083e 100644 --- a/include/dt-bindings/reset/ti-syscon.h +++ b/include/dt-bindings/reset/ti-syscon.h @@ -2,7 +2,7 @@ /* * TI Syscon Reset definitions * - * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef __DT_BINDINGS_RESET_TI_SYSCON_H__ diff --git a/include/dt-bindings/reset/toshiba,tmpv770x.h b/include/dt-bindings/reset/toshiba,tmpv770x.h new file mode 100644 index 000000000000..c1007acb1941 --- /dev/null +++ b/include/dt-bindings/reset/toshiba,tmpv770x.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_RESET_TOSHIBA_TMPV770X_H_ +#define _DT_BINDINGS_RESET_TOSHIBA_TMPV770X_H_ + +/* Reset */ +#define TMPV770X_RESET_PIETHER_2P5M 0 +#define TMPV770X_RESET_PIETHER_25M 1 +#define TMPV770X_RESET_PIETHER_50M 2 +#define TMPV770X_RESET_PIETHER_125M 3 +#define TMPV770X_RESET_HOX 4 +#define TMPV770X_RESET_PCIE_MSTR 5 +#define TMPV770X_RESET_PCIE_AUX 6 +#define TMPV770X_RESET_PIINTC 7 +#define TMPV770X_RESET_PIETHER_BUS 8 +#define TMPV770X_RESET_PISPI0 9 +#define TMPV770X_RESET_PISPI1 10 +#define TMPV770X_RESET_PISPI2 11 +#define TMPV770X_RESET_PISPI3 12 +#define TMPV770X_RESET_PISPI4 13 +#define TMPV770X_RESET_PISPI5 14 +#define TMPV770X_RESET_PISPI6 15 +#define TMPV770X_RESET_PIUART0 16 +#define TMPV770X_RESET_PIUART1 17 +#define TMPV770X_RESET_PIUART2 18 +#define TMPV770X_RESET_PIUART3 19 +#define TMPV770X_RESET_PII2C0 20 +#define TMPV770X_RESET_PII2C1 21 +#define TMPV770X_RESET_PII2C2 22 +#define TMPV770X_RESET_PII2C3 23 +#define TMPV770X_RESET_PII2C4 24 +#define TMPV770X_RESET_PII2C5 25 +#define TMPV770X_RESET_PII2C6 26 +#define TMPV770X_RESET_PII2C7 27 +#define TMPV770X_RESET_PII2C8 28 +#define TMPV770X_RESET_PIPCMIF 29 +#define TMPV770X_RESET_PICKMON 30 +#define TMPV770X_RESET_SBUSCLK 31 +#define TMPV770X_NR_RESET 32 + +#endif /*_DT_BINDINGS_RESET_TOSHIBA_TMPV770X_H_ */ diff --git a/include/dt-bindings/reset/xlnx-versal-resets.h b/include/dt-bindings/reset/xlnx-versal-resets.h new file mode 100644 index 000000000000..895424e9b0e5 --- /dev/null +++ b/include/dt-bindings/reset/xlnx-versal-resets.h @@ -0,0 +1,105 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 Xilinx, Inc. + */ + +#ifndef _DT_BINDINGS_VERSAL_RESETS_H +#define _DT_BINDINGS_VERSAL_RESETS_H + +#define VERSAL_RST_PMC_POR (0xc30c001U) +#define VERSAL_RST_PMC (0xc410002U) +#define VERSAL_RST_PS_POR (0xc30c003U) +#define VERSAL_RST_PL_POR (0xc30c004U) +#define VERSAL_RST_NOC_POR (0xc30c005U) +#define VERSAL_RST_FPD_POR (0xc30c006U) +#define VERSAL_RST_ACPU_0_POR (0xc30c007U) +#define VERSAL_RST_ACPU_1_POR (0xc30c008U) +#define VERSAL_RST_OCM2_POR (0xc30c009U) +#define VERSAL_RST_PS_SRST (0xc41000aU) +#define VERSAL_RST_PL_SRST (0xc41000bU) +#define VERSAL_RST_NOC (0xc41000cU) +#define VERSAL_RST_NPI (0xc41000dU) +#define VERSAL_RST_SYS_RST_1 (0xc41000eU) +#define VERSAL_RST_SYS_RST_2 (0xc41000fU) +#define VERSAL_RST_SYS_RST_3 (0xc410010U) +#define VERSAL_RST_FPD (0xc410011U) +#define VERSAL_RST_PL0 (0xc410012U) +#define VERSAL_RST_PL1 (0xc410013U) +#define VERSAL_RST_PL2 (0xc410014U) +#define VERSAL_RST_PL3 (0xc410015U) +#define VERSAL_RST_APU (0xc410016U) +#define VERSAL_RST_ACPU_0 (0xc410017U) +#define VERSAL_RST_ACPU_1 (0xc410018U) +#define VERSAL_RST_ACPU_L2 (0xc410019U) +#define VERSAL_RST_ACPU_GIC (0xc41001aU) +#define VERSAL_RST_RPU_ISLAND (0xc41001bU) +#define VERSAL_RST_RPU_AMBA (0xc41001cU) +#define VERSAL_RST_R5_0 (0xc41001dU) +#define VERSAL_RST_R5_1 (0xc41001eU) +#define VERSAL_RST_SYSMON_PMC_SEQ_RST (0xc41001fU) +#define VERSAL_RST_SYSMON_PMC_CFG_RST (0xc410020U) +#define VERSAL_RST_SYSMON_FPD_CFG_RST (0xc410021U) +#define VERSAL_RST_SYSMON_FPD_SEQ_RST (0xc410022U) +#define VERSAL_RST_SYSMON_LPD (0xc410023U) +#define VERSAL_RST_PDMA_RST1 (0xc410024U) +#define VERSAL_RST_PDMA_RST0 (0xc410025U) +#define VERSAL_RST_ADMA (0xc410026U) +#define VERSAL_RST_TIMESTAMP (0xc410027U) +#define VERSAL_RST_OCM (0xc410028U) +#define VERSAL_RST_OCM2_RST (0xc410029U) +#define VERSAL_RST_IPI (0xc41002aU) +#define VERSAL_RST_SBI (0xc41002bU) +#define VERSAL_RST_LPD (0xc41002cU) +#define VERSAL_RST_QSPI (0xc10402dU) +#define VERSAL_RST_OSPI (0xc10402eU) +#define VERSAL_RST_SDIO_0 (0xc10402fU) +#define VERSAL_RST_SDIO_1 (0xc104030U) +#define VERSAL_RST_I2C_PMC (0xc104031U) +#define VERSAL_RST_GPIO_PMC (0xc104032U) +#define VERSAL_RST_GEM_0 (0xc104033U) +#define VERSAL_RST_GEM_1 (0xc104034U) +#define VERSAL_RST_SPARE (0xc104035U) +#define VERSAL_RST_USB_0 (0xc104036U) +#define VERSAL_RST_UART_0 (0xc104037U) +#define VERSAL_RST_UART_1 (0xc104038U) +#define VERSAL_RST_SPI_0 (0xc104039U) +#define VERSAL_RST_SPI_1 (0xc10403aU) +#define VERSAL_RST_CAN_FD_0 (0xc10403bU) +#define VERSAL_RST_CAN_FD_1 (0xc10403cU) +#define VERSAL_RST_I2C_0 (0xc10403dU) +#define VERSAL_RST_I2C_1 (0xc10403eU) +#define VERSAL_RST_GPIO_LPD (0xc10403fU) +#define VERSAL_RST_TTC_0 (0xc104040U) +#define VERSAL_RST_TTC_1 (0xc104041U) +#define VERSAL_RST_TTC_2 (0xc104042U) +#define VERSAL_RST_TTC_3 (0xc104043U) +#define VERSAL_RST_SWDT_FPD (0xc104044U) +#define VERSAL_RST_SWDT_LPD (0xc104045U) +#define VERSAL_RST_USB (0xc104046U) +#define VERSAL_RST_DPC (0xc208047U) +#define VERSAL_RST_PMCDBG (0xc208048U) +#define VERSAL_RST_DBG_TRACE (0xc208049U) +#define VERSAL_RST_DBG_FPD (0xc20804aU) +#define VERSAL_RST_DBG_TSTMP (0xc20804bU) +#define VERSAL_RST_RPU0_DBG (0xc20804cU) +#define VERSAL_RST_RPU1_DBG (0xc20804dU) +#define VERSAL_RST_HSDP (0xc20804eU) +#define VERSAL_RST_DBG_LPD (0xc20804fU) +#define VERSAL_RST_CPM_POR (0xc30c050U) +#define VERSAL_RST_CPM (0xc410051U) +#define VERSAL_RST_CPMDBG (0xc208052U) +#define VERSAL_RST_PCIE_CFG (0xc410053U) +#define VERSAL_RST_PCIE_CORE0 (0xc410054U) +#define VERSAL_RST_PCIE_CORE1 (0xc410055U) +#define VERSAL_RST_PCIE_DMA (0xc410056U) +#define VERSAL_RST_CMN (0xc410057U) +#define VERSAL_RST_L2_0 (0xc410058U) +#define VERSAL_RST_L2_1 (0xc410059U) +#define VERSAL_RST_ADDR_REMAP (0xc41005aU) +#define VERSAL_RST_CPI0 (0xc41005bU) +#define VERSAL_RST_CPI1 (0xc41005cU) +#define VERSAL_RST_XRAM (0xc30c05dU) +#define VERSAL_RST_AIE_ARRAY (0xc10405eU) +#define VERSAL_RST_AIE_SHIM (0xc10405fU) + +#endif diff --git a/include/dt-bindings/soc/bcm-pmb.h b/include/dt-bindings/soc/bcm-pmb.h new file mode 100644 index 000000000000..385884468007 --- /dev/null +++ b/include/dt-bindings/soc/bcm-pmb.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later OR MIT */ + +#ifndef __DT_BINDINGS_SOC_BCM_PMB_H +#define __DT_BINDINGS_SOC_BCM_PMB_H + +#define BCM_PMB_PCIE0 0x01 +#define BCM_PMB_PCIE1 0x02 +#define BCM_PMB_PCIE2 0x03 +#define BCM_PMB_HOST_USB 0x04 +#define BCM_PMB_SATA 0x05 + +#endif diff --git a/include/dt-bindings/soc/bcm6318-pm.h b/include/dt-bindings/soc/bcm6318-pm.h new file mode 100644 index 000000000000..05931dce8333 --- /dev/null +++ b/include/dt-bindings/soc/bcm6318-pm.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __DT_BINDINGS_BMIPS_BCM6318_PM_H +#define __DT_BINDINGS_BMIPS_BCM6318_PM_H + +#define BCM6318_POWER_DOMAIN_PCIE 0 +#define BCM6318_POWER_DOMAIN_USB 1 +#define BCM6318_POWER_DOMAIN_EPHY0 2 +#define BCM6318_POWER_DOMAIN_EPHY1 3 +#define BCM6318_POWER_DOMAIN_EPHY2 4 +#define BCM6318_POWER_DOMAIN_EPHY3 5 +#define BCM6318_POWER_DOMAIN_LDO2P5 6 +#define BCM6318_POWER_DOMAIN_LDO2P9 7 +#define BCM6318_POWER_DOMAIN_SW1P0 8 +#define BCM6318_POWER_DOMAIN_PAD 9 + +#endif /* __DT_BINDINGS_BMIPS_BCM6318_PM_H */ diff --git a/include/dt-bindings/soc/bcm63268-pm.h b/include/dt-bindings/soc/bcm63268-pm.h new file mode 100644 index 000000000000..84ded53a732f --- /dev/null +++ b/include/dt-bindings/soc/bcm63268-pm.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __DT_BINDINGS_BMIPS_BCM63268_PM_H +#define __DT_BINDINGS_BMIPS_BCM63268_PM_H + +#define BCM63268_POWER_DOMAIN_SAR 0 +#define BCM63268_POWER_DOMAIN_IPSEC 1 +#define BCM63268_POWER_DOMAIN_MIPS 2 +#define BCM63268_POWER_DOMAIN_DECT 3 +#define BCM63268_POWER_DOMAIN_USBH 4 +#define BCM63268_POWER_DOMAIN_USBD 5 +#define BCM63268_POWER_DOMAIN_ROBOSW 6 +#define BCM63268_POWER_DOMAIN_PCM 7 +#define BCM63268_POWER_DOMAIN_PERIPH 8 +#define BCM63268_POWER_DOMAIN_VDSL_PHY 9 +#define BCM63268_POWER_DOMAIN_VDSL_MIPS 10 +#define BCM63268_POWER_DOMAIN_FAP 11 +#define BCM63268_POWER_DOMAIN_PCIE 12 +#define BCM63268_POWER_DOMAIN_WLAN_PADS 13 + +#endif /* __DT_BINDINGS_BMIPS_BCM63268_PM_H */ diff --git a/include/dt-bindings/soc/bcm6328-pm.h b/include/dt-bindings/soc/bcm6328-pm.h new file mode 100644 index 000000000000..557e1a69b7f7 --- /dev/null +++ b/include/dt-bindings/soc/bcm6328-pm.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __DT_BINDINGS_BMIPS_BCM6328_PM_H +#define __DT_BINDINGS_BMIPS_BCM6328_PM_H + +#define BCM6328_POWER_DOMAIN_ADSL2_MIPS 0 +#define BCM6328_POWER_DOMAIN_ADSL2_PHY 1 +#define BCM6328_POWER_DOMAIN_ADSL2_AFE 2 +#define BCM6328_POWER_DOMAIN_SAR 3 +#define BCM6328_POWER_DOMAIN_PCM 4 +#define BCM6328_POWER_DOMAIN_USBD 5 +#define BCM6328_POWER_DOMAIN_USBH 6 +#define BCM6328_POWER_DOMAIN_PCIE 7 +#define BCM6328_POWER_DOMAIN_ROBOSW 8 +#define BCM6328_POWER_DOMAIN_EPHY 9 + +#endif /* __DT_BINDINGS_BMIPS_BCM6328_PM_H */ diff --git a/include/dt-bindings/soc/bcm6362-pm.h b/include/dt-bindings/soc/bcm6362-pm.h new file mode 100644 index 000000000000..d087ba63c7a1 --- /dev/null +++ b/include/dt-bindings/soc/bcm6362-pm.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __DT_BINDINGS_BMIPS_BCM6362_PM_H +#define __DT_BINDINGS_BMIPS_BCM6362_PM_H + +#define BCM6362_POWER_DOMAIN_SAR 0 +#define BCM6362_POWER_DOMAIN_IPSEC 1 +#define BCM6362_POWER_DOMAIN_MIPS 2 +#define BCM6362_POWER_DOMAIN_DECT 3 +#define BCM6362_POWER_DOMAIN_USBH 4 +#define BCM6362_POWER_DOMAIN_USBD 5 +#define BCM6362_POWER_DOMAIN_ROBOSW 6 +#define BCM6362_POWER_DOMAIN_PCM 7 +#define BCM6362_POWER_DOMAIN_PERIPH 8 +#define BCM6362_POWER_DOMAIN_ADSL_PHY 9 +#define BCM6362_POWER_DOMAIN_GMII_PADS 10 +#define BCM6362_POWER_DOMAIN_FAP 11 +#define BCM6362_POWER_DOMAIN_PCIE 12 +#define BCM6362_POWER_DOMAIN_WLAN_PADS 13 + +#endif /* __DT_BINDINGS_BMIPS_BCM6362_PM_H */ diff --git a/include/dt-bindings/soc/qcom,gpr.h b/include/dt-bindings/soc/qcom,gpr.h new file mode 100644 index 000000000000..3107da59319c --- /dev/null +++ b/include/dt-bindings/soc/qcom,gpr.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ + +#ifndef __DT_BINDINGS_QCOM_GPR_H +#define __DT_BINDINGS_QCOM_GPR_H + +/* DOMAINS */ + +#define GPR_DOMAIN_ID_MODEM 1 +#define GPR_DOMAIN_ID_ADSP 2 +#define GPR_DOMAIN_ID_APPS 3 + +/* Static Services */ + +#define GPR_APM_MODULE_IID 1 +#define GPR_PRM_MODULE_IID 2 +#define GPR_AMDB_MODULE_IID 3 +#define GPR_VCPM_MODULE_IID 4 + +#endif /* __DT_BINDINGS_QCOM_GPR_H */ diff --git a/include/dt-bindings/soc/rockchip,vop2.h b/include/dt-bindings/soc/rockchip,vop2.h new file mode 100644 index 000000000000..6e66a802b96a --- /dev/null +++ b/include/dt-bindings/soc/rockchip,vop2.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ + +#ifndef __DT_BINDINGS_ROCKCHIP_VOP2_H +#define __DT_BINDINGS_ROCKCHIP_VOP2_H + +#define ROCKCHIP_VOP2_EP_RGB0 1 +#define ROCKCHIP_VOP2_EP_HDMI0 2 +#define ROCKCHIP_VOP2_EP_EDP0 3 +#define ROCKCHIP_VOP2_EP_MIPI0 4 +#define ROCKCHIP_VOP2_EP_LVDS0 5 +#define ROCKCHIP_VOP2_EP_MIPI1 6 +#define ROCKCHIP_VOP2_EP_LVDS1 7 + +#endif /* __DT_BINDINGS_ROCKCHIP_VOP2_H */ diff --git a/include/dt-bindings/soc/samsung,boot-mode.h b/include/dt-bindings/soc/samsung,boot-mode.h new file mode 100644 index 000000000000..47ef1cdd3916 --- /dev/null +++ b/include/dt-bindings/soc/samsung,boot-mode.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022 Samsung Electronics Co., Ltd. + * Author: Chanho Park <chanho61.park@samsung.com> + * + * Device Tree bindings for Samsung Boot Mode. + */ + +#ifndef __DT_BINDINGS_SAMSUNG_BOOT_MODE_H +#define __DT_BINDINGS_SAMSUNG_BOOT_MODE_H + +/* Boot mode definitions for Exynos Auto v9 SoC */ + +#define EXYNOSAUTOV9_BOOT_FASTBOOT 0xfa +#define EXYNOSAUTOV9_BOOT_BOOTLOADER 0xfc +#define EXYNOSAUTOV9_BOOT_RECOVERY 0xff + +#endif /* __DT_BINDINGS_SAMSUNG_BOOT_MODE_H */ diff --git a/include/dt-bindings/soc/samsung,exynos-usi.h b/include/dt-bindings/soc/samsung,exynos-usi.h new file mode 100644 index 000000000000..a01af169d249 --- /dev/null +++ b/include/dt-bindings/soc/samsung,exynos-usi.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2021 Linaro Ltd. + * Author: Sam Protsenko <semen.protsenko@linaro.org> + * + * Device Tree bindings for Samsung Exynos USI (Universal Serial Interface). + */ + +#ifndef __DT_BINDINGS_SAMSUNG_EXYNOS_USI_H +#define __DT_BINDINGS_SAMSUNG_EXYNOS_USI_H + +#define USI_V2_NONE 0 +#define USI_V2_UART 1 +#define USI_V2_SPI 2 +#define USI_V2_I2C 3 + +#endif /* __DT_BINDINGS_SAMSUNG_EXYNOS_USI_H */ diff --git a/include/dt-bindings/soc/tegra-pmc.h b/include/dt-bindings/soc/tegra-pmc.h new file mode 100644 index 000000000000..a99a457471ee --- /dev/null +++ b/include/dt-bindings/soc/tegra-pmc.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. + */ + +#ifndef _DT_BINDINGS_SOC_TEGRA_PMC_H +#define _DT_BINDINGS_SOC_TEGRA_PMC_H + +#define TEGRA_PMC_CLK_OUT_1 0 +#define TEGRA_PMC_CLK_OUT_2 1 +#define TEGRA_PMC_CLK_OUT_3 2 +#define TEGRA_PMC_CLK_BLINK 3 + +#define TEGRA_PMC_CLK_MAX 4 + +#endif /* _DT_BINDINGS_SOC_TEGRA_PMC_H */ diff --git a/include/dt-bindings/soc/zte,pm_domains.h b/include/dt-bindings/soc/zte,pm_domains.h deleted file mode 100644 index df044705a5ec..000000000000 --- a/include/dt-bindings/soc/zte,pm_domains.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2017 Linaro Ltd. - * - * Author: Baoyou Xie <baoyou.xie@linaro.org> - */ - -#ifndef _DT_BINDINGS_SOC_ZTE_PM_DOMAINS_H -#define _DT_BINDINGS_SOC_ZTE_PM_DOMAINS_H - -#define DM_ZX296718_SAPPU 0 -#define DM_ZX296718_VDE 1 /* g1v6 */ -#define DM_ZX296718_VCE 2 /* h1v6 */ -#define DM_ZX296718_HDE 3 /* g2v2 */ -#define DM_ZX296718_VIU 4 -#define DM_ZX296718_USB20 5 -#define DM_ZX296718_USB21 6 -#define DM_ZX296718_USB30 7 -#define DM_ZX296718_HSIC 8 -#define DM_ZX296718_GMAC 9 -#define DM_ZX296718_TS 10 -#define DM_ZX296718_VOU 11 - -#endif /* _DT_BINDINGS_SOC_ZTE_PM_DOMAINS_H */ diff --git a/include/dt-bindings/sound/adi,adau1977.h b/include/dt-bindings/sound/adi,adau1977.h new file mode 100644 index 000000000000..8eebec6570f2 --- /dev/null +++ b/include/dt-bindings/sound/adi,adau1977.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef __DT_BINDINGS_ADI_ADAU1977_H__ +#define __DT_BINDINGS_ADI_ADAU1977_H__ + +#define ADAU1977_MICBIAS_5V0 0x0 +#define ADAU1977_MICBIAS_5V5 0x1 +#define ADAU1977_MICBIAS_6V0 0x2 +#define ADAU1977_MICBIAS_6V5 0x3 +#define ADAU1977_MICBIAS_7V0 0x4 +#define ADAU1977_MICBIAS_7V5 0x5 +#define ADAU1977_MICBIAS_8V0 0x6 +#define ADAU1977_MICBIAS_8V5 0x7 +#define ADAU1977_MICBIAS_9V0 0x8 + +#endif /* __DT_BINDINGS_ADI_ADAU1977_H__ */ diff --git a/include/dt-bindings/sound/apq8016-lpass.h b/include/dt-bindings/sound/apq8016-lpass.h index 3c3e16c0aadb..dc605c4bc224 100644 --- a/include/dt-bindings/sound/apq8016-lpass.h +++ b/include/dt-bindings/sound/apq8016-lpass.h @@ -2,9 +2,8 @@ #ifndef __DT_APQ8016_LPASS_H #define __DT_APQ8016_LPASS_H -#define MI2S_PRIMARY 0 -#define MI2S_SECONDARY 1 -#define MI2S_TERTIARY 2 -#define MI2S_QUATERNARY 3 +#include <dt-bindings/sound/qcom,lpass.h> + +/* NOTE: Use qcom,lpass.h to define any AIF ID's for LPASS */ #endif /* __DT_APQ8016_LPASS_H */ diff --git a/include/dt-bindings/sound/cs35l45.h b/include/dt-bindings/sound/cs35l45.h new file mode 100644 index 000000000000..076da4b2c28d --- /dev/null +++ b/include/dt-bindings/sound/cs35l45.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ +/* + * cs35l45.h -- CS35L45 ALSA SoC audio driver DT bindings header + * + * Copyright 2022 Cirrus Logic, Inc. + */ + +#ifndef DT_CS35L45_H +#define DT_CS35L45_H + +/* + * cirrus,asp-sdout-hiz-ctrl + * + * TX_HIZ_UNUSED: TX pin high-impedance during unused slots. + * TX_HIZ_DISABLED: TX pin high-impedance when all channels disabled. + */ +#define CS35L45_ASP_TX_HIZ_UNUSED 0x1 +#define CS35L45_ASP_TX_HIZ_DISABLED 0x2 + +#endif /* DT_CS35L45_H */ diff --git a/include/dt-bindings/sound/meson-aiu.h b/include/dt-bindings/sound/meson-aiu.h new file mode 100644 index 000000000000..1051b8af298b --- /dev/null +++ b/include/dt-bindings/sound/meson-aiu.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_MESON_AIU_H +#define __DT_MESON_AIU_H + +#define AIU_CPU 0 +#define AIU_HDMI 1 +#define AIU_ACODEC 2 + +#define CPU_I2S_FIFO 0 +#define CPU_SPDIF_FIFO 1 +#define CPU_I2S_ENCODER 2 +#define CPU_SPDIF_ENCODER 3 + +#define CTRL_I2S 0 +#define CTRL_PCM 1 +#define CTRL_OUT 2 + +#endif /* __DT_MESON_AIU_H */ diff --git a/include/dt-bindings/sound/meson-g12a-toacodec.h b/include/dt-bindings/sound/meson-g12a-toacodec.h new file mode 100644 index 000000000000..69d7a75592a2 --- /dev/null +++ b/include/dt-bindings/sound/meson-g12a-toacodec.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_MESON_G12A_TOACODEC_H +#define __DT_MESON_G12A_TOACODEC_H + +#define TOACODEC_IN_A 0 +#define TOACODEC_IN_B 1 +#define TOACODEC_IN_C 2 +#define TOACODEC_OUT 3 + +#endif /* __DT_MESON_G12A_TOACODEC_H */ diff --git a/include/dt-bindings/sound/microchip,pdmc.h b/include/dt-bindings/sound/microchip,pdmc.h new file mode 100644 index 000000000000..96cde94ce74f --- /dev/null +++ b/include/dt-bindings/sound/microchip,pdmc.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_MICROCHIP_PDMC_H__ +#define __DT_BINDINGS_MICROCHIP_PDMC_H__ + +/* PDM microphone's pin placement */ +#define MCHP_PDMC_DS0 0 +#define MCHP_PDMC_DS1 1 + +/* PDM microphone clock edge sampling */ +#define MCHP_PDMC_CLK_POSITIVE 0 +#define MCHP_PDMC_CLK_NEGATIVE 1 + +#endif /* __DT_BINDINGS_MICROCHIP_PDMC_H__ */ diff --git a/include/dt-bindings/sound/qcom,lpass.h b/include/dt-bindings/sound/qcom,lpass.h new file mode 100644 index 000000000000..a9404c3b8884 --- /dev/null +++ b/include/dt-bindings/sound/qcom,lpass.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_QCOM_LPASS_H +#define __DT_QCOM_LPASS_H + +#define MI2S_PRIMARY 0 +#define MI2S_SECONDARY 1 +#define MI2S_TERTIARY 2 +#define MI2S_QUATERNARY 3 +#define MI2S_QUINARY 4 + +#define LPASS_DP_RX 5 + +#define LPASS_CDC_DMA_RX0 6 +#define LPASS_CDC_DMA_RX1 7 +#define LPASS_CDC_DMA_RX2 8 +#define LPASS_CDC_DMA_RX3 9 +#define LPASS_CDC_DMA_RX4 10 +#define LPASS_CDC_DMA_RX5 11 +#define LPASS_CDC_DMA_RX6 12 +#define LPASS_CDC_DMA_RX7 13 +#define LPASS_CDC_DMA_RX8 14 +#define LPASS_CDC_DMA_RX9 15 + +#define LPASS_CDC_DMA_TX0 16 +#define LPASS_CDC_DMA_TX1 17 +#define LPASS_CDC_DMA_TX2 18 +#define LPASS_CDC_DMA_TX3 19 +#define LPASS_CDC_DMA_TX4 20 +#define LPASS_CDC_DMA_TX5 21 +#define LPASS_CDC_DMA_TX6 22 +#define LPASS_CDC_DMA_TX7 23 +#define LPASS_CDC_DMA_TX8 24 + +#define LPASS_CDC_DMA_VA_TX0 25 +#define LPASS_CDC_DMA_VA_TX1 26 +#define LPASS_CDC_DMA_VA_TX2 27 +#define LPASS_CDC_DMA_VA_TX3 28 +#define LPASS_CDC_DMA_VA_TX4 29 +#define LPASS_CDC_DMA_VA_TX5 30 +#define LPASS_CDC_DMA_VA_TX6 31 +#define LPASS_CDC_DMA_VA_TX7 32 +#define LPASS_CDC_DMA_VA_TX8 33 + +#define LPASS_MCLK0 0 + +#endif /* __DT_QCOM_LPASS_H */ diff --git a/include/dt-bindings/sound/qcom,q6afe.h b/include/dt-bindings/sound/qcom,q6afe.h index 1df06f8ad5c3..9d5d89cfabcf 100644 --- a/include/dt-bindings/sound/qcom,q6afe.h +++ b/include/dt-bindings/sound/qcom,q6afe.h @@ -2,111 +2,8 @@ #ifndef __DT_BINDINGS_Q6_AFE_H__ #define __DT_BINDINGS_Q6_AFE_H__ -/* Audio Front End (AFE) virtual ports IDs */ -#define HDMI_RX 1 -#define SLIMBUS_0_RX 2 -#define SLIMBUS_0_TX 3 -#define SLIMBUS_1_RX 4 -#define SLIMBUS_1_TX 5 -#define SLIMBUS_2_RX 6 -#define SLIMBUS_2_TX 7 -#define SLIMBUS_3_RX 8 -#define SLIMBUS_3_TX 9 -#define SLIMBUS_4_RX 10 -#define SLIMBUS_4_TX 11 -#define SLIMBUS_5_RX 12 -#define SLIMBUS_5_TX 13 -#define SLIMBUS_6_RX 14 -#define SLIMBUS_6_TX 15 -#define PRIMARY_MI2S_RX 16 -#define PRIMARY_MI2S_TX 17 -#define SECONDARY_MI2S_RX 18 -#define SECONDARY_MI2S_TX 19 -#define TERTIARY_MI2S_RX 20 -#define TERTIARY_MI2S_TX 21 -#define QUATERNARY_MI2S_RX 22 -#define QUATERNARY_MI2S_TX 23 -#define PRIMARY_TDM_RX_0 24 -#define PRIMARY_TDM_TX_0 25 -#define PRIMARY_TDM_RX_1 26 -#define PRIMARY_TDM_TX_1 27 -#define PRIMARY_TDM_RX_2 28 -#define PRIMARY_TDM_TX_2 29 -#define PRIMARY_TDM_RX_3 30 -#define PRIMARY_TDM_TX_3 31 -#define PRIMARY_TDM_RX_4 32 -#define PRIMARY_TDM_TX_4 33 -#define PRIMARY_TDM_RX_5 34 -#define PRIMARY_TDM_TX_5 35 -#define PRIMARY_TDM_RX_6 36 -#define PRIMARY_TDM_TX_6 37 -#define PRIMARY_TDM_RX_7 38 -#define PRIMARY_TDM_TX_7 39 -#define SECONDARY_TDM_RX_0 40 -#define SECONDARY_TDM_TX_0 41 -#define SECONDARY_TDM_RX_1 42 -#define SECONDARY_TDM_TX_1 43 -#define SECONDARY_TDM_RX_2 44 -#define SECONDARY_TDM_TX_2 45 -#define SECONDARY_TDM_RX_3 46 -#define SECONDARY_TDM_TX_3 47 -#define SECONDARY_TDM_RX_4 48 -#define SECONDARY_TDM_TX_4 49 -#define SECONDARY_TDM_RX_5 50 -#define SECONDARY_TDM_TX_5 51 -#define SECONDARY_TDM_RX_6 52 -#define SECONDARY_TDM_TX_6 53 -#define SECONDARY_TDM_RX_7 54 -#define SECONDARY_TDM_TX_7 55 -#define TERTIARY_TDM_RX_0 56 -#define TERTIARY_TDM_TX_0 57 -#define TERTIARY_TDM_RX_1 58 -#define TERTIARY_TDM_TX_1 59 -#define TERTIARY_TDM_RX_2 60 -#define TERTIARY_TDM_TX_2 61 -#define TERTIARY_TDM_RX_3 62 -#define TERTIARY_TDM_TX_3 63 -#define TERTIARY_TDM_RX_4 64 -#define TERTIARY_TDM_TX_4 65 -#define TERTIARY_TDM_RX_5 66 -#define TERTIARY_TDM_TX_5 67 -#define TERTIARY_TDM_RX_6 68 -#define TERTIARY_TDM_TX_6 69 -#define TERTIARY_TDM_RX_7 70 -#define TERTIARY_TDM_TX_7 71 -#define QUATERNARY_TDM_RX_0 72 -#define QUATERNARY_TDM_TX_0 73 -#define QUATERNARY_TDM_RX_1 74 -#define QUATERNARY_TDM_TX_1 75 -#define QUATERNARY_TDM_RX_2 76 -#define QUATERNARY_TDM_TX_2 77 -#define QUATERNARY_TDM_RX_3 78 -#define QUATERNARY_TDM_TX_3 79 -#define QUATERNARY_TDM_RX_4 80 -#define QUATERNARY_TDM_TX_4 81 -#define QUATERNARY_TDM_RX_5 82 -#define QUATERNARY_TDM_TX_5 83 -#define QUATERNARY_TDM_RX_6 84 -#define QUATERNARY_TDM_TX_6 85 -#define QUATERNARY_TDM_RX_7 86 -#define QUATERNARY_TDM_TX_7 87 -#define QUINARY_TDM_RX_0 88 -#define QUINARY_TDM_TX_0 89 -#define QUINARY_TDM_RX_1 90 -#define QUINARY_TDM_TX_1 91 -#define QUINARY_TDM_RX_2 92 -#define QUINARY_TDM_TX_2 93 -#define QUINARY_TDM_RX_3 94 -#define QUINARY_TDM_TX_3 95 -#define QUINARY_TDM_RX_4 96 -#define QUINARY_TDM_TX_4 97 -#define QUINARY_TDM_RX_5 98 -#define QUINARY_TDM_TX_5 99 -#define QUINARY_TDM_RX_6 100 -#define QUINARY_TDM_TX_6 101 -#define QUINARY_TDM_RX_7 102 -#define QUINARY_TDM_TX_7 103 -#define DISPLAY_PORT_RX 104 +/* This file exists due to backward compatibility reasons, Please do not DELETE! */ -#endif /* __DT_BINDINGS_Q6_AFE_H__ */ +#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> +#endif /* __DT_BINDINGS_Q6_AFE_H__ */ diff --git a/include/dt-bindings/sound/qcom,q6asm.h b/include/dt-bindings/sound/qcom,q6asm.h index 1eb77d87c2e8..f59d74f14395 100644 --- a/include/dt-bindings/sound/qcom,q6asm.h +++ b/include/dt-bindings/sound/qcom,q6asm.h @@ -19,4 +19,8 @@ #define MSM_FRONTEND_DAI_MULTIMEDIA15 14 #define MSM_FRONTEND_DAI_MULTIMEDIA16 15 +#define Q6ASM_DAI_TX_RX 0 +#define Q6ASM_DAI_TX 1 +#define Q6ASM_DAI_RX 2 + #endif /* __DT_BINDINGS_Q6_ASM_H__ */ diff --git a/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h b/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h new file mode 100644 index 000000000000..9f7c5103bc82 --- /dev/null +++ b/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h @@ -0,0 +1,226 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_Q6_AUDIO_PORTS_H__ +#define __DT_BINDINGS_Q6_AUDIO_PORTS_H__ + +/* LPASS Audio virtual ports IDs */ +#define HDMI_RX 1 +#define SLIMBUS_0_RX 2 +#define SLIMBUS_0_TX 3 +#define SLIMBUS_1_RX 4 +#define SLIMBUS_1_TX 5 +#define SLIMBUS_2_RX 6 +#define SLIMBUS_2_TX 7 +#define SLIMBUS_3_RX 8 +#define SLIMBUS_3_TX 9 +#define SLIMBUS_4_RX 10 +#define SLIMBUS_4_TX 11 +#define SLIMBUS_5_RX 12 +#define SLIMBUS_5_TX 13 +#define SLIMBUS_6_RX 14 +#define SLIMBUS_6_TX 15 +#define PRIMARY_MI2S_RX 16 +#define PRIMARY_MI2S_TX 17 +#define SECONDARY_MI2S_RX 18 +#define SECONDARY_MI2S_TX 19 +#define TERTIARY_MI2S_RX 20 +#define TERTIARY_MI2S_TX 21 +#define QUATERNARY_MI2S_RX 22 +#define QUATERNARY_MI2S_TX 23 +#define PRIMARY_TDM_RX_0 24 +#define PRIMARY_TDM_TX_0 25 +#define PRIMARY_TDM_RX_1 26 +#define PRIMARY_TDM_TX_1 27 +#define PRIMARY_TDM_RX_2 28 +#define PRIMARY_TDM_TX_2 29 +#define PRIMARY_TDM_RX_3 30 +#define PRIMARY_TDM_TX_3 31 +#define PRIMARY_TDM_RX_4 32 +#define PRIMARY_TDM_TX_4 33 +#define PRIMARY_TDM_RX_5 34 +#define PRIMARY_TDM_TX_5 35 +#define PRIMARY_TDM_RX_6 36 +#define PRIMARY_TDM_TX_6 37 +#define PRIMARY_TDM_RX_7 38 +#define PRIMARY_TDM_TX_7 39 +#define SECONDARY_TDM_RX_0 40 +#define SECONDARY_TDM_TX_0 41 +#define SECONDARY_TDM_RX_1 42 +#define SECONDARY_TDM_TX_1 43 +#define SECONDARY_TDM_RX_2 44 +#define SECONDARY_TDM_TX_2 45 +#define SECONDARY_TDM_RX_3 46 +#define SECONDARY_TDM_TX_3 47 +#define SECONDARY_TDM_RX_4 48 +#define SECONDARY_TDM_TX_4 49 +#define SECONDARY_TDM_RX_5 50 +#define SECONDARY_TDM_TX_5 51 +#define SECONDARY_TDM_RX_6 52 +#define SECONDARY_TDM_TX_6 53 +#define SECONDARY_TDM_RX_7 54 +#define SECONDARY_TDM_TX_7 55 +#define TERTIARY_TDM_RX_0 56 +#define TERTIARY_TDM_TX_0 57 +#define TERTIARY_TDM_RX_1 58 +#define TERTIARY_TDM_TX_1 59 +#define TERTIARY_TDM_RX_2 60 +#define TERTIARY_TDM_TX_2 61 +#define TERTIARY_TDM_RX_3 62 +#define TERTIARY_TDM_TX_3 63 +#define TERTIARY_TDM_RX_4 64 +#define TERTIARY_TDM_TX_4 65 +#define TERTIARY_TDM_RX_5 66 +#define TERTIARY_TDM_TX_5 67 +#define TERTIARY_TDM_RX_6 68 +#define TERTIARY_TDM_TX_6 69 +#define TERTIARY_TDM_RX_7 70 +#define TERTIARY_TDM_TX_7 71 +#define QUATERNARY_TDM_RX_0 72 +#define QUATERNARY_TDM_TX_0 73 +#define QUATERNARY_TDM_RX_1 74 +#define QUATERNARY_TDM_TX_1 75 +#define QUATERNARY_TDM_RX_2 76 +#define QUATERNARY_TDM_TX_2 77 +#define QUATERNARY_TDM_RX_3 78 +#define QUATERNARY_TDM_TX_3 79 +#define QUATERNARY_TDM_RX_4 80 +#define QUATERNARY_TDM_TX_4 81 +#define QUATERNARY_TDM_RX_5 82 +#define QUATERNARY_TDM_TX_5 83 +#define QUATERNARY_TDM_RX_6 84 +#define QUATERNARY_TDM_TX_6 85 +#define QUATERNARY_TDM_RX_7 86 +#define QUATERNARY_TDM_TX_7 87 +#define QUINARY_TDM_RX_0 88 +#define QUINARY_TDM_TX_0 89 +#define QUINARY_TDM_RX_1 90 +#define QUINARY_TDM_TX_1 91 +#define QUINARY_TDM_RX_2 92 +#define QUINARY_TDM_TX_2 93 +#define QUINARY_TDM_RX_3 94 +#define QUINARY_TDM_TX_3 95 +#define QUINARY_TDM_RX_4 96 +#define QUINARY_TDM_TX_4 97 +#define QUINARY_TDM_RX_5 98 +#define QUINARY_TDM_TX_5 99 +#define QUINARY_TDM_RX_6 100 +#define QUINARY_TDM_TX_6 101 +#define QUINARY_TDM_RX_7 102 +#define QUINARY_TDM_TX_7 103 +#define DISPLAY_PORT_RX 104 +#define WSA_CODEC_DMA_RX_0 105 +#define WSA_CODEC_DMA_TX_0 106 +#define WSA_CODEC_DMA_RX_1 107 +#define WSA_CODEC_DMA_TX_1 108 +#define WSA_CODEC_DMA_TX_2 109 +#define VA_CODEC_DMA_TX_0 110 +#define VA_CODEC_DMA_TX_1 111 +#define VA_CODEC_DMA_TX_2 112 +#define RX_CODEC_DMA_RX_0 113 +#define TX_CODEC_DMA_TX_0 114 +#define RX_CODEC_DMA_RX_1 115 +#define TX_CODEC_DMA_TX_1 116 +#define RX_CODEC_DMA_RX_2 117 +#define TX_CODEC_DMA_TX_2 118 +#define RX_CODEC_DMA_RX_3 119 +#define TX_CODEC_DMA_TX_3 120 +#define RX_CODEC_DMA_RX_4 121 +#define TX_CODEC_DMA_TX_4 122 +#define RX_CODEC_DMA_RX_5 123 +#define TX_CODEC_DMA_TX_5 124 +#define RX_CODEC_DMA_RX_6 125 +#define RX_CODEC_DMA_RX_7 126 +#define QUINARY_MI2S_RX 127 +#define QUINARY_MI2S_TX 128 + +#define LPASS_CLK_ID_PRI_MI2S_IBIT 1 +#define LPASS_CLK_ID_PRI_MI2S_EBIT 2 +#define LPASS_CLK_ID_SEC_MI2S_IBIT 3 +#define LPASS_CLK_ID_SEC_MI2S_EBIT 4 +#define LPASS_CLK_ID_TER_MI2S_IBIT 5 +#define LPASS_CLK_ID_TER_MI2S_EBIT 6 +#define LPASS_CLK_ID_QUAD_MI2S_IBIT 7 +#define LPASS_CLK_ID_QUAD_MI2S_EBIT 8 +#define LPASS_CLK_ID_SPEAKER_I2S_IBIT 9 +#define LPASS_CLK_ID_SPEAKER_I2S_EBIT 10 +#define LPASS_CLK_ID_SPEAKER_I2S_OSR 11 +#define LPASS_CLK_ID_QUI_MI2S_IBIT 12 +#define LPASS_CLK_ID_QUI_MI2S_EBIT 13 +#define LPASS_CLK_ID_SEN_MI2S_IBIT 14 +#define LPASS_CLK_ID_SEN_MI2S_EBIT 15 +#define LPASS_CLK_ID_INT0_MI2S_IBIT 16 +#define LPASS_CLK_ID_INT1_MI2S_IBIT 17 +#define LPASS_CLK_ID_INT2_MI2S_IBIT 18 +#define LPASS_CLK_ID_INT3_MI2S_IBIT 19 +#define LPASS_CLK_ID_INT4_MI2S_IBIT 20 +#define LPASS_CLK_ID_INT5_MI2S_IBIT 21 +#define LPASS_CLK_ID_INT6_MI2S_IBIT 22 +#define LPASS_CLK_ID_QUI_MI2S_OSR 23 +#define LPASS_CLK_ID_PRI_PCM_IBIT 24 +#define LPASS_CLK_ID_PRI_PCM_EBIT 25 +#define LPASS_CLK_ID_SEC_PCM_IBIT 26 +#define LPASS_CLK_ID_SEC_PCM_EBIT 27 +#define LPASS_CLK_ID_TER_PCM_IBIT 28 +#define LPASS_CLK_ID_TER_PCM_EBIT 29 +#define LPASS_CLK_ID_QUAD_PCM_IBIT 30 +#define LPASS_CLK_ID_QUAD_PCM_EBIT 31 +#define LPASS_CLK_ID_QUIN_PCM_IBIT 32 +#define LPASS_CLK_ID_QUIN_PCM_EBIT 33 +#define LPASS_CLK_ID_QUI_PCM_OSR 34 +#define LPASS_CLK_ID_PRI_TDM_IBIT 35 +#define LPASS_CLK_ID_PRI_TDM_EBIT 36 +#define LPASS_CLK_ID_SEC_TDM_IBIT 37 +#define LPASS_CLK_ID_SEC_TDM_EBIT 38 +#define LPASS_CLK_ID_TER_TDM_IBIT 39 +#define LPASS_CLK_ID_TER_TDM_EBIT 40 +#define LPASS_CLK_ID_QUAD_TDM_IBIT 41 +#define LPASS_CLK_ID_QUAD_TDM_EBIT 42 +#define LPASS_CLK_ID_QUIN_TDM_IBIT 43 +#define LPASS_CLK_ID_QUIN_TDM_EBIT 44 +#define LPASS_CLK_ID_QUIN_TDM_OSR 45 +#define LPASS_CLK_ID_MCLK_1 46 +#define LPASS_CLK_ID_MCLK_2 47 +#define LPASS_CLK_ID_MCLK_3 48 +#define LPASS_CLK_ID_MCLK_4 49 +#define LPASS_CLK_ID_INTERNAL_DIGITAL_CODEC_CORE 50 +#define LPASS_CLK_ID_INT_MCLK_0 51 +#define LPASS_CLK_ID_INT_MCLK_1 52 +#define LPASS_CLK_ID_MCLK_5 53 +#define LPASS_CLK_ID_WSA_CORE_MCLK 54 +#define LPASS_CLK_ID_WSA_CORE_NPL_MCLK 55 +#define LPASS_CLK_ID_VA_CORE_MCLK 56 +#define LPASS_CLK_ID_TX_CORE_MCLK 57 +#define LPASS_CLK_ID_TX_CORE_NPL_MCLK 58 +#define LPASS_CLK_ID_RX_CORE_MCLK 59 +#define LPASS_CLK_ID_RX_CORE_NPL_MCLK 60 +#define LPASS_CLK_ID_VA_CORE_2X_MCLK 61 +/* Clock ID for MCLK for WSA2 core */ +#define LPASS_CLK_ID_WSA2_CORE_MCLK 62 +/* Clock ID for NPL MCLK for WSA2 core */ +#define LPASS_CLK_ID_WSA2_CORE_2X_MCLK 63 +/* Clock ID for RX Core TX MCLK */ +#define LPASS_CLK_ID_RX_CORE_TX_MCLK 64 +/* Clock ID for RX CORE TX 2X MCLK */ +#define LPASS_CLK_ID_RX_CORE_TX_2X_MCLK 65 +/* Clock ID for WSA core TX MCLK */ +#define LPASS_CLK_ID_WSA_CORE_TX_MCLK 66 +/* Clock ID for WSA core TX 2X MCLK */ +#define LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK 67 +/* Clock ID for WSA2 core TX MCLK */ +#define LPASS_CLK_ID_WSA2_CORE_TX_MCLK 68 +/* Clock ID for WSA2 core TX 2X MCLK */ +#define LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK 69 +/* Clock ID for RX CORE MCLK2 2X MCLK */ +#define LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK 70 + +#define LPASS_HW_AVTIMER_VOTE 101 +#define LPASS_HW_MACRO_VOTE 102 +#define LPASS_HW_DCODEC_VOTE 103 + +#define Q6AFE_MAX_CLK_ID 104 + +#define LPASS_CLK_ATTRIBUTE_INVALID 0x0 +#define LPASS_CLK_ATTRIBUTE_COUPLE_NO 0x1 +#define LPASS_CLK_ATTRIBUTE_COUPLE_DIVIDEND 0x2 +#define LPASS_CLK_ATTRIBUTE_COUPLE_DIVISOR 0x3 + +#endif /* __DT_BINDINGS_Q6_AUDIO_PORTS_H__ */ diff --git a/include/dt-bindings/sound/qcom,wcd9335.h b/include/dt-bindings/sound/qcom,wcd9335.h new file mode 100644 index 000000000000..f5e9f1db091e --- /dev/null +++ b/include/dt-bindings/sound/qcom,wcd9335.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef __DT_SOUND_QCOM_WCD9335_H +#define __DT_SOUND_QCOM_WCD9335_H + +#define AIF1_PB 0 +#define AIF1_CAP 1 +#define AIF2_PB 2 +#define AIF2_CAP 3 +#define AIF3_PB 4 +#define AIF3_CAP 5 +#define AIF4_PB 6 +#define NUM_CODEC_DAIS 7 + +#endif diff --git a/include/dt-bindings/sound/rt5640.h b/include/dt-bindings/sound/rt5640.h index 154c9b4414f2..655f6946388a 100644 --- a/include/dt-bindings/sound/rt5640.h +++ b/include/dt-bindings/sound/rt5640.h @@ -16,6 +16,7 @@ #define RT5640_JD_SRC_GPIO2 4 #define RT5640_JD_SRC_GPIO3 5 #define RT5640_JD_SRC_GPIO4 6 +#define RT5640_JD_SRC_HDA_HEADER 7 #define RT5640_OVCD_SF_0P5 0 #define RT5640_OVCD_SF_0P75 1 diff --git a/include/dt-bindings/sound/sc7180-lpass.h b/include/dt-bindings/sound/sc7180-lpass.h new file mode 100644 index 000000000000..5c1ee8b36b19 --- /dev/null +++ b/include/dt-bindings/sound/sc7180-lpass.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_SC7180_LPASS_H +#define __DT_SC7180_LPASS_H + +#include <dt-bindings/sound/qcom,lpass.h> + +/* NOTE: Use qcom,lpass.h to define any AIF ID's for LPASS */ + +#endif /* __DT_APQ8016_LPASS_H */ diff --git a/include/dt-bindings/sound/tlv320adc3xxx.h b/include/dt-bindings/sound/tlv320adc3xxx.h new file mode 100644 index 000000000000..ec988439da20 --- /dev/null +++ b/include/dt-bindings/sound/tlv320adc3xxx.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Devicetree bindings definitions for tlv320adc3xxx driver. + * + * Copyright (C) 2021 Axis Communications AB + */ +#ifndef __DT_TLV320ADC3XXX_H +#define __DT_TLV320ADC3XXX_H + +#define ADC3XXX_GPIO_DISABLED 0 /* I/O buffers powered down */ +#define ADC3XXX_GPIO_INPUT 1 /* Various non-GPIO inputs */ +#define ADC3XXX_GPIO_GPI 2 /* General purpose input */ +#define ADC3XXX_GPIO_GPO 3 /* General purpose output */ +#define ADC3XXX_GPIO_CLKOUT 4 /* Source set in reg. CLKOUT_MUX */ +#define ADC3XXX_GPIO_INT1 5 /* INT1 output */ +#define ADC3XXX_GPIO_INT2 6 /* INT2 output */ +/* value 7 is reserved */ +#define ADC3XXX_GPIO_SECONDARY_BCLK 8 /* Codec interface secondary BCLK */ +#define ADC3XXX_GPIO_SECONDARY_WCLK 9 /* Codec interface secondary WCLK */ +#define ADC3XXX_GPIO_ADC_MOD_CLK 10 /* Clock output for digital mics */ +/* values 11-15 reserved */ + +#define ADC3XXX_MICBIAS_OFF 0 /* Micbias pin powered off */ +#define ADC3XXX_MICBIAS_2_0V 1 /* Micbias pin set to 2.0V */ +#define ADC3XXX_MICBIAS_2_5V 2 /* Micbias pin set to 2.5V */ +#define ADC3XXX_MICBIAS_AVDD 3 /* Use AVDD voltage for micbias pin */ + +#endif /* __DT_TLV320ADC3XXX_H */ diff --git a/include/dt-bindings/sound/tlv320aic31xx-micbias.h b/include/dt-bindings/sound/tlv320aic31xx-micbias.h deleted file mode 100644 index c6895a18a455..000000000000 --- a/include/dt-bindings/sound/tlv320aic31xx-micbias.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_TLV320AIC31XX_MICBIAS_H -#define __DT_TLV320AIC31XX_MICBIAS_H - -#define MICBIAS_2_0V 1 -#define MICBIAS_2_5V 2 -#define MICBIAS_AVDDV 3 - -#endif /* __DT_TLV320AIC31XX_MICBIAS_H */ diff --git a/include/dt-bindings/sound/tlv320aic31xx.h b/include/dt-bindings/sound/tlv320aic31xx.h new file mode 100644 index 000000000000..4a80238ab250 --- /dev/null +++ b/include/dt-bindings/sound/tlv320aic31xx.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_TLV320AIC31XX_H +#define __DT_TLV320AIC31XX_H + +#define MICBIAS_2_0V 1 +#define MICBIAS_2_5V 2 +#define MICBIAS_AVDDV 3 + +#define PLL_CLKIN_MCLK 0x00 +#define PLL_CLKIN_BCLK 0x01 +#define PLL_CLKIN_GPIO1 0x02 +#define PLL_CLKIN_DIN 0x03 + +#endif /* __DT_TLV320AIC31XX_H */ diff --git a/include/dt-bindings/usb/pd.h b/include/dt-bindings/usb/pd.h index 985f2bbd4d24..e6526b138174 100644 --- a/include/dt-bindings/usb/pd.h +++ b/include/dt-bindings/usb/pd.h @@ -85,4 +85,384 @@ PDO_PPS_APDO_MIN_VOLT(min_mv) | PDO_PPS_APDO_MAX_VOLT(max_mv) | \ PDO_PPS_APDO_MAX_CURR(max_ma)) - #endif /* __DT_POWER_DELIVERY_H */ + /* + * Based on "Table 6-14 Fixed Supply PDO - Sink" of "USB Power Delivery Specification Revision 3.0, + * Version 1.2" + * Initial current capability of the new source when vSafe5V is applied. + */ +#define FRS_DEFAULT_POWER 1 +#define FRS_5V_1P5A 2 +#define FRS_5V_3A 3 + +/* + * SVDM Identity Header + * -------------------- + * <31> :: data capable as a USB host + * <30> :: data capable as a USB device + * <29:27> :: product type (UFP / Cable / VPD) + * <26> :: modal operation supported (1b == yes) + * <25:23> :: product type (DFP) (SVDM version 2.0+ only; set to zero in version 1.0) + * <22:21> :: connector type (SVDM version 2.0+ only; set to zero in version 1.0) + * <20:16> :: Reserved, Shall be set to zero + * <15:0> :: USB-IF assigned VID for this cable vendor + */ + +/* PD Rev2.0 definition */ +#define IDH_PTYPE_UNDEF 0 + +/* SOP Product Type (UFP) */ +#define IDH_PTYPE_NOT_UFP 0 +#define IDH_PTYPE_HUB 1 +#define IDH_PTYPE_PERIPH 2 +#define IDH_PTYPE_PSD 3 +#define IDH_PTYPE_AMA 5 + +/* SOP' Product Type (Cable Plug / VPD) */ +#define IDH_PTYPE_NOT_CABLE 0 +#define IDH_PTYPE_PCABLE 3 +#define IDH_PTYPE_ACABLE 4 +#define IDH_PTYPE_VPD 6 + +/* SOP Product Type (DFP) */ +#define IDH_PTYPE_NOT_DFP 0 +#define IDH_PTYPE_DFP_HUB 1 +#define IDH_PTYPE_DFP_HOST 2 +#define IDH_PTYPE_DFP_PB 3 + +#define VDO_IDH(usbh, usbd, ufp_cable, is_modal, dfp, conn, vid) \ + ((usbh) << 31 | (usbd) << 30 | ((ufp_cable) & 0x7) << 27 \ + | (is_modal) << 26 | ((dfp) & 0x7) << 23 | ((conn) & 0x3) << 21 \ + | ((vid) & 0xffff)) + +/* + * Cert Stat VDO + * ------------- + * <31:0> : USB-IF assigned XID for this cable + */ +#define VDO_CERT(xid) ((xid) & 0xffffffff) + +/* + * Product VDO + * ----------- + * <31:16> : USB Product ID + * <15:0> : USB bcdDevice + */ +#define VDO_PRODUCT(pid, bcd) (((pid) & 0xffff) << 16 | ((bcd) & 0xffff)) + +/* + * UFP VDO (PD Revision 3.0+ only) + * -------- + * <31:29> :: UFP VDO version + * <28> :: Reserved + * <27:24> :: Device capability + * <23:22> :: Connector type (10b == receptacle, 11b == captive plug) + * <21:11> :: Reserved + * <10:8> :: Vconn power (AMA only) + * <7> :: Vconn required (AMA only, 0b == no, 1b == yes) + * <6> :: Vbus required (AMA only, 0b == yes, 1b == no) + * <5:3> :: Alternate modes + * <2:0> :: USB highest speed + */ +/* UFP VDO Version */ +#define UFP_VDO_VER1_2 2 + +/* Device Capability */ +#define DEV_USB2_CAPABLE (1 << 0) +#define DEV_USB2_BILLBOARD (1 << 1) +#define DEV_USB3_CAPABLE (1 << 2) +#define DEV_USB4_CAPABLE (1 << 3) + +/* Connector Type */ +#define UFP_RECEPTACLE 2 +#define UFP_CAPTIVE 3 + +/* Vconn Power (AMA only, set to AMA_VCONN_NOT_REQ if Vconn is not required) */ +#define AMA_VCONN_PWR_1W 0 +#define AMA_VCONN_PWR_1W5 1 +#define AMA_VCONN_PWR_2W 2 +#define AMA_VCONN_PWR_3W 3 +#define AMA_VCONN_PWR_4W 4 +#define AMA_VCONN_PWR_5W 5 +#define AMA_VCONN_PWR_6W 6 + +/* Vconn Required (AMA only) */ +#define AMA_VCONN_NOT_REQ 0 +#define AMA_VCONN_REQ 1 + +/* Vbus Required (AMA only) */ +#define AMA_VBUS_REQ 0 +#define AMA_VBUS_NOT_REQ 1 + +/* Alternate Modes */ +#define UFP_ALTMODE_NOT_SUPP 0 +#define UFP_ALTMODE_TBT3 (1 << 0) +#define UFP_ALTMODE_RECFG (1 << 1) +#define UFP_ALTMODE_NO_RECFG (1 << 2) + +/* USB Highest Speed */ +#define UFP_USB2_ONLY 0 +#define UFP_USB32_GEN1 1 +#define UFP_USB32_4_GEN2 2 +#define UFP_USB4_GEN3 3 + +#define VDO_UFP(ver, cap, conn, vcpwr, vcr, vbr, alt, spd) \ + (((ver) & 0x7) << 29 | ((cap) & 0xf) << 24 | ((conn) & 0x3) << 22 \ + | ((vcpwr) & 0x7) << 8 | (vcr) << 7 | (vbr) << 6 | ((alt) & 0x7) << 3 \ + | ((spd) & 0x7)) + +/* + * DFP VDO (PD Revision 3.0+ only) + * -------- + * <31:29> :: DFP VDO version + * <28:27> :: Reserved + * <26:24> :: Host capability + * <23:22> :: Connector type (10b == receptacle, 11b == captive plug) + * <21:5> :: Reserved + * <4:0> :: Port number + */ +#define DFP_VDO_VER1_1 1 +#define HOST_USB2_CAPABLE (1 << 0) +#define HOST_USB3_CAPABLE (1 << 1) +#define HOST_USB4_CAPABLE (1 << 2) +#define DFP_RECEPTACLE 2 +#define DFP_CAPTIVE 3 + +#define VDO_DFP(ver, cap, conn, pnum) \ + (((ver) & 0x7) << 29 | ((cap) & 0x7) << 24 | ((conn) & 0x3) << 22 \ + | ((pnum) & 0x1f)) + +/* + * Cable VDO (for both Passive and Active Cable VDO in PD Rev2.0) + * --------- + * <31:28> :: Cable HW version + * <27:24> :: Cable FW version + * <23:20> :: Reserved, Shall be set to zero + * <19:18> :: type-C to Type-A/B/C/Captive (00b == A, 01 == B, 10 == C, 11 == Captive) + * <17> :: Reserved, Shall be set to zero + * <16:13> :: cable latency (0001 == <10ns(~1m length)) + * <12:11> :: cable termination type (11b == both ends active VCONN req) + * <10> :: SSTX1 Directionality support (0b == fixed, 1b == cfgable) + * <9> :: SSTX2 Directionality support + * <8> :: SSRX1 Directionality support + * <7> :: SSRX2 Directionality support + * <6:5> :: Vbus current handling capability (01b == 3A, 10b == 5A) + * <4> :: Vbus through cable (0b == no, 1b == yes) + * <3> :: SOP" controller present? (0b == no, 1b == yes) + * <2:0> :: USB SS Signaling support + * + * Passive Cable VDO (PD Rev3.0+) + * --------- + * <31:28> :: Cable HW version + * <27:24> :: Cable FW version + * <23:21> :: VDO version + * <20> :: Reserved, Shall be set to zero + * <19:18> :: Type-C to Type-C/Captive (10b == C, 11b == Captive) + * <17> :: Reserved, Shall be set to zero + * <16:13> :: cable latency (0001 == <10ns(~1m length)) + * <12:11> :: cable termination type (10b == Vconn not req, 01b == Vconn req) + * <10:9> :: Maximum Vbus voltage (00b == 20V, 01b == 30V, 10b == 40V, 11b == 50V) + * <8:7> :: Reserved, Shall be set to zero + * <6:5> :: Vbus current handling capability (01b == 3A, 10b == 5A) + * <4:3> :: Reserved, Shall be set to zero + * <2:0> :: USB highest speed + * + * Active Cable VDO 1 (PD Rev3.0+) + * --------- + * <31:28> :: Cable HW version + * <27:24> :: Cable FW version + * <23:21> :: VDO version + * <20> :: Reserved, Shall be set to zero + * <19:18> :: Connector type (10b == C, 11b == Captive) + * <17> :: Reserved, Shall be set to zero + * <16:13> :: cable latency (0001 == <10ns(~1m length)) + * <12:11> :: cable termination type (10b == one end active, 11b == both ends active VCONN req) + * <10:9> :: Maximum Vbus voltage (00b == 20V, 01b == 30V, 10b == 40V, 11b == 50V) + * <8> :: SBU supported (0b == supported, 1b == not supported) + * <7> :: SBU type (0b == passive, 1b == active) + * <6:5> :: Vbus current handling capability (01b == 3A, 10b == 5A) + * <4> :: Vbus through cable (0b == no, 1b == yes) + * <3> :: SOP" controller present? (0b == no, 1b == yes) + * <2:0> :: USB highest speed + */ +/* Cable VDO Version */ +#define CABLE_VDO_VER1_0 0 +#define CABLE_VDO_VER1_3 3 + +/* Connector Type (_ATYPE and _BTYPE are for PD Rev2.0 only) */ +#define CABLE_ATYPE 0 +#define CABLE_BTYPE 1 +#define CABLE_CTYPE 2 +#define CABLE_CAPTIVE 3 + +/* Cable Latency */ +#define CABLE_LATENCY_1M 1 +#define CABLE_LATENCY_2M 2 +#define CABLE_LATENCY_3M 3 +#define CABLE_LATENCY_4M 4 +#define CABLE_LATENCY_5M 5 +#define CABLE_LATENCY_6M 6 +#define CABLE_LATENCY_7M 7 +#define CABLE_LATENCY_7M_PLUS 8 + +/* Cable Termination Type */ +#define PCABLE_VCONN_NOT_REQ 0 +#define PCABLE_VCONN_REQ 1 +#define ACABLE_ONE_END 2 +#define ACABLE_BOTH_END 3 + +/* Maximum Vbus Voltage */ +#define CABLE_MAX_VBUS_20V 0 +#define CABLE_MAX_VBUS_30V 1 +#define CABLE_MAX_VBUS_40V 2 +#define CABLE_MAX_VBUS_50V 3 + +/* Active Cable SBU Supported/Type */ +#define ACABLE_SBU_SUPP 0 +#define ACABLE_SBU_NOT_SUPP 1 +#define ACABLE_SBU_PASSIVE 0 +#define ACABLE_SBU_ACTIVE 1 + +/* Vbus Current Handling Capability */ +#define CABLE_CURR_DEF 0 +#define CABLE_CURR_3A 1 +#define CABLE_CURR_5A 2 + +/* USB SuperSpeed Signaling Support (PD Rev2.0) */ +#define CABLE_USBSS_U2_ONLY 0 +#define CABLE_USBSS_U31_GEN1 1 +#define CABLE_USBSS_U31_GEN2 2 + +/* USB Highest Speed */ +#define CABLE_USB2_ONLY 0 +#define CABLE_USB32_GEN1 1 +#define CABLE_USB32_4_GEN2 2 +#define CABLE_USB4_GEN3 3 + +#define VDO_CABLE(hw, fw, cbl, lat, term, tx1d, tx2d, rx1d, rx2d, cur, vps, sopp, usbss) \ + (((hw) & 0x7) << 28 | ((fw) & 0x7) << 24 | ((cbl) & 0x3) << 18 \ + | ((lat) & 0x7) << 13 | ((term) & 0x3) << 11 | (tx1d) << 10 \ + | (tx2d) << 9 | (rx1d) << 8 | (rx2d) << 7 | ((cur) & 0x3) << 5 \ + | (vps) << 4 | (sopp) << 3 | ((usbss) & 0x7)) +#define VDO_PCABLE(hw, fw, ver, conn, lat, term, vbm, cur, spd) \ + (((hw) & 0xf) << 28 | ((fw) & 0xf) << 24 | ((ver) & 0x7) << 21 \ + | ((conn) & 0x3) << 18 | ((lat) & 0xf) << 13 | ((term) & 0x3) << 11 \ + | ((vbm) & 0x3) << 9 | ((cur) & 0x3) << 5 | ((spd) & 0x7)) +#define VDO_ACABLE1(hw, fw, ver, conn, lat, term, vbm, sbu, sbut, cur, vbt, sopp, spd) \ + (((hw) & 0xf) << 28 | ((fw) & 0xf) << 24 | ((ver) & 0x7) << 21 \ + | ((conn) & 0x3) << 18 | ((lat) & 0xf) << 13 | ((term) & 0x3) << 11 \ + | ((vbm) & 0x3) << 9 | (sbu) << 8 | (sbut) << 7 | ((cur) & 0x3) << 5 \ + | (vbt) << 4 | (sopp) << 3 | ((spd) & 0x7)) + +/* + * Active Cable VDO 2 + * --------- + * <31:24> :: Maximum operating temperature + * <23:16> :: Shutdown temperature + * <15> :: Reserved, Shall be set to zero + * <14:12> :: U3/CLd power + * <11> :: U3 to U0 transition mode (0b == direct, 1b == through U3S) + * <10> :: Physical connection (0b == copper, 1b == optical) + * <9> :: Active element (0b == redriver, 1b == retimer) + * <8> :: USB4 supported (0b == yes, 1b == no) + * <7:6> :: USB2 hub hops consumed + * <5> :: USB2 supported (0b == yes, 1b == no) + * <4> :: USB3.2 supported (0b == yes, 1b == no) + * <3> :: USB lanes supported (0b == one lane, 1b == two lanes) + * <2> :: Optically isolated active cable (0b == no, 1b == yes) + * <1> :: Reserved, Shall be set to zero + * <0> :: USB gen (0b == gen1, 1b == gen2+) + */ +/* U3/CLd Power*/ +#define ACAB2_U3_CLD_10MW_PLUS 0 +#define ACAB2_U3_CLD_10MW 1 +#define ACAB2_U3_CLD_5MW 2 +#define ACAB2_U3_CLD_1MW 3 +#define ACAB2_U3_CLD_500UW 4 +#define ACAB2_U3_CLD_200UW 5 +#define ACAB2_U3_CLD_50UW 6 + +/* Other Active Cable VDO 2 Fields */ +#define ACAB2_U3U0_DIRECT 0 +#define ACAB2_U3U0_U3S 1 +#define ACAB2_PHY_COPPER 0 +#define ACAB2_PHY_OPTICAL 1 +#define ACAB2_REDRIVER 0 +#define ACAB2_RETIMER 1 +#define ACAB2_USB4_SUPP 0 +#define ACAB2_USB4_NOT_SUPP 1 +#define ACAB2_USB2_SUPP 0 +#define ACAB2_USB2_NOT_SUPP 1 +#define ACAB2_USB32_SUPP 0 +#define ACAB2_USB32_NOT_SUPP 1 +#define ACAB2_LANES_ONE 0 +#define ACAB2_LANES_TWO 1 +#define ACAB2_OPT_ISO_NO 0 +#define ACAB2_OPT_ISO_YES 1 +#define ACAB2_GEN_1 0 +#define ACAB2_GEN_2_PLUS 1 + +#define VDO_ACABLE2(mtemp, stemp, u3p, trans, phy, ele, u4, hops, u2, u32, lane, iso, gen) \ + (((mtemp) & 0xff) << 24 | ((stemp) & 0xff) << 16 | ((u3p) & 0x7) << 12 \ + | (trans) << 11 | (phy) << 10 | (ele) << 9 | (u4) << 8 \ + | ((hops) & 0x3) << 6 | (u2) << 5 | (u32) << 4 | (lane) << 3 \ + | (iso) << 2 | (gen)) + +/* + * AMA VDO (PD Rev2.0) + * --------- + * <31:28> :: Cable HW version + * <27:24> :: Cable FW version + * <23:12> :: Reserved, Shall be set to zero + * <11> :: SSTX1 Directionality support (0b == fixed, 1b == cfgable) + * <10> :: SSTX2 Directionality support + * <9> :: SSRX1 Directionality support + * <8> :: SSRX2 Directionality support + * <7:5> :: Vconn power + * <4> :: Vconn power required + * <3> :: Vbus power required + * <2:0> :: USB SS Signaling support + */ +#define VDO_AMA(hw, fw, tx1d, tx2d, rx1d, rx2d, vcpwr, vcr, vbr, usbss) \ + (((hw) & 0x7) << 28 | ((fw) & 0x7) << 24 \ + | (tx1d) << 11 | (tx2d) << 10 | (rx1d) << 9 | (rx2d) << 8 \ + | ((vcpwr) & 0x7) << 5 | (vcr) << 4 | (vbr) << 3 \ + | ((usbss) & 0x7)) + +#define PD_VDO_AMA_VCONN_REQ(vdo) (((vdo) >> 4) & 1) +#define PD_VDO_AMA_VBUS_REQ(vdo) (((vdo) >> 3) & 1) + +#define AMA_USBSS_U2_ONLY 0 +#define AMA_USBSS_U31_GEN1 1 +#define AMA_USBSS_U31_GEN2 2 +#define AMA_USBSS_BBONLY 3 + +/* + * VPD VDO + * --------- + * <31:28> :: HW version + * <27:24> :: FW version + * <23:21> :: VDO version + * <20:17> :: Reserved, Shall be set to zero + * <16:15> :: Maximum Vbus voltage (00b == 20V, 01b == 30V, 10b == 40V, 11b == 50V) + * <14> :: Charge through current support (0b == 3A, 1b == 5A) + * <13> :: Reserved, Shall be set to zero + * <12:7> :: Vbus impedance + * <6:1> :: Ground impedance + * <0> :: Charge through support (0b == no, 1b == yes) + */ +#define VPD_VDO_VER1_0 0 +#define VPD_MAX_VBUS_20V 0 +#define VPD_MAX_VBUS_30V 1 +#define VPD_MAX_VBUS_40V 2 +#define VPD_MAX_VBUS_50V 3 +#define VPDCT_CURR_3A 0 +#define VPDCT_CURR_5A 1 +#define VPDCT_NOT_SUPP 0 +#define VPDCT_SUPP 1 + +#define VDO_VPD(hw, fw, ver, vbm, curr, vbi, gi, ct) \ + (((hw) & 0xf) << 28 | ((fw) & 0xf) << 24 | ((ver) & 0x7) << 21 \ + | ((vbm) & 0x3) << 15 | (curr) << 14 | ((vbi) & 0x3f) << 7 \ + | ((gi) & 0x3f) << 1 | (ct)) + +#endif /* __DT_POWER_DELIVERY_H */ |