diff options
Diffstat (limited to 'include/uapi')
| -rw-r--r-- | include/uapi/drm/drm.h | 1 | ||||
| -rw-r--r-- | include/uapi/drm/drm_mode.h | 15 | ||||
| -rw-r--r-- | include/uapi/drm/exynos_drm.h | 43 | ||||
| -rw-r--r-- | include/uapi/drm/i915_drm.h | 43 | ||||
| -rw-r--r-- | include/uapi/drm/msm_drm.h | 2 | ||||
| -rw-r--r-- | include/uapi/linux/dma-buf.h | 40 |
6 files changed, 122 insertions, 22 deletions
diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h index b4e92eb12044..a0ebfe7c9a28 100644 --- a/include/uapi/drm/drm.h +++ b/include/uapi/drm/drm.h @@ -669,6 +669,7 @@ struct drm_set_client_cap { __u64 value; }; +#define DRM_RDWR O_RDWR #define DRM_CLOEXEC O_CLOEXEC struct drm_prime_handle { __u32 handle; diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h index 50adb46204c2..c0217434d28d 100644 --- a/include/uapi/drm/drm_mode.h +++ b/include/uapi/drm/drm_mode.h @@ -487,6 +487,21 @@ struct drm_mode_crtc_lut { __u64 blue; }; +struct drm_color_ctm { + /* Conversion matrix in S31.32 format. */ + __s64 matrix[9]; +}; + +struct drm_color_lut { + /* + * Data is U0.16 fixed point format. + */ + __u16 red; + __u16 green; + __u16 blue; + __u16 reserved; +}; + #define DRM_MODE_PAGE_FLIP_EVENT 0x01 #define DRM_MODE_PAGE_FLIP_ASYNC 0x02 #define DRM_MODE_PAGE_FLIP_FLAGS (DRM_MODE_PAGE_FLIP_EVENT|DRM_MODE_PAGE_FLIP_ASYNC) diff --git a/include/uapi/drm/exynos_drm.h b/include/uapi/drm/exynos_drm.h index 312c67d744ae..3947c2eb8d69 100644 --- a/include/uapi/drm/exynos_drm.h +++ b/include/uapi/drm/exynos_drm.h @@ -28,8 +28,21 @@ */ struct drm_exynos_gem_create { __u64 size; - unsigned int flags; - unsigned int handle; + __u32 flags; + __u32 handle; +}; + +/** + * A structure for getting a fake-offset that can be used with mmap. + * + * @handle: handle of gem object. + * @reserved: just padding to be 64-bit aligned. + * @offset: a fake-offset of gem object. + */ +struct drm_exynos_gem_map { + __u32 handle; + __u32 reserved; + __u64 offset; }; /** @@ -42,8 +55,8 @@ struct drm_exynos_gem_create { * be set by driver. */ struct drm_exynos_gem_info { - unsigned int handle; - unsigned int flags; + __u32 handle; + __u32 flags; __u64 size; }; @@ -56,8 +69,8 @@ struct drm_exynos_gem_info { * @edid: the edid data pointer from user side. */ struct drm_exynos_vidi_connection { - unsigned int connection; - unsigned int extensions; + __u32 connection; + __u32 extensions; __u64 edid; }; @@ -206,9 +219,9 @@ struct drm_exynos_ipp_prop_list { * @pos: property of image position(src-cropped,dst-scaler). */ struct drm_exynos_ipp_config { - enum drm_exynos_ops_id ops_id; - enum drm_exynos_flip flip; - enum drm_exynos_degree degree; + __u32 ops_id; + __u32 flip; + __u32 degree; __u32 fmt; struct drm_exynos_sz sz; struct drm_exynos_pos pos; @@ -233,7 +246,7 @@ enum drm_exynos_ipp_cmd { */ struct drm_exynos_ipp_property { struct drm_exynos_ipp_config config[EXYNOS_DRM_OPS_MAX]; - enum drm_exynos_ipp_cmd cmd; + __u32 cmd; __u32 ipp_id; __u32 prop_id; __u32 refresh_rate; @@ -255,8 +268,8 @@ enum drm_exynos_ipp_buf_type { * @user_data: user data. */ struct drm_exynos_ipp_queue_buf { - enum drm_exynos_ops_id ops_id; - enum drm_exynos_ipp_buf_type buf_type; + __u32 ops_id; + __u32 buf_type; __u32 prop_id; __u32 buf_id; __u32 handle[EXYNOS_DRM_PLANAR_MAX]; @@ -280,10 +293,11 @@ enum drm_exynos_ipp_ctrl { */ struct drm_exynos_ipp_cmd_ctrl { __u32 prop_id; - enum drm_exynos_ipp_ctrl ctrl; + __u32 ctrl; }; #define DRM_EXYNOS_GEM_CREATE 0x00 +#define DRM_EXYNOS_GEM_MAP 0x01 /* Reserved 0x03 ~ 0x05 for exynos specific gem ioctl */ #define DRM_EXYNOS_GEM_GET 0x04 #define DRM_EXYNOS_VIDI_CONNECTION 0x07 @@ -301,7 +315,8 @@ struct drm_exynos_ipp_cmd_ctrl { #define DRM_IOCTL_EXYNOS_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + \ DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create) - +#define DRM_IOCTL_EXYNOS_GEM_MAP DRM_IOWR(DRM_COMMAND_BASE + \ + DRM_EXYNOS_GEM_MAP, struct drm_exynos_gem_map) #define DRM_IOCTL_EXYNOS_GEM_GET DRM_IOWR(DRM_COMMAND_BASE + \ DRM_EXYNOS_GEM_GET, struct drm_exynos_gem_info) diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index acf21026c78a..a5524cc95ff8 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -772,10 +772,12 @@ struct drm_i915_gem_execbuffer2 { #define I915_EXEC_HANDLE_LUT (1<<12) /** Used for switching BSD rings on the platforms with two BSD rings */ -#define I915_EXEC_BSD_MASK (3<<13) -#define I915_EXEC_BSD_DEFAULT (0<<13) /* default ping-pong mode */ -#define I915_EXEC_BSD_RING1 (1<<13) -#define I915_EXEC_BSD_RING2 (2<<13) +#define I915_EXEC_BSD_SHIFT (13) +#define I915_EXEC_BSD_MASK (3 << I915_EXEC_BSD_SHIFT) +/* default ping-pong mode */ +#define I915_EXEC_BSD_DEFAULT (0 << I915_EXEC_BSD_SHIFT) +#define I915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT) +#define I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT) /** Tell the kernel that the batchbuffer is processed by * the resource streamer. @@ -812,10 +814,35 @@ struct drm_i915_gem_busy { /** Handle of the buffer to check for busy */ __u32 handle; - /** Return busy status (1 if busy, 0 if idle). - * The high word is used to indicate on which rings the object - * currently resides: - * 16:31 - busy (r or r/w) rings (16 render, 17 bsd, 18 blt, etc) + /** Return busy status + * + * A return of 0 implies that the object is idle (after + * having flushed any pending activity), and a non-zero return that + * the object is still in-flight on the GPU. (The GPU has not yet + * signaled completion for all pending requests that reference the + * object.) + * + * The returned dword is split into two fields to indicate both + * the engines on which the object is being read, and the + * engine on which it is currently being written (if any). + * + * The low word (bits 0:15) indicate if the object is being written + * to by any engine (there can only be one, as the GEM implicit + * synchronisation rules force writes to be serialised). Only the + * engine for the last write is reported. + * + * The high word (bits 16:31) are a bitmask of which engines are + * currently reading from the object. Multiple engines may be + * reading from the object simultaneously. + * + * The value of each engine is the same as specified in the + * EXECBUFFER2 ioctl, i.e. I915_EXEC_RENDER, I915_EXEC_BSD etc. + * Note I915_EXEC_DEFAULT is a symbolic value and is mapped to + * the I915_EXEC_RENDER engine for execution, and so it is never + * reported as active itself. Some hardware may have parallel + * execution engines, e.g. multiple media engines, which are + * mapped to the same identifier in the EXECBUFFER2 ioctl and + * so are not separately reported for busyness. */ __u32 busy; }; diff --git a/include/uapi/drm/msm_drm.h b/include/uapi/drm/msm_drm.h index 81e6e0d1d360..254d3e92d18e 100644 --- a/include/uapi/drm/msm_drm.h +++ b/include/uapi/drm/msm_drm.h @@ -50,6 +50,8 @@ struct drm_msm_timespec { #define MSM_PARAM_GPU_ID 0x01 #define MSM_PARAM_GMEM_SIZE 0x02 #define MSM_PARAM_CHIP_ID 0x03 +#define MSM_PARAM_MAX_FREQ 0x04 +#define MSM_PARAM_TIMESTAMP 0x05 struct drm_msm_param { __u32 pipe; /* in, MSM_PIPE_x */ diff --git a/include/uapi/linux/dma-buf.h b/include/uapi/linux/dma-buf.h new file mode 100644 index 000000000000..fb0dedb7c121 --- /dev/null +++ b/include/uapi/linux/dma-buf.h @@ -0,0 +1,40 @@ +/* + * Framework for buffer objects that can be shared across devices/subsystems. + * + * Copyright(C) 2015 Intel Ltd + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _DMA_BUF_UAPI_H_ +#define _DMA_BUF_UAPI_H_ + +#include <linux/types.h> + +/* begin/end dma-buf functions used for userspace mmap. */ +struct dma_buf_sync { + __u64 flags; +}; + +#define DMA_BUF_SYNC_READ (1 << 0) +#define DMA_BUF_SYNC_WRITE (2 << 0) +#define DMA_BUF_SYNC_RW (DMA_BUF_SYNC_READ | DMA_BUF_SYNC_WRITE) +#define DMA_BUF_SYNC_START (0 << 2) +#define DMA_BUF_SYNC_END (1 << 2) +#define DMA_BUF_SYNC_VALID_FLAGS_MASK \ + (DMA_BUF_SYNC_RW | DMA_BUF_SYNC_END) + +#define DMA_BUF_BASE 'b' +#define DMA_BUF_IOCTL_SYNC _IOW(DMA_BUF_BASE, 0, struct dma_buf_sync) + +#endif |