1 files changed, 0 insertions, 162 deletions
diff --git a/tools/perf/pmu-events/arch/x86/amdfam17h/memory.json b/tools/perf/pmu-events/arch/x86/amdfam17h/memory.json
deleted file mode 100644
index fa2d60d4def0..000000000000
--- a/tools/perf/pmu-events/arch/x86/amdfam17h/memory.json
+++ /dev/null
@@ -1,162 +0,0 @@
-[
-  {
-    "EventName": "ls_locks.bus_lock",
-    "EventCode": "0x25",
-    "BriefDescription": "Bus lock when a locked operations crosses a cache boundary or is done on an uncacheable memory type.",
-    "PublicDescription": "Bus lock when a locked operations crosses a cache boundary or is done on an uncacheable memory type.",
-    "UMask": "0x1"
-  },
-  {
-    "EventName": "ls_dispatch.ld_st_dispatch",
-    "EventCode": "0x29",
-    "BriefDescription": "Load-op-Stores.",
-    "PublicDescription": "Counts the number of operations dispatched to the LS unit. Unit Masks ADDed. Load-op-Stores.",
-    "UMask": "0x4"
-  },
-  {
-    "EventName": "ls_dispatch.store_dispatch",
-    "EventCode": "0x29",
-    "BriefDescription": "Counts the number of operations dispatched to the LS unit. Unit Masks ADDed.",
-    "PublicDescription": "Counts the number of operations dispatched to the LS unit. Unit Masks ADDed.",
-    "UMask": "0x2"
-  },
-  {
-    "EventName": "ls_dispatch.ld_dispatch",
-    "EventCode": "0x29",
-    "BriefDescription": "Counts the number of operations dispatched to the LS unit. Unit Masks ADDed.",
-    "PublicDescription": "Counts the number of operations dispatched to the LS unit. Unit Masks ADDed.",
-    "UMask": "0x1"
-  },
-  {
-    "EventName": "ls_stlf",
-    "EventCode": "0x35",
-    "BriefDescription": "Number of STLF hits."
-  },
-  {
-    "EventName": "ls_dc_accesses",
-    "EventCode": "0x40",
-    "BriefDescription": "The number of accesses to the data cache for load and store references. This may include certain microcode scratchpad accesses, although these are generally rare. Each increment represents an eight-byte access, although the instruction may only be accessing a portion of that. This event is a speculative event."
-  },
-  {
-    "EventName": "ls_l1_d_tlb_miss.all",
-    "EventCode": "0x45",
-    "BriefDescription": "L1 DTLB Miss or Reload off all sizes.",
-    "PublicDescription": "L1 DTLB Miss or Reload off all sizes.",
-    "UMask": "0xff"
-  },
-  {
-    "EventName": "ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss",
-    "EventCode": "0x45",
-    "BriefDescription": "L1 DTLB Miss of a page of 1G size.",
-    "PublicDescription": "L1 DTLB Miss of a page of 1G size.",
-    "UMask": "0x80"
-  },
-  {
-    "EventName": "ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss",
-    "EventCode": "0x45",
-    "BriefDescription": "L1 DTLB Miss of a page of 2M size.",
-    "PublicDescription": "L1 DTLB Miss of a page of 2M size.",
-    "UMask": "0x40"
-  },
-  {
-    "EventName": "ls_l1_d_tlb_miss.tlb_reload_32k_l2_miss",
-    "EventCode": "0x45",
-    "BriefDescription": "L1 DTLB Miss of a page of 32K size.",
-    "PublicDescription": "L1 DTLB Miss of a page of 32K size.",
-    "UMask": "0x20"
-  },
-  {
-    "EventName": "ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss",
-    "EventCode": "0x45",
-    "BriefDescription": "L1 DTLB Miss of a page of 4K size.",
-    "PublicDescription": "L1 DTLB Miss of a page of 4K size.",
-    "UMask": "0x10"
-  },
-  {
-    "EventName": "ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit",
-    "EventCode": "0x45",
-    "BriefDescription": "L1 DTLB Reload of a page of 1G size.",
-    "PublicDescription": "L1 DTLB Reload of a page of 1G size.",
-    "UMask": "0x8"
-  },
-  {
-    "EventName": "ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit",
-    "EventCode": "0x45",
-    "BriefDescription": "L1 DTLB Reload of a page of 2M size.",
-    "PublicDescription": "L1 DTLB Reload of a page of 2M size.",
-    "UMask": "0x4"
-  },
-  {
-    "EventName": "ls_l1_d_tlb_miss.tlb_reload_32k_l2_hit",
-    "EventCode": "0x45",
-    "BriefDescription": "L1 DTLB Reload of a page of 32K size.",
-    "PublicDescription": "L1 DTLB Reload of a page of 32K size.",
-    "UMask": "0x2"
-  },
-  {
-    "EventName": "ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit",
-    "EventCode": "0x45",
-    "BriefDescription": "L1 DTLB Reload of a page of 4K size.",
-    "PublicDescription": "L1 DTLB Reload of a page of 4K size.",
-    "UMask": "0x1"
-  },
-  {
-    "EventName": "ls_tablewalker.perf_mon_tablewalk_alloc_iside",
-    "EventCode": "0x46",
-    "BriefDescription": "Tablewalker allocation.",
-    "PublicDescription": "Tablewalker allocation.",
-    "UMask": "0xc"
-  },
-  {
-    "EventName": "ls_tablewalker.perf_mon_tablewalk_alloc_dside",
-    "EventCode": "0x46",
-    "BriefDescription": "Tablewalker allocation.",
-    "PublicDescription": "Tablewalker allocation.",
-    "UMask": "0x3"
-  },
-  {
-    "EventName": "ls_misal_accesses",
-    "EventCode": "0x47",
-    "BriefDescription": "Misaligned loads."
-  },
-  {
-    "EventName": "ls_pref_instr_disp.prefetch_nta",
-    "EventCode": "0x4b",
-    "BriefDescription": "Software Prefetch Instructions (PREFETCHNTA instruction) Dispatched.",
-    "PublicDescription": "Software Prefetch Instructions (PREFETCHNTA instruction) Dispatched.",
-    "UMask": "0x4"
-  },
-  {
-    "EventName": "ls_pref_instr_disp.store_prefetch_w",
-    "EventCode": "0x4b",
-    "BriefDescription": "Software Prefetch Instructions (3DNow PREFETCHW instruction) Dispatched.",
-    "PublicDescription": "Software Prefetch Instructions (3DNow PREFETCHW instruction) Dispatched.",
-    "UMask": "0x2"
-  },
-  {
-    "EventName": "ls_pref_instr_disp.load_prefetch_w",
-    "EventCode": "0x4b",
-    "BriefDescription": "Prefetch, Prefetch_T0_T1_T2.",
-    "PublicDescription": "Software Prefetch Instructions Dispatched. Prefetch, Prefetch_T0_T1_T2.",
-    "UMask": "0x1"
-  },
-  {
-    "EventName": "ls_inef_sw_pref.mab_mch_cnt",
-    "EventCode": "0x52",
-    "BriefDescription": "The number of software prefetches that did not fetch data outside of the processor core.",
-    "PublicDescription": "The number of software prefetches that did not fetch data outside of the processor core.",
-    "UMask": "0x2"
-  },
-  {
-    "EventName": "ls_inef_sw_pref.data_pipe_sw_pf_dc_hit",
-    "EventCode": "0x52",
-    "BriefDescription": "The number of software prefetches that did not fetch data outside of the processor core.",
-    "PublicDescription": "The number of software prefetches that did not fetch data outside of the processor core.",
-    "UMask": "0x1"
-  },
-  {
-    "EventName": "ls_not_halted_cyc",
-    "EventCode": "0x76",
-    "BriefDescription": "Cycles not in Halt."
-  }
-]