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-rw-r--r--tools/perf/pmu-events/arch/x86/bonnell/memory.json154
1 files changed, 77 insertions, 77 deletions
diff --git a/tools/perf/pmu-events/arch/x86/bonnell/memory.json b/tools/perf/pmu-events/arch/x86/bonnell/memory.json
index 3ae843b20c8a..f8b45b6fb4d3 100644
--- a/tools/perf/pmu-events/arch/x86/bonnell/memory.json
+++ b/tools/perf/pmu-events/arch/x86/bonnell/memory.json
@@ -1,154 +1,154 @@
[
{
- "EventCode": "0x5",
+ "BriefDescription": "Nonzero segbase 1 bubble",
"Counter": "0,1",
- "UMask": "0xf",
- "EventName": "MISALIGN_MEM_REF.SPLIT",
- "SampleAfterValue": "200000",
- "BriefDescription": "Memory references that cross an 8-byte boundary."
- },
- {
"EventCode": "0x5",
- "Counter": "0,1",
- "UMask": "0x9",
- "EventName": "MISALIGN_MEM_REF.LD_SPLIT",
+ "EventName": "MISALIGN_MEM_REF.BUBBLE",
"SampleAfterValue": "200000",
- "BriefDescription": "Load splits"
+ "UMask": "0x97"
},
{
- "EventCode": "0x5",
+ "BriefDescription": "Nonzero segbase load 1 bubble",
"Counter": "0,1",
- "UMask": "0xa",
- "EventName": "MISALIGN_MEM_REF.ST_SPLIT",
+ "EventCode": "0x5",
+ "EventName": "MISALIGN_MEM_REF.LD_BUBBLE",
"SampleAfterValue": "200000",
- "BriefDescription": "Store splits"
+ "UMask": "0x91"
},
{
- "EventCode": "0x5",
+ "BriefDescription": "Load splits",
"Counter": "0,1",
- "UMask": "0x8f",
- "EventName": "MISALIGN_MEM_REF.SPLIT.AR",
+ "EventCode": "0x5",
+ "EventName": "MISALIGN_MEM_REF.LD_SPLIT",
"SampleAfterValue": "200000",
- "BriefDescription": "Memory references that cross an 8-byte boundary (At Retirement)"
+ "UMask": "0x9"
},
{
- "EventCode": "0x5",
+ "BriefDescription": "Load splits (At Retirement)",
"Counter": "0,1",
- "UMask": "0x89",
+ "EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.LD_SPLIT.AR",
"SampleAfterValue": "200000",
- "BriefDescription": "Load splits (At Retirement)"
+ "UMask": "0x89"
},
{
- "EventCode": "0x5",
+ "BriefDescription": "Nonzero segbase ld-op-st 1 bubble",
"Counter": "0,1",
- "UMask": "0x8a",
- "EventName": "MISALIGN_MEM_REF.ST_SPLIT.AR",
+ "EventCode": "0x5",
+ "EventName": "MISALIGN_MEM_REF.RMW_BUBBLE",
"SampleAfterValue": "200000",
- "BriefDescription": "Store splits (Ar Retirement)"
+ "UMask": "0x94"
},
{
- "EventCode": "0x5",
+ "BriefDescription": "ld-op-st splits",
"Counter": "0,1",
- "UMask": "0x8c",
+ "EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.RMW_SPLIT",
"SampleAfterValue": "200000",
- "BriefDescription": "ld-op-st splits"
+ "UMask": "0x8c"
},
{
- "EventCode": "0x5",
+ "BriefDescription": "Memory references that cross an 8-byte boundary.",
"Counter": "0,1",
- "UMask": "0x97",
- "EventName": "MISALIGN_MEM_REF.BUBBLE",
+ "EventCode": "0x5",
+ "EventName": "MISALIGN_MEM_REF.SPLIT",
"SampleAfterValue": "200000",
- "BriefDescription": "Nonzero segbase 1 bubble"
+ "UMask": "0xf"
},
{
- "EventCode": "0x5",
+ "BriefDescription": "Memory references that cross an 8-byte boundary (At Retirement)",
"Counter": "0,1",
- "UMask": "0x91",
- "EventName": "MISALIGN_MEM_REF.LD_BUBBLE",
+ "EventCode": "0x5",
+ "EventName": "MISALIGN_MEM_REF.SPLIT.AR",
"SampleAfterValue": "200000",
- "BriefDescription": "Nonzero segbase load 1 bubble"
+ "UMask": "0x8f"
},
{
- "EventCode": "0x5",
+ "BriefDescription": "Nonzero segbase store 1 bubble",
"Counter": "0,1",
- "UMask": "0x92",
+ "EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.ST_BUBBLE",
"SampleAfterValue": "200000",
- "BriefDescription": "Nonzero segbase store 1 bubble"
+ "UMask": "0x92"
},
{
- "EventCode": "0x5",
+ "BriefDescription": "Store splits",
"Counter": "0,1",
- "UMask": "0x94",
- "EventName": "MISALIGN_MEM_REF.RMW_BUBBLE",
+ "EventCode": "0x5",
+ "EventName": "MISALIGN_MEM_REF.ST_SPLIT",
"SampleAfterValue": "200000",
- "BriefDescription": "Nonzero segbase ld-op-st 1 bubble"
+ "UMask": "0xa"
},
{
- "EventCode": "0x7",
+ "BriefDescription": "Store splits (Ar Retirement)",
"Counter": "0,1",
- "UMask": "0x81",
- "EventName": "PREFETCH.PREFETCHT0",
+ "EventCode": "0x5",
+ "EventName": "MISALIGN_MEM_REF.ST_SPLIT.AR",
"SampleAfterValue": "200000",
- "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed."
+ "UMask": "0x8a"
},
{
- "EventCode": "0x7",
+ "BriefDescription": "L1 hardware prefetch request",
"Counter": "0,1",
- "UMask": "0x82",
- "EventName": "PREFETCH.PREFETCHT1",
- "SampleAfterValue": "200000",
- "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 instructions executed."
+ "EventCode": "0x7",
+ "EventName": "PREFETCH.HW_PREFETCH",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x10"
},
{
- "EventCode": "0x7",
+ "BriefDescription": "Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed",
"Counter": "0,1",
- "UMask": "0x84",
- "EventName": "PREFETCH.PREFETCHT2",
+ "EventCode": "0x7",
+ "EventName": "PREFETCH.PREFETCHNTA",
"SampleAfterValue": "200000",
- "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT2 instructions executed."
+ "UMask": "0x88"
},
{
- "EventCode": "0x7",
+ "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed.",
"Counter": "0,1",
- "UMask": "0x86",
- "EventName": "PREFETCH.SW_L2",
+ "EventCode": "0x7",
+ "EventName": "PREFETCH.PREFETCHT0",
"SampleAfterValue": "200000",
- "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executed"
+ "UMask": "0x81"
},
{
- "EventCode": "0x7",
+ "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 instructions executed.",
"Counter": "0,1",
- "UMask": "0x88",
- "EventName": "PREFETCH.PREFETCHNTA",
+ "EventCode": "0x7",
+ "EventName": "PREFETCH.PREFETCHT1",
"SampleAfterValue": "200000",
- "BriefDescription": "Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed"
+ "UMask": "0x82"
},
{
- "EventCode": "0x7",
+ "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT2 instructions executed.",
"Counter": "0,1",
- "UMask": "0x10",
- "EventName": "PREFETCH.HW_PREFETCH",
- "SampleAfterValue": "2000000",
- "BriefDescription": "L1 hardware prefetch request"
+ "EventCode": "0x7",
+ "EventName": "PREFETCH.PREFETCHT2",
+ "SampleAfterValue": "200000",
+ "UMask": "0x84"
},
{
- "EventCode": "0x7",
+ "BriefDescription": "Any Software prefetch",
"Counter": "0,1",
- "UMask": "0xf",
+ "EventCode": "0x7",
"EventName": "PREFETCH.SOFTWARE_PREFETCH",
"SampleAfterValue": "200000",
- "BriefDescription": "Any Software prefetch"
+ "UMask": "0xf"
},
{
- "EventCode": "0x7",
+ "BriefDescription": "Any Software prefetch",
"Counter": "0,1",
- "UMask": "0x8f",
+ "EventCode": "0x7",
"EventName": "PREFETCH.SOFTWARE_PREFETCH.AR",
"SampleAfterValue": "200000",
- "BriefDescription": "Any Software prefetch"
+ "UMask": "0x8f"
+ },
+ {
+ "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executed",
+ "Counter": "0,1",
+ "EventCode": "0x7",
+ "EventName": "PREFETCH.SW_L2",
+ "SampleAfterValue": "200000",
+ "UMask": "0x86"
}
-] \ No newline at end of file
+]
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