diff options
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/icelake/other.json')
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/icelake/other.json | 622 |
1 files changed, 311 insertions, 311 deletions
diff --git a/tools/perf/pmu-events/arch/x86/icelake/other.json b/tools/perf/pmu-events/arch/x86/icelake/other.json index a806b00f8616..10e8582774ce 100644 --- a/tools/perf/pmu-events/arch/x86/icelake/other.json +++ b/tools/perf/pmu-events/arch/x86/icelake/other.json @@ -1,57 +1,60 @@ [ { - "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", + "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc1", + "EventName": "ASSISTS.ANY", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hardware Examples include AD (page Access Dirty), FP and AVX related assists.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x7" + }, + { + "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C8000", - "Offcore": "1", + "EventCode": "0x28", + "EventName": "CORE_POWER.LVL0_TURBO_LICENSE", "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", + "PublicDescription": "Counts Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.", + "SampleAfterValue": "200003", "Speculative": "1", - "UMask": "0x1" + "UMask": "0x7" }, { - "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that DRAM supplied the request.", + "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_RFO.DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0184000020", - "Offcore": "1", + "EventCode": "0x28", + "EventName": "CORE_POWER.LVL1_TURBO_LICENSE", "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", + "PublicDescription": "Counts Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.", + "SampleAfterValue": "200003", "Speculative": "1", - "UMask": "0x1" + "UMask": "0x18" }, { - "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that DRAM supplied the request.", + "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0184008000", - "Offcore": "1", + "EventCode": "0x28", + "EventName": "CORE_POWER.LVL2_TURBO_LICENSE", "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", + "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchtecture). This includes high current AVX 512-bit instructions.", + "SampleAfterValue": "200003", "Speculative": "1", - "UMask": "0x1" + "UMask": "0x20" }, { - "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that DRAM supplied the request.", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_DATA_RD.LOCAL_DRAM", + "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0184000010", + "MSRValue": "0x10004", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -60,13 +63,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the request.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "EventName": "OCR.DEMAND_CODE_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10003C0002", + "MSRValue": "0x184000004", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -75,25 +78,28 @@ "UMask": "0x1" }, { - "BriefDescription": "Number of PREFETCHNTA instructions executed.", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent or not.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.NTA", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.ANY", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FC03C0004", + "Offcore": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "Speculative": "1", "UMask": "0x1" }, { - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0002", + "MSRValue": "0x10003C0004", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -102,13 +108,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response.", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010004", + "MSRValue": "0x4003C0004", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -117,13 +123,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was sent or not.", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.ANY", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC03C0400", + "MSRValue": "0x2003C0004", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -132,13 +138,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that DRAM supplied the request.", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.DRAM", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0184008000", + "MSRValue": "0x1003C0004", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -147,13 +153,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_SENT", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010002", + "MSRValue": "0x1E003C0004", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -162,13 +168,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the request.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.L3_HIT.SNOOP_MISS", + "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C8000", + "MSRValue": "0x184000004", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -177,13 +183,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", + "BriefDescription": "Counts demand data reads that have any type of response.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED", + "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0002", + "MSRValue": "0x10001", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -192,25 +198,13 @@ "UMask": "0x1" }, { - "BriefDescription": "TMA slots wasted due to incorrect speculation by branch mispredictions", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa4", - "EventName": "TOPDOWN.BR_MISPREDICT_SLOTS", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Number of TMA slots that were wasted due to incorrect speculation by branch mispredictions. This event estimates number of operations that were issued but not retired from the specualtive path as well as the out-of-order engine recovery past a branch misprediction.", - "SampleAfterValue": "10000003", - "Speculative": "1", - "UMask": "0x8" - }, - { - "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", + "BriefDescription": "Counts demand data reads that DRAM supplied the request.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", + "EventName": "OCR.DEMAND_DATA_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0010", + "MSRValue": "0x184000001", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -219,13 +213,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts streaming stores that have any type of response.", + "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was sent or not.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.ANY", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010800", + "MSRValue": "0x3FC03C0001", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -234,13 +228,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts streaming stores that DRAM supplied the request.", + "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.STREAMING_WR.DRAM", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0184000800", + "MSRValue": "0x10003C0001", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -249,13 +243,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that have any type of response.", + "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_RFO.ANY_RESPONSE", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010020", + "MSRValue": "0x4003C0001", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -264,13 +258,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", + "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10003C0001", + "MSRValue": "0x2003C0001", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -279,13 +273,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that DRAM supplied the request.", + "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_DATA_RD.DRAM", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0184000010", + "MSRValue": "0x1003C0001", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -294,13 +288,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was sent.", + "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was sent.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.L3_HIT.SNOOP_SENT", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_SENT", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1E003C8000", + "MSRValue": "0x1E003C0001", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -309,13 +303,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that have any type of response.", + "BriefDescription": "Counts demand data reads that DRAM supplied the request.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_DATA_RD.ANY_RESPONSE", + "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010010", + "MSRValue": "0x184000001", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -324,13 +318,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent or not.", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.ANY", + "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC03C0010", + "MSRValue": "0x10002", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -339,25 +333,28 @@ "UMask": "0x1" }, { - "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x28", - "EventName": "CORE_POWER.LVL1_TURBO_LICENSE", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000002", + "Offcore": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.", - "SampleAfterValue": "200003", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x18" + "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent or not.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", + "EventName": "OCR.DEMAND_RFO.L3_HIT.ANY", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0001", + "MSRValue": "0x3FC03C0002", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -366,13 +363,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was sent.", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_SENT", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1E003C0001", + "MSRValue": "0x10003C0002", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -381,13 +378,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HITM", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10003C0010", + "MSRValue": "0x4003C0002", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -396,13 +393,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads that DRAM supplied the request.", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.DRAM", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0184000001", + "MSRValue": "0x2003C0002", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -411,13 +408,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts streaming stores that DRAM supplied the request.", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.STREAMING_WR.LOCAL_DRAM", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0184000800", + "MSRValue": "0x1003C0002", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -426,13 +423,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the request.", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_SENT", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0184000004", + "MSRValue": "0x1E003C0002", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -441,13 +438,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", + "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0004", + "MSRValue": "0x184000002", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -456,13 +453,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that DRAM supplied the request.", + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that have any type of response.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_RFO.LOCAL_DRAM", + "EventName": "OCR.HWPF_L1D_AND_SWPF.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0184000020", + "MSRValue": "0x10400", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -471,13 +468,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the request.", + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.DRAM", + "EventName": "OCR.HWPF_L1D_AND_SWPF.DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0184000004", + "MSRValue": "0x184000400", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -486,13 +483,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was sent or not.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD", + "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.ANY", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0002", + "MSRValue": "0x3FC03C0400", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -507,7 +504,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0400", + "MSRValue": "0x2003C0400", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -516,13 +513,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent.", + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_SENT", + "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1E003C0020", + "MSRValue": "0x1003C0400", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -531,13 +528,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "EventName": "OCR.HWPF_L1D_AND_SWPF.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0010", + "MSRValue": "0x184000400", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -546,13 +543,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that have any type of response.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "EventName": "OCR.HWPF_L2_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0001", + "MSRValue": "0x10010", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -561,13 +558,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent or not.", + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that DRAM supplied the request.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_RFO.L3_HIT.ANY", + "EventName": "OCR.HWPF_L2_DATA_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC03C0020", + "MSRValue": "0x184000010", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -576,13 +573,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent or not.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.ANY", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0001", + "MSRValue": "0x3FC03C0010", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -591,13 +588,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.L3_HIT.SNOOP_HIT_NO_FWD", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C8000", + "MSRValue": "0x10003C0010", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -606,36 +603,28 @@ "UMask": "0x1" }, { - "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event", - "CollectPEBSRecord": "2", - "Counter": "35", - "EventName": "TOPDOWN.SLOTS", - "PEBScounters": "35", - "PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).", - "SampleAfterValue": "10000003", - "Speculative": "1", - "UMask": "0x4" - }, - { - "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.T1_T2", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0010", + "Offcore": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x4" + "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was sent or not.", + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.ANY", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC03C0001", + "MSRValue": "0x2003C0010", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -644,13 +633,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request.", + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L1D_AND_SWPF.LOCAL_DRAM", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0184000400", + "MSRValue": "0x1003C0010", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -659,25 +648,13 @@ "UMask": "0x1" }, { - "BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa4", - "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of Top-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources.", - "SampleAfterValue": "10000003", - "Speculative": "1", - "UMask": "0x2" - }, - { - "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_NOT_NEEDED", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_SENT", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0020", + "MSRValue": "0x1E003C0010", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -686,25 +663,28 @@ "UMask": "0x1" }, { - "BriefDescription": "Number of PREFETCHT0 instructions executed.", + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that DRAM supplied the request.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.T0", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L2_DATA_RD.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000010", + "Offcore": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x2" + "UMask": "0x1" }, { - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", + "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that have any type of response.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM", + "EventName": "OCR.HWPF_L2_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10003C0004", + "MSRValue": "0x10020", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -713,13 +693,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads that have any type of response.", + "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that DRAM supplied the request.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", + "EventName": "OCR.HWPF_L2_RFO.DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010001", + "MSRValue": "0x184000020", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -728,13 +708,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", + "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent or not.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.ANY", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0004", + "MSRValue": "0x3FC03C0020", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -758,13 +738,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that have any type of response.", + "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.ANY_RESPONSE", + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000018000", + "MSRValue": "0x4003C0020", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -773,25 +753,28 @@ "UMask": "0x1" }, { - "BriefDescription": "Number of PREFETCHW instructions executed.", + "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0020", + "Offcore": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of PREFETCHW instructions executed.", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x8" + "UMask": "0x1" }, { - "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent.", + "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_SENT", + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1E003C0010", + "MSRValue": "0x1003C0020", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -800,13 +783,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request.", + "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L1D_AND_SWPF.DRAM", + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_SENT", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0184000400", + "MSRValue": "0x1E003C0020", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -815,13 +798,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request.", + "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that DRAM supplied the request.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.DRAM", + "EventName": "OCR.HWPF_L2_RFO.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0184000002", + "MSRValue": "0x184000020", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -830,25 +813,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc1", - "EventName": "ASSISTS.ANY", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hardware Examples include AD (page Access Dirty), FP and AVX related assists.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x7" - }, - { - "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", + "BriefDescription": "Counts hardware prefetches to the L3 only that hit a cacheline in the L3 where a snoop was sent or not.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_MISS", + "EventName": "OCR.HWPF_L3.L3_HIT.ANY", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0010", + "MSRValue": "0x3FC03C2380", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -857,13 +828,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent or not.", + "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that have any type of response.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.ANY", + "EventName": "OCR.OTHER.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC03C0004", + "MSRValue": "0x18000", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -872,25 +843,28 @@ "UMask": "0x1" }, { - "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.", + "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that DRAM supplied the request.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x28", - "EventName": "CORE_POWER.LVL2_TURBO_LICENSE", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.OTHER.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184008000", + "Offcore": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchtecture). This includes high current AVX 512-bit instructions.", - "SampleAfterValue": "200003", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x20" + "UMask": "0x1" }, { - "BriefDescription": "Counts streaming stores that hit a cacheline in the L3 where a snoop was sent or not.", + "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.STREAMING_WR.L3_HIT.ANY", + "EventName": "OCR.OTHER.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC03C0800", + "MSRValue": "0x4003C8000", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -899,13 +873,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", + "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_MISS", + "EventName": "OCR.OTHER.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0020", + "MSRValue": "0x2003C8000", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -914,13 +888,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads that DRAM supplied the request.", + "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM", + "EventName": "OCR.OTHER.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0184000001", + "MSRValue": "0x1003C8000", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -929,13 +903,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent.", + "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was sent.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_SENT", + "EventName": "OCR.OTHER.L3_HIT.SNOOP_SENT", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1E003C0004", + "MSRValue": "0x1E003C8000", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -944,13 +918,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent or not.", + "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that DRAM supplied the request.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT.ANY", + "EventName": "OCR.OTHER.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC03C0002", + "MSRValue": "0x184008000", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -959,13 +933,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts hardware prefetches to the L3 only that hit a cacheline in the L3 where a snoop was sent or not.", + "BriefDescription": "Counts streaming stores that have any type of response.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L3.L3_HIT.ANY", + "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC03C2380", + "MSRValue": "0x10800", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -974,25 +948,13 @@ "UMask": "0x1" }, { - "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa4", - "EventName": "TOPDOWN.SLOTS_P", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.", - "SampleAfterValue": "10000003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", + "BriefDescription": "Counts streaming stores that DRAM supplied the request.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_NOT_NEEDED", + "EventName": "OCR.STREAMING_WR.DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0400", + "MSRValue": "0x184000800", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -1001,13 +963,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent.", + "BriefDescription": "Counts streaming stores that hit a cacheline in the L3 where a snoop was sent or not.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_SENT", + "EventName": "OCR.STREAMING_WR.L3_HIT.ANY", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1E003C0002", + "MSRValue": "0x3FC03C0800", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -1016,13 +978,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that have any type of response.", + "BriefDescription": "Counts streaming stores that DRAM supplied the request.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L1D_AND_SWPF.ANY_RESPONSE", + "EventName": "OCR.STREAMING_WR.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010400", + "MSRValue": "0x184000800", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -1031,60 +993,98 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request.", + "BriefDescription": "Number of PREFETCHNTA instructions executed.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0184000002", - "Offcore": "1", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.NTA", "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.", "SampleAfterValue": "100003", "Speculative": "1", "UMask": "0x1" }, { - "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.", + "BriefDescription": "Number of PREFETCHW instructions executed.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x28", - "EventName": "CORE_POWER.LVL0_TURBO_LICENSE", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.", - "SampleAfterValue": "200003", + "PublicDescription": "Counts the number of PREFETCHW instructions executed.", + "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x7" + "UMask": "0x8" }, { - "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", + "BriefDescription": "Number of PREFETCHT0 instructions executed.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0020", - "Offcore": "1", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.T0", "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.", "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x1" + "UMask": "0x2" }, { - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", + "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0004", - "Offcore": "1", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.T1_T2", "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.", "SampleAfterValue": "100003", "Speculative": "1", + "UMask": "0x4" + }, + { + "BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa4", + "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of Top-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources.", + "SampleAfterValue": "10000003", + "Speculative": "1", + "UMask": "0x2" + }, + { + "BriefDescription": "TMA slots wasted due to incorrect speculation by branch mispredictions", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa4", + "EventName": "TOPDOWN.BR_MISPREDICT_SLOTS", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Number of TMA slots that were wasted due to incorrect speculation by branch mispredictions. This event estimates number of operations that were issued but not retired from the specualtive path as well as the out-of-order engine recovery past a branch misprediction.", + "SampleAfterValue": "10000003", + "Speculative": "1", + "UMask": "0x8" + }, + { + "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event", + "CollectPEBSRecord": "2", + "Counter": "Fixed counter 3", + "EventName": "TOPDOWN.SLOTS", + "PEBScounters": "35", + "PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).", + "SampleAfterValue": "10000003", + "Speculative": "1", + "UMask": "0x4" + }, + { + "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa4", + "EventName": "TOPDOWN.SLOTS_P", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.", + "SampleAfterValue": "10000003", + "Speculative": "1", "UMask": "0x1" } ]
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