diff options
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/silvermont/virtual-memory.json')
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/silvermont/virtual-memory.json | 78 |
1 files changed, 39 insertions, 39 deletions
diff --git a/tools/perf/pmu-events/arch/x86/silvermont/virtual-memory.json b/tools/perf/pmu-events/arch/x86/silvermont/virtual-memory.json index ad31479f8f60..b50cee3a5e4c 100644 --- a/tools/perf/pmu-events/arch/x86/silvermont/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/silvermont/virtual-memory.json @@ -1,69 +1,69 @@ [ { - "PEBS": "1", - "PublicDescription": "This event counts the number of load ops retired that had DTLB miss.", - "EventCode": "0x04", + "BriefDescription": "Loads missed DTLB", "Counter": "0,1", - "UMask": "0x8", + "EventCode": "0x04", "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS", + "PEBS": "1", + "PublicDescription": "This event counts the number of load ops retired that had DTLB miss.", "SampleAfterValue": "200003", - "BriefDescription": "Loads missed DTLB" + "UMask": "0x8" }, { - "PublicDescription": "This event counts when a data (D) page walk is completed or started. Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks.", - "EventCode": "0x05", + "BriefDescription": "Total cycles for all the page walks. (I-side and D-side)", "Counter": "0,1", - "UMask": "0x1", - "EventName": "PAGE_WALKS.D_SIDE_WALKS", - "SampleAfterValue": "100003", - "BriefDescription": "D-side page-walks", - "EdgeDetect": "1" + "EventCode": "0x05", + "EventName": "PAGE_WALKS.CYCLES", + "PublicDescription": "This event counts every cycle when a data (D) page walk or instruction (I) page walk is in progress. Since a pagewalk implies a TLB miss, the approximate cost of a TLB miss can be determined from this event.", + "SampleAfterValue": "200003", + "UMask": "0x3" }, { - "PublicDescription": "This event counts every cycle when a D-side (walks due to a load) page walk is in progress. Page walk duration divided by number of page walks is the average duration of page-walks.", - "EventCode": "0x05", + "BriefDescription": "Duration of D-side page-walks in core cycles", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x05", "EventName": "PAGE_WALKS.D_SIDE_CYCLES", + "PublicDescription": "This event counts every cycle when a D-side (walks due to a load) page walk is in progress. Page walk duration divided by number of page walks is the average duration of page-walks.", "SampleAfterValue": "200003", - "BriefDescription": "Duration of D-side page-walks in core cycles" + "UMask": "0x1" }, { - "PublicDescription": "This event counts when an instruction (I) page walk is completed or started. Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks.", - "EventCode": "0x05", + "BriefDescription": "D-side page-walks", "Counter": "0,1", - "UMask": "0x2", - "EventName": "PAGE_WALKS.I_SIDE_WALKS", + "EdgeDetect": "1", + "EventCode": "0x05", + "EventName": "PAGE_WALKS.D_SIDE_WALKS", + "PublicDescription": "This event counts when a data (D) page walk is completed or started. Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks.", "SampleAfterValue": "100003", - "BriefDescription": "I-side page-walks", - "EdgeDetect": "1" + "UMask": "0x1" }, { - "PublicDescription": "This event counts every cycle when a I-side (walks due to an instruction fetch) page walk is in progress. Page walk duration divided by number of page walks is the average duration of page-walks.", - "EventCode": "0x05", + "BriefDescription": "Duration of I-side page-walks in core cycles", "Counter": "0,1", - "UMask": "0x2", + "EventCode": "0x05", "EventName": "PAGE_WALKS.I_SIDE_CYCLES", + "PublicDescription": "This event counts every cycle when a I-side (walks due to an instruction fetch) page walk is in progress. Page walk duration divided by number of page walks is the average duration of page-walks.", "SampleAfterValue": "200003", - "BriefDescription": "Duration of I-side page-walks in core cycles" + "UMask": "0x2" }, { - "PublicDescription": "This event counts when a data (D) page walk or an instruction (I) page walk is completed or started. Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks.", - "EventCode": "0x05", + "BriefDescription": "I-side page-walks", "Counter": "0,1", - "UMask": "0x3", - "EventName": "PAGE_WALKS.WALKS", + "EdgeDetect": "1", + "EventCode": "0x05", + "EventName": "PAGE_WALKS.I_SIDE_WALKS", + "PublicDescription": "This event counts when an instruction (I) page walk is completed or started. Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks.", "SampleAfterValue": "100003", - "BriefDescription": "Total page walks that are completed (I-side and D-side)", - "EdgeDetect": "1" + "UMask": "0x2" }, { - "PublicDescription": "This event counts every cycle when a data (D) page walk or instruction (I) page walk is in progress. Since a pagewalk implies a TLB miss, the approximate cost of a TLB miss can be determined from this event.", - "EventCode": "0x05", + "BriefDescription": "Total page walks that are completed (I-side and D-side)", "Counter": "0,1", - "UMask": "0x3", - "EventName": "PAGE_WALKS.CYCLES", - "SampleAfterValue": "200003", - "BriefDescription": "Total cycles for all the page walks. (I-side and D-side)" + "EdgeDetect": "1", + "EventCode": "0x05", + "EventName": "PAGE_WALKS.WALKS", + "PublicDescription": "This event counts when a data (D) page walk or an instruction (I) page walk is completed or started. Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks.", + "SampleAfterValue": "100003", + "UMask": "0x3" } -]
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