diff options
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/snowridgex/pipeline.json')
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/snowridgex/pipeline.json | 98 |
1 files changed, 38 insertions, 60 deletions
diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/pipeline.json b/tools/perf/pmu-events/arch/x86/snowridgex/pipeline.json index 38dc8044767b..09919fdb9a38 100644 --- a/tools/perf/pmu-events/arch/x86/snowridgex/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/snowridgex/pipeline.json @@ -170,7 +170,7 @@ "Counter": "0,1,2,3", "EventCode": "0xe8", "EventName": "BTCLEAR.ANY", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the total number of BTCLEARS which occurs when the Branch Target Buffer (BTB) predicts a taken branch.", "SampleAfterValue": "200003" @@ -180,9 +180,9 @@ "CollectPEBSRecord": "2", "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.CORE", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "33", - "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1.", + "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1.", "SampleAfterValue": "2000003", "UMask": "0x2" }, @@ -192,9 +192,9 @@ "Counter": "0,1,2,3", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.CORE_P", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses a programmable general purpose performance counter.", + "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses a programmable general purpose performance counter.", "SampleAfterValue": "2000003" }, { @@ -203,7 +203,7 @@ "Counter": "0,1,2,3", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.REF", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses fixed counter 2.", "SampleAfterValue": "2000003", @@ -214,7 +214,7 @@ "CollectPEBSRecord": "2", "Counter": "Fixed counter 2", "EventName": "CPU_CLK_UNHALTED.REF_TSC", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "34", "PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses fixed counter 2.", "SampleAfterValue": "2000003", @@ -227,7 +227,7 @@ "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.REF_TSC_P", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses a programmable general purpose performance counter.", + "PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses a programmable general purpose performance counter.", "SampleAfterValue": "2000003", "UMask": "0x1" }, @@ -237,18 +237,19 @@ "Counter": "0,1,2,3", "EventCode": "0xcd", "EventName": "CYCLES_DIV_BUSY.ANY", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "SampleAfterValue": "2000003" }, { - "BriefDescription": "Counts the number of cycles the integer divider is busy. Does not imply a stall waiting for the divider.", + "BriefDescription": "Counts the number of cycles the integer divider is busy.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xcd", "EventName": "CYCLES_DIV_BUSY.IDIV", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of cycles the integer divider is busy. Does not imply a stall waiting for the divider.", "SampleAfterValue": "200003", "UMask": "0x1" }, @@ -324,7 +325,7 @@ "Counter": "0,1,2,3", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.ANY", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "SampleAfterValue": "20003" }, @@ -334,7 +335,7 @@ "Counter": "0,1,2,3", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.DISAMBIGUATION", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "SampleAfterValue": "20003", "UMask": "0x8" @@ -345,18 +346,18 @@ "Counter": "0,1,2,3", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.PAGE_FAULT", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "SampleAfterValue": "20003", "UMask": "0x20" }, { - "BriefDescription": "Counts the number of machine clears due typically to program modifying data (self modifying code) within 1K of a recently fetched code page.", + "BriefDescription": "Counts the number of machine clears due to program modifying data (self modifying code) within 1K of a recently fetched code page.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.SMC", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "SampleAfterValue": "20003", "UMask": "0x1" @@ -367,7 +368,7 @@ "Counter": "0,1,2,3", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.ALL", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ) even if an FE_bound event occurs during this period. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.", "SampleAfterValue": "1000003", @@ -401,7 +402,7 @@ "Counter": "0,1,2,3", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.MISPREDICT", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003", "UMask": "0x4" @@ -412,7 +413,7 @@ "Counter": "0,1,2,3", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.MONUKE", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003", "UMask": "0x2" @@ -423,7 +424,7 @@ "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.ALL", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003" }, @@ -433,7 +434,7 @@ "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003", "UMask": "0x1" @@ -444,7 +445,7 @@ "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.MEM_SCHEDULER", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003", "UMask": "0x2" @@ -455,7 +456,7 @@ "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003", "UMask": "0x8" @@ -466,7 +467,7 @@ "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.REGISTER", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003", "UMask": "0x20" @@ -477,7 +478,7 @@ "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.REORDER_BUFFER", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003", "UMask": "0x40" @@ -488,7 +489,7 @@ "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.SERIALIZATION", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003", "UMask": "0x10" @@ -499,18 +500,18 @@ "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.STORE_BUFFER", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003", "UMask": "0x4" }, { - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to frontend stalls.", + "BriefDescription": "Counts the total number of issue slots every cycle that were not consumed by the backend due to frontend stalls.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.ALL", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003" }, @@ -520,7 +521,7 @@ "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.BRANCH_DETECT", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.", "SampleAfterValue": "1000003", @@ -532,7 +533,7 @@ "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.BRANCH_RESTEER", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch.", "SampleAfterValue": "1000003", @@ -544,7 +545,7 @@ "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.CISC", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003", "UMask": "0x1" @@ -555,40 +556,18 @@ "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.DECODE", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003", "UMask": "0x8" }, { - "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x71", - "EventName": "TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "UMask": "0x8d" - }, - { - "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to a latency related stalls including BACLEARs, BTCLEARs, ITLB misses, and ICache misses.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x71", - "EventName": "TOPDOWN_FE_BOUND.FRONTEND_LATENCY", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "UMask": "0x72" - }, - { "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to ITLB misses.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.ITLB", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses.", "SampleAfterValue": "1000003", @@ -600,7 +579,7 @@ "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.OTHER", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003", "UMask": "0x80" @@ -611,7 +590,7 @@ "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.PREDECODE", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003", "UMask": "0x4" @@ -632,7 +611,7 @@ "Counter": "0,1,2,3", "EventCode": "0x0e", "EventName": "UOPS_ISSUED.ANY", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of uops issued by the front end every cycle. When 4-uops are requested and only 2-uops are delivered, the event counts 2. Uops_issued correlates to the number of ROB entries. If uop takes 2 ROB slots it counts as 2 uops_issued.", "SampleAfterValue": "200003" @@ -664,7 +643,6 @@ "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.MS", - "PDIR_COUNTER": "na", "PEBS": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of uops that are from complex flows issued by the Microcode Sequencer (MS). This includes uops from flows due to complex instructions, faults, assists, and inserted flows.", |