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2022-02-09peci: Add device detectionIwona Winiarska6-1/+225
2022-02-09peci: Add peci-aspeed controller driverJae Hyun Yoo6-0/+637
2022-02-09peci: Add core infrastructureIwona Winiarska8-0/+305
2022-02-09ARM: dts: aspeed: Add PECI controller nodesIwona Winiarska3-0/+33
2022-02-09dt-bindings: Add bindings for peci-aspeedIwona Winiarska1-0/+72
2022-02-09dt-bindings: Add generic bindings for PECIIwona Winiarska1-0/+33
2022-02-08tools/testing/cxl: Add a physical_node linkDan Williams1-2/+19
2022-02-08tools/testing/cxl: Enumerate mock decodersDan Williams1-19/+97
2022-02-08tools/testing/cxl: Mock one level of switchesDan Williams1-41/+97
2022-02-08tools/testing/cxl: Fix root port to host bridge assignmentDan Williams1-1/+1
2022-02-08tools/testing/cxl: Mock dvsec_ranges()Dan Williams1-0/+10
2022-02-08cxl/core/port: Add endpoint decodersBen Widawsky4-16/+73
2022-02-08cxl/core: Move target_list out of base decoder attributesDan Williams1-1/+2
2022-02-08cxl/mem: Add the cxl_mem driverBen Widawsky13-5/+425
2022-02-08cxl/core/port: Add switch port enumerationDan Williams3-25/+438
2022-02-08cxl/memdev: Add numa_node attributeDan Williams3-0/+27
2022-02-08cxl/pci: Emit device serial numberDan Williams5-0/+24
2022-02-08cxl/pci: Implement wait for media activeBen Widawsky3-1/+58
2022-02-08cxl/pci: Retrieve CXL DVSEC memory infoBen Widawsky3-0/+146
2022-02-08cxl/pci: Cache device DVSEC offsetBen Widawsky2-0/+8
2022-02-08cxl/pci: Store component register base in cxldsBen Widawsky2-0/+14
2022-02-08cxl/core/port: Remove @host argument for dport + decoder enumerationDan Williams10-54/+45
2022-02-08cxl/port: Add a driver for 'struct cxl_port' objectsBen Widawsky11-31/+415
2022-02-08cxl/core: Emit modalias for CXL devicesDan Williams2-9/+26
2022-02-08cxl/core/hdm: Add CXL standard decoder enumeration to the coreDan Williams12-49/+434
2022-02-08cxl/core: Generalize dport enumeration in the coreDan Williams11-238/+238
2022-02-08cxl/pci: Rename pci.h to cxlpci.hDan Williams4-3/+4
2022-02-08cxl/port: Up-level cxl_add_dport() locking requirements to the callerDan Williams3-2/+7
2022-02-08cxl/pmem: Introduce a find_cxl_root() helperDan Williams5-30/+60
2022-02-08cxl/port: Introduce cxl_port_to_pci_bus()Dan Williams3-5/+49
2022-02-08cxl/core/port: Use dedicated lock for decoder target listDan Williams2-7/+25
2022-02-08cxl: Prove CXL lockingDan Williams7-25/+154
2022-02-08cxl/core: Track port depthBen Widawsky2-0/+4
2022-02-08cxl/core/port: Make passthrough decoder init implicitBen Widawsky2-6/+8
2022-02-08cxl/core: Fix cxl_probe_component_regs() error messageDan Williams1-1/+1
2022-02-08cxl/core/port: Clarify decoder creationBen Widawsky3-11/+92
2022-02-08cxl/core: Convert decoder range to resourceBen Widawsky3-18/+35
2022-02-08cxl/decoder: Hide physical address information from non-rootDan Williams1-1/+1
2022-02-08cxl/core/port: Rename bus.c to port.cDan Williams4-4/+4
2022-02-08cxl: Introduce module_cxl_driverBen Widawsky1-0/+3
2022-02-08cxl/acpi: Map component registers for Root PortsBen Widawsky5-54/+80
2022-02-08cxl/pci: Add new DVSEC definitionsBen Widawsky1-0/+15
2022-02-08cxl: Flesh out register namesBen Widawsky2-16/+17
2022-02-08cxl/pci: Defer mailbox status checks to command timeoutsDan Williams1-101/+33
2022-02-08cxl/pci: Implement Interface Ready TimeoutBen Widawsky1-0/+35
2022-02-08cxl: Rename CXL_MEM to CXL_PCIBen Widawsky2-12/+13
2022-02-08Merge branch 'libbpf: Add syscall-specific variant of BPF_KPROBE'Andrii Nakryiko3-0/+64
2022-02-08selftests/bpf: Test BPF_KPROBE_SYSCALL macroHengqi Chen2-0/+29
2022-02-08libbpf: Add BPF_KPROBE_SYSCALL macroHengqi Chen1-0/+35
2022-02-08Merge branch 'Fix accessing syscall arguments'Andrii Nakryiko3-12/+51
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