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path: root/Documentation/devicetree/bindings/clock/fsl,plldig.yaml (follow)
AgeCommit message (Expand)AuthorFilesLines
2020-05-14dt-bindings: Fix incorrect 'reg' property sizesRob Herring1-1/+1
2020-04-16dt-bindings: Clean-up schema indentation formattingRob Herring1-9/+8
2020-03-31dt-bindings: Add missing 'additionalProperties: false'Rob Herring1-0/+2
2020-03-27dt-bindings: Clean-up schema errors due to missing 'addtionalProperties: false'Rob Herring1-0/+3
2020-02-03dt/bindings: clk: fsl,plldig: Drop 'bindings' from schema idStephen Boyd1-1/+1
2020-01-30dt/bindings: clk: Add YAML schemas for LS1028A Display Clock bindingsWen He1-0/+54