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2020-02-24docs: dt: fix several broken doc referencesMauro Carvalho Chehab1-1/+1
There are several DT doc references that require manual fixes. I found 3 cases fixed on this patch: - directory named "binding/" instead of "bindings/"; - .txt to .yaml renames; - file renames (still on txt format); Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Jérôme Pouiller <jerome.pouiller@silabs.com> Acked-by: Mark Brown <broonie@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org>
2020-02-04Merge tag 'powerpc-5.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linuxLinus Torvalds1-4/+4
Pull powerpc updates from Michael Ellerman: "A pretty small batch for us, and apologies for it being a bit late, I wanted to sneak Christophe's user_access_begin() series in. Summary: - Implement user_access_begin() and friends for our platforms that support controlling kernel access to userspace. - Enable CONFIG_VMAP_STACK on 32-bit Book3S and 8xx. - Some tweaks to our pseries IOMMU code to allow SVMs ("secure" virtual machines) to use the IOMMU. - Add support for CLOCK_{REALTIME/MONOTONIC}_COARSE to the 32-bit VDSO, and some other improvements. - A series to use the PCI hotplug framework to control opencapi card's so that they can be reset and re-read after flashing a new FPGA image. As well as other minor fixes and improvements as usual. Thanks to: Alastair D'Silva, Alexandre Ghiti, Alexey Kardashevskiy, Andrew Donnellan, Aneesh Kumar K.V, Anju T Sudhakar, Bai Yingjie, Chen Zhou, Christophe Leroy, Frederic Barrat, Greg Kurz, Jason A. Donenfeld, Joel Stanley, Jordan Niethe, Julia Lawall, Krzysztof Kozlowski, Laurent Dufour, Laurentiu Tudor, Linus Walleij, Michael Bringmann, Nathan Chancellor, Nicholas Piggin, Nick Desaulniers, Oliver O'Halloran, Peter Ujfalusi, Pingfan Liu, Ram Pai, Randy Dunlap, Russell Currey, Sam Bobroff, Sebastian Andrzej Siewior, Shawn Anastasio, Stephen Rothwell, Steve Best, Sukadev Bhattiprolu, Thiago Jung Bauermann, Tyrel Datwyler, Vaibhav Jain" * tag 'powerpc-5.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: (131 commits) powerpc: configs: Cleanup old Kconfig options powerpc/configs/skiroot: Enable some more hardening options powerpc/configs/skiroot: Disable xmon default & enable reboot on panic powerpc/configs/skiroot: Enable security features powerpc/configs/skiroot: Update for symbol movement only powerpc/configs/skiroot: Drop default n CONFIG_CRYPTO_ECHAINIV powerpc/configs/skiroot: Drop HID_LOGITECH powerpc/configs: Drop NET_VENDOR_HP which moved to staging powerpc/configs: NET_CADENCE became NET_VENDOR_CADENCE powerpc/configs: Drop CONFIG_QLGE which moved to staging powerpc: Do not consider weak unresolved symbol relocations as bad powerpc/32s: Fix kasan_early_hash_table() for CONFIG_VMAP_STACK powerpc: indent to improve Kconfig readability powerpc: Provide initial documentation for PAPR hcalls powerpc: Implement user_access_save() and user_access_restore() powerpc: Implement user_access_begin and friends powerpc/32s: Prepare prevent_user_access() for user_access_end() powerpc/32s: Drop NULL addr verification powerpc/kuap: Fix set direction in allow/prevent_user_access() powerpc/32s: Fix bad_kuap_fault() ...
2020-02-01Merge branch 'topic/user-access-begin' into nextMichael Ellerman1-2/+2
Merge the user_access_begin() series from Christophe. This is based on a commit from Linus that went into v5.5-rc7.
2020-01-23Merge branch 'spi-5.6' into spi-nextMark Brown4-73/+108
2020-01-23dt-binding: spi: add NPCM PSPI reset bindingTomer Maimon1-10/+2
Add NPCM Peripheral SPI reset binding documentation, Removing unnecessary aliases use. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20200115162301.235926-4-tmaimon77@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-01-23powerpc/devicetrees: Change 'gpios' to 'cs-gpios' on fsl, spi nodesChristophe Leroy1-4/+4
Since commit 0f0581b24bd0 ("spi: fsl: Convert to use CS GPIO descriptors"), the prefered way to define chipselect GPIOs is using 'cs-gpios' property instead of the legacy 'gpios' property. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/7556683b57d8ce100855857f03d1cd3d2903d045.1574943062.git.christophe.leroy@c-s.fr
2020-01-09dt-bindings: spi_atmel: add microchip,sam9x60-spiClaudiu Beznea1-1/+1
Add microchip,sam9x60-spi to DT bindings documentation. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1578488123-26127-13-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-01-06Merge tag 'spi-fix-v5.5-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spiLinus Torvalds1-2/+2
Pull spi fixes from Mark Brown: "A small collection of fixes here, one to make the newly added PTP timestamping code more accurate, a few driver fixes and a fix for the core DT binding to document the fact that we support eight wire buses" * tag 'spi-fix-v5.5-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: spi: Document Octal mode as valid SPI bus width spi: spi-dw: Add lock protect dw_spi rx/tx to prevent concurrent calls spi: spi-fsl-dspi: Fix 16-bit word order in 32-bit XSPI mode spi: Don't look at TX buffer for PTP system timestamping spi: uniphier: Fix FIFO threshold
2020-01-03spi: Document Octal mode as valid SPI bus widthVignesh Raghavendra1-2/+2
SPI core supports Octal SPI controllers which have 8 IO lines. Therefore document 8 as a valid option for spi-tx{rx}-bus-width Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20200102102118.23318-1-vigneshr@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
2019-12-18dt-bindings: spi: Convert stm32 spi bindings to json-schemaBenjamin Gaignard2-62/+105
Convert the STM32 spi binding to DT schema format using json-schema Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com> CC: Erwan Leray <erwan.leray@st.com> CC: Fabrice Gasnier <fabrice.gasnier@st.com> CC: Amelie Delaunay <amelie.delaunay@st.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20191217090715.13334-1-benjamin.gaignard@st.com Signed-off-by: Mark Brown <broonie@kernel.org>
2019-12-12dt-bindings: Change maintainer addressMaxime Ripard2-2/+2
While my email address has changed for a while, all the schemas I contributed still have the old one unfortunately. Update it. Signed-off-by: Maxime Ripard <maxime@cerno.tech> Signed-off-by: Rob Herring <robh@kernel.org>
2019-11-22dt-bindings: spi: Convert stm32 QSPI bindings to json-schemaBenjamin Gaignard2-47/+83
Convert the STM32 QSPI binding to DT schema format using json-schema Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20191120194444.10540-1-benjamin.gaignard@st.com Signed-off-by: Mark Brown <broonie@kernel.org>
2019-10-24spi: xilinx: add description of new property xlnx,num-transfer-bitsAlvaro Gamez Machado1-1/+3
This property is used to set the number of bits per transfer (bits_per_word). Xilinx' IP core allows either 8, 16 or 32, and is non changeable on runtime, only when instantiating the core. Signed-off-by: Alvaro Gamez Machado <alvaro.gamez@hazent.com> Link: https://lore.kernel.org/r/20191024110757.25820-2-alvaro.gamez@hazent.com Signed-off-by: Mark Brown <broonie@kernel.org>
2019-10-15dt-bindings: spi: sh-msiof: Add r8a774b1 supportFabrizio Castro1-0/+1
Document RZ/G2N (R8A774B1) SoC bindings. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/1570178133-21532-3-git-send-email-fabrizio.castro@bp.renesas.com Signed-off-by: Mark Brown <broonie@kernel.org>
2019-10-15dt-bindings: spi: sh-msiof: Convert bindings to json-schemaSimon Horman2-105/+158
Convert Renesas HSPI bindings documentation to json-schema. Also name bindings documentation file according to the compat string being documented. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20190926102533.17829-1-horms+renesas@verge.net.au Signed-off-by: Mark Brown <broonie@kernel.org>
2019-10-01dt-bindings: snps,dw-apb-ssi: Add optional clock domain informationGareth Williams1-1/+2
Note in the bindings documentation that pclk should be renamed if a clock domain is used to enable the optional bus clock. Signed-off-by: Gareth Williams <gareth.williams.jx@renesas.com> Link: https://lore.kernel.org/r/1568793876-9009-3-git-send-email-gareth.williams.jx@renesas.com Signed-off-by: Mark Brown <broonie@kernel.org>
2019-10-01dt: spi: Add Renesas RZ/N1 binding documentationPhil Edworthy1-0/+11
The Renesas RZ/N1 SPI Controller is based on the Synopsys DW SSI, but has additional registers for software CS control and DMA. This patch does not address the changes required for DMA support, it simply adds the compatible string. The CS functionality is not very useful and also not needed as Linux can use gpios for the CS signals. Add a compatible string to handle any unforeseen issues that may arise, and pave the way for DMA support. Signed-off-by: Gareth Williams <gareth.williams.jx@renesas.com> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Link: https://lore.kernel.org/r/1568793876-9009-2-git-send-email-gareth.williams.jx@renesas.com Signed-off-by: Mark Brown <broonie@kernel.org>
2019-10-01spi: dt-bindings: Convert spi-sifive binding to json-schemaPragnesh Patel2-37/+86
Convert the spi-sifive binding to DT schema format. Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/1568804927-13565-1-git-send-email-pragnesh.patel@sifive.com Signed-off-by: Mark Brown <broonie@kernel.org>
2019-10-01dt-bindings: hspi: Convert bindings to json-schemaSimon Horman2-26/+57
Convert Renesas HSPI bindings documentation to json-schema. Also name bindings documentation file according to the compat string being documented. As a side effect of this change all currently supported/used compat strings are listed while no while card compat string is documented. This, in my opinion, is desirable as only supported hardware should be documented. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20190916075352.32108-1-horms+renesas@verge.net.au Signed-off-by: Mark Brown <broonie@kernel.org>
2019-09-19Merge tag 'devicetree-for-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linuxLinus Torvalds3-55/+120
Pull Devicetree updates from Rob Herring: - a bunch of DT binding conversions to DT schema format - clean-ups of the Arm idle-states binding - support a default number of cells in of_for_each_phandle() when the cells name is missing - expose dtbs_check and dt_binding_check in the make help - convert writting-schema.md to ReST - HiSilicon reset controller binding updates - add documentation for MT8516 RNG * tag 'devicetree-for-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (46 commits) of: restore old handling of cells_name=NULL in of_*_phandle_with_args() bus: qcom: fix spelling mistake "ambigous" -> "ambiguous" of: Let of_for_each_phandle fallback to non-negative cell_count iommu: pass cell_count = -1 to of_for_each_phandle with cells_name dt-bindings: arm: Convert Realtek board/soc bindings to json-schema dt-bindings: arm: Convert Actions Semi bindings to jsonschema dt-bindings: Correct spelling in example schema dt-bindings: cpu: Add a support cpu type for cortex-a55 dt-bindings: gpu: mali-midgard: Add samsung exynos5250 compatible dt-bindings: arm: idle-states: Move exit-latency-us explanation dt-bindings: arm: idle-states: Add punctuation to improve readability dt-bindings: arm: idle-states: Correct "constraint guarantees" dt-bindings: arm: idle-states: Correct references to wake-up delay dt-bindings: arm: idle-states: Use "e.g." and "i.e." consistently pinctrl-mcp23s08: Fix property-name in dt-example dt-bindings: Clarify interrupts-extended usage dt-bindings: Convert Arm Mali Utgard GPU to DT schema dt-bindings: Convert Arm Mali Bifrost GPU to DT schema dt-bindings: Convert Arm Mali Midgard GPU to DT schema dt-bindings: irq: Convert Allwinner NMI Controller to a schema ...
2019-09-16Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds1-0/+1
Pull ARM DT updates from Arnd Bergmann: "This is another huge branch with close to 450 changessets related to devicetree files, roughly half of this for 32-bit and 64-bit respectively. There are lots of cleanups and additional hardware support for platforms we already support based on SoCs from Renesas, ST-Microelectronics, Intel/Altera, Rockchips, Allwinner, Broadcom and other manufacturers. A total of 6 new SoCs and 37 new boards gets added this time, one more SoC will come in a follow-up branch. Most of the new boards are for 64-bit ARM SoCs, the others are typically for the 32-bit Cortex-A7. Going more into details for SoC platforms with new hardware support: - The Snapdragon 855 (SM8150) is Qualcomm's current high-end phone platform, usually paired with an external 5G modem. So far we only support the Qualcomm SM8150 MTP reference platform, but no actual products. - For the slightly older Qualcomm platforms, support for several interesting products is getting added: Three laptops based on Snapdragon 835/MSM8998 (Asus NovaGo, HP Envy X2 and Lenovo Miix 630), one laptop based on Snapdragon 850/sdm850 (Lenovo Yoga C630) and several phones based on the older Snapdragon 410/MSM8916 (Samsung A3 and A5, Longcheer L8150 aka Android One 2nd gen "seed" aka Wileyfox Swift). - Mediatek MT7629 is a new wireless network router chip, similar to the older MT7623. It gets added together with the reference board implementation. - Allwinner V3 is a repackaged version of the existing low-end V3s chip, and is used in the tiny Lichee Pi Zero plus, also added here. There is also a new TV set-top box based on Allwinner H6, the Tanix TX6, and the eMMC variant of the Olimex A64-Olinuxino development board. - NXP i.MX8M Nano is a new member of the ever-expanding i.MX SoC family, similar to the i.MX8M Mini. As usual, there is a large number of new boards for i.MX SoCs: Einfochips i.MX8QXP AI_ML, SolidRun Hummingboard Pulse baseboard and System-on-Module, Boundary Devices i.MX8MQ Nitrogen8M, and TechNexion PICO-PI-IMX8M-DEV for the 64-bit i.MX8 line. For 32-bit, we get the Kontron i.MX6UL N6310 SoM with two baseboards, the PHYTEC phyBOARD-Segin SoM with three baseboards, and the Zodiac Inflight Innovations i.MX7 RMU2 board. - In a different NXP product line, the Layerscape LS1046A "Freeway" reference board gets added. - Amlogic SM1 (S905X3) and G12B (S922X, A311D) are updated chips from their set-top-box line and smart speaker with newer CPU and GPU cores compared to their predecessors. Both are now also supported by the Khadas VIM3 development board series, and the dts files for that get reorganized a bit to better deal with all variants. Another board based on SM1 that gets added is the SEI Robotics SEI610. - There are a handful of new x86 and Power9 server boards using Aspeed BMC chips that are gaining support for running Linux on the BMC through the OpenBMC project: Facebook Minipack/Wedge100/Wedge40, Lenovo Hr855xg2, and Mihawk. Notably these are still new machines using SoCs based on the ARM9 and ARM11 CPU cores, as support for the new Cortex-A7 based AST2600 is still ramping up. - There are three new end-user products using 32-bit Rockchips SoCs: Mecer Xtreme Mini S6 is an Android "mini PC" box based on the low-end RK3229 chip, while the two AOpen products Chromebox Mini (Fievel) and Chromebase Mini (Tiger) run ChromeOS and are meant for commercial settings(digital signage, PoS, ...). - One more single-board computer based on the popular 64-bit RK3399 is added: the Leez RK3399 P710" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (467 commits) arm64: dts: qcom: Add Lenovo Yoga C630 ARM: dts: aspeed-g5: Fixe gpio-ranges upper limit ARM; dts: aspeed: mihawk: File should not be executable ARM: dts: aspeed: swift: Change power supplies to version 2 ARM: dts: aspeed: vesnin: Add secondary SPI flash chip ARM: dts: aspeed: vesnin: Add wdt2 with alt-boot option ARM: dts: aspeed-g4: Add all flash chips ARM: dts: exynos: Enable GPU/Mali T604 on Arndale board ARM: dts: exynos: Enable GPU/Mali T604 on Chromebook Snow ARM: dts: exynos: Add GPU/Mali T604 node to Exynos5250 ARM: dts: exynos: Fix min/max buck4 for GPU on Arndale board ARM: dts: exynos: Mark LDO10 as always-on on Peach Pit/Pi Chromebooks ARM: dts: exynos: Remove not accurate secondary ADC compatible arm64: dts: rockchip: limit clock rate of MMC controllers for RK3328 arm64: dts: meson-sm1-sei610: add stdout-path property back arm64: dts: meson-sm1-sei610: enable DVFS arm64: dts: khadas-vim3: add support for the SM1 based VIM3L dt-bindings: arm: amlogic: add Amlogic SM1 based Khadas VIM3L bindings arm64: dts: khadas-vim3: move common nodes into meson-khadas-vim3.dtsi arm64: dts: meson: g12a: add reset to tdm formatters ...
2019-09-13dt-bindings: spi: update bindings for MT6765 SoCluhua.xu1-0/+1
Add a DT binding documentation for the MT6765 soc. Signed-off-by: luhua.xu <luhua.xu@mediatek.com> Link: https://lore.kernel.org/r/1568195731-3239-2-git-send-email-luhua.xu@mediatek.com Signed-off-by: Mark Brown <broonie@kernel.org>
2019-09-03Merge tag 'imx-bindings-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dtArnd Bergmann1-0/+1
i.MX DT bindings update for 5.4 - Add SoC bindings for i.MX8MN. - Add board bindings for pico-pi-imx8m, Hummingboard Pulse, imx8mq nitrogen, i.MX8QXP AI_ML, ls1046a-frwy etc. - Add vendor prefix for Anvo-Systems and Einfochips. - Update LPUART bindings for i.MX8QXP clock requirement. - Update imx-weim bindings for optional burst clock mode support. - Update EEPROM bindings for Anvo ANV32E61W device support. * tag 'imx-bindings-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: dt-bindings: arm: fsl: Add Kontron i.MX6UL N6310 compatibles dt-bindings: eeprom: at25: Add Anvo ANV32E61W dt-bindings: vendor-prefixes: Add Anvo-Systems dt-bindings: arm: fsl: add Hummingboard Pulse dt-bindings: arm: imx: add imx8mq nitrogen support dt-bindings: fsl: dspi: Add fsl,ls1088a-dspi compatible string dt-bindings: arm: imx: Add the soc binding for i.MX8MN dt-bindings: bus: imx-weim: document optional burst clock mode dt-bindings: arm: fsl: Add the pico-pi-imx8m board dt-bindings: arm: Document i.MX8QXP AI_ML board binding dt-bindings: Add Vendor prefix for Einfochips dt-bindings: arm: nxp: Add device tree binding for ls1046a-frwy board dt-bindings: serial: lpuart: add the clock requirement for imx8qxp dt-bindings: arm: fsl: Add support for ZII i.MX7 RMU2 board Link: https://lore.kernel.org/r/20190825153237.28829-3-shawnguo@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-08-30dt-binding: spi: add NPCM FIU controllerTomer Maimon1-0/+47
Added device tree binding documentation for Nuvoton BMC NPCM Flash Interface Unit(FIU) SPI master controller using SPI-MEM interface. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Link: https://lore.kernel.org/r/20190828142513.228556-2-tmaimon77@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2019-08-24dt-bindings: fsl: dspi: Add fsl,ls1088a-dspi compatible stringChuanhua Han1-0/+1
new compatible string: "fsl,ls1088a-dspi". Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-23Merge branch 'spi-5.3' into spi-5.4Mark Brown1-2/+1
2019-08-22spi: spi-fsl-qspi: Add ls2080a compatibility string to bindingsAshish Kumar1-2/+1
There are 2 version of QSPI-IP, according to which controller registers sets can be big endian or little endian.There are some other minor changes like RX fifo depth etc. The big endian version uses driver compatible "fsl,ls1021a-qspi" and little endian version uses driver compatible "fsl,ls2080a-qspi" Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Signed-off-by: Ashish Kumar <ashish.kumar@nxp.com> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Han Xu <han.xu@nxp.com> Link: https://lore.kernel.org/r/1565691791-26167-1-git-send-email-Ashish.Kumar@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2019-08-22spi: fsl-qspi: Enhance binding to extend example for flash entryAshish Kumar1-1/+5
Add example for adding flash entry on various boards' dts using flash manufacture spansion/cypress. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Link: https://lore.kernel.org/r/1565691791-26167-3-git-send-email-Ashish.Kumar@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2019-08-20spi: Fix the number of CS lines documented as an exampleManivannan Sadhasivam1-1/+1
The number of CS lines is mentioned as 2 in the spi-controller binding but however in the example, 4 cs-gpios are used. Hence fix that to mention 4. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20190820115000.32041-1-manivannan.sadhasivam@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
2019-08-13dt-bindings: spi: meson: convert to yamlNeil Armstrong3-55/+120
Now that we have the DT validation in place, let's convert the device tree bindings for the Amlogic SPI controllers over to two separate YAML schemas. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Rob Herring <robh@kernel.org>
2019-08-05Merge tag 'spi-fix-v5.3-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spiLinus Torvalds1-1/+0
Pull spi fixes from Mark Brown: "A bunch of small, device specific things here plus a DT bindings fix for the new validatable YAML binding format. The most notable thing is the fix for GPIO chip selects which fixes a corner case in updates of that code to modern APIs, unfortunately due to a historical mess the code around GPIO support is obscure, fragile and an ABI which makes and attempt to improve the situation painful" * tag 'spi-fix-v5.3-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: spi: pxa2xx: Add support for Intel Tiger Lake spi: bcm2835: Fix 3-wire mode if DMA is enabled spi: pxa2xx: Balance runtime PM enable/disable on error spi: gpio: Add SPI_MASTER_GPIO_SS flag spi: spi-fsl-qspi: change i.MX7D RX FIFO size spi: dt-bindings: spi-controller: remove unnecessary 'maxItems: 1' from reg
2019-07-26spi: sprd: Change the hwlock support to be optionalBaolin Wang1-3/+8
No need to add hardware spinlock proctection due to add multiple msater channel, so change it to be optional in documentation. Signed-off-by: Baolin Wang <baolin.wang@linaro.org> Link: https://lore.kernel.org/r/23d51f5d9c9cc647ad0c5a1fb950d3d9fb9c1303.1564125131.git.baolin.wang@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
2019-07-20dt-bindings: Ensure child nodes are of type 'object'Rob Herring2-0/+2
Properties which are child node definitions need to have an explict type. Otherwise, a matching (DT) property can silently match when an error is desired. Fix this up tree-wide. Once this is fixed, the meta-schema will enforce this on any child node definitions. Cc: Chen-Yu Tsai <wens@csie.org> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Brian Norris <computersforpeace@gmail.com> Cc: Marek Vasut <marek.vasut@gmail.com> Cc: Richard Weinberger <richard@nod.at> Cc: Vignesh Raghavendra <vigneshr@ti.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: linux-mtd@lists.infradead.org Cc: linux-gpio@vger.kernel.org Cc: linux-stm32@st-md-mailman.stormreply.com Cc: linux-spi@vger.kernel.org Acked-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Alexandre TORGUE <alexandre.torgue@st.com> Signed-off-by: Rob Herring <robh@kernel.org>
2019-07-10spi: dt-bindings: spi-controller: remove unnecessary 'maxItems: 1' from regRob Herring1-1/+0
Mixing array constraints like 'maxItems' and string or integer value constraints like 'minimum' don't make sense. Also, with only value constraints, it is implied we have a single value. So lets remove 'maxItems: 1'. Cc: Mark Brown <broonie@kernel.org> Cc: linux-spi@vger.kernel.org Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20190709192631.16394-1-robh@kernel.org Signed-off-by: Mark Brown <broonie@kernel.org>
2019-06-28dt-bindings: spi: stm32-qspi: add dma propertiesLudovic Barre1-1/+4
This patch adds description of dma properties (optional). Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-06-04spi: Add DT bindings for SynquacerMasahisa Kojima1-0/+27
This patch adds documentation for Device-Tree bindings for the Socionext Synquacer spi driver. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-05-23spi: dt-bindings: Convert Arm pl022 to json-schemaRob Herring2-70/+165
Convert the Arm pl022 binding to DT schema format. The clock binding was missing, so it is added to the schema. It really should be required as well, but there are some platforms (spear) not yet using DT clock binding. Cc: Mark Brown <broonie@kernel.org> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-spi@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-05-22spi: dt-bindings: Convert spi-gpio binding to json-schemaRob Herring2-43/+72
Convert the spi-gpio binding to DT schema format. Cc: Mark Brown <broonie@kernel.org> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-spi@vger.kernel.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-05-21spi: sun6i: Add YAML schemasMaxime Ripard2-44/+106
Switch the DT binding to a YAML schema to enable the DT validation. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-05-21spi: sun4i: Add YAML schemasMaxime Ripard2-23/+86
Switch the DT binding to a YAML schema to enable the DT validation. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-05-21spi: Add YAML schemas for the generic SPI optionsMaxime Ripard2-111/+162
The SPI controllers have a bunch of generic options that are needed in a device tree. Add a YAML schemas for those. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-05-02dt-bindings: spi: spi-mt65xx: add support for MT8516Leilk Liu1-0/+1
Add binding documentation of spi-mt65xx for MT8516 SOC. Signed-off-by: Leilk Liu <leilk.liu@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-05-02spi: sh-msiof: Document r8a77470 bindingsCao Van Dong1-0/+1
Document SoC specific bindings for R-Car RZ/G1C(r8a77470) SoC. Signed-off-by: Cao Van Dong <cv-dong@jinso.co.jp> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-04-08spi: document tx/rx clock delay propertiesSowjanya Komatineni1-0/+20
Tegra SPI controller has TX and RX trimmers to tuning the delay of SPI master clock with respect to the data. TX and RX tap values are based on the platform validation across the PVT and the trimmer values vary based on the trace lengths to the corresponding SPI devices. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-04-05dt-bindings: spi: Add device tree binding documentation for Zynq QSPI controllerNaga Sureshkumar Relli1-0/+25
This patch adds the dts binding document for Zynq SOC QSPI controller. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-03-25spi: mt7621: Move SPI driver out of stagingStefan Roese1-0/+26
This patch moves the MT7621 SPI driver, which is used on some Ralink / MediaTek MT76xx MIPS SoC's, out of the staging directory. No changes to the source code are done in this patch. This driver version was tested successfully on an MT7688 based platform with an SPI NOR on CS0 and an SPI NAND on CS1 without any issues (so far). This patch also documents the devicetree bindings for the MT7621 SPI device driver. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Rob Herring <robh@kernel.org> Cc: Mark Brown <broonie@kernel.org> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: NeilBrown <neil@brown.name> Cc: Sankalp Negi <sankalpnegi2310@gmail.com> Cc: Chuanhong Guo <gch981213@gmail.com> Cc: John Crispin <john@phrozen.org> Cc: Armando Miraglia <arma2ff0@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-03-20dt-bindings: snps,dw-apb-ssi: Add optional clock bindings documentationGareth Williams1-1/+7
Add documentation to the Synopsys SPI dt-bindings to support an optional interface clock that may be used for register access. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Signed-off-by: Gareth Williams <gareth.williams.jx@renesas.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-03-20dt-bindings: snps,dw-apb-ssi: Add mandatory clock bindings documentationPhil Edworthy1-1/+3
The Synopsys SSI driver uses a mandatory clock that is not documented, so detail it in the device tree bindings. Also correct the spelling of "pins" in the "Optional Properties" section for the driver. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Signed-off-by: Gareth Williams <gareth.williams.jx@renesas.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-03-18spi: spi-fsl-spi: support use of the SPISEL_BOOT signal on MPC8309Rasmus Villemoes1-0/+4
The MPC8309 has a dedicated signal, SPISEL_BOOT, usually used as chip select for the flash device from which the bootloader is loaded. It is not an ordinary gpio, but is simply controlled via the SPI_CS register in the system configuration. To allow accessing such a spi slave, we need to teach fsl_spi_cs_control() how to control the SPISEL_BOOT signal. To distinguish the gpio-controlled slaves, continue to have those use chip_select values of 0..ngpios-1, and use chip_select == ngpios for the boot flash. I'm not too happy with all the ifdeffery, but it seems to be necessary for guarding the sysdev/fsl_soc.h and use of get_immrbase() (spi-fsl-lib.c already contains similar ifdeffery). Googling suggests that the MPC8306 is similar, with the SPI_CS register at the same offset. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-03-18doc: lpspi: Document DT bindings for LPSPI clocksClark Wang1-2/+8
Add introductions of clocks and clock-names strings. Signed-off-by: Clark Wang <xiaoning.wang@nxp.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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