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path: root/arch/arc/mm/tlb.c (follow)
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2021-08-26ARC: mm: support 3 levels of page tablesVineet Gupta1-2/+2
2021-08-26ARC: mm: switch pgtable_t back to struct page *Vineet Gupta1-37/+0
2021-08-24ARC: mm: move MMU specific bits out of ASID allocatorVineet Gupta1-7/+4
2021-08-24ARC: mm: Fixes to allow STRICT_MM_TYPECHECKSVineet Gupta1-5/+8
2021-08-24ARC: mm: remove tlb paranoid codeVineet Gupta1-40/+0
2021-08-24ARC: mm: use SCRATCH_DATA0 register for caching pgdir in ARCv2 onlyVineet Gupta1-2/+2
2021-08-24ARC: retire MMUv1 and MMUv2 supportVineet Gupta1-145/+18
2021-05-10ARC: mm: PAE: use 40-bit physical page maskVladimir Isaev1-1/+1
2020-11-17ARC: mm: fix spelling mistakesFlavio Suligoi1-12/+12
2019-10-28ARC: mm: tlb flush optim: elide redundant uTLB invalidates for MMUv3Vineet Gupta1-5/+0
2019-10-28ARC: mm: tlb flush optim: elide repeated uTLB invalidate in loopVineet Gupta1-45/+29
2019-10-28ARCv2: mm: TLB Miss optim: SMP builds can cache pgd pointer in mmu scratch regVineet Gupta1-1/+1
2019-06-19treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500Thomas Gleixner1-4/+1
2019-05-20ARC: fix build warningsVineet Gupta1-5/+8
2017-11-06ARCv2: Accomodate HS48 MMUv5 by relaxing MMU ver checkingVineet Gupta1-24/+33
2017-09-01ARC: Re-enable MMU upon Machine Check exceptionJose Abreu1-3/+0
2017-08-28ARC: set boot print log level to PR_INFONoam Camus1-1/+1
2017-08-04ARCv2: PAE40: set MSB even if !CONFIG_ARC_HAS_PAE40 but PAE exists in SoCVineet Gupta1-1/+11
2017-03-02sched/headers: Prepare to remove the <linux/mm_types.h> dependency from <linux/sched.h>Ingo Molnar1-0/+2
2016-10-28ARC: boot log: remove awkward space comma from MMU lineVineet Gupta1-3/+3
2016-05-09ARC: [plat-eznps] Use dedicated user stack topNoam Camus1-0/+6
2016-05-09ARC: Make vmalloc size configurableNoam Camus1-0/+5
2016-03-11ARC: Fix misspellings in comments.Adam Buchbinder1-4/+4
2015-11-16ARC: comments updateVineet Gupta1-2/+2
2015-10-29ARC: mm: PAE40 supportVineet Gupta1-5/+22
2015-10-28ARC: mm: PAE40: switch to using phys_addr_t for physical addressesVineet Gupta1-5/+5
2015-10-28ARC: mm: Improve Duplicate PD Fault handlerVineet Gupta1-24/+24
2015-10-17ARC: boot log: decode more mmu config itemsVineet Gupta1-6/+8
2015-10-17ARC: boot log: move helper macros to header for reuseVineet Gupta1-1/+1
2015-10-17ARC: mm: compute TLB size as needed from ways * setsVineet Gupta1-5/+4
2015-10-17ARCv2: mm: THP: flush_pmd_tlb_range make SMP safeVineet Gupta1-2/+25
2015-10-17ARCv2: mm: THP: Implement flush_pmd_tlb_range() optimizationVineet Gupta1-0/+20
2015-10-17ARCv2: mm: THP: boot validation/reportingVineet Gupta1-1/+7
2015-10-17ARCv2: mm: THP supportVineet Gupta1-0/+81
2015-06-22ARCv2: MMUv4: TLB programming Model changesVineet Gupta1-3/+51
2015-06-19ARC: compress cpuinfo_arc_mmu (mainly save page size in KB)Vineet Gupta1-4/+4
2014-10-13ARC: boot: cpu feature print enhancementsVineet Gupta1-5/+3
2013-11-06ARC: [SMP] TLB flushVineet Gupta1-0/+73
2013-11-06ARC: [SMP] ASID allocationVineet Gupta1-6/+8
2013-11-06ARC: Fix bogus gcc warning and micro-optimise TLB iteration loopVineet Gupta1-2/+2
2013-08-30ARC: [ASID] Track ASID allocation cycles/generationsVineet Gupta1-15/+7
2013-08-30ARC: [ASID] get_new_mmu_context() to conditionally allocate new ASIDVineet Gupta1-6/+7
2013-08-30ARC: [ASID] Refactor the TLB paranoid debug codeVineet Gupta1-11/+13
2013-08-30ARC: No need to flush the TLB in early bootVineet Gupta1-7/+0
2013-08-30ARC: MMUv4 preps/3 - Abstract out TLB Insert/DeleteVineet Gupta1-40/+54
2013-08-30ARC: MMUv4 preps/2 - Reshuffle PTE bitsVineet Gupta1-8/+3
2013-08-29ARC: MMUv4 preps/1 - Fold PTE K/U access flagsVineet Gupta1-2/+17
2013-06-27arc: delete __cpuinit usage from all arc filesPaul Gortmaker1-2/+2
2013-06-22ARC: [mm] Assume pagecache page dirty by defaultVineet Gupta1-1/+1
2013-06-22ARC: [mm] Zero page optimizationVineet Gupta1-1/+5
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