aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arc/mm (follow)
AgeCommit message (Expand)AuthorFilesLines
2016-04-04mm, fs: get rid of PAGE_CACHE_* and page_cache_{get,release} macrosKirill A. Shutemov1-1/+1
2016-03-19ARCv2: ioremap: Support dynamic peripheral address spaceVineet Gupta2-2/+22
2016-03-19ARC: dma: reintroduce platform specific dma<->physVineet Gupta1-5/+4
2016-03-19ARC: dma: ioremap: use phys_addr_t consistenctly in code pathsVineet Gupta3-30/+32
2016-03-19ARC: dma: pass_phys() not sg_virt() to cache opsVineet Gupta1-2/+2
2016-03-19ARC: dma: non-coherent pages need V-P mapping if in HIGHMEMVineet Gupta1-15/+32
2016-03-19ARC: dma: Use struct page based page allocator helpersVineet Gupta1-8/+17
2016-03-11ARC: Fix misspellings in comments.Adam Buchbinder3-6/+6
2016-01-20arc: convert to dma_map_opsChristoph Hellwig1-47/+105
2016-01-15mm: differentiate page_mapped() from page_mapcount() for compound pagesKirill A. Shutemov1-2/+2
2015-12-21ARC: mm: HIGHMEM: Fix section mismatch splatVineet Gupta1-2/+2
2015-12-17ARC: [plat-sim] unbork non default CONFIG_LINUX_LINK_BASEVineet Gupta1-1/+3
2015-11-16ARC: comments updateVineet Gupta1-2/+2
2015-11-14ARC: use ASL assembler mnemonicVineet Gupta1-3/+3
2015-10-29ARC: mm: PAE40 supportVineet Gupta3-10/+72
2015-10-28ARC: mm: PAE40: tlbex.S: Explicitify the size of pte_tVineet Gupta1-9/+12
2015-10-28ARC: mm: PAE40: switch to using phys_addr_t for physical addressesVineet Gupta2-18/+18
2015-10-28ARC: mm: HIGHMEM: populate high memory from DTVineet Gupta1-6/+64
2015-10-28ARC: mm: HIGHMEM: kmap API implementationVineet Gupta2-0/+141
2015-10-28ARC: mm: preps ahead of HIGHMEM support #2Vineet Gupta1-26/+14
2015-10-28ARC: mm: preps ahead of HIGHMEM supportVineet Gupta2-8/+21
2015-10-28ARC: mm: Improve Duplicate PD Fault handlerVineet Gupta1-24/+24
2015-10-28ARC: Ensure DT mem base is same as what kernel is built withVineet Gupta1-0/+2
2015-10-17ARC: boot log: decode more mmu config itemsVineet Gupta1-6/+8
2015-10-17ARC: boot log: move helper macros to header for reuseVineet Gupta2-4/+3
2015-10-17ARC: mm: compute TLB size as needed from ways * setsVineet Gupta1-5/+4
2015-10-17ARCv2: mm: THP: flush_pmd_tlb_range make SMP safeVineet Gupta1-2/+25
2015-10-17ARCv2: mm: THP: Implement flush_pmd_tlb_range() optimizationVineet Gupta1-0/+20
2015-10-17ARCv2: mm: THP: boot validation/reportingVineet Gupta1-1/+7
2015-10-17ARCv2: mm: THP supportVineet Gupta2-4/+96
2015-10-09ARC: mm: pte flags comsetic cleanups, commentsVineet Gupta1-1/+1
2015-08-21ARC: Eliminate some ARCv2 specific code for ARCompact buildVineet Gupta2-28/+34
2015-08-20ARCv2: IOC: Allow boot time disableAlexey Brodkin1-3/+4
2015-08-20ARCv2: SLC: Allow boot time disableVineet Gupta1-2/+19
2015-08-20ARCv2: Support IO Coherency and permutations involving L1 and L2 cachesAlexey Brodkin2-16/+116
2015-07-06ARC: Don't memzero twice in dma_alloc_coherent for __GFP_ZEROVineet Gupta1-2/+2
2015-07-06ARCv2: guard SLC DMA ops with spinlockAlexey Brodkin1-2/+10
2015-07-01Merge tag 'arc-4.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arcLinus Torvalds5-248/+434
2015-06-25ARCv2: [vdk] dts files and defconfig for HS38 VDKRuud Derwig1-0/+2
2015-06-25ARCv2: SLC: Handle explcit flush for DMA ops (w/o IO-coherency)Vineet Gupta2-2/+74
2015-06-22ARCv2: MMUv4: support aliasing icache configVineet Gupta1-1/+13
2015-06-22ARCv2: MMUv4: cache programming model changesVineet Gupta1-15/+97
2015-06-22ARCv2: MMUv4: TLB programming Model changesVineet Gupta2-3/+75
2015-06-22ARCv2: Support for ARCv2 ISA and HS38x coresVineet Gupta1-2/+0
2015-06-19ARC: entry.S: confine EXCEPTION_* macros to one fileVineet Gupta1-15/+1
2015-06-19ARC: untangle cache flush loopVineet Gupta1-25/+55
2015-06-19ARC: cacheflush: No need to retain DC_CTRL from __before_dc_op()Vineet Gupta1-20/+19
2015-06-19ARC: cacheflush: move some code around, delete old commentsVineet Gupta1-165/+102
2015-06-19ARC: mm/cache_arc700.c -> mm/cache.cVineet Gupta2-1/+1
2015-06-19ARC: compress cpuinfo_arc_mmu (mainly save page size in KB)Vineet Gupta1-4/+4
Copyright © 1996 – 2023 Jason A. Donenfeld. All Rights Reverse Engineered.