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2019-07-30ARM: dts: socfpga: add missing reset-names for dmaDinh Nguyen1-0/+1
The dma dts node was missing the reset-names = "dma". The reset driver needs this line to get the reset property. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2019-07-30ARM: dts: socfpga: update to new Denali NAND bindingMasahiro Yamada1-1/+1
With commit d8e8fd0ebf8b ("mtd: rawnand: denali: decouple controller and NAND chips"), the Denali NAND controller driver migrated to the new controller/chip representation. Update DT for it. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2019-01-29ARM: dts: socfpga: update more missing reset propertiesSimon Goldschmidt1-0/+4
Add reset property for dma, can and sdram on socfpga gen5. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2019-01-14ARM: dts: socfpga: update missing reset property peripheralsDinh Nguyen1-0/+12
Add reset property for gpio, i2c, sdmmc, nand, qspi, spi, uart, and watchdog on base socfpga and socfpga_arria10. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-11-28ARM: dts: socfpga: use tabs for indentationSimon Goldschmidt1-1/+1
In two of the gen5 socfpga devicetree files, there are some lines indented using spaces instead of tabs. Fix this by correctly indenting them with tabs. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-11-28arm: dts: socfpga: remove dma-mask propertyDinh Nguyen1-1/+0
The dma-mask property has been removed from the NAND driver. Remove the property from the DTS files. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-11-28arm: dts: socfpga*.dts*: use SPDX-License-IdentifierSimon Goldschmidt1-14/+2
Follow the recent trend for the license description. This is also in an effort to fully sync the devicetrees with U-Boot. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-10-09ARM: dts: socfgpa: remove ethernet aliases from dtsiDinh Nguyen1-2/+0
Not all boards use two ethernet devices and/or use them in different order. As almost all in-tree boards already define their own ethernet aliases, remove them from the dtsi and add the aliases to the two boards, that are missing their own definition. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> [dinguyen@kernel.org: rebased to latest dts changes] Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-09-17ARM: dts: socfpga: add timer resets for SoCFPGA platformDinh Nguyen1-0/+8
Add the resets property for all the timers on the Cyclone5/Arria5/Arria10 platforms. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-08-30ARM: dts: socfpga: update NAND clocking for c5/a5Dinh Nguyen1-2/+10
The NAND IP needs 3 clocks(nand_x_clk, nand_clk, and nand_ecc_clk). The nand_x_clk and nand_ecc_clk are derived from the nand_clk. The nand_x_clk has a fixed divider of 4. Also, update the NAND dts property with the correct clocks property. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> --- v2: add nand_ecc_clk and update commit message
2018-05-14ARM: dts: socfpga: Fix NAND controller node compatibleMarek Vasut1-1/+1
The compatible string for the Denali NAND controller is incorrect, fix it by replacing it with one matching the DT bindings and the driver. Cc: stable@vger.kernel.org Signed-off-by: Marek Vasut <marex@denx.de> Fixes: d837a80d19 ("ARM: dts: socfpga: add nand controller nodes") Cc: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-05-14ARM: dts: socfpga: Fix NAND controller clock supplyMarek Vasut1-1/+1
The Denali NAND x-clock should be supplied by nand_x_clk, not by nand_clk. Fix this, otherwise the Denali driver gets incorrect clock frequency information and incorrectly configures the NAND timing. Cc: stable@vger.kernel.org Signed-off-by: Marek Vasut <marex@denx.de> Fixes: d837a80d19 ("ARM: dts: socfpga: add nand controller nodes") Cc: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-03-23arm: dts: socfpga: fix GIC PPI warningPhilipp Puschmann1-1/+1
Fixes the warning "GIC: PPI13 is secure or misconfigured" by changing the interrupt type from level_low to edge_raising Signed-off-by: Philipp Puschmann <pp@emlix.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-01-23ARM: dts: socfpga: add i2c reset signalsTim Sander1-0/+4
Add the reset signals for the i2c controllers on Cyclone5-based SoCFPGA boards to the dtsi. Signed-off-by: Tim Sander <tim.sander@hbm.com> Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-06-23ARM: dts: socfpga: Fix the ethernet clock phandleMarek Vasut1-2/+2
The ethernet block clock phandle must point to the clock node which represents the clock which directly supply the ethernet block. This is emac_x_clk , not emacx_clk , so fix this. From: Pavel Machek <pavel@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-03-06ARM: dts: socfpga: Add support for PMUFlorian Vaussard1-0/+9
The dual Cortex-A9 MPCore inside socfpga has a standard PMU unit for each core mapped in the DAP memory space. Add support for it! Tested with perf on a Cyclone 5 SoC DK. Reported-by: Alberto Dassatti <alberto.dassatti@heig-vd.ch> Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch> Tested-by: Alberto Dassatti <alberto.dassatti@heig-vd.ch> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-03-06ARM: dts: socfpga: Add labels for CPU nodesFlorian Vaussard1-2/+2
This makes it easier to reference the CPU nodes afterwards. Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-03-06ARM: dts: socfpga: Do not include skeleton.dtsiFlorian Vaussard1-1/+0
The skeleton.dtsi file is now deprecated as noted in commit 9c0da3cc61f1 ("ARM: dts: explicitly mark skeleton.dtsi as deprecated"). The SoCFPGA device trees already contain the nodes that are defined in skeleton.dtsi (#address-cells, #size-cells, chosen, aliases, memory). Including skeleton.dtsi is useless and will produce the following warning when compiled with W=1: Node /memory has a reg or ranges property, but no unit name Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-03-06ARM: dts: socfpga: Remove unneeded unit namesFlorian Vaussard1-2/+2
Node eccmgr has a unit name, but do not have a reg property as only the child nodes do have this property. Likewise the usbphy node do not have a reg property. This will trigger the following warnings when compiled with W=1: Node /soc/eccmgr@ffd08140 has a unit name, but no reg property Node /soc/usbphy@0 has a unit name, but no reg property Remove the superfluous unit names. Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-03-06ARM: dts: socfpga: Add unit name to clock nodesFlorian Vaussard1-19/+19
Most clock nodes in Arria5, Cyclone5 and Arria10 have a reg property but does not have a unit name. This will trigger several warnings like this one (when compiled with W=1): Node /soc/clkmgr@ffd04000/clocks/periph_pll has a reg or ranges property, but no unit name Add the corresponding unit name to each node. Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-01-06ARM: dts: socfpga: add missing compatible string for SDRAM controllerDinh Nguyen1-1/+1
Add "altr,sdr-ctl" to the SDRAM controller node. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-01-06ARM: dts: socfpga: add base fpga region and fpga bridgesAlan Tull1-0/+27
Add h2f and lwh2f bridges. Add base FPGA Region to support DT overlays for FPGA programming. Add l3regs. Signed-off-by: Alan Tull <atull@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> --- v2: removed fpga-bridges, ranges, and reset-names
2017-01-05ARM: dts: socfpga: fpga manager data is 32 bitsDinh Nguyen1-1/+1
Adjust regs property for the FPGA manager data register to properly reflect that it is a single 32 bit register. Signed-off-by: Dalon Westergreen <dwesterg@altera.com> Signed-off-by: Alan Tull <atull@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2016-11-21ARM: dts: socfpga: fine-tune L2 cache configurationMarek Vasut1-0/+5
Enable double-linefill and increase prefetch offset, which gives considerable read performance boost. The following numbers were obtained using lmbench 3.0 bw_mem tool, for easier comparison, the numbers are pasted in two columns. The test machine has Cyclone V SoC running at 800MHz MPU clock and 512MiB 333MHz 16bit DDR3 DRAM. Without patch | With patch $ for i in rd wr rdwr cp fwr frd fcp bzero bcopy ; do echo $i ; bw_mem 64M $i ; done rd | rd 64.00 526.46 | 64.00 1151.06 wr | wr 64.00 329.95 | 64.00 346.14 rdwr | rdwr 64.00 342.07 | 64.00 367.24 cp | cp 64.00 239.79 | 64.00 322.47 fwr | fwr 64.00 1027.90 | 64.00 1025.38 frd | frd 64.00 322.36 | 64.00 641.89 fcp | fcp 64.00 256.99 | 64.00 408.41 bzero | bzero 64.00 1028.43 | 64.00 1025.07 bcopy | bcopy 64.00 294.73 | 64.00 357.19 Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-11-09ARM: dts: socfpga: add nand controller nodesSteffen Trumtrar1-0/+13
Add the denali nand controller to the socfpga dtsi. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2016-10-18ARM: dts: socfpga: add qspi nodeSteffen Trumtrar1-0/+14
Add the qspi node to the socfpga dtsi file. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-10-18ARM: dts: socfpga: enable arm,shared-override in the pl310Dinh Nguyen1-0/+1
Enable the bit(22) shared-override bit for the SoCFPGA family. While at it, enable the prefetch-data and prefetch-instr settings for the Arria10. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-04-11ARM: dts: socfpga: add reset control for USBDinh Nguyen1-0/+4
Add the resets property for the 2 USB controllers. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-03-20Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-socLinus Torvalds1-1/+1
Pull ARM DT updates from Arnd Bergmann: "These are all the updates to device tree files for 32-bit platforms, plus a couple of related 64-bit updates: New SoC support: - Allwinner A83T - Axis Artpec-6 SoC - Mediatek MT7623 SoC - TI Keystone K2G SoC - ST Microelectronics stm32f469 New board or machine support: - ARM Juno R2 - Buffalo Linkstation LS-QVL and LS-GL - Cubietruck plus - D-Link DIR-885L - DT support for ARM RealView PB1176 and PB11MPCore - Google Nexus 7 - Homlet v2 - Itead Ibox - Lamobo R1 - LG Optimus Black - Logicpd dm3730 - Raspberry Pi Model A Other changes include - Lots of updates for Qualcomm APQ8064, MSM8974 and others - Improved support for Nokia N900 and other OMAP machines - Common clk support for lpc32xx - HDLCD display on ARM - Improved stm32f429 support - Improved Renesas device support, r8a779x and others - Lots of Rockchip updates - Samsung cleanups - ADC support for Atmel SAMA5D2 - BCM2835 (Raspberry Pi) improvements - Broadcom Northstar Plus enhancements - OMAP GPMC rework - Several improvements for Atmel SAMA5D2 / Xplained - Global change to remove inofficial "arm,amba-bus" compatible string" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (350 commits) ARM, ARM64: dts: drop "arm,amba-bus" in favor of "simple-bus" ARM: dts: artpec: dual-license on artpec6.dtsi ARM: dts: ux500: add synaptics RMI4 for Ux500 TVK DT arm64: dts: juno/vexpress: fix node name unit-address presence warnings arm64: dts: foundation-v8: add SBSA Generic Watchdog device node ARM: dts: at91: sama5d2 Xplained: add leds node ARM: dts: at91: sama5d2 Xplained: add user push button ARM: dts: at91: sama5d2 Xplained: set pin muxing for usb gadget and usb host ARM: dts: stm32f429: Enable Ethernet on Eval board ARM: dts: omap3-sniper: TWL4030 keypad support Revert "ARM: dts: DRA7: Add dt nodes for PWMSS" ARM: dts: dm814x: dra62x: Disable wait pin monitoring for NAND ARM: dts: dm814x: dra62x: Fix NAND device nodes ARM: dts: stm32f429: Add Ethernet support ARM: dts: stm32f429: Add system config bank node ARM: dts: at91: sama5d2: add nand0 and nfc0 nodes ARM: dts: at91: sama5d2: add dma properties to UART nodes ARM: dts: at91: sama5d2 Xplained: Correct the macb irq pinctrl node ARM: dts: exynos: Don't overheat the Odroid XU3-Lite on high load ARM: dts: exynos: Add cooling levels for Exynos5422/5800 CPUs ...
2016-03-12ARM, ARM64: dts: drop "arm,amba-bus" in favor of "simple-bus"Masahiro Yamada1-1/+1
The compatible string "simple-bus" is well defined in ePAPR, while I see no documentation for the "arm,amba-bus" arnywhere in ePAPR or Documentation/devicetree/. DT is also used by other projects than Linux kernel. It is not a good idea to rely on such an unofficial binding. This commit - replaces "arm,amba-bus" with "simple-bus" - drops "arm,amba-bus" where it is used along with "simple-bus" Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2016-02-11ARM: dts: Add Altera L2 Cache and OCRAM EDAC entriesThor Thayer1-0/+20
Add the device tree entries and bindings needed to support the Altera L2 cache and On-Chip RAM EDAC. This patch relies upon an earlier patch to declare and setup On-chip RAM properly: 8b907c8b62ac ("arm: dts: socfpga: Add OCRAM node") Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Acked-by: Rob Herring <robh@kernel.org> Cc: devicetree@vger.kernel.org Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: galak@codeaurora.org Cc: grant.likely@linaro.org Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: ijc+devicetree@hellion.org.uk Cc: Kumar Gala <galak@codeaurora.org> Cc: linux-arm-kernel@lists.infradead.org Cc: linux@arm.linux.org.uk Cc: linux-doc@vger.kernel.org Cc: linux-edac <linux-edac@vger.kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: m.chehab@samsung.com Cc: Pawel Moll <pawel.moll@arm.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Russell King <linux@arm.linux.org.uk> Link: http://lkml.kernel.org/r/1455132384-17108-2-git-send-email-tthayer@opensource.altera.com Signed-off-by: Borislav Petkov <bp@suse.de>
2015-12-21ARM: socfpga: dts: Enable MMC support at correct place in the DTMarek Vasut1-0/+1
The socfpga.dtsi explicitly enabled MMC support, but not all boards are equiped with an MMC card. There are setups which only have QSPI NOR. Therefore, disable the MMC support on socfpga.dtsi level and enable it on per-board basis. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alan Tull <atull@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Olof Johansson <olof@lixom.net> Cc: Thor Thayer <tthayer@altera.com> Cc: Vince Bridgers <vbridgers2013@gmail.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-10-22Merge tag 'socfpga_for_v4.4_cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into next/dtOlof Johansson1-64/+64
SoCFPGA dts cleanup for v4.4 - Re-order DTS nodes into correct alphabetical order * tag 'socfpga_for_v4.4_cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: ARM: socfpga: dts: sort nodes alphabetically Signed-off-by: Olof Johansson <olof@lixom.net>
2015-10-16ARM: socfpga: dts: sort nodes alphabeticallySteffen Trumtrar1-64/+64
The sorting policy for this file is alphabetically. Reorder all nodes, that are out of place. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-10-15ARM: socfpga: dts: add fpga managerAlan Tull1-0/+7
Add FPGA manager to device tree for SoCFPGA. Signed-off-by: Alan Tull <atull@opensource.altera.com> Reviewed-by: Moritz Fischer <moritz.fischer@ettus.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-08-13Merge tag 'socfpga_dts_for_v4.3_part_2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into next/dtOlof Johansson1-0/+1
SoCFPGA DTS updates for v4.3, take 2 - Add DTS property "altr,modrst-offset" for reset driver to use - Add updated reset defines for the reset driver - Add reset property for EMACs on Arria10 * tag 'socfpga_dts_for_v4.3_part_2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: ARM: socfpga: dts: Add resets for EMACs on Arria10 ARM: socfpga: dts: add "altr,modrst-offset" property dt-bindings: Add reset manager offsets for Arria10 Signed-off-by: Olof Johansson <olof@lixom.net>
2015-08-09ARM: socfpga: dts: add "altr,modrst-offset" propertyDinh Nguyen1-0/+1
The "altr,modrst-offset" property represents the offset into the reset manager that is the first register to be used by the driver to bring peripherals out of reset. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-07-24ARM: socfpga: dts: add osc1 as a possible parent for dbg_base_clkDinh Nguyen1-1/+1
The dbg_base_clk can also have osc1 has a parent. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-07-22ARM: socfpga: dts: add missing clock gates to socfpga.dtsiMatthew Gerlach1-1/+30
The gates for the clocks coming out of the sdram pll were missing. The change adds the missing nodes to the device tree. Signed-off-by: Matthew Gerlach <mgerlach@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-07-22ARM: socfpga: dts: Fix gpio dts entry for the correct clockDinh Nguyen1-3/+3
The correct clock for the HPS gpio(s) should be the l4_mp_clk. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-07-22ARM: socfpga: dts: Correct the parent clock for l3_sp_clk and dbg_clkDinh Nguyen1-2/+2
The l3_sp_clk's parent should be the l3_mp_clk. This will account for the extra divider that is present for the l3_mp_clk. The dbg_clk's parent should be the dbg_at_clk. This will account for the extra divider that is present for the dbg_at_clk. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-07-20ARM: dts: socfpga: enable the data and instruction prefetch for the l2 cacheDinh Nguyen1-0/+2
Just in case the firmware did not enable data and instruction prefetch in the L2 cache controller, we enable it in the kernel. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-06-10Merge tag 'socfpga_dts_for_v4.2_part_3' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into next/dtKevin Hilman1-0/+1
SoCFPGA updates for v4.2 part 3 - Add SCU node for Arria 10 - Add enable-method for cpu nodes - Add SDRAM controller binding doc - Enable gpio-leds on SoCFPGA Socrates board * tag 'socfpga_dts_for_v4.2_part_3' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: ARM: socfpga: socrates: add gpio-leds ARM: socfpga: socrates: enable gpio0/1 ARM: socfpga: dts: add sdram controller dt binding doc ARM: socfpga: dts: add enable-method property for cpu nodes ARM: socfpga: dts: add the a9-scu node for arria10
2015-06-02ARM: socfpga: dts: add enable-method property for cpu nodesDinh Nguyen1-0/+1
Add the enable-method property for the cpu node on socfpga.dtsi and socfpga_arria10.dtsi. This is for CPU_METHOD_OF_DECLARE to use to enable the secondary core. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-05-13Merge tag 'socfpga_dts_for_v4.2_part_2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into next/dtArnd Bergmann1-0/+5
Merge "SoCFPGA update for v4.2 part 2" from Dinh Nguyen: - Add a DTS node for the A9 SCU * tag 'socfpga_dts_for_v4.2_part_2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: ARM: socfpga: dts: add the a9-scu node
2015-05-13ARM: socfpga: dts: add the a9-scu nodeDinh Nguyen1-0/+5
Add the dts node for the A9 SCU. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-05-11ARM: socfpga: dts: Add tx-fifo-depth and rx-fifo-depth propertiesVince Bridgers1-0/+4
Add tx-fifo-depth and rx-fifo-depth devicetree properties for socfpga stmmac. These devicetree properties will be used to configure certain features of the stmmac on the socfpga. Signed-off-by: Vince Bridgers <vbridger@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-05-11ARM: socfpga: dts: Add a clock node for sdmmc CIUDinh Nguyen1-1/+9
The CIU(Card Interface Unit) get its clock from the sdmmc_clk_divided clock which is used to clock the card. The sdmmc_clk_divided clock is the sdmmc_clk passed through a fixed divider of 4. This patch adds the sdmmc_clk_divided node and makes the sdmmc_clk it's parent. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> --- v2: renamed ciu_clk to sdmmc_clk_divided
2015-03-19ARM: socfpga: dts: fix spi1 interruptMark James1-1/+1
The socfpga.dtsi currently has the wrong interrupt number set for SPI master 1 Trying to use the master without this change results in the kernel boot process waiting forever for an interrupt that will never occur while attempting to probe any slave devices configured in the device tree as being under SPI master 1. The change works for the Cyclone V, and according to the Arria 5 handbook should be good there too. Signed-off-by: Mark James <maj@jamers.net> Acked-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-03-04ARM: socfpga: fix uart DMA binding errorSteffen Trumtrar1-0/+6
socfpga.dtsi is missing the DMA channels for the uart nodes. This will produce the following errors: of_dma_request_slave_channel: dma-names property of node '/soc/serial0@ffc02000' missing or empty ttyS0 - failed to request DMA Provide the correct DMA channels to fix this. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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