linux-dev - Linux kernel development work

Age	Commit message (Collapse)	Author	Files	Lines
2017-06-23	ARM: dts: socfpga: Add second ethernet alias to VINING FPGA	Marek Vasut	1	-0/+1
	Add DT alias for the second ethernet present on mainboard rev 1.10. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-06-23	ARM: dts: socfpga: Drop LED node from VINING FPGA	Marek Vasut	1	-28/+0
	Drop the LED node from VINing FPGA DT because the LED wiring is different on each mainboard revision. This wiring is therefore handled in mainboard DT Overlays. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-06-23	ARM: dts: socfpga: Remove I2C EEPROMs from VINING FPGA	Marek Vasut	1	-32/+2
	Remove the EEPROMs attached to the I2C expander ports which lead to the backplane slots from the main VIN\|ING DTS file. These EEPROMs are bound using separate DTO files, which lets us handle both two-slot and six-slot configuration of the backplane. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-06-23	ARM: dts: socfpga: Enable QSPI support on VINING FPGA	Marek Vasut	1	-0/+38
	Enable the QSPI node and add the flash chips. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-03-06	ARM: dts: socfpga: Add unit name to memory nodes	Florian Vaussard	1	-1/+1
	Memory nodes in Arria5, Cyclone5 and Arria10 do not have a unit name. This will trigger several warnings like this one (when compiled with W=1): Node /memory has a reg or ranges property, but no unit name Add the corresponding unit name to each node. Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2016-11-08	ARM: dts: socfpga: add specific compatible strings for boards	Dinh Nguyen	1	-1/+1
	Add a more specific board compatible entry for all of the SOCFPGA Cyclone 5 based boards. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> --- v3: Be a bit more specific with the c5 dk and sockit, use "altr,socfpga-cyclone5-socdk" and "terasic,socfpga-cyclone5-sockit" v2: remove extra space and add a comma between compatible entries
2016-06-08	ARM: dts: socfpga: Add missing PHY phandle	Marek Vasut	1	-0/+1
	Add missing PHY phandle into the DT, otherwise the stmmac code won't detect the PHY correctly anymore. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-04-22	ARM: dts: socfpga: Add samtec VIN\|ING board	Marek Vasut	1	-0/+310
	Add support for board based on the popular Altera Cyclone V SoC. This board has the following properties: - 1 GiB of DRAM - 1 Gigabit ethernet - 1 USB gadget port - 1 USB host port with an on-board hub - 2 QSPI NORs connected to the Cadence QSPI core - Multiple I2C EEPROMs and one I2C temperature sensor Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>