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2022-05-12ARM: dts: socfpga: align SPI NOR node name with dtschemaKrzysztof Kozlowski1-2/+2
The node names should be generic and SPI NOR dtschema expects "flash". Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2021-12-03ARM: socfpga: dts: fix qspi node compatibleDinh Nguyen1-2/+2
The QSPI flash node needs to have the required "jedec,spi-nor" in the compatible string. Fixes: 1df99da8953 ("ARM: dts: socfpga: Enable QSPI in Arria10 devkit") Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2019-07-30ARM: dts: socfpga: Adjust GMAC1 clock and TXD lines skew on VINING FPGAMarek Vasut1-2/+6
Adjust GMAC1 clock lines skew to maximum (+960 ps) and TXD lines skew to minimum (-420 ps), to improve signal integrity. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2019-07-30ARM: dts: socfpga: Fix up button mapping on VINING FPGAMarek Vasut1-5/+17
Add missing buttons and signals to the VINING FPGA device tree, so they are presented to the userspace via gpio-keys evdev. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-11-28arm: dts: socfpga*.dts*: use SPDX-License-IdentifierSimon Goldschmidt1-44/+2
Follow the recent trend for the license description. This is also in an effort to fully sync the devicetrees with U-Boot. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-08-30ARM: dts: socfpga: use stdout-path for chosen nodeSimon Goldschmidt1-1/+2
Use stdout-path dts property for kernel console. There were two socfpga boards left not using stdout-path: socrates and vining. Make sure they match the other boards. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-04-24ARM: dts: consistently use 'atmel' as at24 manufacturer in cyclone5Bartosz Golaszewski1-3/+3
Using 'at' or 'at24' as the <manufacturer> part of the compatible string is now deprecated. Use a correct value: 'atmel,<model>'. Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-12-21ARM: dts: socfpga: Add generic compatible string for I2C EEPROMJavier Martinez Canillas1-1/+1
The at24 driver allows to register I2C EEPROM chips using different vendor and devices, but the I2C subsystem does not take the vendor into account when matching using the I2C table since it only has device entries. But when matching using an OF table, both the vendor and device has to be taken into account so the driver defines only a set of compatible strings using the "atmel" vendor as a generic fallback for compatible I2C devices. So add this generic fallback to the device node compatible string to make the device to match the driver using the OF device ID table. Signed-off-by: Javier Martinez Canillas <javierm@redhat.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-06-23ARM: dts: socfpga: Add second ethernet alias to VINING FPGAMarek Vasut1-0/+1
Add DT alias for the second ethernet present on mainboard rev 1.10. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-06-23ARM: dts: socfpga: Drop LED node from VINING FPGAMarek Vasut1-28/+0
Drop the LED node from VINing FPGA DT because the LED wiring is different on each mainboard revision. This wiring is therefore handled in mainboard DT Overlays. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-06-23ARM: dts: socfpga: Remove I2C EEPROMs from VINING FPGAMarek Vasut1-32/+2
Remove the EEPROMs attached to the I2C expander ports which lead to the backplane slots from the main VIN|ING DTS file. These EEPROMs are bound using separate DTO files, which lets us handle both two-slot and six-slot configuration of the backplane. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-06-23ARM: dts: socfpga: Enable QSPI support on VINING FPGAMarek Vasut1-0/+38
Enable the QSPI node and add the flash chips. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-03-06ARM: dts: socfpga: Add unit name to memory nodesFlorian Vaussard1-1/+1
Memory nodes in Arria5, Cyclone5 and Arria10 do not have a unit name. This will trigger several warnings like this one (when compiled with W=1): Node /memory has a reg or ranges property, but no unit name Add the corresponding unit name to each node. Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2016-11-08ARM: dts: socfpga: add specific compatible strings for boardsDinh Nguyen1-1/+1
Add a more specific board compatible entry for all of the SOCFPGA Cyclone 5 based boards. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> --- v3: Be a bit more specific with the c5 dk and sockit, use "altr,socfpga-cyclone5-socdk" and "terasic,socfpga-cyclone5-sockit" v2: remove extra space and add a comma between compatible entries
2016-06-08ARM: dts: socfpga: Add missing PHY phandleMarek Vasut1-0/+1
Add missing PHY phandle into the DT, otherwise the stmmac code won't detect the PHY correctly anymore. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-04-22ARM: dts: socfpga: Add samtec VIN|ING boardMarek Vasut1-0/+310
Add support for board based on the popular Altera Cyclone V SoC. This board has the following properties: - 1 GiB of DRAM - 1 Gigabit ethernet - 1 USB gadget port - 1 USB host port with an on-board hub - 2 QSPI NORs connected to the Cadence QSPI core - Multiple I2C EEPROMs and one I2C temperature sensor Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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