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path: root/arch/arm/mm/cache-l2x0.c (follow)
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2019-08-29ARM: 8890/1: l2x0: add marvell,ecc-enable property for auroraChris Packham1-0/+5
2019-08-29ARM: 8886/1: l2x0: support parity-enable/disable on auroraChris Packham1-0/+7
2019-08-29ARM: 8887/1: aurora-l2: add prefix to MAX_RANGE_SIZEJan Luebbe1-2/+2
2019-08-29ARM: 8902/1: l2c: move cache-aurora-l2.h to asm/hardwareJan Luebbe1-1/+1
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 333Thomas Gleixner1-13/+1
2017-03-17ARM: 8659/1: l2c: allow CA9 optimizations to be disabledChris Brandt1-2/+11
2016-12-25cpu/hotplug: Cleanup state namesThomas Gleixner1-1/+1
2016-09-06ARM: 8611/1: l2x0: add PMU supportMark Rutland1-0/+6
2016-08-12ARM: 8593/1: cache-l2x0.c: Do not clear bit 23 in prefetch control registerAndrey Smirnov1-5/+2
2016-08-12ARM: 8592/1: cache-l2x0.c: Replace magic numbersAndrey Smirnov1-2/+4
2016-07-15arm/l2c: Convert to hotplug state machineRichard Cochran1-14/+13
2016-05-05ARM: 8569/1: pl2x0: Add OF control of cache power managementBrad Mouring1-5/+21
2015-12-22ARM: 8482/1: l2x0: make it possible to disable outer sync from DTLinus Walleij1-3/+10
2015-11-16ARM: 8448/1: add some L220 DT settingsLinus Walleij1-0/+20
2015-07-10ARM: 8395/1: l2c: Add support for the "arm,shared-override" propertyGeert Uytterhoeven1-0/+5
2015-06-10ARM: 8391/1: l2c: add options to overwrite prefetching behaviorHauke Mehrtens1-0/+20
2015-05-15ARM: l2c: avoid passing auxiliary control register through enable methodRussell King1-15/+17
2015-05-15ARM: l2c: only unlock caches if NS_LOCKDOWN bit is setRussell King1-1/+25
2015-05-15ARM: l2c: clean up l2c_configure()Russell King1-9/+14
2015-05-15ARM: l2c: write auxiliary control register firstRussell King1-2/+2
2015-05-15ARM: l2c: restore the behaviour documented above l2c_enable()Russell King1-5/+5
2015-04-14Merge branches 'misc', 'vdso' and 'fixes' into for-nextRussell King1-17/+16
2015-03-18ARM: 8310/1: l2c: Fix prefetch settings dt parsingFabrice Gasnier1-17/+16
2015-03-10ARM: 8309/1: l2c: enforce use of cache-level propertyFlorian Fainelli1-0/+7
2015-02-12Merge branch 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-armLinus Torvalds1-209/+230
2015-02-06ARM: 8297/1: cache-l2x0: optimize aurora range operationsArnd Bergmann1-46/+22
2015-02-06ARM: 8296/1: cache-l2x0: clean up aurora cache handlingArnd Bergmann1-73/+38
2015-01-20ARM: cache-l2x0.c: Make it clear that cache-l2x0 handles L310 cache controllerPavel Machek1-1/+1
2015-01-20ARM: l2c: fix commentGeert Uytterhoeven1-1/+1
2015-01-16ARM: 8262/1: l2c: Add support for overriding prefetch settingsTomasz Figa1-0/+54
2015-01-16ARM: 8260/1: l2c: Add interface to ask hypervisor to configure L2CTomasz Figa1-0/+6
2015-01-16ARM: 8259/1: l2c: Refactor the driver to use commit-like interfaceTomasz Figa1-96/+116
2015-01-16ARM: 8258/1: l2c: use l2c_write_sec() for restoring latency and filter regsMarek Szyprowski1-16/+16
2014-10-29ARM: 8183/1: l2c: Improve l2c310_of_parse() error messageFabio Estevam1-2/+2
2014-10-29ARM: 8182/1: l2c: Make l2x0_cache_size_of_parse() return 'int'Fabio Estevam1-6/+16
2014-10-02ARM: 8169/1: l2c: parse cache properties from ePAPR definitionsLinus Walleij1-0/+121
2014-08-05Merge branches 'fixes' and 'misc' into for-nextRussell King1-1/+1
2014-07-18ARM: make it easier to check the CPU part number correctlyRussell King1-1/+1
2014-07-07ARM: l2c: fix revision checkingRussell King1-1/+1
2014-06-29ARM: 8076/1: mm: add support for HW coherent systems in PL310 cacheThomas Petazzoni1-0/+31
2014-05-30ARM: l2c: trial at enabling some Cortex-A9 optimisationsRussell King1-3/+70
2014-05-30ARM: l2c: add warnings for stuff modifying aux_ctrl register valuesRussell King1-3/+22
2014-05-30ARM: l2c: print a warning with L2C-310 caches if the cache size is modifiedRussell King1-0/+2
2014-05-30ARM: l2c: remove old .set_debug methodRussell King1-19/+2
2014-05-30ARM: l2c: always enable non-secure access to lockdown registersRussell King1-2/+21
2014-05-30ARM: l2c: always enable low power modesRussell King1-0/+12
2014-05-30ARM: l2c: add automatic enable of early BRESPRussell King1-3/+22
2014-05-30ARM: l2c: move L2 cache register saving to a more sensible locationRussell King1-12/+22
2014-05-30ARM: l2c: check that DT files specify the required "cache-unified" propertyRussell King1-0/+4
2014-05-30ARM: l2c: fix register namingRussell King1-28/+29
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