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2019-04-12arm64: tegra: Add L2 cache topology to Tegra210Joseph Lo1-0/+8
Add L2 cache and make it the next level of cache for each of the CPUs. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-04-12arm64: tegra: Add CPU idle states properties for Tegra210Joseph Lo1-0/+19
Add idle states properties for generic ARM CPU idle driver. This includes a cpu-sleep state which is the power down state of CPU cores. Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-04-12arm64: tegra: Fix timer node for Tegra210Joseph Lo1-3/+11
Fix timer node to make it work with Tegra210 timer driver. Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-07arm64: tegra: Update compatible for Tegra210 I2CSowjanya Komatineni1-6/+6
Update I2C device node compatible string to be appropriate. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-07arm64: tegra: Add SDMMC auto-calibration settingsSowjanya Komatineni1-2/+55
Add SDMMC initial pad offsets used by auto calibration process. Add SDMMC fixed drive strengths for Tegra210, Tegra186 and Tegra194 which are used when calibration timeouts. Fixed drive strengths are based on Pre SI Analysis of the pads. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-07arm64: tegra: Add CPU clocks on Tegra210Joseph Lo1-0/+6
Add CPU clocks for Tegra210. Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-07arm64: tegra: Add DFLL clock on Tegra210Joseph Lo1-0/+19
Add essential DFLL clock properties for Tegra210. Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-01-25arm64: tegra: Fix register range of apbmisc on Tegra210Joseph Lo1-1/+1
Fix the register range of apbmisc, that originally inherited from Tegra124. Reported-by: Mark Zhang <markz@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-11-28arm64: dts: tegra210: Add power-domains for xHCIJon Hunter1-0/+2
Populate the power-domain properties for the xHCI device for Tegra210. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-08-27arm64: dts: tegra210: Enable HS400Aapo Vienamo1-0/+1
Enable HS400 signaling on Tegra210 SDMMC4 controller. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-08-27arm64: dts: tegra210: Add SDMMC4 DQS trim valueAapo Vienamo1-0/+1
Add the HS400 DQS trim value for Tegra210 SDMMC4. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-08-27arm64: dts: tegra210: Assign clocks for sdmmc1 and sdmmc4Aapo Vienamo1-0/+8
Use assigned-clock properties to configure pllc4 as the parent clock for sdmmc4 on Tegra210. pllc4 offers better jitter perfomance than the default pllp and is required by HS200 and HS400 modes. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-08-27arm64: dts: tegra210: Add SDHCI tap and trim valuesAapo Vienamo1-0/+8
Add SDHCI inbound and outbound SDHCI sampling trimmer values for Tegra210. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-08-27arm64: dts: tegra210: Add sdmmc pad auto calibration offsetsAapo Vienamo1-0/+12
Add the calibration offset properties used for automatic pad drive strength calibration. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-08-27arm64: dts: Add Tegra210 sdmmc pinctrl voltage statesAapo Vienamo1-0/+27
Add pad voltage configuration nodes for sdmmc pads with configurable voltages on Tegra210. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-14arm64: tegra: Add SATA node for Tegra210Preetham Ramchandra1-0/+16
Populate the SATA node for Tegra210. Signed-off-by: Preetham Ramchandra <pchandru@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-15arm64: tegra: Use sor1_out clockThierry Reding1-2/+2
Use the sor1_out clock instead of sor1_src. This is a more accurate model of the hardware and allows for more complicated configurations such as HDMI 2.0. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-11-02License cleanup: add SPDX GPL-2.0 license identifier to files with no licenseGreg Kroah-Hartman1-0/+1
Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine the correct license. By default all files without license information are under the default license of the kernel, which is GPL version 2. Update the files which contain no license information with the 'GPL-2.0' SPDX license identifier. The SPDX identifier is a legally binding shorthand, which can be used instead of the full boiler plate text. This patch is based on work done by Thomas Gleixner and Kate Stewart and Philippe Ombredanne. How this work was done: Patches were generated and checked against linux-4.14-rc6 for a subset of the use cases: - file had no licensing information it it. - file was a */uapi/* one with no licensing information in it, - file was a */uapi/* one with existing licensing information, Further patches will be generated in subsequent months to fix up cases where non-standard license headers were used, and references to license had to be inferred by heuristics based on keywords. The analysis to determine which SPDX License Identifier to be applied to a file was done in a spreadsheet of side by side results from of the output of two independent scanners (ScanCode & Windriver) producing SPDX tag:value files created by Philippe Ombredanne. Philippe prepared the base worksheet, and did an initial spot review of a few 1000 files. The 4.13 kernel was the starting point of the analysis with 60,537 files assessed. Kate Stewart did a file by file comparison of the scanner results in the spreadsheet to determine which SPDX license identifier(s) to be applied to the file. She confirmed any determination that was not immediately clear with lawyers working with the Linux Foundation. Criteria used to select files for SPDX license identifier tagging was: - Files considered eligible had to be source code files. - Make and config files were included as candidates if they contained >5 lines of source - File already had some variant of a license header in it (even if <5 lines). All documentation files were explicitly excluded. The following heuristics were used to determine which SPDX license identifiers to apply. - when both scanners couldn't find any license traces, file was considered to have no license information in it, and the top level COPYING file license applied. For non */uapi/* files that summary was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 11139 and resulted in the first patch in this series. If that file was a */uapi/* path one, it was "GPL-2.0 WITH Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 WITH Linux-syscall-note 930 and resulted in the second patch in this series. - if a file had some form of licensing information in it, and was one of the */uapi/* ones, it was denoted with the Linux-syscall-note if any GPL family license was found in the file or had no licensing in it (per prior point). Results summary: SPDX license identifier # files ---------------------------------------------------|------ GPL-2.0 WITH Linux-syscall-note 270 GPL-2.0+ WITH Linux-syscall-note 169 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17 LGPL-2.1+ WITH Linux-syscall-note 15 GPL-1.0+ WITH Linux-syscall-note 14 ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5 LGPL-2.0+ WITH Linux-syscall-note 4 LGPL-2.1 WITH Linux-syscall-note 3 ((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3 ((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1 and that resulted in the third patch in this series. - when the two scanners agreed on the detected license(s), that became the concluded license(s). - when there was disagreement between the two scanners (one detected a license but the other didn't, or they both detected different licenses) a manual inspection of the file occurred. - In most cases a manual inspection of the information in the file resulted in a clear resolution of the license that should apply (and which scanner probably needed to revisit its heuristics). - When it was not immediately clear, the license identifier was confirmed with lawyers working with the Linux Foundation. - If there was any question as to the appropriate license identifier, the file was flagged for further research and to be revisited later in time. In total, over 70 hours of logged manual review was done on the spreadsheet to determine the SPDX license identifiers to apply to the source files by Kate, Philippe, Thomas and, in some cases, confirmation by lawyers working with the Linux Foundation. Kate also obtained a third independent scan of the 4.13 code base from FOSSology, and compared selected files where the other two scanners disagreed against that SPDX file, to see if there was new insights. The Windriver scanner is based on an older version of FOSSology in part, so they are related. Thomas did random spot checks in about 500 files from the spreadsheets for the uapi headers and agreed with SPDX license identifier in the files he inspected. For the non-uapi files Thomas did random spot checks in about 15000 files. In initial set of patches against 4.14-rc6, 3 files were found to have copy/paste license identifier errors, and have been fixed to reflect the correct identifier. Additionally Philippe spent 10 hours this week doing a detailed manual inspection and review of the 12,461 patched files from the initial patch version early this week with: - a full scancode scan run, collecting the matched texts, detected license ids and scores - reviewing anything where there was a license detected (about 500+ files) to ensure that the applied SPDX license was correct - reviewing anything where there was no detection but the patch license was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied SPDX license was correct This produced a worksheet with 20 files needing minor correction. This worksheet was then exported into 3 different .csv files for the different types of files to be modified. These .csv files were then reviewed by Greg. Thomas wrote a script to parse the csv files and add the proper SPDX tag to the file, in the format that the file expected. This script was further refined by Greg based on the output to detect more types of files automatically and to distinguish between header and source .c files (which need different comment types.) Finally Greg ran the script using the .csv files to generate the patches. Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-06-13arm64: dts: nvidia: fix PCI bus dtc warningsRob Herring1-1/+3
dtc recently added PCI bus checks. Fix these warnings. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Alexandre Courbot <gnurou@gmail.com> Cc: linux-tegra@vger.kernel.org Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-03-20arm64: tegra: Enable IOMMU for host1x on Tegra210Mikko Perttunen1-0/+2
The host1x driver now supports operation behind an IOMMU, so add its IOMMU domain to the device tree. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-03-20arm64: tegra: Enable VIC on Tegra210Mikko Perttunen1-1/+16
Enable the VIC (Video Image Compositor) host1x unit on Tegra210 systems. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-12-07arm64: tegra: Add PCIe host bridge on Tegra210Thierry Reding1-0/+63
Add the PCIe host bridge found on Tegra X1. It implements two root ports that support x4 and x1 configurations, respectively. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Bjorn Helgaas <helgaas@kernel.org>
2016-10-12Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/rzhang/linuxLinus Torvalds1-0/+127
Pull thermal managament updates from Zhang Rui: - Enhance thermal "userspace" governor to export the reason when a thermal event is triggered and delivered to user space. From Srinivas Pandruvada - Introduce a single TSENS thermal driver for the different versions of the TSENS IP that exist, on different qcom msm/apq SoCs'. Support for msm8916, msm8960, msm8974 and msm8996 families is also added. From Rajendra Nayak - Introduce hardware-tracked trip points support to the device tree thermal sensor framework. The framework supports an arbitrary number of trip points. Whenever the current temperature is changed, the trip points immediately below and above the current temperature are found, driver callback is invoked to program the hardware to get notified when either of the two trip points are triggered. Hardware-tracked trip points support for rockchip thermal driver is also added at the same time. From Sascha Hauer, Caesar Wang - Introduce a new thermal driver, which enables TMU (Thermal Monitor Unit) on QorIQ platform. From Jia Hongtao - Introduce a new thermal driver for Maxim MAX77620. From Laxman Dewangan - Introduce a new thermal driver for Intel platforms using WhiskeyCove PMIC. From Bin Gao - Add mt2701 chip support to MTK thermal driver. From Dawei Chien - Enhance Tegra thermal driver to enable soctherm node and set "critical", "hot" trips, for Tegra124, Tegra132, Tegra210. From Wei Ni - Add resume support for tango thermal driver. From Marc Gonzalez - several small fixes and improvements for rockchip, qcom, imx, rcar, mtk thermal drivers and thermal core code. From Caesar Wang, Keerthy, Rocky Hao, Wei Yongjun, Peter Robinson, Bui Duc Phuc, Axel Lin, Hugh Kang * 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/rzhang/linux: (48 commits) thermal: int3403: Process trip change notification thermal: int340x: New Interface to read trip and notify thermal: user_space gov: Add additional information in uevent thermal: Enhance thermal_zone_device_update for events arm64: tegra: set hot trips for Tegra210 arm64: tegra: set critical trips for Tegra210 arm64: tegra: add soctherm node for Tegra210 arm64: tegra: set hot trips for Tegra132 arm64: tegra: set critical trips for Tegra132 arm64: tegra: use tegra132-soctherm for Tegra132 arm: tegra: set hot trips for Tegra124 arm: tegra: set critical trips for Tegra124 thermal: tegra: add hw-throttle for Tegra132 thermal: tegra: add hw-throttle function of: Add bindings of hw throttle for Tegra soctherm thermal: mtk_thermal: Check return value of devm_thermal_zone_of_sensor_register thermal: Add Mediatek thermal driver for mt2701. dt-bindings: thermal: Add binding document for Mediatek thermal controller thermal: max77620: Add thermal driver for reporting junction temp thermal: max77620: Add DT binding doc for thermal driver ...
2016-09-27arm64: tegra: set hot trips for Tegra210Wei Ni1-9/+32
Enable throttle function for SOC_THERM. Set "hot" trips for cpu and gpu thermal zones, which can trigger the SOC_THERM hardware throttle. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
2016-09-27arm64: tegra: set critical trips for Tegra210Wei Ni1-0/+60
Set general "critical" trip temperatures for cpu, gpu, mem and pllx thermal zones on Tegra210, these trips can trigger shut down or reset. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
2016-09-27arm64: tegra: add soctherm node for Tegra210Wei Ni1-0/+44
Adds soctherm node for Tegra210, and add cpu, gpu, mem, pllx as thermal-zones. Set critical trip temperatures for them. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
2016-08-24arm64: tegra: Add SOR power-domain for Tegra210Jon Hunter1-0/+27
Add node for SOR power-domain for Tegra210 and populate the SOR power-domain phandle for DPAUX, DSI, MIPI-CAL and SOR and nodes that are dependent on this power-domain. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-08-24arm64: tegra: Add ADMA node for Tegra210Jon Hunter1-0/+32
Populate the ADMA node for Tegra210. The ADMA is used by the Audio Processing Engine (APE) on Tegra210 for moving data between the APE and system memory. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-08-24arm64: tegra: Add AGIC node for Tegra210Jon Hunter1-0/+12
Populate the Audio GIC (AGIC) node for Tegra210. This interrupt controller is used by the Audio Processing Engine to route interrupts to the main CPU interrupt controller. The AGIC is based on the ARM GIC400 and so uses the clock name "clk" as specified by the GIC binding document for GIC400 devices. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-08-24arm64: tegra: Drop clock and reset names for XUSB powergatesJon Hunter1-6/+0
Drop the clock and reset names for the Tegra210 XUSB powergates because these are not currently used and not required by the Tegra PMC binding documentation. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-08-16arm64: tegra: Simplify Tegra210 GPIO compatible valueStephen Warren1-1/+1
The compatible value need only include an entry for the specific HW generation, plus the oldest HW version that introduced changes it is backwards-compatible with; intermediate versions aren't necessary. Since Tegra124 GPIO is backwards-compatible with Tegra30 GPIO, there's no need to include the Tegra124 value in the Tegra210 DTS. This makes the kernel DT better match the copy of the DT files included in U-Boot. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-14arm64: tegra: Add sor1_src clockThierry Reding1-1/+2
The sor1 IP block needs the sor1_src clock to configure the clock tree depending on whether it's running in HDMI or DP mode. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-14arm64: tegra: Add XUSB powergates on Tegra210Jon Hunter1-0/+24
The Tegra210 XUSB subsystem has 3 power partitions which are XUSBA (super-speed logic), XUSBB (USB device logic) and XUSBC (USB host logic). Populate the device-tree nodes for these XUSB partitions. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-14arm64: tegra: Add DPAUX pinctrl bindingsJon Hunter1-0/+54
Add the DPAUX pinctrl states for the DPAUX nodes defining all three possible states of "aux", "i2c" and "off". Also add the 'i2c-bus' node for the DPAUX nodes so that the I2C driver core does not attempt to parse the pinctrl state nodes. Populate the nodes for the pinctrl clients of the DPAUX pin controller. There are two clients for each DPAUX instance, namely the SOR and one of the I2C adapters. The SOR clients may used the DPAUX pins in either AUX or I2C modes and so for these devices we don't define any of the generic pinctrl states (default, idle, etc) because the SOR driver will directly set the state needed. For I2C clients only the I2C mode is used and so we can simplify matters by using the generic pinctrl states for default and idle. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-14arm64: tegra: Add ACONNECT bus node for Tegra210Jon Hunter1-0/+12
Add the ACONNECT bus node for Tegra210 which is used to interface to the various devices in the Audio Processing Engine (APE). Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-14arm64: tegra: Add audio powergate node for Tegra210Jon Hunter1-0/+9
Add the audio powergate for Tegra210. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-14arm64: tegra: Correct Tegra210 XUSB mailbox interruptJon Hunter1-1/+1
The XUSB mailbox interrupt for Tegra210 is 40 and not 49 which is for the XUSB pad controller. For some Tegra210 boards, this is causing USB connect and disconnect events to go undetected. Fix this by changing the interrupt number for the XUSB mailbox to 40. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-14arm64: tegra: Add Tegra210 XUSB controllerThierry Reding1-0/+35
Add a device tree node for the Tegra XUSB controller. It contains a phandle to the XUSB pad controller for control of the PHYs assigned to the USB ports. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-14arm64: tegra: Add Tegra210 XUSB pad controllerThierry Reding1-0/+155
Add a device tree node for the XUSB pad controller found on Tegra210. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-05-10Merge tag 'tegra-for-4.7-gm20b' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt64Arnd Bergmann1-2/+6
Merge "arm64: tegra: Enable GM20B GPU on Tegra210" from Thierry Reding: Complement the GM20B GPU device tree node on Tegra210 with missing properties to make it usable. * tag 'tegra-for-4.7-gm20b' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: arm64: tegra: Add IOMMU node to GM20B on Tegra210 arm64: tegra: Add reference clock to GM20B on Tegra210 dt-bindings: Add documentation for GM20B GPU dt-bindings: gk20a: Document iommus property dt-bindings: gk20a: Fix typo in compatible name
2016-04-26arm64: tegra: Add IOMMU node to GM20B on Tegra210Alexandre Courbot1-0/+3
The operating system driver can take advantage of the IOMMU to remove the need for physically contiguous memory buffers. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-26arm64: tegra: Add reference clock to GM20B on Tegra210Alexandre Courbot1-2/+3
This clock is required for the GPU to operate. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11arm64: tegra: Remove unused #power-domain-cells propertyJon Hunter1-2/+0
Remove the "#power-domain-cells" property which was incorrectly included by commit e53095857166 ("arm64: tegra: Add Tegra210 support"). Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11arm64: tegra: Fix copy/paste typo in several DTS includesThierry Reding1-1/+1
The comment about the 8250 vs. APB DMA-enabled UART devices that was added for Tegra20 and Tegra30 in commit b6551bb933f9 ("ARM: tegra: dts: add aliases and DMA requestor for serial controller") introduced a typo that has since spread to various other DTS include files. Fix all occurrences of this typo. Suggested-by: Ralf Ramsauer <ralf@ramses-pyramidenbau.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11arm64: tegra: Remove 0, prefix from unit-addressesThierry Reding1-59/+59
When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-03-04arm64: Fix misspellings in comments.Adam Buchbinder1-1/+1
Signed-off-by: Adam Buchbinder <adam.buchbinder@gmail.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2015-11-24arm64: tegra: Add Tegra210 supportThierry Reding1-0/+805
Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
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