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2022-07-08arm64: tegra: Adjust whitespace around '='Krzysztof Kozlowski1-1/+1
Fix whitespace coding style: use single space instead of tabs or multiple spaces around '=' sign in property assignment. No functional changes (same DTB). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-07-08arm64: tegra: Add OPE device on Tegra210 and laterSameer Pujar1-0/+40
Output Processing Engine (OPE) is a client of AHUB and is present on Tegra210 and later generations of Tegra SoC. Add this device on the relevant SoC DTSI files. Signed-off-by: Sameer Pujar <spujar@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-05-04arm64: tegra: Add missing DFLL reset on Tegra210Diogo Ivo1-2/+3
Commit 4782c0a5dd88 ("clk: tegra: Don't deassert reset on enabling clocks") removed deassertion of reset lines when enabling peripheral clocks. This breaks the initialization of the DFLL driver which relied on this behaviour. In order to be able to fix this, add the corresponding reset to the DT. Tested on Google Pixel C. Cc: stable@vger.kernel.org Fixes: 4782c0a5dd88 ("clk: tegra: Don't deassert reset on enabling clocks") Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-17arm64: tegra: Add host1x hotflush reset on Tegra210Thierry Reding1-2/+2
Add the host1x memory client hotflush reset on Tegra210. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Sort Tegra210 XUSB clocks correctlyThierry Reding1-2/+2
Make the order of the clocks and clock-names properties match the order in the device tree bindings. This isn't strictly necessary from a point of view of the operating system because matching will be done based on the clock-names, but it makes it easier to validate the device trees against the DT schema. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Add missing TSEC properties on Tegra210Thierry Reding1-0/+11
Add missing interrupts, clocks, clock-names, reset and reset-names properties for the TSEC blocks found on Tegra210. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Rename thermal zones nodesThierry Reding1-4/+4
The DT schema requires that nodes representing thermal zones include a "-thermal" suffix in their name. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-10-07arm64: tegra: Remove useless usb-ehci compatible stringThierry Reding1-2/+2
There's no such thing as a generic USB EHCI controller. The EHCI controllers found on Tegra SoCs are instantiations that need Tegra- specific glue to work properly, so drop the generic compatible string and keep only the Tegra-specific ones. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-10-07arm64: tegra: Add few AHUB devices for Tegra210 and laterSameer Pujar1-0/+77
Add DT nodes for following AHUB devices: * SFC (Sampling Frequency Converter) * MVC (Master Volume Control) * AMX (Audio Multiplexer) * ADX (Audio Demultiplexer) * Mixer Above devices are added for Tegra210, Tegra186 and Tegra194 generations of Tegra SoC. Signed-off-by: Sameer Pujar <spujar@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-01-27arm64: tegra: Enable QSPI on Jetson NanoSowjanya Komatineni1-2/+3
This patch enables QSPI on Jetson Nano. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-01-27arm64: tegra: Audio graph header for Tegra210Sameer Pujar1-0/+182
Expose a header which describes DT bindings required to use audio-graph based sound card. All Tegra210 based platforms can include this header and add platform specific information. Currently, from SoC point of view, all links are exposed for ADMAIF, AHUB, I2S and DMIC components. Signed-off-by: Sameer Pujar <spujar@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-01-27arm64: tegra: Order nodes alphabetically on Tegra210Thierry Reding1-40/+40
Device tree nodes are ordered by unit-address and alphabetically by name if a node doesn't have a unit-address. The thermal sensor and timer nodes were not sorted in the correct order, so do that now. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-01-27arm64: tegra: Add XUSB pad controller's "nvidia,pmc" property on Tegra210JC Kuo1-0/+1
PMC driver provides USB sleepwalk registers access to XUSB PADCTL driver. This commit adds a "nvidia,pmc" property which points to PMC node to XUSB PADCTL device node. Signed-off-by: JC Kuo <jckuo@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-01-27arm64: tegra: Add power-domain for Tegra210 HDASameer Pujar1-0/+1
HDA initialization is failing occasionally on Tegra210 and following print is observed in the boot log. Because of this probe() fails and no sound card is registered. [16.800802] tegra-hda 70030000.hda: no codecs found! Codecs request a state change and enumeration by the controller. In failure cases this does not seem to happen as STATETS register reads 0. The problem seems to be related to the HDA codec dependency on SOR power domain. If it is gated during HDA probe then the failure is observed. Building Tegra HDA driver into kernel image avoids this failure but does not completely address the dependency part. Fix this problem by adding 'power-domains' DT property for Tegra210 HDA. Note that Tegra186 and Tegra194 HDA do this already. Fixes: 742af7e7a0a1 ("arm64: tegra: Add Tegra210 support") Depends-on: 96d1f078ff0 ("arm64: tegra: Add SOR power-domain for Tegra210") Cc: <stable@vger.kernel.org> Signed-off-by: Sameer Pujar <spujar@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-11-26arm64: tegra: Change order of SATA resets for Tegra132 and Tegra210Sowjanya Komatineni1-3/+3
Tegra AHCI dt-binding doc is converted from text based to yaml based. dtbs_check valdiation strictly follows reset-names order specified in yaml dt-binding. Tegra124 thru Tegra210 has 3 resets sata, sata-oob and sata-cold. Tegra186 has 2 resets sata and sata-cold. This patch changes order of SATA resets to maintain proper resets order for commonly available resets across Tegra124 thru Tegra186 for dtbs_check to pass. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-11-26arm64: tegra: Add XUSB pad controller interruptJC Kuo1-0/+1
This commit adds "interrupts" property to Tegra210/Tegra186/Tegra194 XUSB PADCTL node. XUSB PADCTL interrupt will be raised when USB wake event happens. This is required for supporting XUSB host controller ELPG. Signed-off-by: JC Kuo <jckuo@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-11-25arm64: tegra: Rename ADMA device nodes for Tegra210Sameer Pujar1-1/+1
DMA device nodes should follow regex pattern of "^dma-controller(@.*)?$". This is a preparatory patch to use YAML doc format for ADMA. Signed-off-by: Sameer Pujar <spujar@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-11-25arm64: tegra: Add missing hot temperatures to Tegra210 thermal-zonesNicolas Chauvet1-0/+12
According to dmesg, thermal-zones for mem and cpu are missing hot temperatures properties. throttrip: pll: missing hot temperature ... throttrip: mem: missing hot temperature ... Adding them will clear the messages. Signed-off-by: Nicolas Chauvet <kwizart@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-11-25arm64: tegra: Add missing gpu-throt-level to Tegra210 socthermNicolas Chauvet1-0/+1
On Jetson TX1 the following message can be seen: tegra_soctherm 700e2000.thermal-sensor: throttle-cfg: heavy: no throt prop or invalid prop This patch will fix the invalid prop issue according to the binding. Signed-off-by: Nicolas Chauvet <kwizart@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-10-24Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds1-4/+146
Pull ARM Devicetree updates from Olof Johansson: "As usual, most of the changes are to devicetrees. Besides smaller fixes, some refactorings and cleanups, some of the new platforms and chips (or significant features) supported are below: Broadcom boards: - Cisco Meraki MR32 (BCM53016-based) - BCM2711 (RPi4) display pipeline support Actions Semi boards: - Caninos Loucos Labrador SBC (S500-based) - RoseapplePi SBC (S500-based) Allwinner SoCs/boards: - A100 SoC with Perf1 board - Mali, DMA, Cetrus and IR support for R40 SoC Amlogic boards: - Libretch S905x CC V2 board - Hardkernel ODROID-N2+ board Aspeed boards/platforms: - Wistron Mowgli (AST2500-based, Power9 OpenPower server) - Facebook Wedge400 (AST2500-based, ToR switch) Hisilicon SoC: - SD5203 SoC Nvidia boards: - Tegra234 VDK, for pre-silicon Orin SoC NXP i.MX boards: - Librem 5 phone - i.MX8MM DDR4 EVK - Variscite VAR-SOM-MX8MN SoM - Symphony board - Tolino Shine 2 HD - TQMa6 SoM - Y Soft IOTA Orion Rockchip boards: - NanoPi R2S board - A95X-Z2 board - more Rock-Pi4 variants STM32 boards: - Odyssey SOM board (STM32MP157CAC-based) - DH DRC02 board Toshiba SoCs/boards: - Visconti SoC and TPMV7708 board" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (638 commits) ARM: dts: nspire: Fix SP804 users arm64: dts: lg: Fix SP804 users arm64: dts: lg: Fix SP805 clocks ARM: mstar: Fix up the fallout from moving the dts/dtsi files ARM: mstar: Add mstar prefix to all of the dtsi/dts files ARM: mstar: Add interrupt to pm_uart ARM: mstar: Add interrupt controller to base dtsi ARM: dts: meson8: remove two invalid interrupt lines from the GPU node arm64: dts: ti: k3-j7200-common-proc-board: Add USB support arm64: dts: ti: k3-j7200-common-proc-board: Configure the SERDES lane function arm64: dts: ti: k3-j7200-main: Add USB controller arm64: dts: ti: k3-j7200-main.dtsi: Add USB to SERDES lane MUX arm64: dts: ti: k3-j7200-main: Add SERDES lane control mux dt-bindings: ti-serdes-mux: Add defines for J7200 SoC ARM: dts: hisilicon: add SD5203 dts ARM: dts: hisilicon: fix the system controller compatible nodes arm64: dts: zynqmp: Fix leds subnode name for zcu100/ultra96 v1 arm64: dts: zynqmp: Remove undocumented u-boot properties arm64: dts: zynqmp: Remove additional compatible string for i2c IPs arm64: dts: zynqmp: Rename buses to be align with simple-bus yaml ...
2020-09-02arm64: tegra: Add DT binding for AHUB componentsSameer Pujar1-0/+140
This patch adds few AHUB modules for Tegra210, Tegra186 and Tegra194. Bindings for following modules are added. * AHUB added as a child node under ACONNECT * AHUB includes many HW accelerators and below components are added as its children. * ADMAIF * I2S * DMIC * DSPK (added for Tegra186 and Tegra194 only, since Tegra210 does not have this module) Signed-off-by: Sameer Pujar <spujar@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-08-28arm64: tegra: Add missing timeout clock to Tegra210 SDMMCSowjanya Komatineni1-8/+12
commit 742af7e7a0a1 ("arm64: tegra: Add Tegra210 support") Tegra210 uses separate SDMMC_LEGACY_TM clock for data timeout and this clock is not enabled currently which is not recommended. Tegra SDMMC advertises 12Mhz as timeout clock frequency in host capability register. So, this clock should be kept enabled by SDMMC driver. Fixes: 742af7e7a0a1 ("arm64: tegra: Add Tegra210 support") Cc: stable <stable@vger.kernel.org> # 5.4 Tested-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Link: https://lore.kernel.org/r/1598548861-32373-5-git-send-email-skomatineni@nvidia.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-08-27arm64: tegra: Describe display controller outputs for Tegra210Thierry Reding1-4/+6
Both display controllers can drive both DSI and both SOR outputs on Tegra210. Describe this in device tree so that the operating system doesn't have to guess. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-16arm64: tegra: Add #{address,size}-cells for VI I2C on Tegra210Thierry Reding1-0/+3
The VI I2C controller provides an I2C bus and therefore needs to define the #address-cells and #size-cells properties. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-16arm64: tegra: Add missing clocks and power-domains to Tegra210 VI I2CSowjanya Komatineni1-0/+6
Tegra210 VI I2C is in VE power domain and i2c-vi node should have power-domains property. Current Tegra210 i2c-vi device node is missing both VI I2C clocks and power-domains property. This patch adds them. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Add clocks and resets for ISP on Tegra210Thierry Reding1-0/+6
The ISP blocks take a clock and a reset as inputs, so add those to the device tree nodes. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Fix compatible string for DPAUX on Tegra210Thierry Reding1-1/+1
The Tegra210 DPAUX controller is not compatible with that found on Tegra124, so it must have a separate compatible string. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Fix order of XUSB controller clocksThierry Reding1-2/+2
This is purely to make the json-schema validation tools happy because they cannot deal with string arrays that may be in arbitrary order. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Rename agic -> interrupt-controllerThierry Reding1-1/+1
Device tree nodes for interrupt controllers should be named "interrupt- controller", so rename the AGIC accordingly. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Do not mark host1x as simple busThierry Reding1-1/+1
The host1x is not a simple bus, so drop the corresponding compatible string. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Use proper tuple notationThierry Reding1-10/+10
Tuple boundaries should be marked by < and > to make it clear which cells are part of the same tuple. This also helps the json-schema based validation tooling to properly parse this data. While at it, also remove the "immovable" bit from PCI addresses. All of these addresses are in fact "movable". Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23arm64: tegra: Rename sdhci nodes to mmcThierry Reding1-4/+4
The new json-schema based validation tools require SD/MMC controller nodes to be named mmc. Rename all references to them. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23arm64: tegra: Remove parent clock from display controllersThierry Reding1-6/+4
The display controller's parent clock depends on the output that's consuming data from the display controller, so it needs to be specified as the parent of the corresponding output. The device tree bindings do specify this, so just correct the existing device trees that get this wrong. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23arm64: tegra: Add interrupt-names for host1xThierry Reding1-0/+1
Interrupt names are used to distinguish between the syncpoint and general host1x interrupts. Make sure they are available in the DT so that drivers can use them if necessary. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23arm64: tegra: Remove extra compatible for Tegra210 SDHCIThierry Reding1-4/+4
The SDHCI on Tegra210 is in fact not compatible with the one found on Tegra124. Remove the extra compatible string to reflect that. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-05-20arm64: tegra: Add Tegra VI CSI support in device treeSowjanya Komatineni1-1/+45
Tegra210 contains VI controller for video input capture from MIPI CSI camera sensors and also supports built-in test pattern generator. CSI ports can be one-to-one mapped to VI channels for capturing from an external sensor or from built-in test pattern generator. This patch adds support for VI and CSI and enables them in Tegra210 device tree. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-05-20arm64: tegra: Add reset-cells to memory controllerSowjanya Komatineni1-0/+1
Tegra210 device tree is missing reset-cells property for the memory controller node. This patch adds it. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-05-20arm64: tegra: Fix SOR powergate clocks and resetSowjanya Komatineni1-2/+3
Tegra210 device tree lists CSI clock and reset under SOR powergate node. But Tegra210 has CSICIL in SOR partition and CSI in VENC partition. So, this patch includes fix for SOR powergate node. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-05-20arm64: tegra: Hook up EMC cooling deviceThierry Reding1-5/+23
The external memory controller can be used as a cooling device for the LPDDR chips. Hook it up to the "mem" thermal zone of the SOCTHERM block so that temperature polling can be enabled on the EMC when a given temperature is exceeded. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-05-20arm64: tegra: Add external memory controller node for Tegra210Joseph Lo1-0/+11
Add external memory controller (EMC) node for Tegra210 Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-12arm64: tegra: Add clock-cells property to Tegra PMC nodeSowjanya Komatineni1-2/+4
Tegra132 and Tegra210 PMC blocks have clk_out_1, clk_out_2, clk_out_3, and a blink clock as a part of the PMC. These clocks were erroneously provided by the clock and reset controller and are now provided by the PMC instead because that's where the primary controls are. Clock IDs for these clocks are defined in the PMC dt-bindings. This patch updates the device tree to include the PMC dt-bindings header and adds the #clock-cells property with one clock specifier to the PMC node. Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-12arm64: tegra: Add XUDC node for Tegra210Nagarjuna Kristam1-0/+19
Tegra210 has one XUSB device mode controller, which can be operated in HS and SS modes. Add DT entry for XUSB device mode controller. Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29arm64: tegra: Enable wake from deep sleep on RTC alarmSowjanya Komatineni1-1/+4
This patch updates device tree for RTC and PMC to allow system wake from deep sleep on RTC alarm. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29arm64: tegra: Add PMU on Tegra210Thierry Reding1-0/+10
The NVIDIA Tegra210 contains an ARM PMU v3 that can be used to gather statistics about the processors and their memory system. Add a device tree node so that this functionality can be exposed. Reported-by: William Cohen <giantklein@gmail.com> Tested-by: William Cohen <giantklein@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29arm64: tegra: Add blank lines for better readabilityThierry Reding1-0/+3
Separate the individual thermal zones by a blank line for improved readability. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29arm64: tegra: Add SOR0_OUT clock on Tegra210Thierry Reding1-1/+2
This clock was not previously used because it is a fixed clock. However, adding it here allows operating systems to deal with SOR0 the same way as SOR1. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29arm64: tegra: Hook up edp interrupt on Tegra210 SOCTHERMThierry Reding1-1/+3
For some reason this was never hooked up. Do it now so that over-current interrupts can be logged. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-06-21arm64: tegra: Add PEX DPD states as pinctrl propertiesManikanta Maddireddy1-0/+19
Add PEX deep power down states as pinctrl properties to set in PCIe driver. In Tegra210, BIAS pads are not in power down mode when clamps are applied. To set the pads in DPD, pass the PEX DPD states as pinctrl properties to PCIe driver. Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-06-20arm64: tegra: Fix AGIC register rangeJon Hunter1-1/+1
The Tegra AGIC interrupt controller is an ARM GIC400 interrupt controller. Per the ARM GIC device-tree binding, the first address region is for the GIC distributor registers and the second address region is for the GIC CPU interface registers. The address space for the distributor registers is 4kB, but currently this is incorrectly defined as 8kB for the Tegra AGIC and overlaps with the CPU interface registers. Correct the address space for the distributor to be 4kB. Cc: stable@vger.kernel.org Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Fixes: bcdbde433542 ("arm64: tegra: Add AGIC node for Tegra210") Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-06-14arm64: tegra: Don't use architected timer for suspend on Tegra210Thierry Reding1-0/+1
Due to an integration issue the architected timer on Tegra210 does not remain on during system suspend (a.k.a. SC7). Mark it accordingly so that it isn't considered as a means to track suspend time. Signed-off-by: Thierry Reding <treding@nvidia.com>
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