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path: root/arch/arm64/include/asm/cache.h (follow)
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2020-10-28arm64: avoid -Woverride-init warningArnd Bergmann1-0/+1
2020-10-25treewide: Convert macro and uses of __section(foo) to __section("foo")Joe Perches1-1/+1
2020-02-22arm64: Ask the compiler to __always_inline functions used by KVM at HYPJames Morse1-1/+1
2019-10-25arm64: Fake the IminLine size on systems affected by Neoverse-N1 #1542419James Morse1-1/+2
2019-08-13arm64: prefer __section from compiler_attributes.hNick Desaulniers1-1/+1
2019-07-08Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linuxLinus Torvalds1-1/+4
2019-06-19treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 234Thomas Gleixner1-12/+1
2019-06-17arm64/mm: Correct the cache line size warning with non coherent deviceMasayoshi Mizuma1-0/+7
2019-06-04arm64: cacheinfo: Update cache_line_size detected from DT or PPTTShaokun Zhang1-5/+1
2019-01-16kasan, arm64: remove redundant ARCH_SLAB_MINALIGN defineAndrey Konovalov1-2/+0
2019-01-08kasan, arm64: use ARCH_SLAB_MINALIGN instead of manual aligningAndrey Konovalov1-0/+6
2018-10-16arm64: cpufeature: Fix handling of CTR_EL0.IDC fieldSuzuki K Poulose1-0/+40
2018-07-05arm64: Fix mismatched cache line size detectionSuzuki K Poulose1-0/+4
2018-05-15arm64: Increase ARCH_DMA_MINALIGN to 128Catalin Marinas1-2/+2
2018-05-11Revert "arm64: Increase the max granular size"Catalin Marinas1-1/+1
2018-03-27Revert "arm64: Revert L1_CACHE_SHIFT back to 6 (64-byte cache line size)"Will Deacon1-3/+3
2018-03-09arm64: Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDCShanker Donthineni1-0/+4
2018-03-06arm64: Revert L1_CACHE_SHIFT back to 6 (64-byte cache line size)Catalin Marinas1-3/+3
2017-03-20arm64: cache: Identify VPIPT I-cachesWill Deacon1-0/+7
2017-03-20arm64: cache: Merge cachetype.h into cache.hWill Deacon1-1/+30
2015-10-28arm64: Increase the max granular sizeTirumalesh Chalamarla1-1/+1
2014-12-03arm64: Implement support for read-mostly sectionsJungseok Lee1-0/+2
2014-05-09arm64: Implement cache_line_size() based on CTR_EL0.CWGCatalin Marinas1-1/+12
2012-09-17arm64: Cache maintenance routinesCatalin Marinas1-0/+32
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