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path: root/arch/arm64/kernel/cpufeature.c (follow)
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2022-05-16arm64/fp: Rename SVE and SME LEN field name to _WIDTHMark Brown1-2/+2
2022-05-16Merge branch 'for-next/sme' into for-next/sysreg-genCatalin Marinas1-0/+107
2022-05-04arm64/sysreg: Standardise ID_AA64ISAR0_EL1 macro namesMark Brown1-35/+35
2022-05-04arm64: Update name of ID_AA64ISAR0_EL1_ATOMIC to reflect ARMMark Brown1-3/+3
2022-04-27arm64/sme: Add ID_AA64SMFR0_EL1 to __read_sysreg_by_encoding()Mark Brown1-0/+1
2022-04-22arm64/sme: Identify supported SME vector lengths at bootMark Brown1-0/+47
2022-04-22arm64/sme: Basic enumeration supportMark Brown1-0/+59
2022-03-14Merge branch 'for-next/spectre-bhb' into for-next/coreWill Deacon1-0/+12
2022-03-14Merge branch 'for-next/fpsimd' into for-next/coreWill Deacon1-69/+107
2022-03-14Merge branch 'for-next/pauth' into for-next/coreWill Deacon1-9/+50
2022-03-14Merge branch 'for-next/mte' into for-next/coreWill Deacon1-0/+1
2022-03-07arm64: cpufeature: Add missing .field_width for GIC system registersMark Brown1-0/+1
2022-02-25arm64/mte: Add hwcap for asymmetric modeMark Brown1-0/+1
2022-02-25arm64: cpufeature: Always specify and use a field width for capabilitiesMark Brown1-66/+101
2022-02-25arm64: cpufeature: Remove cpu_has_fwb() checkVladimir Murzin1-9/+0
2022-02-25arm64: Add support of PAuth QARMA3 architected algorithmVladimir Murzin1-2/+39
2022-02-25arm64: cpufeature: Mark existing PAuth architected algorithm as QARMA5Vladimir Murzin1-8/+12
2022-02-25arm64: cpufeature: Account min_field_value when cheking secondaries for PAuthVladimir Murzin1-1/+1
2022-02-24arm64: Use the clearbhb instruction in mitigationsJames Morse1-0/+1
2022-02-16arm64: Add percpu vectors for EL1James Morse1-0/+11
2022-01-28arm64: cpufeature: List early Cortex-A510 parts as having broken dbmJames Morse1-0/+3
2021-12-13arm64: cpufeature: add HWCAP for FEAT_RPRESJoey Gouly1-0/+2
2021-12-13arm64: add ID_AA64ISAR2_EL1 sys registerJoey Gouly1-0/+9
2021-12-13arm64: cpufeature: add HWCAP for FEAT_AFPJoey Gouly1-0/+2
2021-11-11Merge tag 'char-misc-5.16-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-miscLinus Torvalds1-0/+1
2021-11-08arm64: arm64_ftr_reg->name may not be a human-readable stringReiji Watanabe1-3/+7
2021-11-07Merge tag 'coresight-fixes-v5.16' of gitolite.kernel.org:pub/scm/linux/kernel/git/coresight/linux into char-misc-linusGreg Kroah-Hartman1-0/+1
2021-11-04arm64: cpufeature: Export this_cpu_has_cap helperArnd Bergmann1-0/+1
2021-10-29Merge branch 'for-next/sve' into for-next/coreWill Deacon1-3/+3
2021-10-29Merge branch 'for-next/mte' into for-next/coreWill Deacon1-0/+10
2021-10-21arm64/sve: Put system wide vector length information into structsMark Brown1-3/+3
2021-10-19arm64: Add HWCAP for self-synchronising virtual counterMarc Zyngier1-1/+2
2021-10-19arm64: Add a capability for FEAT_ECVMarc Zyngier1-0/+10
2021-10-07arm64: mte: CPU feature detection for Asymm MTEVincenzo Frascino1-0/+10
2021-09-23arm64: Restore forced disabling of KPTI on ThunderXdann frazier1-2/+6
2021-09-07Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds1-4/+4
2021-08-31Merge remote-tracking branch 'tip/sched/arm64' into for-next/coreCatalin Marinas1-1/+50
2021-08-26Merge branches 'for-next/mte', 'for-next/misc' and 'for-next/kselftest', remote-tracking branch 'arm64/for-next/perf' into for-next/coreCatalin Marinas1-3/+4
2021-08-20arm64: Hook up cmdline parameter to allow mismatched 32-bit EL0Will Deacon1-0/+7
2021-08-20arm64: Advertise CPUs capable of running 32-bit applications in sysfsWill Deacon1-0/+19
2021-08-20arm64: Prevent offlining first CPU with 32-bit EL0 on mismatched systemWill Deacon1-1/+24
2021-08-20KVM: arm64: Add feature register flag definitionsFuad Tabba1-4/+4
2021-08-03arm64/cpufeature: Optionally disable MTE via command-lineYee Lee1-0/+3
2021-08-02arm64: unnecessary end 'return;' in void functionsJason Wang1-2/+0
2021-07-30arm64: cpufeature: Use defined macro instead of magic numbersShaokun Zhang1-1/+1
2021-07-12arm64: Add missing header <asm/smp.h> in two filesCarlos Bilbao1-0/+1
2021-06-24Merge branch 'for-next/insn' into for-next/coreWill Deacon1-0/+1
2021-06-22arm64: Restrict undef hook for cpufeature registersRaphael Gault1-2/+2
2021-06-11arm64: Allow mismatched 32-bit EL0 supportWill Deacon1-13/+101
2021-06-11arm64: cpuinfo: Split AArch32 registers out into a separate structWill Deacon1-35/+39
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