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Now that we no longer refer to mod->arch.ftrace_trampolines in the body
of ftrace_make_call(), we can use IS_ENABLED() rather than ifdeffery,
and make the code easier to follow. Likewise in ftrace_make_nop().
Let's do so.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Torsten Duwe <duwe@suse.de>
Tested-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
Tested-by: Torsten Duwe <duwe@suse.de>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
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This patch implements FTRACE_WITH_REGS for arm64, which allows a traced
function's arguments (and some other registers) to be captured into a
struct pt_regs, allowing these to be inspected and/or modified. This is
a building block for live-patching, where a function's arguments may be
forwarded to another function. This is also necessary to enable ftrace
and in-kernel pointer authentication at the same time, as it allows the
LR value to be captured and adjusted prior to signing.
Using GCC's -fpatchable-function-entry=N option, we can have the
compiler insert a configurable number of NOPs between the function entry
point and the usual prologue. This also ensures functions are AAPCS
compliant (e.g. disabling inter-procedural register allocation).
For example, with -fpatchable-function-entry=2, GCC 8.1.0 compiles the
following:
| unsigned long bar(void);
|
| unsigned long foo(void)
| {
| return bar() + 1;
| }
... to:
| <foo>:
| nop
| nop
| stp x29, x30, [sp, #-16]!
| mov x29, sp
| bl 0 <bar>
| add x0, x0, #0x1
| ldp x29, x30, [sp], #16
| ret
This patch builds the kernel with -fpatchable-function-entry=2,
prefixing each function with two NOPs. To trace a function, we replace
these NOPs with a sequence that saves the LR into a GPR, then calls an
ftrace entry assembly function which saves this and other relevant
registers:
| mov x9, x30
| bl <ftrace-entry>
Since patchable functions are AAPCS compliant (and the kernel does not
use x18 as a platform register), x9-x18 can be safely clobbered in the
patched sequence and the ftrace entry code.
There are now two ftrace entry functions, ftrace_regs_entry (which saves
all GPRs), and ftrace_entry (which saves the bare minimum). A PLT is
allocated for each within modules.
Signed-off-by: Torsten Duwe <duwe@suse.de>
[Mark: rework asm, comments, PLTs, initialization, commit message]
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Torsten Duwe <duwe@suse.de>
Tested-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
Tested-by: Torsten Duwe <duwe@suse.de>
Cc: AKASHI Takahiro <takahiro.akashi@linaro.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Josh Poimboeuf <jpoimboe@redhat.com>
Cc: Julien Thierry <jthierry@redhat.com>
Cc: Will Deacon <will@kernel.org>
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So that assembly code can more easily manipulate the FP (x29) within a
pt_regs, add an S_FP asm-offsets definition.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Torsten Duwe <duwe@suse.de>
Tested-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
Tested-by: Torsten Duwe <duwe@suse.de>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
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For FTRACE_WITH_REGS, we're going to want to generate a MOV (register)
instruction as part of the callsite intialization. As MOV (register) is
an alias for ORR (shifted register), we can generate this with
aarch64_insn_gen_logical_shifted_reg(), but it's somewhat verbose and
difficult to read in-context.
Add a aarch64_insn_gen_move_reg() wrapper for this case so that we can
write callers in a more straightforward way.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Torsten Duwe <duwe@suse.de>
Tested-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
Tested-by: Torsten Duwe <duwe@suse.de>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
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Currently we lazily-initialize a module's ftrace PLT at runtime when we
install the first ftrace call. To do so we have to apply a number of
sanity checks, transiently mark the module text as RW, and perform an
IPI as part of handling Neoverse-N1 erratum #1542419.
We only expect the ftrace trampoline to point at ftrace_caller() (AKA
FTRACE_ADDR), so let's simplify all of this by intializing the PLT at
module load time, before the module loader marks the module RO and
performs the intial I-cache maintenance for the module.
Thus we can rely on the module having been correctly intialized, and can
simplify the runtime work necessary to install an ftrace call in a
module. This will also allow for the removal of module_disable_ro().
Tested by forcing ftrace_make_call() to use the module PLT, and then
loading up a module after setting up ftrace with:
| echo ":mod:<module-name>" > set_ftrace_filter;
| echo function > current_tracer;
| modprobe <module-name>
Since FTRACE_ADDR is only defined when CONFIG_DYNAMIC_FTRACE is
selected, we wrap its use along with most of module_init_ftrace_plt()
with ifdeffery rather than using IS_ENABLED().
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Torsten Duwe <duwe@suse.de>
Tested-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
Tested-by: Torsten Duwe <duwe@suse.de>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: James Morse <james.morse@arm.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Will Deacon <will@kernel.org>
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When we load a module, we have to perform some special work for a couple
of named sections. To do this, we iterate over all of the module's
sections, and perform work for each section we recognize.
To make it easier to handle the unexpected absence of a section, and to
make the section-specific logic easer to read, let's factor the section
search into a helper. Similar is already done in the core module loader,
and other architectures (and ideally we'd unify these in future).
If we expect a module to have an ftrace trampoline section, but it
doesn't have one, we'll now reject loading the module. When
ARM64_MODULE_PLTS is selected, any correctly built module should have
one (and this is assumed by arm64's ftrace PLT code) and the absence of
such a section implies something has gone wrong at build time.
Subsequent patches will make use of the new helper.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Torsten Duwe <duwe@suse.de>
Tested-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
Tested-by: Torsten Duwe <duwe@suse.de>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: James Morse <james.morse@arm.com>
Cc: Will Deacon <will@kernel.org>
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As it was found recently, the Performance Monitoring Unit (PMU) on the
Allwinner A64 SoC was not generating (the right) interrupts. With the
SPI numbers from the manual the kernel did not receive any overflow
interrupts, so perf was not happy at all.
It turns out that the numbers were just off by 4, so the PMU interrupts
are from 148 to 151, not from 152 to 155 as the manual describes.
This was found by playing around with U-Boot, which typically does not
use interrupts, so the GIC is fully available for experimentation:
With *every* PPI and SPI enabled, an overflowing PMU cycle counter was
found to set a bit in one of the GICD_ISPENDR registers, with careful
counting this was determined to be number 148.
Tested with perf record and perf top on a Pine64-LTS. Also tested with
tasksetting to every core to confirm the assignment between IRQs and
cores.
This somewhat "revert-fixes" commit ed3e9406bcbc ("arm64: dts: allwinner:
a64: Drop PMU node").
Fixes: 34a97fcc71c2 ("arm64: dts: allwinner: a64: Add PMU node")
Fixes: ed3e9406bcbc ("arm64: dts: allwinner: a64: Drop PMU node")
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
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NVIDIA Carmel CPUs don't implement ID_AA64PFR0_EL1.CSV3 but
aren't susceptible to Meltdown, so add Carmel to kpti_safe_list[].
Signed-off-by: Rich Wiley <rwiley@nvidia.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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commit 9b31cf493ffa ("arm64: mm: Introduce MAX_USER_VA_BITS definition")
introduced the MAX_USER_VA_BITS definition, which was used to support
the arm64 mm use-cases where the user-space could use 52-bit virtual
addresses whereas the kernel-space would still could a maximum of 48-bit
virtual addressing.
But, now with commit b6d00d47e81a ("arm64: mm: Introduce 52-bit Kernel
VAs"), we removed the 52-bit user/48-bit kernel kconfig option and hence
there is no longer any scenario where user VA != kernel VA size
(even with CONFIG_ARM64_FORCE_52BIT enabled, the same is true).
Hence we can do away with the MAX_USER_VA_BITS macro as it is equal to
VA_BITS (maximum VA space size) in all possible use-cases. Note that
even though the 'vabits_actual' value would be 48 for arm64 hardware
which don't support LVA-8.2 extension (even when CONFIG_ARM64_VA_BITS_52
is enabled), VA_BITS would still be set to a value 52. Hence this change
would be safe in all possible VA address space combinations.
Cc: James Morse <james.morse@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Steve Capper <steve.capper@arm.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: linux-kernel@vger.kernel.org
Cc: kexec@lists.infradead.org
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Bhupesh Sharma <bhsharma@redhat.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Calculate the page-aligned end address more simply.
The local variable, "length" is unneeded.
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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ROC-RK3308-CC is a rk3308 based board designed by Firelfy,
with eMMC and 256MB DDR3 and RTL8188 Wifi on board.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Link: https://lore.kernel.org/r/20191030072811.29882-1-andy.yan@rock-chips.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Correct the voltage supplies according to the board schematics
ROC-3399-PC-V10-A-20180804.
Signed-off-by: Markus Reichl <m.reichl@fivetechno.de>
Link: https://lore.kernel.org/r/22b56700-3c9e-0f60-cd74-7ff24d4f1a23@fivetechno.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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rk3399-roc-pc has vcc_sys 5V supply for USB and other peripherals.
Add the GPIO pin to enable the regulator.
Signed-off-by: Markus Reichl <m.reichl@fivetechno.de>
Link: https://lore.kernel.org/r/c72db0ad-c261-af4f-efe6-22bbcf4a0b7b@fivetechno.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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rk3399-roc-pc has a power and a recovery button, enable them.
Signed-off-by: Markus Reichl <m.reichl@fivetechno.de>
Link: https://lore.kernel.org/r/1ce152cc-bd6b-63af-7892-221e084d087f@fivetechno.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Enable the phy node ion the px30 evb board.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20190917082659.25549-13-heiko@sntech.de
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Add the usb2phy node on the px30 and hook it up to the usb controllers
it supplies.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20190917082659.25549-12-heiko@sntech.de
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Having a default optee node in a soc devicetree is not really good.
For one there is no guarantee that any tee got loaded and there's even
the possibility that a completely different TEE got loaded.
OP-Tee however will insert relevant nodes to the devicetree (firmware
+reserved memory sections) during its own startup, so there really is
no need to provide a default node.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20191023224409.3550-1-heiko@sntech.de
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Set the supplying regulator and enable the gpu node on the rk3399-puma som.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20191023223954.3139-1-heiko@sntech.de
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The px30 soc contains a controller for one-time-programmable memory,
so add the necessary node for it and the fields defined in it by default.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20191023224113.3268-1-heiko@sntech.de
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The TCON TOP node in the H6 DTSI has a reset name that isn't described in
the binding. Remove it.
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
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Enable Allwinner's USB 3.0 phy and the host controller. Orange Pi 3
board has GL3510 USB 3.0 4-port hub connected to the SoC's USB 3.0
port. All four ports are exposed via USB3-A connectors. VBUS is
always on, since it's powered directly from DCIN (VCC-5V) and
not switchable.
Signed-off-by: Ondrej Jirman <megous@megous.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
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Allwinner H6 SoC features USB3 functionality, with a DWC3 controller and
a custom PHY.
Add device tree nodes for them.
Signed-off-by: Ondrej Jirman <megous@megous.com>
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
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Teres-I has an anx6345 bridge connected to the RGB666 LCD output, and
the I2C controlling signals are connected to I2C0 bus.
Enable it in the device tree, and enable the display engine, video mixer
and tcon0 as well.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Torsten Duwe <duwe@suse.de>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
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The update of the VDSO data is depending on __arch_use_vsyscall() returning
True. This is a leftover from the attempt to map the features of various
architectures 1:1 into generic code.
The usage of __arch_use_vsyscall() in the actual vsyscall implementations
got dropped and replaced by the requirement for the architecture code to
return U64_MAX if the global clocksource is not usable in the VDSO.
But the __arch_use_vsyscall() check in the update code stayed which causes
the VDSO data to be stale or invalid when an architecture actually
implements that function and returns False when the current clocksource is
not usable in the VDSO.
As a consequence the VDSO implementations of clock_getres(), time(),
clock_gettime(CLOCK_.*_COARSE) operate on invalid data and return bogus
information.
Remove the __arch_use_vsyscall() check from the VDSO update function and
update the VDSO data unconditionally.
[ tglx: Massaged changelog and removed the now useless implementations in
asm-generic/ARM64/MIPS ]
Fixes: 44f57d788e7deecb50 ("timekeeping: Provide a generic update_vsyscall() implementation")
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Vincenzo Frascino <vincenzo.frascino@arm.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: stable@vger.kernel.org
Link: https://lkml.kernel.org/r/1571887709-11447-1-git-send-email-chenhc@lemote.com
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i.MX fixes for 5.4, 3rd round:
- Fix the GPIO number that is controlling core voltage on
imx8mq-zii-ultra board.
* tag 'imx-fixes-5.4-3' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
arm64: dts: zii-ultra: fix ARM regulator GPIO handle
Link: https://lore.kernel.org/r/20191104084513.GW24620@dragon
Signed-off-by: Olof Johansson <olof@lixom.net>
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Since the EXCEPTION_TABLE is read-only, collapse it into RO_DATA. Also
removes the redundant ALIGN, which is already present at the end of the
RO_DATA macro.
Signed-off-by: Kees Cook <keescook@chromium.org>
Signed-off-by: Borislav Petkov <bp@suse.de>
Acked-by: Will Deacon <will@kernel.org>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
Cc: linux-alpha@vger.kernel.org
Cc: linux-arch@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-c6x-dev@linux-c6x.org
Cc: linux-ia64@vger.kernel.org
Cc: linuxppc-dev@lists.ozlabs.org
Cc: linux-s390@vger.kernel.org
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Peter Collingbourne <pcc@google.com>
Cc: Rick Edgecombe <rick.p.edgecombe@intel.com>
Cc: Segher Boessenkool <segher@kernel.crashing.org>
Cc: x86-ml <x86@kernel.org>
Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
Link: https://lkml.kernel.org/r/20191029211351.13243-19-keescook@chromium.org
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Rename RW_DATA_SECTION to RW_DATA. (Calling this a "section" is a lie,
since it's multiple sections and section flags cannot be applied to
the macro.)
Signed-off-by: Kees Cook <keescook@chromium.org>
Signed-off-by: Borislav Petkov <bp@suse.de>
Acked-by: Heiko Carstens <heiko.carstens@de.ibm.com> # s390
Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> # m68k
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: linux-alpha@vger.kernel.org
Cc: linux-arch@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-c6x-dev@linux-c6x.org
Cc: linux-ia64@vger.kernel.org
Cc: linux-s390@vger.kernel.org
Cc: linuxppc-dev@lists.ozlabs.org
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Rick Edgecombe <rick.p.edgecombe@intel.com>
Cc: Segher Boessenkool <segher@kernel.crashing.org>
Cc: Will Deacon <will@kernel.org>
Cc: x86-ml <x86@kernel.org>
Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
Link: https://lkml.kernel.org/r/20191029211351.13243-14-keescook@chromium.org
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The .notes section should be non-executable read-only data. As such,
move it to the RO_DATA macro instead of being per-architecture defined.
Signed-off-by: Kees Cook <keescook@chromium.org>
Signed-off-by: Borislav Petkov <bp@suse.de>
Acked-by: Heiko Carstens <heiko.carstens@de.ibm.com> # s390
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: linux-alpha@vger.kernel.org
Cc: linux-arch@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-c6x-dev@linux-c6x.org
Cc: linux-ia64@vger.kernel.org
Cc: linux-s390@vger.kernel.org
Cc: linuxppc-dev@lists.ozlabs.org
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Rick Edgecombe <rick.p.edgecombe@intel.com>
Cc: Segher Boessenkool <segher@kernel.crashing.org>
Cc: Will Deacon <will@kernel.org>
Cc: x86-ml <x86@kernel.org>
Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
Link: https://lkml.kernel.org/r/20191029211351.13243-11-keescook@chromium.org
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None of these at803x properties are documented anywhere, so just
remove them.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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With phy-reset-gpios are enabled for i.MX8MM-EVK board, phy
will be reset. Without CONFIG_AT803X_PHY as y, board will stop
booting in NFS DHCP, because phy is not ready. So mark
CONFIG_AT803X_PHY from m to y to make board boot when using nfs rootfs.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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The GPIO handle is referencing the wrong GPIO, so the voltage did not
actually change as intended. The pinmux is already correct, so just
correct the GPIO number.
Fixes: 4a13b3bec3b4 (arm64: dts: imx: add Zii Ultra board support)
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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vreg_lvs1a_1p8 and vreg_lvs2a_1p8 are both feeding pins in the low speed
connectors and should as such alway be on, so enable them.
Acked-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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mvebu dt64 for 5.5 (part 1)
- Add new Marvell CN9130 SoC support (CN9130 is made of one AP807 and
one internal CP115, similar to the Armada 7K/8K using AP806 and
CP110).
- Reorganize EspressoBin device tree to add new variant of the boards
(Armada 3270 based)
- Add firmware node for turris Mox (Armada 3720 based)
* tag 'mvebu-dt64-5.5-1' of git://git.infradead.org/linux-mvebu: (23 commits)
arm64: dts: armada-3720-turris-mox: add firmware node
arm64: dts: marvell: add ESPRESSObin variants
arm64: dts: marvell: Add support for Marvell CN9132-DB
arm64: dts: marvell: Add support for Marvell CN9131-DB
arm64: dts: marvell: Add support for Marvell CN9130-DB
arm64: dts: marvell: Add support for Marvell CN9130 SoC support
arm64: dts: marvell: Add support for CP115
arm64: dts: marvell: Externalize PCIe macros from CP11x file
arm64: dts: marvell: Drop PCIe I/O ranges from CP11x file
arm64: dts: marvell: Prepare the introduction of CP115
arm64: dts: marvell: Fix CP110 NAND controller node multi-line comment alignment
arm64: dts: marvell: Add AP807-quad cache description
arm64: dts: marvell: Add AP806-quad cache description
arm64: dts: marvell: Add AP806-dual cache description
arm64: dts: marvell: Add support for AP807/AP807-quad
dt-bindings: marvell: Declare the CN913x SoC compatibles
dt-bindings: marvell: Convert the SoC compatibles description to YAML
arm64: dts: marvell: Move clocks to AP806 specific file
arm64: dts: marvell: Prepare the introduction of AP807 based SoCs
MAINTAINERS: Add new Marvell CN9130-based files to track
...
Link: https://lore.kernel.org/r/87zhhc3bo6.fsf@FE-laptop
Signed-off-by: Olof Johansson <olof@lixom.net>
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arm64: tegra: Device tree changes for v5.5-rc1
Adds support for DP and XUSB on various boards, enables SMMU support for
more devices and fixes a couple of DTC warnings and inconsistencies that
are reported at runtime.
These changes along with some of the driver changes in other branches
allow suspend/resume support on Tegra210 devices (e.g. Jetson TX1 and
Jetson Nano).
* tag 'tegra-for-5.5-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (25 commits)
arm64: tegra: Add Jetson Nano SC7 timings
arm64: tegra: Add Jetson TX1 SC7 timings
arm64: tegra: Enable wake from deep sleep on RTC alarm
arm64: tegra: Add PMU on Tegra210
arm64: tegra: Add blank lines for better readability
arm64: tegra: Enable DisplayPort on Jetson AGX Xavier
arm64: tegra: p2888: Rename regulators for consistency
arm64: tegra: Enable DP support on Jetson TX2
arm64: tegra: Fix compatible for SOR1
arm64: tegra: Enable DP support on Jetson Nano
arm64: tegra: Add SOR0_OUT clock on Tegra210
arm64: tegra: Assume no CLKREQ presence by default
arm64: tegra: Enable SMMU for VIC on Tegra186
arm64: tegra: Enable XUSB host controller on Jetson TX2
arm64: tegra: Enable SMMU for XUSB host on Tegra186
arm64: tegra: Enable XUSB pad controller on Jetson TX2
arm64: tegra: Add ethernet alias on Jetson AGX Xavier
arm64: tegra: Fix compatible string for EQOS on Tegra194
arm64: tegra: Hook up edp interrupt on Tegra210 SOCTHERM
arm64: tegra: Fix base address for SOR1 on Tegra194
...
Link: https://lore.kernel.org/r/20191102144521.3863321-8-thierry.reding@gmail.com
Signed-off-by: Olof Johansson <olof@lixom.net>
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This patch adds the device tree to support Toradex Colibri iMX8X a
computer on module which can be used on different carrier boards.
The module consists of an NXP i.MX 8X family SoC (either i.MX 8DualX or
8QuadXPlus), a PF8100 PMIC, a FastEthernet PHY, 1 or 2 GB of LPDDR4
RAM, some level shifters, a Micron eMMC, a USB hub, an AD7879 resistive
touch controller, an SGTL5000 audio codec and on-module CSI as well as
DSI-LVDS FFC receptacles plus an optional Bluetooth/Wi-Fi module.
Anything that is not self-contained on the module is disabled by
default.
The device tree for the Colibri Evaluation Board includes the module's
device tree and enables the supported peripherals of the carrier board
(the Colibri Evaluation Board supports almost all of them).
So far there is no display or USB functionality supported at all but
basic console UART, eMMC and Ethernet functionality work fine.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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One new patch to the arm64 defconfig to enable the new crypto engine
driver.
* tag 'sunxi-config64-for-5.5-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
arm64: defconfig: add new Allwinner crypto options
Link: https://lore.kernel.org/r/539241d6-9b2e-4d5b-bd63-f912cf6ebf96.lettre@localhost
Signed-off-by: Olof Johansson <olof@lixom.net>
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Our usual bunch of DT patches, with this time mostly:
- Mali GPU support for the H6
- Two new crypto drivers enablement
- A few fixes to our DTs, fixed through the validation effort
- New boards: NanoPi Duo2
* tag 'sunxi-dt-for-5.5-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (22 commits)
dt-bindings: arm: sunxi: add FriendlyARM NanoPi Duo2
ARM: dts: sun8i: add FriendlyARM NanoPi Duo2
arm64: allwinner: h6: Enable GPU node for Tanix TX6
arm64: dts: allwinner: bluetooth for Emlid Neutis N5
ARM: dts: sunxi: h3/h5: add missing uart2 rts/cts pins
ARM: dts: sun9i: a80: Add Security System node
ARM: dts: sun8i: a83t: Add Security System node
arm64: dts: allwinner: sun50i: Add Crypto Engine node on H6
arm64: dts: allwinner: sun50i: Add crypto engine node on H5
arm64: dts: allwinner: sun50i: Add Crypto Engine node on A64
ARM: dts: sun8i: H3: Add Crypto Engine node
ARM: dts: sun8i: R40: add crypto engine node
dt-bindings: crypto: Add DT bindings documentation for sun8i-ce Crypto Engine
arm64: dts: allwinner: Add mali GPU supply for H6 boards
arm64: dts: allwinner: Add ARM Mali GPU node for H6
ARM: dts: sun8i: a83t: a711: Add touchscreen node
ARM: dts: sun5i: olinuxino micro: Fix AT24 node name
ARM: dts: sun9i: Add missing watchdog clocks
arm64: dts: sun50i: sopine-baseboard: Expose serial1, serial2 and serial3
arm64: dts: allwinner: orange-pi-3: Enable UART1 / Bluetooth
...
Link: https://lore.kernel.org/r/1bf18c83-f41d-4353-9ca2-9585b8693df2.lettre@localhost
Signed-off-by: Olof Johansson <olof@lixom.net>
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The standard DT property is called "#interrupt-cells".
Link: https://lore.kernel.org/r/20191101160356.32034-2-geert+renesas@glider.be
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Chanho Min <chanho.min@lge.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
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The standard DT property is called "#interrupt-cells".
Link: https://lore.kernel.org/r/20191101160356.32034-1-geert+renesas@glider.be
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Chanho Min <chanho.min@lge.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
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Renesas ARM64 DT updates for v5.5 (take two)
- Video-Input and Serial-ATA support on RZ/G2N,
- Color Management Module support on various R-Car Gen3 SoCs,
- Initial support for the R-Car M3-W+ (r8a77961) SoC on the
Salvator-XS board.
* tag 'renesas-arm64-dt-for-v5.5-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
arm64: dts: renesas: Add support for Salvator-XS with R-Car M3-W+
arm64: dts: renesas: Add Renesas R8A77961 SoC support
arm64: dts: renesas: Prepare for rename of ARCH_R8A7796 to ARCH_R8A77960
dt-bindings: clock: Add r8a77961 CPG Core Clock Definitions
dt-bindings: power: Add r8a77961 SYSC power domain definitions
arm64: dts: renesas: r8a774b1: Add SATA controller node
arm64: dts: renesas: rcar-gen3: Add CMM units
arm64: dts: renesas: r8a774b1: Add VIN and CSI-2 support
Link: https://lore.kernel.org/r/20191101155842.31467-5-geert+renesas@glider.be
Signed-off-by: Olof Johansson <olof@lixom.net>
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Renesas ARM64 defconfig updates for v5.5 (take two)
- Enable support for the new R-Car M3-W+ (r8a77961) SoC.
* tag 'renesas-arm64-defconfig-for-v5.5-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
arm64: defconfig: Enable R8A77961 SoC
Link: https://lore.kernel.org/r/20191101155842.31467-4-geert+renesas@glider.be
Signed-off-by: Olof Johansson <olof@lixom.net>
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ARM64: hisilicon: defconfig updates for 5.5
- enable ARM SMMUv3 PMU and hisi ZIP controller as module for
Kunpeng920 SoC
* tag 'hisi-arm64-defconfig-for-5.5' of git://github.com/hisilicon/linux-hisi:
arm64: defconfig: Enable SMMU v3 PMCG
arm64: defconfig: Enable HiSilicon ZIP controller
Link: https://lore.kernel.org/r/5DB95B1E.8060607@hisilicon.com
Signed-off-by: Olof Johansson <olof@lixom.net>
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ARM64: DT: Hisilicon SoCs DT updates for 5.5
- add Mali450 MP4 GPU node in the hi6220 SoC
* tag 'hisi-arm64-dt-for-5.5' of git://github.com/hisilicon/linux-hisi:
arm64: dts: hisilicon: Add Mali-450 MP4 GPU DT entry
Link: https://lore.kernel.org/r/5DB95AAB.8060405@hisilicon.com
Signed-off-by: Olof Johansson <olof@lixom.net>
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Realtek ARM64 based SoC DT for v5.5
Add RTD1293 and RTD1296 DTs. Add the watchdog for all of RTD129x DTs.
Add reset controllers for RTD129x and start using them for UARTs.
* tag 'realtek-arm64-dt-for-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-realtek:
arm64: dts: realtek: Add RTD129x UART resets
arm64: dts: realtek: Add RTD129x reset controller nodes
dt-bindings: reset: Add Realtek RTD1295
arm64: dts: realtek: Add watchdog node for RTD129x
arm64: dts: realtek: Add oscillator for RTD129x
arm64: dts: realtek: Add RTD1296 and Synology DS418
dt-bindings: arm: realtek: Document RTD1296 and Synology DS418
arm64: dts: realtek: Add RTD1293 and Synology DS418j
arm64: dts: realtek: Change dual-license from MIT to BSD
dt-bindings: arm: realtek: Document RTD1293 and Synology DS418j
dt-bindings: arm: realtek: Tidy up conversion to json-schema
Link: https://lore.kernel.org/r/20191030041000.31848-2-afaerber@suse.de
Signed-off-by: Olof Johansson <olof@lixom.net>
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Realtek ARM64 based SoC for v5.5
Enable reset controllers and add a mailing list to MAINTAINERS.
* tag 'realtek-arm64-soc-for-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-realtek:
arm64: realtek: Select reset controller
MAINTAINERS: Add mailing list for Realtek SoCs
Link: https://lore.kernel.org/r/20191030041000.31848-1-afaerber@suse.de
Signed-off-by: Olof Johansson <olof@lixom.net>
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The following build warning is seen with W=1:
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi:531.20-581.5: Warning (simple_bus_reg): /soc/tmu@1f00000: simple-bus unit address format error, expected "1f80000"
Fix it by adjusting the tmu unit address to match its reg entry.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Move thermal-zone node from the soc node to the root node.
thermal-zone node does not have any register properties and thus
shouldn't be placed on the bus.
This fixes the following build warnings with W=1:
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi:583.17-612.5: Warning (simple_bus_reg): /soc/thermal-zones: missing or empty reg/ranges property
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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The following build warning is seen with W=1:
arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts:196.10-208.4: Warning (avoid_unnecessary_addr_size): /soc/i2c@2000000/fpga@66: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property
Fix it by removing the unnecessary #address-cells/#size-cells.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Machine compatible string normally is located in board DT, remove
the duplicated one from SoC dtsi.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Machine compatible string normally is located in board DT, remove
the duplicated one from SoC dtsi.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Mark Rutland
Torsten Duwe
Andre Przywara
Rich Wiley
Bhupesh Sharma
Masahiro Yamada
Andy Yan
Markus Reichl
Heiko Stuebner
Maxime Ripard
Ondrej Jirman
Icenowy Zheng
Huacai Chen
Olof Johansson
Kees Cook
Fabio Estevam
Peng Fan
Lucas Stach
Bjorn Andersson
Marcel Ziswiler
Geert Uytterhoeven
Anson Huang