linux-dev - Linux kernel development work

Age	Commit message (Expand)	Author	Files	Lines
2022-07-14	MIPS: Remove VR41xx support	Thomas Bogendoerfer	1	-14/+0
2022-02-22	MIPS: remove asm/war.h	Thomas Bogendoerfer	1	-1/+0
2021-09-23	MIPS: Avoid macro redefinitions	Paul Cercueil	1	-77/+113
2021-06-29	MIPS: set mips32r5 for virt extensions	Nick Desaulniers	1	-4/+4
2021-02-11	MIPS: Make check condition for SDBBP consistent with EJTAG spec	Tiezhu Yang	1	-0/+4
2020-09-21	MIPS: Loongson-3: Enable COP2 usage in kernel	Huacai Chen	1	-0/+7
2020-09-07	MIPS: Convert MIPS34K_MISSED_ITLB_WAR into a config option	Thomas Bogendoerfer	1	-2/+2
2020-08-24	MIPS: Remove PNX833x alias NXP_STB22x	Thomas Bogendoerfer	1	-12/+0
2020-07-31	MIPS: handle Loongson-specific GSExc exception	WANG Xuerui	1	-0/+3
2020-07-31	MIPS: add definitions for Loongson-specific CP0.Diag1 register	WANG Xuerui	1	-0/+8
2020-07-08	MIPS: Unify naming style of vendor CP0.Config6 bits	Huacai Chen	1	-14/+14
2020-06-04	KVM: MIPS: Add CONFIG6 and DIAG registers emulation	Huacai Chen	1	-0/+4
2020-05-24	MIPS: Tidy up CP0.Config6 bits definition	Huacai Chen	1	-13/+24
2020-05-22	mips: Add CONFIG/CONFIG6/Cause reg fields macro	Serge Semin	1	-0/+19
2020-05-22	mips: Add CP0 Write Merge config support	Serge Semin	1	-0/+3
2020-05-21	mips: MAAR: Use more precise address mask	Serge Semin	1	-1/+1
2020-05-19	mips: MAAR: Add XPA mode support	Serge Semin	1	-0/+10
2020-05-17	MIPS: define more Loongson CP0.Config6 and CP0.Diag feature bits	WANG Xuerui	1	-0/+6
2020-01-22	MIPS: Add MAC2008 Support	Jiaxun Yang	1	-0/+3
2019-11-22	MIPS: Ingenic: Disable abandoned HPTLB function.	Zhou Yanjie	1	-0/+6
2019-08-05	MIPS: Ingenic: Disable broken BTB lookup optimization.	Zhou Yanjie	1	-0/+4
2019-02-04	MIPS: MemoryMapID (MMID) Support	Paul Burton	1	-0/+4
2019-02-04	MIPS: Add GINVT instruction helpers	Paul Burton	1	-0/+7
2018-11-09	MIPS: Avoid using .set mips0 to restore ISA	Paul Burton	1	-10/+20
2018-10-16	MIPS: Cleanup DSP ASE detection	Paul Burton	1	-1/+19
2018-08-13	Merge tag 'mips_4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux	Linus Torvalds	1	-10/+19
2018-08-07	MIPS: Use dins to simplify __write_64bit_c0_split()	Paul Burton	1	-1/+10
2018-08-07	MIPS: Use read-write output operand in __write_64bit_c0_split()	Paul Burton	1	-9/+7
2018-07-27	Revert "MIPS: BCM47XX: Enable 74K Core ExternalSync for PCIe erratum"	Rafał Miłecki	1	-3/+0
2018-07-23	MIPS: Loongson64: Define and use some CP0 registers	Huacai Chen	1	-0/+2
2018-06-18	MIPS: BCM47XX: Enable 74K Core ExternalSync for PCIe erratum	Tokunori Ikegami	1	-0/+3
2018-05-15	MIPS: Probe for MIPS MT perf counters per TC	Matt Redfearn	1	-0/+5
2018-02-19	MIPS: Add crc instruction support flag to elf_hwcap	Marcin Nowakowski	1	-0/+1
2018-01-22	MIPS: XPA: Standardise readx/writex accessors	James Hogan	1	-10/+10
2018-01-22	MIPS: XPA: Allow use of $0 (zero) to MTHC0	James Hogan	1	-2/+2
2018-01-22	MIPS: XPA: Use XPA instructions in assembly	James Hogan	1	-10/+16
2018-01-22	MIPS: VZ: Pass GC0 register names in $n format	James Hogan	1	-188/+188
2018-01-22	MIPS: VZ: Update helpers to use new asm macros	James Hogan	1	-127/+37
2018-01-22	MIPS: Add helpers for assembler macro instructions	James Hogan	1	-0/+83
2018-01-09	MIPS: mipsregs.h: Make read_c0_prid use const accessor	James Hogan	1	-1/+1
2018-01-09	MIPS: mipsregs.h: Add read const Cop0 macros	James Hogan	1	-10/+27
2017-11-08	MIPS: Use SLL by 0 for 32-bit truncation in `__read_64bit_c0_split'	Maciej W. Rozycki	1	-8/+6
2017-09-21	MIPS: Fix input modify in __write_64bit_c0_split()	James Hogan	1	-6/+9
2017-08-30	MIPS: Add accessor & bit definitions for GlobalNumber	Paul Burton	1	-0/+13
2017-07-05	MIPS: MIPS16e2: Identify ASE presence	Maciej W. Rozycki	1	-0/+1
2017-03-28	KVM: MIPS/VZ: Handle Octeon III guest.PRid register	James Hogan	1	-0/+2
2017-03-28	MIPS: Add Octeon III register accessors & definitions	James Hogan	1	-0/+36
2017-03-28	MIPS: Add some missing guest CP0 accessors & defs	James Hogan	1	-2/+14
2017-03-28	MIPS: Separate MAAR V bit into VL and VH for XPA	James Hogan	1	-1/+7
2017-02-14	MIPS: Unify perf counter register definitions	James Hogan	1	-0/+33