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path: root/arch/mips/kernel/traps.c (follow)
AgeCommit message (Expand)AuthorFilesLines
2009-06-17MIPS: Move Cavium CP0 hwrena impl bits to cpu-feature-overrides.hDavid Daney1-4/+0
2009-06-17MIPS: Allow CPU specific overriding of CP0 hwrena impl bits.David Daney1-1/+1
2009-03-30MIPS: Use BUG_ON() where possible.Ralf Baechle1-2/+1
2009-03-23MIPS: R2: Fix problem with code that incorrectly modifies ebase.Chris Dearman1-5/+7
2009-01-30MIPS: Read watch registers with interrupts disabled.David Daney1-1/+7
2009-01-30MIPS: R2: Fix broken installation of cache error handler.Ralf Baechle1-2/+6
2009-01-11MIPS: For Cavium OCTEON set hwrena and lazily restore CP2 state.David Daney1-0/+21
2008-10-30MIPS: Switch FPU emulator trap to BREAK instruction.Ralf Baechle1-0/+16
2008-10-30MIPS: Consider value of c0_ebase when computing value of exception base.David Daney1-4/+9
2008-10-11MIPS: Watch exception handling for HARDWARE_WATCHPOINTS.David Daney1-5/+19
2008-10-03[MIPS] SMTC: Fix holes in SMTC and FPU affinity support.Kevin D. Kissell1-2/+4
2008-09-21[MIPS] Fix potential latency problem due to non-atomic cpu_wait.Atsushi Nemoto1-6/+16
2008-09-05[MIPS] Fix WARNING: at kernel/smp.c:290Thomas Bogendoerfer1-5/+7
2008-09-05[MIPS] Fix data bus error recoveryThomas Bogendoerfer1-2/+4
2008-07-30[MIPS] kgdb: add arch support for the kernel's kgdb coreJason Wessel1-0/+21
2008-07-15[MIPS] Replace use of print_symbol with new %sP pointer format.Ralf Baechle1-4/+4
2008-07-15[MIPS] Remove board_watchpoint_handlerDavid Daney1-6/+0
2008-06-05[MIPS] Fix check for valid stack pointer during backtraceThomas Bogendoerfer1-7/+9
2008-04-28[MIPS] Fix handling of trap and breakpoint instructionsRalf Baechle1-52/+37
2008-04-28[MIPS] Add support for MIPS CMP platform.Ralf Baechle1-12/+99
2008-04-28[MIPS] Add noulri kernel argument to disable "rdhwr $29" usermode support.Chris Dearman1-1/+12
2008-03-12[MIPS] Fix loads of section missmatchesRalf Baechle1-3/+4
2008-03-12[MIPS] Added missing cases for rdhwr emulationChris Dearman1-6/+25
2007-12-14[MIPS] Ensure that ST0_FR is never set on a 32 bit kernelChris Dearman1-3/+3
2007-11-15[MIPS] Fix shadow register support.Ralf Baechle1-65/+3
2007-10-19Use helpers to obtain task pid in printks (arch code)Alexey Dobriyan1-1/+1
2007-10-18[MIPS] time: Move R4000 clockevent device code to separate configurable fileRalf Baechle1-0/+11
2007-10-17[MIPS] SYNC emulation for MIPS I processorsMaciej W. Rozycki1-78/+86
2007-10-16[MIPS] IP22: Fix warning.Ralf Baechle1-6/+15
2007-10-11[MIPS] Make facility to convert CPU types to strings generally available.Ralf Baechle1-1/+2
2007-10-11[MIPS] Fix "no space between function name and open parenthesis" warnings.Ralf Baechle1-13/+13
2007-10-11[MIPS] Allow hardwiring of the CPU type to a single type for optimization.Ralf Baechle1-3/+3
2007-10-11[MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code.Ralf Baechle1-0/+6
2007-10-11[MIPS] Kill useless volatile keywordRalf Baechle1-2/+2
2007-08-27[MIPS] Maintain si_code field properly for FP exceptionsThiemo Seufer1-3/+18
2007-08-27[MIPS] SMTC: Fix duplicate status dumps on NMIThiemo Seufer1-9/+1
2007-07-31[MIPS] Fixup secure computing stuff.Ralf Baechle1-1/+1
2007-07-17Report that kernel is tainted if there was an OOPSPavel Emelianov1-0/+1
2007-07-13[MIPS] Make show_code static and add __user tagAtsushi Nemoto1-3/+3
2007-07-13[MIPS] Add some __user tagsAtsushi Nemoto1-1/+1
2007-07-12[MIPS] Sparse: Use NULL for pointerAtsushi Nemoto1-1/+1
2007-07-10[MIPS] PMC MSP71xx mips commonMarc St-Jean1-0/+6
2007-07-10[MIPS] Enable support for the userlocal hardware registerRalf Baechle1-1/+8
2007-07-10[MIPS] FP affinity: Coding style cleanups Ralf Baechle1-30/+29
2007-07-10[MIPS] Remove unused watchpoint support and arch/mips/lib-{32,64}Atsushi Nemoto1-1/+0
2007-07-10[MIPS] Transform old-style macros to newer "__noreturn"Robert P. J. Day1-1/+1
2007-07-06[MIPS] Fix timer/performance interrupt detectionChris Dearman1-4/+4
2007-06-20[MIPS] Don't drag a platform specific header into generic arch code.Ralf Baechle1-3/+17
2007-06-11[MIPS] SMTC: The MT ASE requires to initialize c0_pagemask and c0_wired.Ralf Baechle1-0/+7
2007-06-11[MIPS] SMTC: Don't continue in set_vi_srs_handler on detected bad arguments.Ralf Baechle1-2/+3
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