| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2018-10-22 | RISC-V: Use Linux logical CPU number instead of hartid |   Atish Patra | 1 | -3/+13 |
| 2018-06-07 | riscv: use NULL instead of a plain 0 |   Luc Van Oostenryck | 1 | -1/+1 |
| 2018-01-30 | RISC-V: Limit the scope of TLB shootdowns |   Andrew Waterman | 1 | -8/+12 |
| 2018-01-07 | riscv: remove CONFIG_MMU ifdefs |   Christoph Hellwig | 1 | -4/+0 |
| 2017-12-01 | RISC-V: User-Visible Changes |   Palmer Dabbelt | 1 | -0/+2 |
| 2017-11-30 | RISC-V: Flush I$ when making a dirty page executable | Andrew Waterman | 1 | -0/+2 |
| 2017-11-28 | RISC-V: `sfence.vma` orderes the instruction cache | Palmer Dabbelt | 1 | -1/+4 |
| 2017-09-26 | RISC-V: Atomic and Locking Code |   Palmer Dabbelt | 1 | -0/+64 |
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index : linux-dev | |
| Linux kernel development work - see feature branches | Jason A. Donenfeld |
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