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2022-10-14Merge tag 'riscv-for-linus-6.1-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linuxLinus Torvalds1-23/+16
2022-10-13Merge patch series "Some style cleanups for recent extension additions"Palmer Dabbelt1-23/+16
2022-10-13riscv: use BIT() marco for cpufeature probingHeiko Stuebner1-2/+2
2022-10-13riscv: drop some idefs from CMO initializationHeiko Stuebner1-13/+9
2022-10-13riscv: cleanup svpbmt cpufeature probingHeiko Stuebner1-8/+5
2022-10-02RISC-V: Probe Svinval extension form ISA stringMayuresh Chitale1-0/+1
2022-08-16riscv: Ensure isa-ext static keys are writableAndrew Jones1-1/+1
2022-08-11RISC-V: Add Sstc extension supportPalmer Dabbelt1-0/+1
2022-08-11RISC-V: Enable sstc extension parsing from DTAtish Patra1-0/+1
2022-08-11arch/riscv: add Zihintpause supportDao Lu1-0/+1
2022-08-10riscv: implement Zicbom-based CMO instructions + the t-head variantPalmer Dabbelt1-0/+24
2022-07-28riscv: Add support for non-coherent devices using zicbom extensionHeiko Stuebner1-0/+24
2022-07-19RISC-V: Support for 64bit hartid on RV64 platformsPalmer Dabbelt1-2/+4
2022-07-19riscv: cpu: Add 64bit hartid support on RV64Sunil V L1-2/+4
2022-06-16RISC-V: Some Svpbmt fixes and cleanupsPalmer Dabbelt1-26/+11
2022-06-16riscv: remove usage of function-pointers from cpufeatures and t-head errataHeiko Stuebner1-22/+10
2022-06-16riscv: drop cpufeature_apply_feature tracking variableHeiko Stuebner1-4/+1
2022-06-16riscv: switch has_fpu() to the unified static key mechanismJisheng Zhang1-7/+0
2022-06-16riscv: introduce unified static key mechanism for ISA extensionsJisheng Zhang1-0/+7
2022-06-04Merge tag 'bitmap-for-5.19-rc1' of https://github.com/norov/linuxLinus Torvalds1-4/+3
2022-06-03risc-v: replace bitmap_weight with bitmap_empty in riscv_fill_hwcap()Yury Norov1-4/+3
2022-05-11riscv: add memory-type errata for T-HeadHeiko Stuebner1-1/+6
2022-05-11riscv: add RISC-V Svpbmt extension supportHeiko Stuebner1-1/+74
2022-03-21RISC-V: Add sscofpmf extension supportAtish Patra1-0/+2
2022-03-17RISC-V: Do no continue isa string parsing without correct XLENAtish Patra1-0/+5
2022-03-17RISC-V: Implement multi-letter ISA extension probing frameworkAtish Patra1-6/+16
2022-03-17RISC-V: Extract multi-letter extension names from "riscv, isa"Tsukasa OI1-8/+27
2022-03-17RISC-V: Minimal parser for "riscv, isa" stringsTsukasa OI1-11/+61
2022-03-17RISC-V: Correctly print supported extensionsTsukasa OI1-3/+5
2021-05-29riscv: Add __init section marker to some functions againJisheng Zhang1-1/+1
2021-05-25riscv: Turn has_fpu into a static key if FPU=yJisheng Zhang1-2/+2
2020-05-04RISC-V: Add bitmap reprensenting ISA features common across CPUsAnup Patel1-3/+80
2019-10-28riscv: add missing header file includesPaul Walmsley1-0/+1
2019-06-19treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 234Thomas Gleixner1-12/+1
2019-03-04RISC-V: Assign hwcap as per comman capabilities.Atish Patra1-19/+22
2019-02-11riscv: use for_each_of_cpu_node iteratorJohan Hovold1-2/+3
2019-02-11riscv: add missing newlines to printk messagesJohan Hovold1-4/+4
2018-12-21RISC-V: Fix of_node_* refcountAtish Patra1-0/+2
2018-10-31RISC-V: properly determine hardware capsAndreas Schwab1-3/+5
2018-10-22riscv: Add support to no-FPU systemsPalmer Dabbelt1-0/+8
2018-10-22RISC-V: Mask out the F extension on systems without DPalmer Dabbelt1-0/+7
2018-10-22Auto-detect whether a FPU existsAlan Kao1-0/+8
2017-09-26RISC-V: User-facing APIPalmer Dabbelt1-0/+61