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AgeCommit message (Expand)AuthorFilesLines
2019-11-17riscv: add nommu supportChristoph Hellwig1-0/+6
2019-11-17riscv: clear the instruction cache and all registers when bootingChristoph Hellwig1-1/+87
2019-11-17riscv: read the hart ID from mhartid on bootDamien Le Moal1-0/+8
2019-11-05riscv: abstract out CSR names for supervisor vs machine modeChristoph Hellwig1-6/+6
2019-09-20arch/riscv: disable excess harts before picking main boot hartXiang Wang1-3/+5
2019-09-16Merge tag 'riscv/for-v5.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linuxLinus Torvalds1-1/+1
2019-09-13riscv: modify the Image header to improve compatibility with the ARM64 headerPaul Walmsley1-2/+2
2019-08-30riscv: Using CSR numbers to access CSRsBin Meng1-1/+1
2019-07-11RISC-V: Add an Image header that boot loader can parse.Atish Patra1-0/+32
2019-07-09RISC-V: Setup initial page tables in two stagesAnup Patel1-8/+9
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286Thomas Gleixner1-9/+1
2019-05-16RISC-V: Avoid using invalid intermediate translationsPalmer Dabbelt1-2/+10
2019-05-16RISC-V: Access CSRs using CSR numbersAnup Patel1-8/+8
2019-04-25riscv: cleanup the parse_dtb calling conventionsChristoph Hellwig1-2/+1
2019-04-25riscv: simplify the stack pointer setup in head.SChristoph Hellwig1-4/+1
2019-04-25riscv: clear all pending interrupts when bootingChristoph Hellwig1-1/+2
2018-11-20RISC-V: Build flat and compressed kernel imagesAnup Patel1-0/+10
2018-10-22RISC-V: Use Linux logical CPU number instead of hartidAtish Patra1-1/+3
2018-08-13RISC-V: Add the directive for alignment of stvec's valueZong Li1-0/+2
2018-02-20Rename sbi_save to parse_dtb to improve code readabilityMichael Clark1-1/+1
2018-01-30riscv: rename sptbr to satpChristoph Hellwig1-3/+3
2017-11-30RISC-V: move empty_zero_page definition to C and export itOlof Johansson1-3/+0
2017-09-26RISC-V: Init and Halt CodePalmer Dabbelt1-0/+157