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2019-10-09RISC-V: entry: Remove unneeded need_resched() loopValentin Schneider1-2/+1
2019-10-07riscv: Correct the handling of unexpected ebreak in do_trap_break()Vincent Chen1-3/+3
2019-10-07riscv: avoid sending a SIGTRAP to a user thread trapped in WARN()Vincent Chen1-1/+1
2019-10-07riscv: avoid kernel hangs when trapped in BUG()Vincent Chen1-3/+3
2019-10-01RISC-V: Clear load reservations while restoring hart contextsPalmer Dabbelt1-1/+20
2019-09-20riscv: Avoid interrupts being erroneously enabled in handle_exception()Vincent Chen1-1/+5
2019-09-20RISC-V: Export kernel symbols for kvmAtish Patra2-0/+2
2019-09-20arch/riscv: disable excess harts before picking main boot hartXiang Wang1-3/+5
2019-09-16Merge tag 'riscv/for-v5.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linuxLinus Torvalds8-35/+187
2019-09-16Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linuxLinus Torvalds1-0/+3
2019-09-13riscv: modify the Image header to improve compatibility with the ARM64 headerPaul Walmsley1-2/+2
2019-09-05riscv: cleanup riscv_cpuid_to_hartid_maskChristoph Hellwig1-0/+1
2019-09-05riscv: optimize send_ipi_singleChristoph Hellwig1-1/+7
2019-09-05riscv: cleanup send_ipi_maskChristoph Hellwig1-9/+7
2019-09-05riscv: refactor the IPI codeChristoph Hellwig1-24/+31
2019-09-05riscv: Add support for perf registers samplingMao Han2-0/+45
2019-09-04riscv: Add perf callchain supportMao Han3-3/+98
2019-08-30riscv: Using CSR numbers to access CSRsBin Meng3-8/+8
2019-08-30Merge tag 'common/for-v5.4-rc1/cpu-topology' into for-v5.4-rc1-branchPaul Walmsley1-0/+3
2019-08-14riscv: Correct the initialized flow of FP registerVincent Chen1-2/+9
2019-08-14Merge tag 'common/for-v5.4-rc1/cpu-topology' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux into for-next/cpu-topologyWill Deacon1-0/+3
2019-07-31riscv: Fix perf record without libelf supportMao Han1-1/+1
2019-07-22RISC-V: Parse cpu topology during boot.Atish Patra1-0/+3
2019-07-18Merge tag 'riscv/for-v5.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linuxLinus Torvalds3-31/+43
2019-07-11RISC-V: Add an Image header that boot loader can parse.Atish Patra1-0/+32
2019-07-09RISC-V: Setup initial page tables in two stagesAnup Patel2-12/+11
2019-07-08Merge branch 'siginfo-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/ebiederm/user-namespaceLinus Torvalds2-6/+7
2019-07-01riscv: Remove gate area stubsAndy Lutomirski1-19/+0
2019-06-21Merge tag 'spdx-5.2-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/spdxLinus Torvalds4-40/+4
2019-06-19treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500Thomas Gleixner1-4/+1
2019-06-19treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 234Thomas Gleixner3-36/+3
2019-06-17Merge tag 'riscv-for-v5.2/fixes-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linuxLinus Torvalds1-0/+1
2019-06-11riscv: export pm_power_off againAndreas Schwab1-0/+1
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286Thomas Gleixner20-180/+20
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174Thomas Gleixner2-18/+2
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157Thomas Gleixner1-9/+1
2019-05-29signal: Remove the task parameter from force_sig_faultEric W. Biederman1-2/+2
2019-05-29signal: Explicitly call force_sig_fault on currentEric W. Biederman1-1/+1
2019-05-29signal/riscv: Remove tsk parameter from do_trapEric W. Biederman1-3/+4
2019-05-27signal: Remove task parameter from force_sigEric W. Biederman1-1/+1
2019-05-24treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 120Thomas Gleixner3-42/+3
2019-05-21treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner2-0/+2
2019-05-19Merge tag 'riscv-for-linus-5.2-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linuxLinus Torvalds14-125/+115
2019-05-16RISC-V: Avoid using invalid intermediate translationsPalmer Dabbelt1-2/+10
2019-05-16riscv: Support BUG() in kernel moduleVincent Chen1-1/+1
2019-05-16riscv: Add the support for c.ebreak check in is_valid_bugaddr()Vincent Chen1-3/+17
2019-05-16riscv: move flush_icache_{all,mm} to cacheflush.cGary Guo1-49/+0
2019-05-16RISC-V: Access CSRs using CSR numbersAnup Patel5-25/+25
2019-05-16RISC-V: Add interrupt related SCAUSE defines in asm/csr.hAnup Patel1-12/+4
2019-05-16RISC-V: Fix minor checkpatch issues.Atish Patra1-2/+2