linux-dev - Linux kernel development work

Age	Commit message (Expand)	Author	Files	Lines
2018-11-30	Merge tag 'trace-v4.20-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/rostedt/linux-trace	Linus Torvalds	1	-12/+2
2018-11-27	riscv/function_graph: Simplify with function_graph_enter()	Steven Rostedt (VMware)	1	-12/+2
2018-11-20	RISC-V: recognize S/U mode bits in print_isa	Patrick Stählin	1	-3/+6
2018-11-20	RISC-V: Build flat and compressed kernel images	Anup Patel	2	-1/+11
2018-11-12	RISC-V: Silence some module warnings on 32-bit	Olof Johansson	1	-6/+6
2018-10-31	RISC-V: properly determine hardware caps	Andreas Schwab	1	-3/+5
2018-10-22	RISC-V: SMP cleanup and new features	Palmer Dabbelt	7	-47/+195
2018-10-22	RISC-V: Fix some RV32 bugs and build failures	Palmer Dabbelt	1	-0/+3
2018-10-22	riscv: Add support to no-FPU systems	Palmer Dabbelt	6	-115/+168
2018-10-22	RISC-V: remove the unused return_to_handler export	Christoph Hellwig	1	-1/+0
2018-10-22	RISC-V: Add FP register ptrace support for gdb.	Jim Wilson	1	-0/+52
2018-10-22	RISC-V: Mask out the F extension on systems without D	Palmer Dabbelt	1	-0/+7
2018-10-22	RISC-V: Don't set cacheinfo.{physical_line_partition,attributes}	Palmer Dabbelt	1	-7/+0
2018-10-22	RISC-V: Show IPI stats	Anup Patel	2	-7/+40
2018-10-22	RISC-V: Show CPU ID and Hart ID separately in /proc/cpuinfo	Anup Patel	1	-4/+6
2018-10-22	RISC-V: Use Linux logical CPU number instead of hartid	Atish Patra	5	-22/+45
2018-10-22	RISC-V: Add logical CPU indexing for RISC-V	Atish Patra	2	-0/+23
2018-10-22	RISC-V: Use WRITE_ONCE instead of direct access	Atish Patra	1	-2/+3
2018-10-22	RISC-V: Use mmgrab()	Palmer Dabbelt	1	-1/+2
2018-10-22	RISC-V: Rename im_okay_therefore_i_am to found_boot_cpu	Palmer Dabbelt	1	-4/+5
2018-10-22	RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartid	Palmer Dabbelt	2	-3/+6
2018-10-22	RISC-V: Disable preemption before enabling interrupts	Atish Patra	1	-1/+5
2018-10-22	RISC-V: Comment on the TLB flush in smp_callin()	Palmer Dabbelt	1	-0/+4
2018-10-22	RISC-V: Filter ISA and MMU values in cpuinfo	Palmer Dabbelt	1	-7/+61
2018-10-22	RISC-V: Don't set cacheinfo.{physical_line_partition,attributes}	Palmer Dabbelt	1	-7/+0
2018-10-22	RISC-V: No need to pass scause as arg to do_IRQ()	Anup Patel	2	-3/+2
2018-10-22	RISC-V: Use swiotlb on RV64 only	Zong Li	1	-0/+3
2018-10-22	Auto-detect whether a FPU exists	Alan Kao	3	-3/+15
2018-10-22	Allow to disable FPU support	Alan Kao	3	-2/+9
2018-10-22	Refactor FPU code in signal setup/return procedures	Alan Kao	1	-27/+41
2018-10-22	Extract FPU context operations from entry.S	Alan Kao	3	-87/+107
2018-10-02	RISCV: Fix end PFN for low memory	Atish Patra	1	-1/+1
2018-09-04	riscv: Do not overwrite initrd_start and initrd_end	Guenter Roeck	1	-7/+0
2018-08-28	RISC-V: Use a less ugly workaround for unused variable warnings	Palmer Dabbelt	1	-14/+1
2018-08-20	RISC-V: Define sys_riscv_flush_icache when SMP=n	Palmer Dabbelt	1	-2/+10
2018-08-13	RISC-V: Fix !CONFIG_SMP compilation error	Atish Patra	1	-1/+0
2018-08-13	RISC-V: Add the directive for alignment of stvec's value	Zong Li	1	-0/+2
2018-08-13	clocksource: new RISC-V SBI timer driver	Palmer Dabbelt	3	-9/+4
2018-08-13	RISC-V: implement low-level interrupt handling	Christoph Hellwig	2	-11/+45
2018-08-13	RISC-V: simplify software interrupt / IPI code	Christoph Hellwig	1	-4/+2
2018-08-13	RISC-V: remove timer leftovers	Christoph Hellwig	1	-21/+0
2018-08-13	RISC-V: Add early printk support via the SBI console	Palmer Dabbelt	1	-0/+27
2018-08-13	RISC-V: Don't increment sepc after breakpoint.	Jim Wilson	1	-1/+0
2018-08-13	RISC-V: Use KBUILD_CFLAGS instead of KCFLAGS when building the vDSO	Palmer Dabbelt	1	-2/+2
2018-07-04	RISC-V: Fix the rv32i kernel build	Palmer Dabbelt	1	-11/+11
2018-07-04	RISC-V: Fix PTRACE_SETREGSET bug.	Jim Wilson	1	-1/+1
2018-07-04	RISC-V: Don't include irq-riscv-intc.h	Palmer Dabbelt	1	-4/+0
2018-07-04	riscv: remove unnecessary of_platform_populate call	Rob Herring	1	-5/+0
2018-07-04	RISC-V: fix R_RISCV_ADD32/R_RISCV_SUB32 relocations	Andreas Schwab	1	-2/+2
2018-07-04	RISC-V: Change variable type for 32-bit compatible	Zong Li	1	-11/+11