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2019-11-28Merge tag 'ioremap-5.5' of git://git.infradead.org/users/hch/ioremapLinus Torvalds2-85/+1
2019-11-22Merge branch 'next/nommu' into for-nextPaul Walmsley6-15/+41
2019-11-22Merge branch 'next/misc' into for-nextPaul Walmsley1-9/+4
2019-11-17riscv: add nommu supportChristoph Hellwig4-4/+18
2019-11-13riscv: implement remote sfence.i using IPIsChristoph Hellwig1-6/+18
2019-11-12riscv: Use PMD_SIZE to replace PTE_PARENT_SIZEZong Li1-9/+4
2019-11-11riscv: use the generic ioremap codeChristoph Hellwig2-85/+0
2019-11-05riscv: abstract out CSR names for supervisor vs machine modeChristoph Hellwig2-5/+5
2019-10-29RISC-V: Issue a tlb page flush if possibleAtish Patra1-1/+4
2019-10-29RISC-V: Issue a local tlbflush if possible.Atish Patra1-2/+17
2019-10-29RISC-V: Do not invoke SBI call if cpumask is emptyAtish Patra1-0/+3
2019-10-28riscv: add missing header file includesPaul Walmsley1-0/+1
2019-10-28riscv: mark some code and data as file-staticPaul Walmsley1-1/+1
2019-10-28riscv: init: merge split string literals in preprocessor directivePaul Walmsley1-2/+1
2019-10-28riscv: add prototypes for assembly language functions from head.SPaul Walmsley2-0/+4
2019-10-23riscv: Fix undefined reference to vmemmap_populate_basepagesKefeng Wang1-1/+1
2019-10-01riscv: Fix memblock reservation for device tree blobAlbert Ou1-1/+11
2019-09-05riscv: move the TLB flush logic out of lineChristoph Hellwig2-0/+38
2019-09-05riscv: cleanup riscv_cpuid_to_hartid_maskChristoph Hellwig1-1/+0
2019-08-30RISC-V: Implement sparsememLogan Gunthorpe1-0/+10
2019-08-30riscv: Using CSR numbers to access CSRsBin Meng2-7/+2
2019-07-18Merge tag 'riscv/for-v5.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linuxLinus Torvalds4-68/+315
2019-07-09RISC-V: Setup initial page tables in two stagesAnup Patel1-52/+255
2019-07-08Merge branch 'siginfo-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/ebiederm/user-namespaceLinus Torvalds1-3/+3
2019-07-04riscv: remove free_initrd_memChristoph Hellwig1-5/+0
2019-07-04riscv: ccache: Remove unused variableYash Shah1-4/+7
2019-07-03riscv: Introduce huge page support for 32/64bit kernelAlexandre Ghiti2-0/+46
2019-07-01RISC-V: Fix memory reservation in setup_bootmem()Anup Patel1-7/+7
2019-06-26riscv: mm: Fix code commentShihPo Hung1-3/+0
2019-06-17Merge tag 'riscv-for-v5.2/fixes-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linuxLinus Torvalds1-0/+13
2019-06-17riscv: mm: synchronize MMU after pte changeShihPo Hung1-0/+13
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286Thomas Gleixner3-27/+3
2019-05-29signal/riscv: Remove tsk parameter from do_trapEric W. Biederman1-3/+3
2019-05-24treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 120Thomas Gleixner2-28/+2
2019-05-21treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner1-0/+1
2019-05-19Merge tag 'riscv-for-linus-5.2-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linuxLinus Torvalds5-6/+310
2019-05-16riscv: fix locking violation in page fault handlerAndreas Schwab1-1/+2
2019-05-16RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCsYash Shah2-0/+176
2019-05-16riscv: move switch_mm to its own fileGary Guo2-0/+70
2019-05-16riscv: move flush_icache_{all,mm} to cacheflush.cGary Guo1-0/+61
2019-05-16RISC-V: Access CSRs using CSR numbersAnup Patel1-5/+1
2019-05-14riscv: switch over to generic free_initmem()Mike Rapoport1-5/+0
2019-04-10RISC-V: Fix Maximum Physical Memory 2GiB option for 64bit systemsAnup Patel1-0/+8
2019-03-26RISC-V: Always compile mm/init.c with cmodel=medany and notraceAnup Patel2-0/+34
2019-02-21RISC-V: Free-up initrd in free_initrd_mem()Anup Patel1-1/+2
2019-02-21RISC-V: Implement compile-time fixed mappingsAnup Patel1-0/+34
2019-02-21RISC-V: Move setup_vm() to mm/init.cAnup Patel1-0/+49
2019-02-21RISC-V: Move setup_bootmem() to mm/init.cAnup Patel1-0/+70
2019-01-23riscv: fixup max_low_pfn with PFN_DOWN.Guo Ren1-1/+2
2018-10-31mm: remove include/linux/bootmem.hMike Rapoport1-2/+1