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2021-06-01perf/x86/rapl: Use CPUID bit on AMD and Hygon partsAndrew Cooper1-4/+2
2021-04-19perf/x86/rapl: Add support for Intel Alder LakeZhang Rui1-0/+2
2021-02-10perf/x86/rapl: Fix psys-energy event on Intel SPR platformZhang Rui1-12/+9
2021-02-10perf/x86/rapl: Only check lower 32bits for RAPL energy countersZhang Rui1-5/+8
2020-11-17perf/x86: fix sysfs type mismatchesSami Tolvanen1-13/+1
2020-09-10perf/x86/rapl: Add AMD Fam19h RAPL supportKim Phillips1-0/+1
2020-08-14perf/x86/rapl: Add support for Intel SPR platformZhang Rui1-0/+20
2020-08-14perf/x86/rapl: Support multiple RAPL unit quirksZhang Rui1-9/+15
2020-08-14perf/x86/rapl: Fix missing psys sysfs attributesZhang Rui1-1/+1
2020-07-28perf/x86/rapl: Add Hygon Fam18h RAPL supportPu Wen1-1/+2
2020-05-28perf/x86/rapl: Add AMD Fam17h RAPL supportStephane Eranian1-0/+18
2020-05-28perf/x86/rapl: Flip logic on default events visibilityStephane Eranian1-0/+11
2020-05-28perf/x86/rapl: Refactor to share the RAPL code between Intel and AMD CPUsStephane Eranian1-6/+23
2020-05-28perf/x86/rapl: Move RAPL support to common x86 codeStephane Eranian1-0/+805
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