| Age | Commit message (Expand) | Author | Files | Lines |
| 2021-04-19 | perf/x86: Add structures for the attributes of Hybrid PMUs |  Kan Liang | 2 | -0/+62 |
| 2021-04-19 | perf/x86: Register hybrid PMUs |  Kan Liang | 3 | -21/+223 |
| 2021-04-19 | perf/x86: Factor out x86_pmu_show_pmu_cap |  Kan Liang | 2 | -9/+19 |
| 2021-04-19 | perf/x86: Remove temporary pmu assignment in event_init |  Kan Liang | 1 | -11/+0 |
| 2021-04-19 | perf/x86/intel: Factor out intel_pmu_check_extra_regs |  Kan Liang | 1 | -14/+21 |
| 2021-04-19 | perf/x86/intel: Factor out intel_pmu_check_event_constraints |  Kan Liang | 1 | -35/+47 |
| 2021-04-19 | perf/x86/intel: Factor out intel_pmu_check_num_counters |  Kan Liang | 1 | -14/+24 |
| 2021-04-19 | perf/x86: Hybrid PMU support for extra_regs |  Kan Liang | 3 | -8/+13 |
| 2021-04-19 | perf/x86: Hybrid PMU support for event constraints |  Kan Liang | 4 | -5/+10 |
| 2021-04-19 | perf/x86: Hybrid PMU support for hardware cache event |  Kan Liang | 2 | -3/+11 |
| 2021-04-19 | perf/x86: Hybrid PMU support for unconstrained |  Kan Liang | 2 | -1/+12 |
| 2021-04-19 | perf/x86: Hybrid PMU support for counters |  Kan Liang | 4 | -25/+56 |
| 2021-04-19 | perf/x86: Hybrid PMU support for intel_ctrl |  Kan Liang | 3 | -14/+24 |
| 2021-04-19 | perf/x86/intel: Hybrid PMU support for perf capabilities |  Kan Liang | 4 | -7/+57 |
| 2021-04-19 | perf/x86: Track pmu in per-CPU cpu_hw_events |  Kan Liang | 5 | -12/+24 |
| 2021-04-16 | perf/amd/uncore: Fix sysfs type mismatch |  Nathan Chancellor | 1 | -3/+3 |
| 2021-04-16 | x86/events/amd/iommu: Fix sysfs type mismatch |  Nathan Chancellor | 1 | -3/+3 |
| 2021-04-16 | Merge branches 'iommu/fixes', 'arm/mediatek', 'arm/smmu', 'arm/exynos', 'unisoc', 'x86/vt-d', 'x86/amd' and 'core' into next |  Joerg Roedel | 2 | -19/+1 |
| 2021-04-16 | perf/x86: Move cpuc->running into P4 specific code |  Kan Liang | 3 | -5/+13 |
| 2021-04-07 | iommu/amd: Move a few prototypes to include/linux/amd-iommu.h |  Christoph Hellwig | 2 | -19/+1 |
| 2021-04-02 | Merge tag 'v5.12-rc5' into WIP.x86/core, to pick up recent NOP related changes |  Ingo Molnar | 2 | -1/+4 |
| 2021-04-02 | perf/x86/intel/uncore: Enable IIO stacks to PMON mapping for multi-segment SKX |  Alexander Antonov | 3 | -34/+47 |
| 2021-04-02 | perf/x86/intel/uncore: Generic support for the MMIO type of uncore blocks |  Kan Liang | 4 | -0/+101 |
| 2021-04-02 | perf/x86/intel/uncore: Generic support for the PCI type of uncore blocks |  Kan Liang | 4 | -7/+177 |
| 2021-04-02 | perf/x86/intel/uncore: Rename uncore_notifier to uncore_pci_sub_notifier |  Kan Liang | 1 | -6/+14 |
| 2021-04-02 | perf/x86/intel/uncore: Generic support for the MSR type of uncore blocks |  Kan Liang | 4 | -10/+182 |
| 2021-04-02 | perf/x86/intel/uncore: Parse uncore discovery tables |  Kan Liang | 4 | -8/+448 |
| 2021-03-21 | x86: Fix various typos in comments, take #2 |  Ingo Molnar | 3 | -3/+3 |
| 2021-03-21 | x86: Remove unusual Unicode characters from comments |  Ingo Molnar | 1 | -6/+6 |
| 2021-03-21 | Merge branch 'linus' into x86/cleanups, to resolve conflict |  Ingo Molnar | 2 | -1/+4 |
| 2021-03-18 | x86: Fix various typos in comments |  Ingo Molnar | 9 | -15/+15 |
| 2021-03-16 | perf/x86/intel: Fix unchecked MSR access error caused by VLBR_EVENT |  Kan Liang | 1 | -0/+3 |
| 2021-03-16 | perf/x86/intel: Fix a crash caused by zero PEBS status |  Kan Liang | 1 | -1/+1 |
| 2021-03-15 | perf/x86/intel/ds: Check return values of insn decoder functions |  Borislav Petkov | 1 | -5/+5 |
| 2021-03-15 | perf/x86/intel/ds: Check insn_get_length() retval |  Borislav Petkov | 1 | -6/+5 |
| 2021-03-10 | x86/perf: Use RET0 as default for guest_get_msrs to handle "no PMU" case |  Sean Christopherson | 1 | -9/+6 |
| 2021-03-06 | perf/x86/intel: Set PERF_ATTACH_SCHED_CB for large PEBS and LBR |  Kan Liang | 1 | -1/+4 |
| 2021-02-10 | perf/x86/rapl: Fix psys-energy event on Intel SPR platform |  Zhang Rui | 1 | -12/+9 |
| 2021-02-10 | perf/x86/rapl: Only check lower 32bits for RAPL energy counters |  Zhang Rui | 1 | -5/+8 |
| 2021-02-10 | perf/x86/rapl: Add msr mask support |  Zhang Rui | 2 | -4/+10 |
| 2021-02-10 | perf/x86/kvm: Add Cascade Lake Xeon steppings to isolation_ucodes[] |  Jim Mattson | 1 | -0/+3 |
| 2021-02-01 | perf/x86/intel: Support CPUID 10.ECX to disable fixed counters |  Kan Liang | 3 | -11/+36 |
| 2021-02-01 | perf/x86/intel: Add perf core PMU support for Sapphire Rapids |  Kan Liang | 3 | -10/+427 |
| 2021-02-01 | perf/x86/intel: Filter unsupported Topdown metrics event |  Kan Liang | 2 | -2/+14 |
| 2021-02-01 | perf/x86/intel: Factor out intel_update_topdown_event() |  Kan Liang | 1 | -7/+13 |
| 2021-02-01 | perf/core: Add PERF_SAMPLE_WEIGHT_STRUCT |  Kan Liang | 1 | -8/+9 |
| 2021-01-27 | perf/intel: Remove Perfmon-v4 counter_freezing support |  Peter Zijlstra | 2 | -154/+1 |
| 2021-01-27 | x86/perf: Use static_call for x86_pmu.guest_get_msrs |  Like Xu | 2 | -20/+20 |
| 2021-01-14 | perf/x86/intel/uncore: With > 8 nodes, get pci bus die id from NUMA info |  Steve Wahl | 1 | -28/+65 |
| 2021-01-14 | perf/x86/intel/uncore: Store the logical die id instead of the physical die id. |  Steve Wahl | 4 | -57/+39 |