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2019-03-06x86: Add TSX Force Abort CPUID/MSRPeter Zijlstra (Intel)1-0/+1
2018-12-26Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds1-0/+1
2018-12-21KVM: x86: Add CPUID support for new instruction WBNOINVDRobert Hoo1-0/+1
2018-12-18x86/speculation: Add support for STIBP always-on preferred modeThomas Lendacky1-0/+1
2018-10-25x86/cpufeatures: Enumerate MOVDIR64B instructionFenghua Yu1-0/+1
2018-10-25x86/cpufeatures: Enumerate MOVDIRI instructionFenghua Yu1-0/+1
2018-08-14Merge branch 'l1tf-final' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tipLinus Torvalds1-1/+4
2018-08-13Merge branch 'x86/pti' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tipLinus Torvalds1-0/+1
2018-08-03x86/speculation: Support Enhanced IBRS on future CPUsSai Praneeth1-0/+1
2018-08-03x86/cpufeatures: Add EPT_AD feature bitPeter Feiner1-1/+1
2018-06-21x86/cpufeatures: Add detection of L1D cache flush support.Konrad Rzeszutek Wilk1-0/+1
2018-06-20x86/speculation/l1tf: Add sysfs reporting for l1tfAndi Kleen1-0/+2
2018-06-06x86/bugs: Add AMD's SPEC_CTRL MSR usageKonrad Rzeszutek Wilk1-0/+1
2018-06-06x86/bugs: Add AMD's variant of SSB_NOKonrad Rzeszutek Wilk1-0/+1
2018-05-17x86/speculation: Add virtualized speculative store bypass disable supportTom Lendacky1-0/+1
2018-05-17x86/cpufeatures: Add FEATURE_ZENThomas Gleixner1-0/+1
2018-05-17x86/cpufeatures: Disentangle SSBD enumerationThomas Gleixner1-4/+3
2018-05-17x86/cpufeatures: Disentangle MSR_SPEC_CTRL enumeration from IBRSThomas Gleixner1-0/+1
2018-05-17x86/speculation: Use synthetic bits for IBRS/IBPB/STIBPBorislav Petkov1-4/+6
2018-05-09x86/bugs: Rename _RDS to _SSBDKonrad Rzeszutek Wilk1-2/+2
2018-05-03x86/bugs/AMD: Add support to disable RDS on Fam[15,16,17]h if requestedKonrad Rzeszutek Wilk1-0/+1
2018-05-03x86/bugs: Provide boot parameters for the spec_store_bypass_disable mitigationKonrad Rzeszutek Wilk1-0/+1
2018-05-03x86/cpufeatures: Add X86_FEATURE_RDSKonrad Rzeszutek Wilk1-0/+1
2018-05-03x86/bugs: Expose /sys/../spec_store_bypassKonrad Rzeszutek Wilk1-0/+1
2018-04-26x86/cpufeatures: Enumerate cldemote instructionFenghua Yu1-0/+1
2018-03-12x86/cpufeatures: Add Intel PCONFIG cpufeatureKirill A. Shutemov1-0/+1
2018-03-12x86/cpufeatures: Add Intel Total Memory Encryption cpufeatureKirill A. Shutemov1-0/+1
2018-02-20x86/speculation: Use IBRS if available before calling into firmwareDavid Woodhouse1-0/+1
2018-02-01Merge branch 'x86/hyperv' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tipRadim Krčmář1-6/+24
2018-01-29Merge branch 'x86-pti-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tipLinus Torvalds1-6/+16
2018-01-27x86/cpufeatures: Clean up Spectre v2 related CPUID flagsDavid Woodhouse1-9/+9
2018-01-26x86/speculation: Add basic IBPB (Indirect Branch Prediction Barrier) supportDavid Woodhouse1-0/+2
2018-01-26x86/cpufeatures: Add AMD feature bits for Speculation ControlDavid Woodhouse1-0/+3
2018-01-26x86/cpufeatures: Add Intel feature bits for Speculation ControlDavid Woodhouse1-0/+3
2018-01-26x86/cpufeatures: Add CPUID_7_EDX CPUID leafDavid Woodhouse1-3/+5
2018-01-18x86/intel_rdt: Enumerate L2 Code and Data Prioritization (CDP) featureFenghua Yu1-0/+1
2018-01-17x86/cpufeature: Move processor tracing out of scattered featuresPaolo Bonzini1-1/+1
2018-01-16Merge branch 'sev-v9-p2' of https://github.com/codomania/kvmPaolo Bonzini1-0/+1
2018-01-15x86/retpoline: Fill RSB on context switch for affected CPUsDavid Woodhouse1-0/+1
2018-01-12x86/retpoline: Add initial retpoline supportDavid Woodhouse1-0/+2
2018-01-06x86/cpufeatures: Add X86_BUG_SPECTRE_V[12]David Woodhouse1-0/+2
2018-01-05x86/pti: Rename BUG_CPU_INSECURE to BUG_CPU_MELTDOWNThomas Gleixner1-1/+1
2017-12-23x86/mm: Use INVPCID for __native_flush_tlb_single()Dave Hansen1-0/+1
2017-12-23x86/cpufeatures: Add X86_BUG_CPU_INSECUREThomas Gleixner1-1/+2
2017-12-17x86: Make X86_BUG_FXSAVE_LEAK detectable in CPUID on AMDRudolf Marek1-0/+1
2017-12-17x86/cpufeature: Add User-Mode Instruction Prevention definitionsRicardo Neri1-0/+1
2017-12-06x86/cpufeatures: Make X86_BUG_FXSAVE_LEAK detectable in CPUID on AMDRudolf Marek1-0/+1
2017-12-04x86/CPU/AMD: Add the Secure Encrypted Virtualization CPU featureTom Lendacky1-0/+1
2017-11-08x86/cpufeature: Add User-Mode Instruction Prevention definitionsRicardo Neri1-0/+1
2017-11-07x86/cpufeatures: Fix various details in the feature definitionsIngo Molnar1-75/+74
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