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path: root/arch/x86/include/asm/tlbflush.h (follow)
AgeCommit message (Expand)AuthorFilesLines
2018-11-28x86/speculation: Prepare for conditional IBPB in switch_mm()Thomas Gleixner1-2/+6
2018-10-29x86/mm/pat: Disable preemption around __flush_tlb_all()Sebastian Andrzej Siewior1-0/+6
2018-10-09x86/mm/tlb: Add freed_tables element to flush_tlb_infoRik van Riel1-0/+1
2018-10-09x86/mm/tlb: Add freed_tables argument to flush_tlb_mm_rangeRik van Riel1-4/+6
2018-10-09x86/mm/tlb: Always use lazy TLB modeRik van Riel1-16/+0
2018-10-09x86/mm: Page size aware flush_tlb_mm_range()Peter Zijlstra1-4/+8
2018-08-31x86/nmi: Fix NMI uaccess race against CR3 switchingAndy Lutomirski1-0/+40
2018-08-23x86/mm: Only use tlb_remove_table() for paravirtPeter Zijlstra1-0/+3
2018-08-22x86/mm/tlb: Revert the recent lazy TLB patchesPeter Zijlstra1-5/+16
2018-07-17x86/mm/tlb: Always use lazy TLB modeRik van Riel1-16/+0
2018-07-17x86/mm/tlb: Leave lazy TLB mode at page table free timeRik van Riel1-0/+5
2018-04-05x86/mm: Fix bogus warning during EFI bootup, use boot_cpu_has() instead of this_cpu_has() in build_cr3_noflush()Sai Praneeth1-1/+6
2018-02-15x86/mm: Rename flush_tlb_single() and flush_tlb_one() to __flush_tlb_one_[user|kernel]()Andy Lutomirski1-7/+20
2018-01-30x86/speculation: Use Indirect Branch Prediction Barrier in context switchTim Chen1-0/+2
2018-01-14Merge branch 'x86-pti-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tipLinus Torvalds1-3/+3
2018-01-14x86/pti: Fix !PCID and sanitize definesThomas Gleixner1-3/+3
2017-12-31Merge branch 'x86-pti-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tipLinus Torvalds1-6/+8
2017-12-31x86/mm: Remove preempt_disable/enable() from __native_flush_tlb()Thomas Gleixner1-6/+8
2017-12-29Merge branch 'x86-pti-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tipLinus Torvalds1-31/+171
2017-12-23x86/mm: Clarify the whole ASID/kernel PCID/user PCID namingPeter Zijlstra1-12/+43
2017-12-23x86/mm: Use INVPCID for __native_flush_tlb_single()Dave Hansen1-1/+22
2017-12-23x86/mm: Use/Fix PCID to optimize user/kernel switchesPeter Zijlstra1-12/+79
2017-12-23x86/mm: Allow flushing for future ASID switchesDave Hansen1-8/+29
2017-12-23Merge branch 'x86-pti-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tipLinus Torvalds1-64/+72
2017-12-22x86/mm: Create asm/invpcid.hPeter Zijlstra1-48/+1
2017-12-22x86/mm: Put MMU to hardware ASID translation in one placeDave Hansen1-11/+18
2017-12-22x86/mm: Remove hard-coded ASID limit checksDave Hansen1-2/+18
2017-12-22x86/mm: Move the CR3 construction functions to tlbflush.hDave Hansen1-0/+26
2017-12-22x86/mm: Add comments to clarify which TLB-flush functions are supposed to flush whatPeter Zijlstra1-2/+21
2017-12-22x86/mm: Remove superfluous barriersPeter Zijlstra1-7/+1
2017-12-22x86/microcode: Dont abuse the TLB-flush interfacePeter Zijlstra1-13/+6
2017-11-25x86/tlb: Disable interrupts when changing CR4Nadav Amit1-3/+8
2017-11-25x86/tlb: Refactor CR4 setting and shadow writeNadav Amit1-13/+11
2017-11-02License cleanup: add SPDX GPL-2.0 license identifier to files with no licenseGreg Kroah-Hartman1-0/+1
2017-10-18x86/mm: Remove debug/x86/tlb_defer_switch_to_init_mmAndy Lutomirski1-8/+12
2017-10-18x86/mm: Tidy up "x86/mm: Flush more aggressively in lazy TLB mode"Andy Lutomirski1-1/+6
2017-10-14x86/mm: Flush more aggressively in lazy TLB modeAndy Lutomirski1-0/+24
2017-09-06x86/mm: Reinitialize TLB state on hotplug and resumeAndy Lutomirski1-0/+2
2017-07-25x86/mm: Implement PCID based optimization: try to preserve old TLB entries using PCIDAndy Lutomirski1-2/+16
2017-07-05x86/mm: Enable CR4.PCIDE on supported systemsAndy Lutomirski1-0/+8
2017-07-05x86/mm: Rework lazy TLB mode and TLB freshness trackingAndy Lutomirski1-4/+0
2017-07-05x86/mm: Track the TLB's tlb_gen and update the flushing algorithmAndy Lutomirski1-3/+40
2017-07-05x86/mm: Give each mm TLB flush generation a unique IDAndy Lutomirski1-0/+18
2017-06-22x86/mm: Remove reset_lazy_tlbstate()Andy Lutomirski1-8/+0
2017-06-13x86/mm: Split read_cr3() into read_cr3_pa() and __read_cr3()Andy Lutomirski1-2/+2
2017-06-05x86/mm: Rework lazy TLB to track the actual loaded mmAndy Lutomirski1-2/+10
2017-06-05x86/mm: Remove the UP asm/tlbflush.h code, always use the (formerly) SMP codeAndy Lutomirski1-75/+1
2017-06-05x86/mm: Refactor flush_tlb_mm_range() to merge local and remote casesAndy Lutomirski1-1/+0
2017-06-05x86/mm: Pass flush_tlb_info to flush_tlb_others() etcAndy Lutomirski1-8/+11
2017-05-24mm, x86/mm: Make the batched unmap TLB flush API more genericAndy Lutomirski1-0/+8
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