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2014-10-29perf/x86/intel: Revert incomplete and undocumented Broadwell client supportIngo Molnar1-171/+2
2014-10-15Merge branch 'for-3.18-consistent-ops' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/percpuLinus Torvalds1-9/+9
2014-09-24perf/x86/intel: Use Broadwell cache event list for HaswellAndi Kleen1-2/+2
2014-09-24perf/x86: Add INST_RETIRED.ALL workaroundsAndi Kleen1-0/+19
2014-09-24perf/x86/intel: Add Broadwell core supportAndi Kleen1-0/+150
2014-09-24perf/x86/intel: Document all Haswell modelsAndi Kleen1-4/+4
2014-09-24perf/x86/intel: Remove incorrect model number from Haswell perfAndi Kleen1-1/+0
2014-08-26x86: Replace __get_cpu_var usesChristoph Lameter1-9/+9
2014-08-13perf/x86: Use extended offcore mask on HaswellAndi Kleen1-1/+1
2014-08-13perf/x86/intel: Update Intel modelsPeter Zijlstra1-25/+26
2014-07-16perf/x86/intel: Protect LBR and extra_regs against KVM lyingKan Liang1-1/+65
2014-07-16perf/x86/intel: Use proper dTLB-load-misses event on IvyBridgeVince Weaver1-0/+3
2014-07-02perf/x86/intel: ignore CondChgd bit to avoid false NMI handlingHATAYAMA Daisuke1-0/+9
2014-05-07perf/x86/intel: Fix Silvermont's event constraintsYan, Zheng1-1/+0
2014-02-21perf/x86: Correctly use FEATURE_PDCMPeter Zijlstra1-4/+1
2014-02-21perf, nmi: Fix unknown NMI warningMarkus Metzger1-4/+2
2013-10-04perf/x86: Suppress duplicated abort LBR recordsAndi Kleen1-0/+1
2013-10-04Merge branch 'perf/urgent' into perf/coreIngo Molnar1-0/+1
2013-09-23perf/x86/intel: Add model number for Avoton SilvermontYan, Zheng1-0/+1
2013-09-12perf/x86/intel: Clean up EVENT_ATTR_STR() muckIngo Molnar1-18/+17
2013-09-12perf/x86/intel: Clean up checkpoint-interrupt bitsPeter Zijlstra1-9/+13
2013-09-12perf/x86/intel: Add Haswell TSX event aliasesAndi Kleen1-0/+27
2013-09-12perf/x86/intel: Avoid checkpointed counters causing excessive TSX abortsAndi Kleen1-0/+37
2013-09-12perf/x86/intel: Fix Silvermont offcore masksPeter Zijlstra1-2/+2
2013-09-12perf/x86: Add constraint for IVB CYCLE_ACTIVITY:CYCLES_LDM_PENDINGStephane Eranian1-0/+1
2013-09-02perf/x86: Add Silvermont (22nm Atom) supportYan, Zheng1-0/+158
2013-09-02perf/x86: use INTEL_UEVENT_EXTRA_REG to define MSR_OFFCORE_RSP_XYan, Zheng1-9/+13
2013-08-12perf/x86: Add Haswell ULT model number used in Macbook Air and other systemsAndi Kleen1-0/+1
2013-06-26perf/x86: Fix shared register mutual exclusion enforcementStephane Eranian1-2/+0
2013-06-26perf/x86/intel: Support full width countingAndi Kleen1-0/+7
2013-06-19perf/x86/intel: Add mem-loads/stores support for HaswellAndi Kleen1-0/+10
2013-06-19perf/x86/intel: Move NMI clearing to end of PMI handlerAndi Kleen1-8/+12
2013-06-19perf/x86/intel: Add Haswell PEBS supportAndi Kleen1-2/+4
2013-06-19perf/x86/intel: Add simple Haswell PMU supportAndi Kleen1-1/+84
2013-06-19perf/x86: Only print PMU state when also WARN()'ingDave Hansen1-2/+6
2013-06-19perf/x86: Fix broken PEBS-LL support on SNB-EP/IVB-EPStephane Eranian1-1/+1
2013-05-05Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tipLinus Torvalds1-4/+9
2013-05-04perf/x86: Blacklist all MEM_*_RETIRED events for Ivy BridgePeter Zijlstra1-4/+9
2013-04-21Merge branch 'perf/urgent' into perf/coreIngo Molnar1-4/+17
2013-04-16perf/x86: Fix offcore_rsp valid mask for SNB/IVBStephane Eranian1-4/+16
2013-04-10perf/x86: Add Sandy Bridge constraints for CYCLE_ACTIVITY.*Andi Kleen1-0/+2
2013-04-01perf/x86: Add support for PEBS Precise StoreStephane Eranian1-0/+2
2013-04-01perf/x86: Export PEBS load latency threshold register to sysfsStephane Eranian1-0/+3
2013-04-01perf/x86: Add memory profiling via PEBS Load LatencyStephane Eranian1-0/+24
2013-04-01perf/x86: Add flags to event constraintsStephane Eranian1-1/+5
2013-03-18perf/x86: Add SNB/SNB-EP scheduling constraints for cycle_activity eventStephane Eranian1-0/+4
2013-02-20perf/x86: Add Intel IvyBridge event scheduling constraintsStephane Eranian1-1/+22
2013-01-24x86/perf: Add IvyBridge EP supportYouquan Song1-0/+1
2013-01-24perf/x86: Enable Intel Lincroft/Penwell/Cloverview Atom supportShuoX Liu1-1/+4
2012-10-24perf/x86: Add hardware events translations for AMD cpusJiri Olsa1-2/+9
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