aboutsummaryrefslogtreecommitdiffstats
path: root/arch/xtensa/include/asm/processor.h (follow)
AgeCommit message (Expand)AuthorFilesLines
2022-10-12Merge tag 'mm-nonmm-stable-2022-10-11' of git://git.kernel.org/pub/scm/linux/kernel/git/akpm/mmLinus Torvalds1-3/+0
2022-09-13xtensa: add FDPIC and static PIE support for noMMUMax Filippov1-0/+3
2022-09-11kernel: exit: cleanup release_thread()Kefeng Wang1-3/+0
2022-05-01xtensa: add xtensa_xsr macroMax Filippov1-0/+7
2022-03-25Merge tag 'xtensa-20220325' of https://github.com/jcmvbkbc/linux-xtensaLinus Torvalds1-7/+3
2022-03-20xtensa: fix xtensa_wsr always writing 0Max Filippov1-2/+2
2022-03-19xtensa: merge stack alignment definitionsMax Filippov1-5/+1
2022-02-25uaccess: remove CONFIG_SET_FSArnd Bergmann1-7/+0
2021-11-06Merge tag 'xtensa-20211105' of git://github.com/jcmvbkbc/linux-xtensaLinus Torvalds1-6/+26
2021-10-18xtensa: definitions for call0 ABIMax Filippov1-6/+26
2021-10-15sched: Add wrapper for get_wchan() to keep task blockedKees Cook1-1/+1
2020-02-01xtensa: clean up optional XCHAL_* definitionsMax Filippov1-4/+0
2019-11-29xtensa: rearrange syscall tracingMax Filippov1-1/+2
2019-09-01xtensa: add support for call0 ABI in userspaceMax Filippov1-1/+8
2019-09-01xtensa: clean up PS_WOE_BIT usageMax Filippov1-1/+1
2019-05-06xtensa: replace variant/core.h with asm/core.hMax Filippov1-1/+1
2019-04-03xtensa: fix initialization of pt_regs::syscall in start_threadMax Filippov1-9/+12
2018-12-04xtensa: clean up WSR*/RSR*/get_sr/set_srMax Filippov1-5/+13
2018-11-16Merge tag 'xtensa-20181115' of git://github.com/jcmvbkbc/linux-xtensaLinus Torvalds1-1/+5
2018-11-05xtensa: make sure bFLT stack is 16 byte alignedMax Filippov1-1/+5
2018-10-31treewide: remove current_text_addrNick Desaulniers1-8/+0
2018-08-20xtensa: drop unneeded platform/hardware.h headersMax Filippov1-1/+0
2017-09-22arch: remove unused *_segments() macros/functionsTobias Klauser1-5/+0
2017-06-28arch: remove unused macro/function thread_saved_pc()Tobias Klauser1-2/+0
2017-05-01xtensa: clean up access to spilled registers locationsMax Filippov1-0/+15
2016-11-17locking/core: Provide common cpu_relax_yield() definitionChristian Borntraeger1-1/+0
2016-11-16locking/core, arch: Remove cpu_relax_lowlatency()Christian Borntraeger1-1/+0
2016-11-16locking/core: Introduce cpu_relax_yield()Christian Borntraeger1-0/+1
2016-07-24xtensa: minimize use of PLATFORM_DEFAULT_MEM_{ADDR,SIZE}Max Filippov1-1/+1
2016-03-11xtensa: support hardware breakpoints/watchpointsMax Filippov1-5/+4
2016-01-11xtensa: make fake NMI configurableMax Filippov1-7/+5
2015-08-17xtensa: implement fake NMIMax Filippov1-2/+29
2014-07-17arch, locking: Ciao arch_mutex_cpu_relax()Davidlohr Bueso1-0/+1
2014-01-14xtensa: add MX irqchipMax Filippov1-0/+20
2013-02-23xtensa: dispatch medium-priority interruptsMarc Gauthier1-2/+2
2012-12-18xtensa: clean up files to make them code-style compliantChris Zankel1-5/+5
2012-10-25xtensa: switch to generic kernel_thread()Max Filippov1-3/+1
2012-05-16fork: move the real prepare_to_copy() users to arch_dup_task_struct()Suresh Siddha1-3/+0
2010-05-02xtensa: Shuffle include statements to fix linker scriptChris Zankel1-1/+0
2009-04-02xtensa: nommu supportJohannes Weiner1-0/+6
2009-04-02xtensa: enforce slab alignment to maximum register widthOskar Schirmer1-0/+2
2008-11-06xtensa: move headers files to arch/xtensa/includeChris Zankel1-0/+193
Copyright © 1996 – 2023 Jason A. Donenfeld. All Rights Reverse Engineered.