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2022-09-19arm64: dts: renesas: white-hawk-cpu: Add push switchesGeert Uytterhoeven1-0/+37
Describe the three Push Switches on the White Hawk CPU board, so they can be used for user input. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/e18d0d5087a514db611295f5d1e13c950cf7dae7.1662715538.git.geert+renesas@glider.be
2022-09-19arm64: dts: renesas: white-hawk-cpu: Add GP LEDsGeert Uytterhoeven1-0/+28
Describe the three General Purpose LEDs on the White Hawk CPU board, so they can be used as indicator LEDs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/007acd941ef925057f1f9b925ed4e339dbd29a74.1662715538.git.geert+renesas@glider.be
2022-09-19arm64: dts: renesas: r8a779g0: Add GPIO nodesGeert Uytterhoeven1-0/+135
Add device nodes for the General Purpose Input/Output (GPIO) blocks on the Renesas R-Car V4H (R8A779G0) SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/81176a5e12a5828cdcdd4b107d0b2e5970232c31.1662715538.git.geert+renesas@glider.be
2022-09-19arm64: dts: apple: Add WiFi module and antenna propertiesHector Martin6-0/+22
Add the new module-instance/antenna-sku properties required to select WiFi firmwares properly to all board device trees. Signed-off-by: Hector Martin <marcan@marcan.st> Reviewed-by: Mark Kettenis <kettenis@openbsd.org> Acked-by: Hector Martin <marcan@marcan.st> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/E1oZDoI-0077b3-Dd@rmk-PC.armlinux.org.uk
2022-09-19Merge branch kvm-arm64/single-step-async-exception into kvmarm-master/nextMarc Zyngier4-2/+45
* kvm-arm64/single-step-async-exception: : . : Single-step fixes from Reiji Watanabe: : : "This series fixes two bugs of single-step execution enabled by : userspace, and add a test case for KVM_GUESTDBG_SINGLESTEP to : the debug-exception test to verify the single-step behavior." : . KVM: arm64: selftests: Add a test case for KVM_GUESTDBG_SINGLESTEP KVM: arm64: selftests: Refactor debug-exceptions to make it amenable to new test cases KVM: arm64: Clear PSTATE.SS when the Software Step state was Active-pending KVM: arm64: Preserve PSTATE.SS for the guest while single-step is enabled Signed-off-by: Marc Zyngier <maz@kernel.org>
2022-09-19KVM: arm64: Clear PSTATE.SS when the Software Step state was Active-pendingReiji Watanabe4-2/+32
While userspace enables single-step, if the Software Step state at the last guest exit was "Active-pending", clear PSTATE.SS on guest entry to restore the state. Currently, KVM sets PSTATE.SS to 1 on every guest entry while userspace enables single-step for the vCPU (with KVM_GUESTDBG_SINGLESTEP). It means KVM always makes the vCPU's Software Step state "Active-not-pending" on the guest entry, which lets the VCPU perform single-step (then Software Step exception is taken). This could cause extra single-step (without returning to userspace) if the Software Step state at the last guest exit was "Active-pending" (i.e. the last exit was triggered by an asynchronous exception after the single-step is performed, but before the Software Step exception is taken. See "Figure D2-3 Software step state machine" and "D2.12.7 Behavior in the active-pending state" in ARM DDI 0487I.a for more info about this behavior). Fix this by clearing PSTATE.SS on guest entry if the Software Step state at the last exit was "Active-pending" so that KVM restore the state (and the exception is taken before further single-step is performed). Fixes: 337b99bf7edf ("KVM: arm64: guest debug, add support for single-step") Signed-off-by: Reiji Watanabe <reijiw@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220917010600.532642-3-reijiw@google.com
2022-09-19KVM: arm64: Preserve PSTATE.SS for the guest while single-step is enabledReiji Watanabe2-0/+13
Preserve the PSTATE.SS value for the guest while userspace enables single-step (i.e. while KVM manipulates the PSTATE.SS) for the vCPU. Currently, while userspace enables single-step for the vCPU (with KVM_GUESTDBG_SINGLESTEP), KVM sets PSTATE.SS to 1 on every guest entry, not saving its original value. When userspace disables single-step, KVM doesn't restore the original value for the subsequent guest entry (use the current value instead). Exception return instructions copy PSTATE.SS from SPSR_ELx.SS only in certain cases when single-step is enabled (and set it to 0 in other cases). So, the value matters only when the guest enables single-step (and when the guest's Software step state isn't affected by single-step enabled by userspace, practically), though. Fix this by preserving the original PSTATE.SS value while userspace enables single-step, and restoring the value once it is disabled. This fix modifies the behavior of GET_ONE_REG/SET_ONE_REG for the PSTATE.SS while single-step is enabled by userspace. Presently, GET_ONE_REG/SET_ONE_REG gets/sets the current PSTATE.SS value, which KVM will override on the next guest entry (i.e. the value userspace gets/sets is not used for the next guest entry). With this patch, GET_ONE_REG/SET_ONE_REG will get/set the guest's preserved value, which KVM will preserve and try to restore after single-step is disabled. Fixes: 337b99bf7edf ("KVM: arm64: guest debug, add support for single-step") Signed-off-by: Reiji Watanabe <reijiw@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220917010600.532642-2-reijiw@google.com
2022-09-19Merge remote-tracking branch 'arm64/for-next/sysreg' into kvmarm-master/nextMarc Zyngier27-484/+768
Merge arm64/for-next/sysreg in order to avoid upstream conflicts due to the never ending sysreg repainting... Signed-off-by: Marc Zyngier <maz@kernel.org>
2022-09-19m68k: defconfig: Update defconfigs for v6.0-rc2Geert Uytterhoeven12-24/+24
- Drop CONFIG_NF_CONNTRACK_PROCFS=n (no longer auto-enabled since commit aa5762c34213aba7 ("netfilter: conntrack: NF_CONNTRACK_PROCFS should no longer default to y")), - Enable modular build of the new HCTR2 and ARIA crypto algorithms, - Drop CONFIG_CRYPTO_BLAKE2S=m (removed in commit 2d16803c562ecc64 ("crypto blake2s - remove shash module")). Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Link: https://lore.kernel.org/r/01a6abf7bc23a478d6a6c6801c6812ae96714620.1660559393.git.geert@linux-m68k.org Link: https://lore.kernel.org/r/1fbe623e5d69bdce0352445c06e1b2c9fb8d123e.1661767119.git.geert@linux-m68k.org
2022-09-19m68k: Allow kexec on M68KCLASSIC with MMU enabled onlyGreg Ungerer1-1/+1
None of the no-MMU CPU types (classic or ColdFire) or ColdFire with MMU enabled have support for kexec yet, so the configuration as it stands is not quite right, and it will fail to compile on them. Make CONFIG_KEXEC depend on both CONFIG_M68KCLASSIC and CONFIG_MMU. Signed-off-by: Greg Ungerer <gerg@linux-m68k.org> Link: https://lore.kernel.org/r/20220831012539.3416470-1-gerg@linux-m68k.org Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2022-09-19m68k: Move from strlcpy with unused retval to strscpyWolfram Sang1-1/+1
Follow the advice of the below link and prefer 'strscpy' in this subsystem. Conversion is 1:1 because the return value is not used. Generated by a coccinelle script. Link: https://lore.kernel.org/r/CAHk-=wgfRnXz0W3D37d01q3JFkr_i_uTL=V6A6G1oUZcprmknw@mail.gmail.com/ Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20220818205941.6240-1-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2022-09-18arm64: dts: renesas: white-hawk: Add Ethernet sub-boardGeert Uytterhoeven2-0/+17
Add a DTS file for the R-Car V4H White Hawk RAVB/Ethernet(1000Base-T1) sub-board (RTP8A779G0ASKB0SE0SA000), and include it from the main r8a779g0-white-hawk.dts. For now its contents are limited to the Board ID EEPROM. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/991600919513dd05a9a7d9c170c6924baf14d1a2.1662715538.git.geert+renesas@glider.be
2022-09-18arm64: dts: renesas: white-hawk: Add CSI/DSI sub-boardGeert Uytterhoeven2-0/+16
Add a DTS file for the R-Car V4H White Hawk CSI/DSI sub-board (RTP8A779G0ASKB0SC0SA000), and include it from the main r8a779g0-white-hawk.dts. For now its contents are limited to the Board ID EEPROM. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/265f7782743c539c57906e8207785f8b0d80d5d0.1662715538.git.geert+renesas@glider.be
2022-09-18arm64: dts: renesas: white-hawk: Add I2C0 and EEPROMsGeert Uytterhoeven2-0/+29
Enable the I2C0 bus on the White Hawk CPU board, and describe the I2C EEPROMs present on the White Hawk CPU and BreakOut boards. Based on a larger patch in the BSP by Takeshi Kihara. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/d01cada6f2d3e44dd6cb26cfa8e4ce6382f1fbff.1662715538.git.geert+renesas@glider.be
2022-09-18arm64: dts: renesas: r8a779g0: Add I2C nodesGeert Uytterhoeven1-0/+84
Add device nodes for the I2C Bus Interfaces on the Renesas R-Car V4H (R8A779G0) SoC. Extracted from a larger patch in the BSP by Takeshi Kihara. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/272fd18fed2d7addfbdb7945ae2134988a7c3a7e.1662715538.git.geert+renesas@glider.be
2022-09-18arm64: dts: renesas: white-hawk-cpu: Add serial port pin controlGeert Uytterhoeven1-0/+15
Complete the description of the serial console and the external serial clock by adding pin control. Based on larger patch in the BSP by Takeshi Kihara. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/74c862ef6e46b4af398d9b371ff38fae17b3db05.1662715538.git.geert+renesas@glider.be
2022-09-18arm64: dts: renesas: r8a779g0: Add pinctrl device nodeGeert Uytterhoeven1-0/+9
Add a device node for the Pin Function Controller on the Renesas R-Car V4H (R8A779G0) SoC. Based on a larger patch in the BSP by Takeshi Kihara. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/ecddcadd2fad46b1cf4c9be3ec750f360b9730e4.1662715538.git.geert+renesas@glider.be
2022-09-18arm64: dts: renesas: white-hawk-cpu: Enable watchdog timerGeert Uytterhoeven1-0/+5
Enable the watchdog timer on the White Hawk CPU board. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/77a0e29d965032115de1f07ceecb2d5d07db74eb.1662715538.git.geert+renesas@glider.be
2022-09-18arm64: dts: renesas: r8a779g0: Add RWDT nodeGeert Uytterhoeven1-0/+11
Add a device node for the RCLK Watchdog Timer (RWDT) on the Renesas R-Car V4H (R8A779G0) SoC. Based on a patch in the BSP by Thanh Quan. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/187904c279be6654ea3deb11b7250b64dd18c3b5.1662715538.git.geert+renesas@glider.be
2022-09-18ARM: shmobile: Drop selecting SOC_BUSLad Prabhakar1-1/+0
Don't automatically select the SOC_BUS config option as we already have automatically selected it as part of the SOC_RENESAS config option [0] as renesas-soc.c [1] uses the APIs provided by SOC_BUS config option. [0] drivers/soc/renesas/Kconfig [1] drivers/soc/renesas/renesas-soc.c Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220915233852.415407-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-09-18arm64: renesas: Drop selecting SOC_BUSLad Prabhakar1-1/+0
Don't automatically select the SOC_BUS config option as we already have automatically selected it as part of the SOC_RENESAS config option [0] as renesas-soc.c [1] uses the APIs provided by SOC_BUS config option. [0] drivers/soc/renesas/Kconfig [1] drivers/soc/renesas/renesas-soc.c Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220915233640.415305-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-09-17Merge tag 'at91-dt-6.1-2' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/dtArnd Bergmann21-4/+413
AT91 DT for v6.1 #2 It contains: - new SAMA5D3 based board, namely SAMA5D3-EDS - adjustments to pass the DT binding validations - disable AES on some LAN966 based boards as they are reserverd by secure OS * tag 'at91-dt-6.1-2' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: spi: dt-bindings: atmel,at91rm9200-spi: Add DMA related properties ARM: dts: at91: Add `atmel,usart-mode` required property to serial nodes ARM: dts: at91: sam9x60ek: Add DBGU compatibles to uart1 ARM: dts: at91: sama7g5: Swap rx and tx for spi11 dts: arm: at91: Add SAMA5D3-EDS Board dt-bindings: arm: at91: Add info on SAMA5D3-EDS ARM: dts: lan966x: disable aes Link: https://lore.kernel.org/r/20220916105407.1287452-1-claudiu.beznea@microchip.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-17efi/libstub: use EFI provided memcpy/memset routinesArd Biesheuvel3-25/+0
The stub is used in different execution environments, but on arm64, RISC-V and LoongArch, we still use the core kernel's implementation of memcpy and memset, as they are just a branch instruction away, and can generally be reused even from code such as the EFI stub that runs in a completely different address space. KAsan complicates this slightly, resulting in the need for some hacks to expose the uninstrumented, __ prefixed versions as the normal ones, as the latter are instrumented to include the KAsan checks, which only work in the core kernel. Unfortunately, #define'ing memcpy to __memcpy when building C code does not guarantee that no explicit memcpy() calls will be emitted. And with the upcoming zboot support, which consists of a separate binary which therefore needs its own implementation of memcpy/memset anyway, it's better to provide one explicitly instead of linking to the existing one. Given that EFI exposes implementations of memmove() and memset() via the boot services table, let's wire those up in the appropriate way, and drop the references to the core kernel ones. Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
2022-09-17RISC-V: Avoid coupling the T-Head CMOs and ZicbomPalmer Dabbelt1-1/+5
We could make the T-Head CMOs depend on a new-enough assembler to have Zicbom, but it's not strictly necessary because the T-Head CMOs circumvent the assembler. Fixes: 8f7e001e0325 ("RISC-V: Clean up the Zicbom block size probing") Reported-by: kernel test robot <lkp@intel.com> Reported-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20220915170900.22685-1-palmer@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-09-17riscv: fix a nasty sigreturn bug...Al Viro1-0/+2
riscv has an equivalent of arm bug fixed by 653d48b22166 ("arm: fix really nasty sigreturn bug"); if signal gets caught by an interrupt that hits when we have the right value in a0 (-513), *and* another signal gets delivered upon sigreturn() (e.g. included into the blocked mask for the first signal and posted while the handler had been running), the syscall restart logics will see regs->cause equal to EXC_SYSCALL (we are in a syscall, after all) and a0 already restored to its original value (-513, which happens to be -ERESTARTNOINTR) and assume that we need to apply the usual syscall restart logics. Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Fixes: e2c0cdfba7f6 ("RISC-V: User-facing API") Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/YxJEiSq%2FCGaL6Gm9@ZenIV/ Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-09-17riscv: make t-head erratas depend on MMUHeiko Stuebner1-2/+2
Both basic extensions of SVPBMT and ZICBOM depend on CONFIG_MMU. Make the T-Head errata implementations of the similar functionality also depend on it to prevent build errors. Fixes: a35707c3d850 ("riscv: add memory-type errata for T-Head") Fixes: d20ec7529236 ("riscv: implement cache-management errata for T-Head SoCs") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Guo Ren <guoren@kernel.org> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20220907154932.2858518-1-heiko@sntech.de Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-09-17riscv: fix RISCV_ISA_SVPBMT kconfig dependency warningRandy Dunlap1-0/+1
RISCV_ISA_SVPBMT selects RISCV_ALTERNATIVE which depends on !XIP_KERNEL. Therefore RISCV_ISA_SVPBMT should also depend on !XIP_KERNEL so quieten this kconfig warning: WARNING: unmet direct dependencies detected for RISCV_ALTERNATIVE Depends on [n]: !XIP_KERNEL [=y] Selected by [y]: - RISCV_ISA_SVPBMT [=y] && 64BIT [=y] && MMU [=y] Fixes: ff689fd21cb1 ("riscv: add RISC-V Svpbmt extension support") Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Cc: stable@vger.kernel.org Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20220709014929.14221-1-rdunlap@infradead.org/ Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-09-17arm64: dts: ls1046a-qds: Modify the qspi flash frequencyPankaj Bansal1-1/+1
The qspi flash in ls1046a QDS board can operate at 50MHz frequency. Therefore, update the maximum supported freq in dts file. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17arm64: dts: ls1046a-qds: add mmio based mdio-mux nodes for FPGALi Yang1-2/+153
There is mmio based mdio mux function in the FPGA device on ls1046a-qds board. Add the mmio based mdio-mux nodes to ls1043a-qds boards and add simple-mfd as a compatbile for the FPGA node to reflect the multi-function nature of it. Signed-off-by: Camelia Groza <camelia.groza@nxp.com> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17arm64: dts: ls1046a: add gpios based i2c recovery informationLi Yang1-4/+8
Add scl-gpios property for i2c recovery and add SoC specific compatible string for SoC specific fixup. Signed-off-by: Zhang Ying <ying.zhang22455@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17arm64: dts: ls1046a: use a pseudo-bus to constrain usb and sata dma sizeLaurentiu Tudor1-38/+46
Wrap the usb and sata controllers in an intermediate simple-bus and use it to constrain the dma address size of these usb controllers to the 40 bits that they generate toward the interconnect. This is required because the SoC uses 48 bits address sizes and this mismatch would lead to smmu context faults because the usb generates 40-bit addresses while the smmu page tables are populated with 48-bit wide addresses. Suggested-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17arm64: dts: ls1046a: make dma-coherent global to the SoCLi Yang1-4/+1
These SoCs are really completely dma coherent in their entirety so add the dma-coherent property at the soc level in the device tree and drop the instances where it's specifically added to a few select devices. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17arm64: dts: ls1046a: add missing dma ranges propertyLaurentiu Tudor1-0/+1
These chips have a 48-bit address size so make sure that the dma-ranges reflects this. Otherwise the linux kernel's dma sub-system will set the default dma masks to full 64-bit, badly breaking dmas. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17arm64: dts: ls1046a: Add big-endian property for PCIe nodesHou Zhiqiang1-0/+3
Add the big-endian property for LS1046A PCIe RC nodes. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17arm64: dts: ls1046a: Add the PME interrupt and big-endian to PCIe EP nodesXiaowei Bao1-0/+9
Add the PME interrupt porperty and big-endian property in PCIe EP nodes. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17arm64: dts: ls1046a: Enable usb3-lpm-capable for usb3 nodeLi Yang1-0/+3
Enable USB3 HW LPM feature for ls1046a. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17arm64: dts: ls1043a-rdb: add pcf85263 rtc nodeLi Yang1-0/+10
Add the missing node for rtc device under i2c and fix style problems at the same time. Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17arm64: dts: ls1043a-qds: add mmio based mdio-mux supportLi Yang1-2/+171
There is mmio based mdio mux function in the FPGA device on ls1043a-qds board. Add the mmio based mdio-mux nodes to ls1043a-qds boards and add simple-mfd as a compatbile for the FPGA node to reflect the multi-function nature of it. Also connect the ethernet interfaces to these phy interfaces. Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17arm64: dts: ls1043a: use a pseudo-bus to constrain usb and sata dma sizeLaurentiu Tudor1-42/+50
Wrap the usb and sata controllers in an intermediate simple-bus and use it to constrain the dma address size of these usb controllers to the 40 bits that they generate toward the interconnect. This is required because the SoC uses 48 bits address sizes and this mismatch would lead to smmu context faults because the usb generates 40-bit addresses while the smmu page tables are populated with 48-bit wide addresses. Suggested-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17arm64: dts: ls1043a: add gpio based i2c recovery informationLi Yang1-4/+8
Add scl-gpios property for i2c recovery and add SoC specific compatible string for SoC specific fixup. Signed-off-by: Zhang Ying <ying.zhang22455@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17arm64: dts: ls1043a: make dma-coherent global to the SoCLi Yang1-3/+1
ls1043a is really completely dma coherent in their entirety so add the dma-coherent property at the soc level in the device tree and drop the instances where it's specifically added to a few select devices. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17arm64: dts: ls1043a: add missing dma ranges propertyLaurentiu Tudor1-0/+1
ls1043a has a 48-bit address size so make sure that the dma-ranges reflects this. Otherwise the linux kernel's dma sub-system will set the default dma masks to full 64-bit, badly breaking dmas. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17arm64: dts: ls1043a: Add big-endian property for PCIe nodesHou Zhiqiang1-0/+3
Add the big-endian property for LS1043A PCIe nodes for accessing PEX_LUT and PF register block. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17arm64: dts: ls1043a: Add SCFG phandle for PCIe nodesHou Zhiqiang1-0/+3
The LS1043A PCIe controller has some control registers in SCFG block, so add the SCFG phandle for each PCIe controller node. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17arm64: dts: ls1043a: use pcie aer/pme interruptsLi Yang1-9/+9
After the binding has been updated to include more specific interrupt definition, update the dts to use the more specific interrupt names. Signed-off-by: Po Liu <po.liu@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17arm64: dts: ls1043a: Enable usb3-lpm-capable for usb3 nodeLi Yang1-0/+3
Enable USB3 HW LPM feature for ls1043a. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17arm64: dts: ls1043a: fix the wrong size of dcfg spaceLi Yang1-1/+1
The size of the block should be 0x1000 instead of 0x10000. Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17arm64: dts: ls208x: remove NXP Erratum A008585 from LS2088A.Pankaj Bansal2-2/+5
NXP Erratum A008585 affects A57 core cluster used in LS2085 rev1. However this problem has been fixed in A72 core cluster used in LS2088. Therefore remove the erratum from LS2088A. Keeping it only in LS2085. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by: Sandeep Malik <sandeep.malik@nxp.com> Acked-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17arm64: dts: ls208xa-rdb: fix errata E-00013Biwen Li1-0/+2
Specify a channel zero in idle state to avoid enterring tri-stated state for PCA9547. Some information about E-00013: - Description: I2C1 and I2C3 buses are missing pull-up. - Impact: When the PCA954x device is tri-stated, the I2C bus will float. This makes the I2C bus and its associated downstream devices inaccessible. - Hardware fix: Populate resistors R189 and R190 for I2C1 and resistors R228 and R229 for I2C3. - Software fix: Remove the tri-state option from the PCA954x driver(PCA954x always on enable status, specify a channel zero in dts to fix the errata E-00013). Signed-off-by: Biwen Li <biwen.li@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17arm64: dts: ls2081a-rdb: Add DTS for NXP LS2081ARDBPriyanka Jain2-0/+133
This patch adds support for NXP LS2081ARDB board which has LS2081A SoC. LS2081A SoC is 40-pin derivative of LS2088A SoC. From functional perspective both are same. Hence, LS2088a SoC dtsi file is included from LS2081ARDB dts. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Tao Yang <b31903@freescale.com> Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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