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2021-12-15ARM: tegra: Add device-tree for ASUS Transformer EeePad TF101Nikola Milosavljevic3-1/+1282
Add device-tree for Tegra20-based ASUS Transformer EeePad TF101. Link: https://wiki.postmarketos.org/wiki/ASUS_Eee_Pad_Transformer_(asus-tf101) Co-developed-by: David Heidelberg <david@ixit.cz> Signed-off-by: David Heidelberg <david@ixit.cz> Co-developed-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Co-developed-by: Antoni Aloy Torrens <aaloytorrens@gmail.com> Signed-off-by: Antoni Aloy Torrens <aaloytorrens@gmail.com> Signed-off-by: Nikola Milosavljevic <mnidza@outlook.com> Co-developed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> [treding@nvidia.com: cosmetic fixups] Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-15ARM: tegra: Avoid phandle indirection on OuyaThierry Reding1-3934/+4202
Move the default state pinmux definition into the pinmux node. There's no need for the indirection via the phandle. Note that the phandle indirection is kept for the EMC operating performance point tables because they reference nodes that are defined in an external file. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-15ARM: tegra: Fix I2C mux reset GPIO reference on CardhuThierry Reding1-1/+1
Use the correct "reset-gpios" property for the I2C mux reset GPIO reference instead of the deprecated "reset-gpio" property. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-15ARM: tegra: Fix SLINK compatible string on Tegra30Thierry Reding1-6/+6
The SLINK controller found on Tegra30 is not compatible with its predecessor found on Tegra20. Drop the fallback compatible string. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-15ARM: tegra: Remove stray #reset-cells propertyThierry Reding1-1/+0
The Ouya board specifies the #reset-cells property for the GPIO controller. Since the GPIO controller doesn't provide reset controls this is not needed, so they can be dropped. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-15ARM: tegra: nexus7: Drop clock-frequency from NFC nodeDavid Heidelberg2-3/+0
The clock-frequency property was never used and is deprecated now. Remove it from Nexus 7 device-tree. Signed-off-by: David Heidelberg <david@ixit.cz> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-15ARM: tegra: Remove unsupported properties on ApalisThierry Reding3-9/+0
The +V1.2_VDD_CORE regulator on Apalis and Colibri boards uses the unsupported ti,vsel{0,1}-state-low properties. It turns out that these are in fact the default and can be overridden by ti,vsel{0,1}-state-high properties if needed. Drop them since they are not needed. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-15ARM: tegra: Use correct vendor prefix for InvensenseThierry Reding1-1/+1
The correct vendor prefix for Invensense is "invensense," rather than "invn,". Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-15ARM: tegra: Add dummy backlight power suppliesThierry Reding2-0/+6
The Medcom Wide and PAZ00 boards don't specify the power supply for the backlight, which means that the Linux driver will provide a dummy one. Wire up an explicit dummy to also make the DT schema validation succeed. Unfortunately I don't have access to the schematics for the Medcom Wide, so I don't know if a more accurate description is possible. The AC100 (PAZ00) schematics from here: https://www.s-manuals.com/pdf/motherboard/compal/compal_la-6352p_r1.0a_schematics.pdf aren't entirely clear which one of the supplies powers backlight, but the panel supply is probably close enough. Based on work by David Heidelberg <david@ixit.cz>. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-15ARM: tegra: Remove PHY reset GPIO references from USB controller nodeThierry Reding5-10/+0
The PHY reset GPIO references belong in the USB PHY nodes, where they already exist. There is no need to keep them in the USB controller's device tree node as well. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-15ARM: tegra: Add compatible string for built-in ASIX on Colibri boardsThierry Reding2-0/+2
The device tree node for the built-in ASIX Ethernet device on Colibri boards needs a compatible string in order to pass DT schema validation. Add the USB VID,PID compatible string as required by the DT schema for USB devices. Reviewed-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-15ARM: config: multi v7: Enable display drivers used by Tegra devicesDmitry Osipenko1-0/+5
Enable display-related drivers used by various Tegra-based tablets. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-15ARM: tegra_defconfig: Enable drivers wanted by Acer Chromebooks and ASUS tabletsDmitry Osipenko1-0/+12
Enable charger, touchpad and EC drivers found on Acer Tegra124 (Nyan) Chromebooks, display bridge found on ASUS TF700T and audio codecs found on ASUS tablets. Suggested-by: Thomas Graichen <thomas.graichen@gmail.com> # Nyan options Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-15x86/xen: Use correct #ifdef guard for xen_initdom_restore_msi()Arnd Bergmann1-1/+1
The #ifdef check around the definition doesn't match the one around the declaration, leading to a link failure when CONFIG_XEN_DOM0 is enabled but CONFIG_XEN_PV_DOM0 is not: x86_64-linux-ld: arch/x86/kernel/apic/msi.o: in function `arch_restore_msi_irqs': msi.c:(.text+0x29a): undefined reference to `xen_initdom_restore_msi' Change the declaration to use the same check that was already present around the function definition. Fixes: ae72f3156729 ("PCI/MSI: Make arch_restore_msi_irqs() less horrible.") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/20211215140209.451379-1-arnd@kernel.org
2021-12-15Merge tag 'asahi-soc-dt-5.17-v2' of https://github.com/AsahiLinux/linux into arm/dtArnd Bergmann2-40/+47
Apple SoC DT updates for 5.17, round 2: - Various cleanups (removing useless props, sorting nodes, renaming things) - Add PMGR min-state binding & props (see PMGR pull for driver change) - Initial compatibles for t600x machines (M1 Pro/Max). This covers the bindings that just need compatible bumps & minor tweaks, no driver changes. - Add watchdog node (driver not merged yet, hopefully will be; binding went in the previous pull) - Add missing power-domains property to the mailbox binding * tag 'asahi-soc-dt-5.17-v2' of https://github.com/AsahiLinux/linux: dt-bindings: mailbox: apple,mailbox: Add power-domains property arm64: dts: apple: t8103: Sort nodes by address arm64: dts: apple: t8103: Rename clk24 to clkref arm64: dts: apple: t8103: Add watchdog node dt-bindings: pinctrl: apple,pinctrl: Add apple,t6000-pinctrl compatible dt-bindings: pci: apple,pcie: Add t6000 support dt-bindings: i2c: apple,i2c: Add apple,t6000-i2c compatible dt-bindings: arm: apple: Add t6000/t6001 MacBook Pro 14/16" compatibles arm64: dts: apple: t8103: Add apple,min-state to DCP PMGR nodes dt-bindings: power: apple,pmgr-pwrstate: Add apple,min-state prop arm64: dts: apple: t8103: Remove PCIe max-link-speed properties Link: https://lore.kernel.org/r/a24faafd-f2ae-c3a7-5327-b27da7d9e34b@marcan.st Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-12-15Merge tag 'stm32-dt-for-v5.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into arm/dtArnd Bergmann7-17/+273
STM32 DT for v5.17, round 1 Highlights: ---------- -MCU: - fix ili9341 for dtbs_check warnings on stm32f429 disco. - MPU: - ST boards: - tune HS USB phys on stm32mp15 EV1 and DKx boards. - add pull-up on USART3/UART7 RX pins on STM32MP15 DKx boards. - use correct pinctrl setting for STUSB1600 on STM32MP15 DK boards. - ENGICAM: - enable LVDS pannel on i.Core STM32MP1 EDIMM2.2. - add "i.Core STM32MP1 C.TOUCH 2.0 10.1" OF" support: EDIMM compliant general purpose carrier board with ETH 10/100, WIFI/BT, CAN, ... * tag 'stm32-dt-for-v5.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: ARM: dts: stm32: Add Engicam i.Core STM32MP1 C.TOUCH 2.0 10.1" OF dt-bindings: arm: stm32: Add Engicam i.Core STM32MP1 C.TOUCH 2.0 10.1" OF ARM: dts: stm32: Enable LVDS panel on i.Core STM32MP1 EDIMM2.2 ARM: dts: stm32: fix stusb1600 pinctrl used on stm32mp157c-dk ARM: dts: stm32: tune the HS USB PHYs on stm32mp157c-ev1 ARM: dts: stm32: tune the HS USB PHYs on stm32mp15xx-dkx ARM: dts: stm32: clean uart4_idle_pins_a node for stm32mp15 ARM: dts: stm32: add pull-up to USART3 and UART7 RX pins on STM32MP15 DKx boards ARM: dts: stm32: fix dtbs_check warning on ili9341 dts binding on stm32f429 disco Link: https://lore.kernel.org/r/dfe942db-5af7-bb82-22b6-3bd866c9017d@foss.st.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-12-15Merge branch kvm-arm64/pkvm-cleanups-5.17 into kvmarm-master/nextMarc Zyngier7-6/+19
* kvm-arm64/pkvm-cleanups-5.17: : . : pKVM cleanups from Quentin Perret: : : This series is a collection of various fixes and cleanups for KVM/arm64 : when running in nVHE protected mode. The first two patches are real : fixes/improvements, the following two are minor cleanups, and the last : two help satisfy my paranoia so they're certainly optional. : . KVM: arm64: pkvm: Make kvm_host_owns_hyp_mappings() robust to VHE KVM: arm64: pkvm: Stub io map functions KVM: arm64: Make __io_map_base static KVM: arm64: Make the hyp memory pool static KVM: arm64: pkvm: Disable GICv2 support KVM: arm64: pkvm: Fix hyp_pool max order Signed-off-by: Marc Zyngier <maz@kernel.org>
2021-12-15KVM: arm64: pkvm: Make kvm_host_owns_hyp_mappings() robust to VHEQuentin Perret1-0/+3
The kvm_host_owns_hyp_mappings() function should return true if and only if the host kernel is responsible for creating the hypervisor stage-1 mappings. That is only possible in standard non-VHE mode, or during boot in protected nVHE mode. But either way, none of this makes sense in VHE, so make sure to catch this case as well, hence making the function return sensible values in any context (VHE or not). Suggested-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Quentin Perret <qperret@google.com> Acked-by: Will Deacon <will@kernel.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20211208152300.2478542-7-qperret@google.com
2021-12-15KVM: arm64: pkvm: Stub io map functionsQuentin Perret1-0/+6
Now that GICv2 is disabled in nVHE protected mode there should be no other reason for the host to use create_hyp_io_mappings() or kvm_phys_addr_ioremap(). Add sanity checks to make sure that assumption remains true looking forward. Signed-off-by: Quentin Perret <qperret@google.com> Acked-by: Will Deacon <will@kernel.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20211208152300.2478542-6-qperret@google.com
2021-12-15KVM: arm64: Make __io_map_base staticQuentin Perret2-2/+2
The __io_map_base variable is used at EL2 to track the end of the hypervisor's "private" VA range in nVHE protected mode. However it doesn't need to be used outside of mm.c, so let's make it static to keep all the hyp VA allocation logic in one place. Signed-off-by: Quentin Perret <qperret@google.com> Acked-by: Will Deacon <will@kernel.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20211208152300.2478542-5-qperret@google.com
2021-12-15KVM: arm64: Make the hyp memory pool staticQuentin Perret2-2/+1
The hyp memory pool struct is sized to fit exactly the needs of the hypervisor stage-1 page-table allocator, so it is important it is not used for anything else. As it is currently used only from setup.c, reduce its visibility by marking it static. Signed-off-by: Quentin Perret <qperret@google.com> Reviewed-by: Andrew Walbran <qwandor@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20211208152300.2478542-4-qperret@google.com
2021-12-15KVM: arm64: pkvm: Disable GICv2 supportQuentin Perret2-1/+6
GICv2 requires having device mappings in guests and the hypervisor, which is incompatible with the current pKVM EL2 page ownership model which only covers memory. While it would be desirable to support pKVM with GICv2, this will require a lot more work, so let's make the current assumption clear until then. Co-developed-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Quentin Perret <qperret@google.com> Acked-by: Will Deacon <will@kernel.org> Link: https://lore.kernel.org/r/20211208152300.2478542-3-qperret@google.com
2021-12-15KVM: arm64: pkvm: Fix hyp_pool max orderQuentin Perret1-1/+1
The EL2 page allocator in protected mode maintains a per-pool max order value to optimize allocations when the memory region it covers is small. However, the max order value is currently under-estimated whenever the number of pages in the region is a power of two. Fix the estimation. Signed-off-by: Quentin Perret <qperret@google.com> Acked-by: Will Deacon <will@kernel.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20211208152300.2478542-2-qperret@google.com
2021-12-15x86/boot: Move EFI range reservation after cmdline parsingMike Rapoport1-3/+3
The memory reservation in arch/x86/platform/efi/efi.c depends on at least two command line parameters. Put it back later in the boot process and move efi_memblock_x86_reserve_range() out of early_memory_reserve(). An attempt to fix this was done in 8d48bf8206f7 ("x86/boot: Pull up cmdline preparation and early param parsing") but that caused other troubles so it got reverted. The bug this is addressing is: Dan reports that Anjaneya Chagam can no longer use the efi=nosoftreserve kernel command line parameter to suppress "soft reservation" behavior. This is due to the fact that the following call-chain happens at boot: early_reserve_memory |-> efi_memblock_x86_reserve_range |-> efi_fake_memmap_early which does if (!efi_soft_reserve_enabled()) return; and that would have set EFI_MEM_NO_SOFT_RESERVE after having parsed "nosoftreserve". However, parse_early_param() gets called *after* it, leading to the boot cmdline not being taken into account. See also https://lore.kernel.org/r/e8dd8993c38702ee6dd73b3c11f158617e665607.camel@intel.com [ bp: Turn into a proper patch. ] Signed-off-by: Mike Rapoport <rppt@kernel.org> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lore.kernel.org/r/20211213112757.2612-4-bp@alien8.de
2021-12-15arm64: dts: apple: t8103: Sort nodes by addressHector Martin1-28/+28
We decided to keep SoC nodes sorted by address for sanity; fix a couple that slipped into the wrong place. Reviewed-by: Sven Peter <sven@svenpeter.dev> Signed-off-by: Hector Martin <marcan@marcan.st>
2021-12-15arm64: dts: apple: t8103: Rename clk24 to clkrefHector Martin1-10/+10
We now know that this frequency comes from the external reference oscillator and is used for various SoC blocks, and isn't just a random 24MHz clock, so let's call it something more appropriate. Reviewed-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Sven Peter <sven@svenpeter.dev> Signed-off-by: Hector Martin <marcan@marcan.st>
2021-12-15arm64: remove __dma_*_area() aliasesMark Rutland1-21/+3
The __dma_inv_area() and __dma_clean_area() aliases make cache.S harder to navigate, but don't gain us anything in practice. For clarity, let's remove them along with their redundant comments. The only users are __dma_map_area() and __dma_unmap_area(), which need to be position independent, and can call __pi_dcache_inval_poc() and __pi_dcache_clean_poc() directly. There should be no functional change as a result of this patch. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Cc: Ard Biesheuvel <ardb@kernel.org> Cc: Fuad Tabba <tabba@google.com> Cc: Marc Zyngier <maz@kernel.org> Cc: Will Deacon <will@kernel.org> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Ard Biesheuvel <ardb@kernel.org> Link: https://lore.kernel.org/r/20211206124715.4101571-4-mark.rutland@arm.com Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2021-12-15Revert "x86/boot: Pull up cmdline preparation and early param parsing"Borislav Petkov1-39/+27
This reverts commit 8d48bf8206f77aa8687f0e241e901e5197e52423. It turned out to be a bad idea as it broke supplying mem= cmdline parameters due to parse_memopt() requiring preparatory work like setting up the e820 table in e820__memory_setup() in order to be able to exclude the range specified by mem=. Pulling that up would've broken Xen PV again, see threads at https://lkml.kernel.org/r/20210920120421.29276-1-jgross@suse.com due to xen_memory_setup() needing the first reservations in early_reserve_memory() - kernel and initrd - to have happened already. This could be fixed again by having Xen do those reservations itself... Long story short, revert this and do a simpler fix in a later patch. Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lore.kernel.org/r/20211213112757.2612-3-bp@alien8.de
2021-12-15Revert "x86/boot: Mark prepare_command_line() __init"Borislav Petkov1-1/+1
This reverts commit c0f2077baa4113f38f008b8e912b9fb3ff8d43df. Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lore.kernel.org/r/20211213112757.2612-2-bp@alien8.de
2021-12-15Merge branch 'for-v5.17/dt-usi' into next/dt64Krzysztof Kozlowski2-8/+32
2021-12-14arm64: dts: qcom: add minimal DTS for Microsoft Surface Duo 2Katherine Perez2-0/+370
This is a minimal devicetree for Microsoft Surface Duo 2 with SM8350 Chipset Signed-off-by: Katherine Perez <kaperez@linux.microsoft.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211209183246.842880-2-kaperez@linux.microsoft.com
2021-12-14arm64: dts: qcom: sdm845-oneplus-*: add msm-id and board-idCaleb Connolly2-0/+4
The msm-id and board-id can be used to select the correct dtb when multiple are provided to the bootloader. Multiple DTBs can be provided on sdm845 devices using boot image header v1 by appending them all to the kernel image before creating the boot image. The bootloader then selects them like this: Best match DTB tags 321/00000008/0x00000000/20001/20014/20115/20018/0/(offset)0x79998E27/(size)0x000173CD Using pmic info 0x20014/0x20115/0x20018/0x0 for device 0x20014/0x20115/0x20018/0x0 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211209225938.2427342-1-caleb.connolly@linaro.org
2021-12-14ARM: dts: qcom: sdx65: Add pincontrol nodeVamsi krishna Lanka1-0/+12
This commit adds pincontrol node to SDX65 dts. Signed-off-by: Vamsi Krishna Lanka <quic_vamslank@quicinc.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1635552125-16407-4-git-send-email-quic_vamslank@quicinc.com
2021-12-14ARM: dts: qcom: Add SDX65 platform and MTP board supportVamsi krishna Lanka3-1/+237
Add basic devicetree support for SDX65 platform and MTP board from Qualcomm. The SDX65 platform features an ARM Cortex A7 CPU which forms the Application Processor Sub System (APSS) along with standard Qualcomm peripherals like GCC, TLMM, BLSP, QPIC, and BAM etc... Also, there exists the networking parts such as IPA, MHI, PCIE-EP, EMAC, and Modem etc.. This commit adds basic devicetree support that includes GCC, RPMh clock, INTC and Debug UART. Signed-off-by: Vamsi Krishna Lanka <quic_vamslank@quicinc.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1635552125-16407-3-git-send-email-quic_vamslank@quicinc.com
2021-12-15Merge branch 'topic/ppc-kvm' into nextMichael Ellerman3-15/+13
Bring in some more KVM commits from our KVM topic branch.
2021-12-14Merge tag 'ixp4xx-arm-soc-v5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik into arm/socArnd Bergmann1-13/+0
Some IXP4xx SoC and driver related changes for v5.17: - Drop unused Kconfig options - Drop unused platform data header file * tag 'ixp4xx-arm-soc-v5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik: ARM: ixp4xx: remove unused header file pata_ixp4xx_cf.h ARM: ixp4xx: remove dead configs CPU_IXP43X and CPU_IXP46X Link: https://lore.kernel.org/r/CACRpkdZXZBpexMUuwTV-RB7_QAjBQkSbRsaBtgFShcqxuNTUgw@mail.gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-12-14ARM: configs: gemini: Activate crypto driverLinus Walleij1-2/+1
This enables the SL3516 crypto driver on the Gemini platforms where it is available, by default in the defconfig. Clean up some noise around the crypto options while we're at it. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Cc: Corentin Labbe <clabbe@baylibre.com> Link: https://lore.kernel.org/r/20211206011158.4180141-1-linus.walleij@linaro.org' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-12-14arm64: Enable KCSANKefeng Wang3-0/+4
This patch enables KCSAN for arm64, with updates to build rules to not use KCSAN for several incompatible compilation units. Recent GCC version(at least GCC10) made outline-atomics as the default option(unlike Clang), which will cause linker errors for kernel/kcsan/core.o. Disables the out-of-line atomics by no-outline-atomics to fix the linker errors. Meanwhile, as Mark said[1], some latent issues are needed to be fixed which isn't just a KCSAN problem, we make the KCSAN depends on EXPERT for now. Tested selftest and kcsan_test(built with GCC11 and Clang 13), and all passed. [1] https://lkml.kernel.org/r/YadiUPpJ0gADbiHQ@FVFF77S0Q05N Acked-by: Marco Elver <elver@google.com> # kernel/kcsan Tested-by: Joey Gouly <joey.gouly@arm.com> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> Link: https://lore.kernel.org/r/20211211131734.126874-1-wangkefeng.wang@huawei.com [catalin.marinas@arm.com: added comment to justify EXPERT] Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2021-12-14arm64/fp: Add comments documenting the usage of state restore functionsMark Brown1-2/+5
Add comments to help people figure out when fpsimd_bind_state_to_cpu() and fpsimd_update_current_state() are used. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20211207163250.1373542-1-broonie@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2021-12-14arm64/sve: Generalise vector length configuration prctl() for SMEMark Brown4-31/+34
In preparation for adding SME support update the bulk of the implementation for the vector length configuration prctl() calls to be independent of vector type. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20211210184133.320748-3-broonie@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2021-12-14arm64/sve: Make sysctl interface for SVE reusable by SMEMark Brown1-6/+9
The vector length configuration for SME is very similar to that for SVE so in order to allow reuse refactor the SVE configuration so that it takes the vector type from the struct ctl_table. Since there's no dedicated space for this we repurpose the extra1 field to store the vector type, this is otherwise unused for integer sysctls. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20211210184133.320748-2-broonie@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2021-12-14Merge branch 'for-next/perf-cpu' into for-next/perfWill Deacon1-68/+43
* for-next/perf-cpu: arm64: perf: Support new DT compatibles arm64: perf: Simplify registration boilerplate arm64: perf: Support Denver and Carmel PMUs
2021-12-14arm64: Use BTI C directly and unconditionallyMark Brown3-25/+9
Now we have a macro for BTI C that looks like a regular instruction change all the users of the current BTI_C macro to just emit a BTI C directly and remove the macro. This does mean that we now unconditionally BTI annotate all assembly functions, meaning that they are worse in this respect than code generated by the compiler. The overhead should be minimal for implementations with a reasonable HINT implementation. Signed-off-by: Mark Brown <broonie@kernel.org> Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Acked-by: Mark Rutland <mark.rutland@arm.com> Link: https://lore.kernel.org/r/20211214152714.2380849-4-broonie@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2021-12-14arm64: Unconditionally override SYM_FUNC macrosMark Brown1-5/+11
Currently we only override the SYM_FUNC macros when we need to insert BTI C into them, do this unconditionally to make it more likely that we'll notice bugs in our override. Suggested-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org> Acked-by: Mark Rutland <mark.rutland@arm.com> Link: https://lore.kernel.org/r/20211214152714.2380849-3-broonie@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2021-12-14arm64: Add macro version of the BTI instructionMark Brown3-11/+16
BTI is only available from v8.5 so we need to encode it using HINT in generic code and for older toolchains. Add an assembler macro based on one written by Mark Rutland which lets us use the mnemonic and update the existing users. Suggested-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Ard Biesheuvel <ardb@kernel.org> Acked-by: Will Deacon <will@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org> Acked-by: Mark Rutland <mark.rutland@arm.com> Link: https://lore.kernel.org/r/20211214152714.2380849-2-broonie@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2021-12-14Merge 'arm64/for-next/fixes' into for-next/btiCatalin Marinas2-1/+7
Needed for the arch/arm64/kernel/entry-ftrace.S fix. * commit 'arm64/for-next/fixes^^': arm64: ftrace: add missing BTIs arm64: kexec: use __pa_symbol(empty_zero_page) arm64: update PAC description for kernel
2021-12-14arm64: perf: Support new DT compatiblesRobin Murphy1-0/+12
Wire up the new DT compatibles so we can present appropriate PMU names to userspace for the latest and greatest CPUs. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Link: https://lore.kernel.org/r/62d14ba12d847ec7f1fba7cb0b3b881b437e1cc5.1639490264.git.robin.murphy@arm.com Signed-off-by: Will Deacon <will@kernel.org>
2021-12-14arm64: perf: Simplify registration boilerplateRobin Murphy1-82/+31
With the trend for per-core events moving to userspace JSON, registering names for PMUv3 implementations is increasingly a pure boilerplate exercise. Let's wrap things a step further so we can generate the basic PMUv3 init function with a macro invocation, and reduce further new addition to just 2 lines each. Suggested-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Robin Murphy <robin.murphy@arm.com> Link: https://lore.kernel.org/r/b79477ea3b97f685d00511d4ecd2f686184dca34.1639490264.git.robin.murphy@arm.com Signed-off-by: Will Deacon <will@kernel.org>
2021-12-14arm64: perf: Support Denver and Carmel PMUsThierry Reding1-0/+14
Add support for the NVIDIA Denver and Carmel PMUs using the generic PMUv3 event map for now. Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Thierry Reding <treding@nvidia.com> [ rm: reorder entries alphabetically ] Signed-off-by: Robin Murphy <robin.murphy@arm.com> Link: https://lore.kernel.org/r/5f0f69d47acca78a9e479501aa4d8b429e23cf11.1639490264.git.robin.murphy@arm.com Signed-off-by: Will Deacon <will@kernel.org>
2021-12-14Merge tag 'renesas-arm-soc-for-v5.17-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/socArnd Bergmann1-1/+4
Renesas ARM SoC updates for v5.17 - Add a missing of_node_put(). * tag 'renesas-arm-soc-for-v5.17-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: ARM: shmobile: rcar-gen2: Add missing of_node_put() Link: https://lore.kernel.org/r/cover.1638530611.git.geert+renesas@glider.be Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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