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2021-12-06ARM: percpu: add SMP_ON_UP supportArd Biesheuvel6-22/+107
Permit the use of the TPIDRPRW system register for carrying the per-CPU offset in generic SMP configurations that also target non-SMP capable ARMv6 cores. This uses the SMP_ON_UP code patching framework to turn all TPIDRPRW accesses into reads/writes of entry #0 in the __per_cpu_offset array. While at it, switch over some existing direct TPIDRPRW accesses in asm code to invocations of a new helper that is patched in the same way when necessary. Note that CPU_V6+SMP without SMP_ON_UP results in a kernel that does not boot on v6 CPUs without SMP extensions, so add this dependency to Kconfig as well. Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Nicolas Pitre <nico@fluxnic.net> Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Tested-by: Marc Zyngier <maz@kernel.org> Tested-by: Vladimir Murzin <vladimir.murzin@arm.com> # ARMv7M
2021-12-06ARM: assembler: add optimized ldr/str macros to load variables from memoryArd Biesheuvel3-6/+43
We will be adding variable loads to various hot paths, so it makes sense to add a helper macro that can load variables from asm code without the use of literal pool entries. On v7 or later, we can simply use MOVW/MOVT pairs, but on earlier cores, this requires a bit of hackery to emit a instruction sequence that implements this using a sequence of ADD/LDR instructions. Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Nicolas Pitre <nico@fluxnic.net> Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Tested-by: Marc Zyngier <maz@kernel.org> Tested-by: Vladimir Murzin <vladimir.murzin@arm.com> # ARMv7M
2021-12-06ARM: module: implement support for PC-relative group relocationsArd Biesheuvel2-0/+88
Add support for the R_ARM_ALU_PC_Gn_NC and R_ARM_LDR_PC_G2 group relocations [0] so we can use them in modules. These will be used to load the current task pointer from a global variable without having to rely on a literal pool entry to carry the address of this variable, which may have a significant negative impact on cache utilization for variables that are used often and in many different places, as each occurrence will result in a literal pool entry and therefore a line in the D-cache. [0] 'ELF for the ARM architecture' https://github.com/ARM-software/abi-aa/releases Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Nicolas Pitre <nico@fluxnic.net> Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Tested-by: Marc Zyngier <maz@kernel.org> Tested-by: Vladimir Murzin <vladimir.murzin@arm.com> # ARMv7M
2021-12-06ARM: entry: preserve thread_info pointer in switch_toArd Biesheuvel1-8/+9
Tweak the UP stack protector handling code so that the thread info pointer is preserved in R7 until set_current is called. This is needed for a subsequent patch that implements THREAD_INFO_IN_TASK and set_current for UP as well. This also means we will prefer the per-task protector on UP systems that implement the thread ID registers, so tweak the preprocessor conditionals to reflect this. Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Nicolas Pitre <nico@fluxnic.net> Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Tested-by: Marc Zyngier <maz@kernel.org> Tested-by: Vladimir Murzin <vladimir.murzin@arm.com> # ARMv7M
2021-12-06irqchip: nvic: Use GENERIC_IRQ_MULTI_HANDLERVladimir Murzin2-8/+5
Rather then restructuring the ARMv7M entrly logic per TODO, just move NVIC to GENERIC_IRQ_MULTI_HANDLER. Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Tested-by: Marc Zyngier <maz@kernel.org> Tested-by: Vladimir Murzin <vladimir.murzin@arm.com> # ARMv7M
2021-12-06ARM: remove old-style irq entryArnd Bergmann6-56/+2
The last user of arch_irq_handler_default is gone now, so the entry-macro-multi.S file and all references to mach/entry-macro.S can be removed, as well as the asm_do_IRQ() entrypoint into the interrupt handling routines implemented in C. Note: The ARMv7-M entry still uses its own top-level IRQ entry, calling nvic_handle_irq() from assembly. This could be changed to go through generic_handle_arch_irq() as well, but it's unclear to me if there are any benefits. Signed-off-by: Arnd Bergmann <arnd@arndb.de> [ardb: keep irq_handler macro as it carries all the IRQ stack handling] Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Tested-by: Marc Zyngier <maz@kernel.org> Tested-by: Vladimir Murzin <vladimir.murzin@arm.com> # ARMv7M Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
2021-12-06ARM: iop32x: use GENERIC_IRQ_MULTI_HANDLERArnd Bergmann6-43/+43
iop32x uses the entry-macro.S file for both the IRQ entry and for hooking into the arch_ret_to_user code path. This is done because the cp6 registers have to be enabled before accessing any of the interrupt controller registers but have to be disabled when running in user space. There is also a lazy-enable logic in cp6.c, but during a hardirq, we know it has to be enabled. Both the cp6-enable code and the code to read the IRQ status can be lifted into the normal generic_handle_arch_irq() path, but the cp6-disable code has to remain in the user return code. As nothing other than iop32x uses this hook, just open-code it there with an ifdef for the platform that can eventually be removed when iop32x has reached the end of its life. The cp6-enable path in the IRQ entry has an extra cp_wait barrier that the trap version does not have, but it is harmless to do it in both cases to simplify the logic here at the cost of a few extra cycles for the trap. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Tested-by: Marc Zyngier <maz@kernel.org> Tested-by: Vladimir Murzin <vladimir.murzin@arm.com> # ARMv7M
2021-12-06ARM: iop32x: offset IRQ numbers by 1Arnd Bergmann4-33/+37
iop32x is one of the last platforms to use IRQ 0, and this has apparently stopped working in a 2014 cleanup without anyone noticing. This interrupt is used for the DMA engine, so most likely this has not actually worked in the past 7 years, but it's also not essential for using this board. I'm splitting out this change from my GENERIC_IRQ_MULTI_HANDLER conversion so it can be backported if anyone cares. Fixes: a71b092a9c68 ("ARM: Convert handle_IRQ to use __handle_domain_irq") Signed-off-by: Arnd Bergmann <arnd@arndb.de> [ardb: take +1 offset into account in mask/unmask and init as well] Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Tested-by: Marc Zyngier <maz@kernel.org> Tested-by: Vladimir Murzin <vladimir.murzin@arm.com> # ARMv7M Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
2021-12-06ARM: footbridge: use GENERIC_IRQ_MULTI_HANDLERArnd Bergmann3-107/+88
Footbridge still uses the classic IRQ entry path in assembler, but this is easily converted into an equivalent C version. In this case, the correlation between IRQ numbers and bits in the status register is non-obvious, and the priorities are handled by manually checking each bit in a static order, re-reading the status register after each handled event. I moved the code into the new file and edited the syntax without changing this sequence to keep the behavior as close as possible to what it traditionally did. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Tested-by: Marc Zyngier <maz@kernel.org> Tested-by: Vladimir Murzin <vladimir.murzin@arm.com> # ARMv7M Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
2021-12-06x86/mm: Flush global TLB when switching to trampoline page-tableJoerg Roedel3-10/+29
Move the switching code into a function so that it can be re-used and add a global TLB flush. This makes sure that usage of memory which is not mapped in the trampoline page-table is reliably caught. Also move the clearing of CR4.PCIDE before the CR3 switch because the cr4_clear_bits() function will access data not mapped into the trampoline page-table. Signed-off-by: Joerg Roedel <jroedel@suse.de> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lore.kernel.org/r/20211202153226.22946-4-joro@8bytes.org
2021-12-06x86/mm/64: Flush global TLB on boot and AP bringupJoerg Roedel4-7/+27
The AP bringup code uses the trampoline_pgd page-table which establishes global mappings in the user range of the address space. Flush the global TLB entries after the indentity mappings are removed so no stale entries remain in the TLB. Signed-off-by: Joerg Roedel <jroedel@suse.de> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lore.kernel.org/r/20211202153226.22946-3-joro@8bytes.org
2021-12-06KVM: arm64: Move host EL1 code out of hyp/ directoryWill Deacon8-63/+80
kvm/hyp/reserved_mem.c contains host code executing at EL1 and is not linked into the hypervisor object. Move the file into kvm/pkvm.c and rework the headers so that the definitions shared between the host and the hypervisor live in asm/kvm_pkvm.h. Signed-off-by: Will Deacon <will@kernel.org> Tested-by: Fuad Tabba <tabba@google.com> Reviewed-by: Fuad Tabba <tabba@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20211202171048.26924-4-will@kernel.org
2021-12-06KVM: arm64: Generate hyp_constants.h for the hostWill Deacon3-0/+28
In order to avoid exposing hypervisor (EL2) data structures directly to the host, generate hyp_constants.h to provide constants such as structure sizes to the host without dragging in the definitions themselves. Signed-off-by: Will Deacon <will@kernel.org> Tested-by: Fuad Tabba <tabba@google.com> Reviewed-by: Fuad Tabba <tabba@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20211202171048.26924-3-will@kernel.org
2021-12-06arm64: Add missing include of asm/cpufeature.h to asm/mmu.hWill Deacon1-0/+1
asm/mmu.h refers to cpus_have_const_cap() in the definition of arm64_kernel_unmapped_at_el0() so include asm/cpufeature.h directly rather than force all users of the header to do it themselves. Signed-off-by: Will Deacon <will@kernel.org> Tested-by: Fuad Tabba <tabba@google.com> Reviewed-by: Fuad Tabba <tabba@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20211202171048.26924-2-will@kernel.org
2021-12-06KVM: arm64: Constify kvm_io_gic_opsRikard Falkeborn2-2/+2
The only usage of kvm_io_gic_ops is to make a comparison with its address and to pass its address to kvm_iodevice_init() which takes a pointer to const kvm_io_device_ops as input. Make it const to allow the compiler to put it in read-only memory. Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20211204213518.83642-1-rikard.falkeborn@gmail.com
2021-12-06Merge 5.16-rc4 into tty-nextGreg Kroah-Hartman88-459/+776
We need the tty/serial driver fixes in here as well. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-12-06ARM: dts: stm32: Add Engicam i.Core STM32MP1 C.TOUCH 2.0 10.1" OFJagan Teki2-0/+133
Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose Carrier board. Genaral features: - Ethernet 10/100 - Wifi/BT - USB Type A/OTG - Audio Out - CAN - 10" LVDS Panel (SN65DSI84 DSI-LVDS bridge on SoM) i.Core STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam. 10.1" OF is a capacitive touch 10.1" Open Frame panel solutions. i.Core STM32MP1 needs to mount on top of C.TOUCH 2.0 carrier with pluged 10.1" OF for creating complete i.Core STM32MP1 C.TOUCH 2.0 10.1" Open Frame board. Add support for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-12-06ARM: dts: stm32: Enable LVDS panel on i.Core STM32MP1 EDIMM2.2Jagan Teki1-0/+85
Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit has plugged with 7" LVDS panel. Engicam i.Core STM32MP1 SoM has SN65DSI84 DSI to LVDS bridge. This patch adds a display pipeline to connect DSI to SN65DSI84 to 7" LVDS panel. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-12-06arm64: dts: exynos: Rename hsi2c nodes to i2c for Exynos5433 and Exynos7Sam Protsenko2-24/+24
In Device Tree specification it's recommended to use "i2c" name for I2C nodes. Now that i2c-exynos5 dt-schema binding was added, it shows some warnings like this when validating HS-I2C nodes: hsi2c@xxxxxxxxx: $nodename:0: 'hsi2c@xxxxxxxx' does not match '^i2c(@.*)?' From schema: Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml Rename hsi2c@* to i2c@* to fix those warnings. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20211204215820.17378-9-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-12-06ARM: dts: exynos: Rename hsi2c nodes to i2c for Exynos5260Sam Protsenko1-4/+4
In Device Tree specification it's recommended to use "i2c" name for I2C nodes. Now that i2c-exynos5 dt-schema binding was added, it shows some warnings like this when validating HS-I2C nodes: hsi2c@xxxxxxxxx: $nodename:0: 'hsi2c@xxxxxxxx' does not match '^i2c(@.*)?' From schema: Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml Rename hsi2c@* to i2c@* to fix those warnings. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20211204215820.17378-8-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-12-06arm64: defconfig: enable drivers for TQ TQMa8MxML-MBa8MxAlexander Stein1-0/+7
With the device tree in place, enable missing drivers as modules, if possible. PHY driver needs built-in for interrupt support. Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-06arm64: dts: freescale: add initial device tree for TQMa8Mx with i.MX8MAlexander Stein3-0/+710
This adds support for TQMa8Mx module on MBa8Mx board. Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-06arm64: dts: freescale: add initial device tree for TQMa8MQNL with i.MX8MNAlexander Stein3-0/+560
This adds support for TQMa8MQNL module on MBa8Mx board. Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-06arm64: dts: freescale: add initial device tree for TQMa8MQML with i.MX8MMAlexander Stein4-0/+871
This adds support for TQMa8MQML module on MBa8Mx board. Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-06arm64: dts: imx8ulp: Add the basic dts for imx8ulp evk boardJacky Bai2-0/+65
Add the basic dts file for i.MX8ULP EVK board. Only the necessary devices for minimal system boot up are enabled: enet, emmc, usb, console uart. some of the devices' pin status may lost during low power mode, so additional sleep pinctrl properties are included by default. Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-06arm64: dts: imx8ulp: Add the basic dtsi file for imx8ulpJacky Bai2-0/+1374
Add the basic dtsi support for i.MX8ULP. i.MX 8ULP is part of the ULP family with emphasis on extreme low-power techniques using the 28 nm fully depleted silicon on insulator process. Like i.MX 7ULP, i.MX 8ULP continues to be based on asymmetric architecture, however will add a third DSP domain for advanced voice/audio capability and a Graphics domain where it is possible to access graphics resources from the application side or the realtime side. Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-06arm64: defconfig: Enable OV5640Adam Ford1-0/+1
The Beacon EmbeddedWorks imx8mm development kit has a TD Next 5640 Camera. Enable the OV5640 driver to use the camera. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-06arm64: defconfig: Enable VIDEO_IMX_MEDIAAdam Ford1-0/+1
To use a camera, the CSIS and CSI drivers need to be enabled with VIDEO_IMX_MEDIA. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-06arm64: dts: imx8mm-beacon: Enable OV5640 CameraAdam Ford1-0/+58
The baseboard has support for a TDNext 5640 Camera which uses an OV5640 connected to a 2-lane CSI2 interface. With the CSI and mipi_csi2 drivers pointing to an OV5640 camera, the media pipeline can be configured with the following: media-ctl --links "'ov5640 1-003c':0->'imx7-mipi-csis.0':0[1]" The camera and various nodes in the pipeline can be configured for UYVY: media-ctl -v -V "'ov5640 1-003c':0 [fmt:UYVY8_1X16/640x480 field:none]" media-ctl -v -V "'csi':0 [fmt:UYVY8_1X16/640x480 field:none]" Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-06arm64: dts: imx8mm: Add CSI nodesAdam Ford1-0/+51
There is a csi bridge and csis interface that tie together to allow csi2 capture. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Tim Harvey <tharvey@gateworks.com> Tested-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-06arm64: dts: imx8mq: fix the schema check errors for fsl,tmu-calibrationDavid Heidelberg1-40/+40
fsl,tmu-calibration is in u32-matrix. Use matching property syntax. No functional changes. Fixes warnings as: $ make dtbs_check ... arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dt.yaml: tmu@30260000: \ fsl,tmu-calibration:0: Additional items are not allowed (1, 41, 2, 47, \ 3, 53, 4, 61, 5, 67, 6, 75, 7, 81, 8, 87, 9, 95, 10, 103, 11, 111, 65536, \ 27, 65537, 35, 65538, 43, 65539, 51, 65540, 59, 65541, 67, 65542, 75, \ 65543, 85, 65544, 93, 65545, 103, 65546, 112, 131072, 23, 131073, 35, \ 131074, 45, 131075, 55, 131076, 65, 131077, 75, 131078, 87, 131079, 99, \ 131080, 111, 196608, 21, 196609, 33, 196610, 45, 196611, 57, 196612, 69, \ 196613, 83, 196614, 95, 196615, 113 were unexpected) From schema: Documentation/devicetree/bindings/thermal/qoriq-thermal.yaml ... Signed-off-by: David Heidelberg <david@ixit.cz> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-06ARM: dts: imx6ull-pinfunc: Fix CSI_DATA07__ESAI_TX0 pad nameFabio Estevam1-1/+1
According to the i.MX6ULL Reference Manual, pad CSI_DATA07 may have the ESAI_TX0 functionality, not ESAI_T0. Also, NXP's i.MX Config Tools 10.0 generates dtsi with the MX6ULL_PAD_CSI_DATA07__ESAI_TX0 naming, so fix it accordingly. There are no devicetree users in mainline that use the old name, so just remove the old entry. Fixes: c201369d4aa5 ("ARM: dts: imx6ull: add imx6ull support") Reported-by: George Makarov <georgemakarov1@gmail.com> Signed-off-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-06arm64: dts: lx2162a: Add CAN nodes for LX2162A-QDSKuldeep Singh1-0/+8
Enable CAN support for LX2162A-QDS in board dts. Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-06arm64: dts: imx8mq: remove interconnect property from lcdifMartin Kepplinger1-2/+0
The mxsfb driver handling imx8mq lcdif doesn't yet request the interconnect bandwidth that's needed at runtime when the description is present in the DT node. So remove that description and bring it back when it's supported. Fixes: ad1abc8a03fd ("arm64: dts: imx8mq: Add interconnect for lcdif") Signed-off-by: Martin Kepplinger <martin.kepplinger@puri.sm> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-06ARM: ixp4xx: remove dead configs CPU_IXP43X and CPU_IXP46XLukas Bulwahn1-13/+0
Commit 73d04ca5f4ac ("ARM: ixp4xx: Delete Intel reference design boardfiles") removes the definition of the configs MACH_IXDP465 and MACH_KIXRP435, but misses to remove the configs CPU_IXP43X and CPU_IXP46X that depend on those removed configs, and hence are dead now. Fortunately, ./scripts/checkkconfigsymbols.py warns: MACH_IXDP465 Referencing files: arch/arm/mach-ixp4xx/Kconfig MACH_KIXRP435 Referencing files: arch/arm/mach-ixp4xx/Kconfig Remove the dead configs CPU_IXP43X and CPU_IXP46X. A further quick grep for the name of those two symbols did not show any use of the two config symbols; so, there are no further clean-up activities beyond this config removal needed. Signed-off-by: Lukas Bulwahn <lukas.bulwahn@gmail.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-12-06ARM: dts: Add Goramo MultiLink device treeLinus Walleij3-0/+198
This adds a device tree for the Goramo MultiLink IXP425-based WAN router. Cc: Krzysztof Hałasa <khalasa@piap.pl> Cc: openwrt-devel@lists.openwrt.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-12-06ARM: dts: Add FSG3 system controller and LEDsLinus Walleij1-0/+59
This adds the system controller on CS2 and the LEDs on it. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-12-06ARM: dts: imx6qdl: add TQ-Systems MBa6x device treesMarkus Niebel11-0/+785
Add device trees for the MBa6x mainboard with TQMa6Q/QP/DL SoMs. As discussed, all new files are added with GPL-2.0-only license, as they are too tightly intertwined with the SoC DTSIs imx6dl.dtsi and imx6q.dtsi, which are GPL-2.0. Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com> Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-06ARM: dts: imx6qdl-tqma6: add ERR006687 hardware workaround for "a" variantMatthias Schiffer1-0/+20
The TQMa6x "a" has a workaround for ERR006687 implemented in hardware. Add the required pinmuxing and related setup to make use of this. As board DTS files based on the TQMa6x SoMs will define their own pinmuxing for the FEC ethernet controller as well, we can't apply this pin group unconditionally; instead, it is the responsibility of the board DTs derived from imx6qdl-tqma6a.dtsi to include this group. Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-06ARM: dts: add JOZ Access PointOleksij Rempel2-0/+457
JOZ Access Point is imx6ull based device designed for agricultural cleaning machines. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-05Merge tag 'for-5.16/parisc-6' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linuxLinus Torvalds4-22/+26
Pull parisc fixes from Helge Deller: "Some bug and warning fixes: - Fix "make install" to use debians "installkernel" script which is now in /usr/sbin - Fix the bindeb-pkg make target by giving the correct KBUILD_IMAGE file name - Fix compiler warnings by annotating parisc agp init functions with __init - Fix timekeeping on SMP machines with dual-core CPUs - Enable some more config options in the 64-bit defconfig" * tag 'for-5.16/parisc-6' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux: parisc: Mark cr16 CPU clocksource unstable on all SMP machines parisc: Fix "make install" on newer debian releases parisc/agp: Annotate parisc agp init functions with __init parisc: Enable sata sil, audit and usb support on 64-bit defconfig parisc: Fix KBUILD_IMAGE for self-extracting kernel
2021-12-05Merge tag 'x86_urgent_for_v5.16_rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tipLinus Torvalds8-43/+154
Pull x86 fixes from Borislav Petkov: - Fix a couple of SWAPGS fencing issues in the x86 entry code - Use the proper operand types in __{get,put}_user() to prevent truncation in SEV-ES string io - Make sure the kernel mappings are present in trampoline_pgd in order to prevent any potential accesses to unmapped memory after switching to it - Fix a trivial list corruption in objtool's pv_ops validation - Disable the clocksource watchdog for TSC on platforms which claim that the TSC is constant, doesn't stop in sleep states, CPU has TSC adjust and the number of sockets of the platform are max 2, to prevent erroneous markings of the TSC as unstable. - Make sure TSC adjust is always checked not only when going idle - Prevent a stack leak by initializing struct _fpx_sw_bytes properly in the FPU code - Fix INTEL_FAM6_RAPTORLAKE define naming to adhere to the convention * tag 'x86_urgent_for_v5.16_rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/xen: Add xenpv_restore_regs_and_return_to_usermode() x86/entry: Use the correct fence macro after swapgs in kernel CR3 x86/entry: Add a fence for kernel entry SWAPGS in paranoid_entry() x86/sev: Fix SEV-ES INS/OUTS instructions for word, dword, and qword x86/64/mm: Map all kernel memory into trampoline_pgd objtool: Fix pv_ops noinstr validation x86/tsc: Disable clocksource watchdog for TSC on qualified platorms x86/tsc: Add a timer to make sure TSC_adjust is always checked x86/fpu/signal: Initialize sw_bytes in save_xstate_epilog() x86/cpu: Drop spurious underscore from RAPTOR_LAKE #define
2021-12-05Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds10-51/+106
Pull more kvm fixes from Paolo Bonzini: - Static analysis fix - New SEV-ES protocol for communicating invalid VMGEXIT requests - Ensure APICv is considered inactive if there is no APIC - Fix reserved bits for AMD PerfEvtSeln register * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: KVM: SVM: Do not terminate SEV-ES guests on GHCB validation failure KVM: SEV: Fall back to vmalloc for SEV-ES scratch area if necessary KVM: SEV: Return appropriate error codes if SEV-ES scratch setup fails KVM: x86/mmu: Retry page fault if root is invalidated by memslot update KVM: VMX: Set failure code in prepare_vmcs02() KVM: ensure APICv is considered inactive if there is no APIC KVM: x86/pmu: Fix reserved bits for AMD PerfEvtSeln register
2021-12-05x86/sme: Explicitly map new EFI memmap table as encryptedTom Lendacky2-1/+3
Reserving memory using efi_mem_reserve() calls into the x86 efi_arch_mem_reserve() function. This function will insert a new EFI memory descriptor into the EFI memory map representing the area of memory to be reserved and marking it as EFI runtime memory. As part of adding this new entry, a new EFI memory map is allocated and mapped. The mapping is where a problem can occur. This new memory map is mapped using early_memremap() and generally mapped encrypted, unless the new memory for the mapping happens to come from an area of memory that is marked as EFI_BOOT_SERVICES_DATA memory. In this case, the new memory will be mapped unencrypted. However, during replacement of the old memory map, efi_mem_type() is disabled, so the new memory map will now be long-term mapped encrypted (in efi.memmap), resulting in the map containing invalid data and causing the kernel boot to crash. Since it is known that the area will be mapped encrypted going forward, explicitly map the new memory map as encrypted using early_memremap_prot(). Cc: <stable@vger.kernel.org> # 4.14.x Fixes: 8f716c9b5feb ("x86/mm: Add support to access boot related data in the clear") Link: https://lore.kernel.org/all/ebf1eb2940405438a09d51d121ec0d02c8755558.1634752931.git.thomas.lendacky@amd.com/ Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> [ardb: incorporate Kconfig fix by Arnd] Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
2021-12-05KVM: SVM: Do not terminate SEV-ES guests on GHCB validation failureTom Lendacky2-46/+71
Currently, an SEV-ES guest is terminated if the validation of the VMGEXIT exit code or exit parameters fails. The VMGEXIT instruction can be issued from userspace, even though userspace (likely) can't update the GHCB. To prevent userspace from being able to kill the guest, return an error through the GHCB when validation fails rather than terminating the guest. For cases where the GHCB can't be updated (e.g. the GHCB can't be mapped, etc.), just return back to the guest. The new error codes are documented in the lasest update to the GHCB specification. Fixes: 291bd20d5d88 ("KVM: SVM: Add initial support for a VMGEXIT VMEXIT") Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Message-Id: <b57280b5562893e2616257ac9c2d4525a9aeeb42.1638471124.git.thomas.lendacky@amd.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-12-05KVM: SEV: Fall back to vmalloc for SEV-ES scratch area if necessarySean Christopherson1-4/+4
Use kvzalloc() to allocate KVM's buffer for SEV-ES's GHCB scratch area so that KVM falls back to __vmalloc() if physically contiguous memory isn't available. The buffer is purely a KVM software construct, i.e. there's no need for it to be physically contiguous. Cc: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Sean Christopherson <seanjc@google.com> Message-Id: <20211109222350.2266045-3-seanjc@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-12-05KVM: SEV: Return appropriate error codes if SEV-ES scratch setup failsSean Christopherson1-13/+17
Return appropriate error codes if setting up the GHCB scratch area for an SEV-ES guest fails. In particular, returning -EINVAL instead of -ENOMEM when allocating the kernel buffer could be confusing as userspace would likely suspect a guest issue. Fixes: 8f423a80d299 ("KVM: SVM: Support MMIO for an SEV-ES guest") Cc: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Sean Christopherson <seanjc@google.com> Message-Id: <20211109222350.2266045-2-seanjc@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-12-04parisc: Mark cr16 CPU clocksource unstable on all SMP machinesHelge Deller1-21/+7
In commit c8c3735997a3 ("parisc: Enhance detection of synchronous cr16 clocksources") I assumed that CPUs on the same physical core are syncronous. While booting up the kernel on two different C8000 machines, one with a dual-core PA8800 and one with a dual-core PA8900 CPU, this turned out to be wrong. The symptom was that I saw a jump in the internal clocks printed to the syslog and strange overall behaviour. On machines which have 4 cores (2 dual-cores) the problem isn't visible, because the current logic already marked the cr16 clocksource unstable in this case. This patch now marks the cr16 interval timers unstable if we have more than one CPU in the system, and it fixes this issue. Fixes: c8c3735997a3 ("parisc: Enhance detection of synchronous cr16 clocksources") Signed-off-by: Helge Deller <deller@gmx.de> Cc: <stable@vger.kernel.org> # v5.15+
2021-12-04parisc: Fix "make install" on newer debian releasesHelge Deller1-0/+1
On newer debian releases the debian-provided "installkernel" script is installed in /usr/sbin. Fix the kernel install.sh script to look for the script in this directory as well. Signed-off-by: Helge Deller <deller@gmx.de> Cc: <stable@vger.kernel.org> # v3.13+
2021-12-04x86/realmode: Add comment for Global bit usage in trampoline_pgdJoerg Roedel1-0/+5
Document the fact that using the trampoline_pgd will result in the creation of global TLB entries in the user range of the address space. Signed-off-by: Joerg Roedel <jroedel@suse.de> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20211202153226.22946-2-joro@8bytes.org
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