aboutsummaryrefslogtreecommitdiffstats
path: root/arch
AgeCommit message (Collapse)AuthorFilesLines
2021-09-30KVM: Make kvm_make_vcpus_request_mask() use pre-allocated cpu_kick_maskVitaly Kuznetsov3-13/+2
kvm_make_vcpus_request_mask() already disables preemption so just like kvm_make_all_cpus_request_except() it can be switched to using pre-allocated per-cpu cpumasks. This allows for improvements for both users of the function: in Hyper-V emulation code 'tlb_flush' can now be dropped from 'struct kvm_vcpu_hv' and kvm_make_scan_ioapic_request_mask() gets rid of dynamic allocation. cpumask_available() checks in kvm_make_vcpu_request() and kvm_kick_many_cpus() can now be dropped as they checks for an impossible condition: kvm_init() makes sure per-cpu masks are allocated. Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com> Reviewed-by: Sean Christopherson <seanjc@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210903075141.403071-9-vkuznets@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-09-30KVM: Drop 'except' parameter from kvm_make_vcpus_request_mask()Vitaly Kuznetsov2-2/+2
Both remaining callers of kvm_make_vcpus_request_mask() pass 'NULL' for 'except' parameter so it can just be dropped. No functional change intended ©. Suggested-by: Sean Christopherson <seanjc@google.com> Reviewed-by: Sean Christopherson <seanjc@google.com> Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210903075141.403071-6-vkuznets@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-09-30KVM: x86: hyper-v: Avoid calling kvm_make_vcpus_request_mask() with vcpu_mask==NULLVitaly Kuznetsov1-6/+9
In preparation to making kvm_make_vcpus_request_mask() use for_each_set_bit() switch kvm_hv_flush_tlb() to calling kvm_make_all_cpus_request() for 'all cpus' case. Note: kvm_make_all_cpus_request() (unlike kvm_make_vcpus_request_mask()) currently dynamically allocates cpumask on each call and this is suboptimal. Both kvm_make_all_cpus_request() and kvm_make_vcpus_request_mask() are going to be switched to using pre-allocated per-cpu masks. Reviewed-by: Sean Christopherson <seanjc@google.com> Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210903075141.403071-4-vkuznets@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-09-30KVM: nVMX: Reset vmxon_ptr upon VMXOFF emulation.Vitaly Kuznetsov2-0/+2
Currently, 'vmx->nested.vmxon_ptr' is not reset upon VMXOFF emulation. This is not a problem per se as we never access it when !vmx->nested.vmxon. But this should be done to avoid any issue in the future. Also, initialize the vmxon_ptr when vcpu is created. Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com> Signed-off-by: Yu Zhang <yu.c.zhang@linux.intel.com> Message-Id: <20210929175154.11396-3-yu.c.zhang@linux.intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-09-30KVM: nVMX: Use INVALID_GPA for pointers used in nVMX.Yu Zhang2-32/+32
Clean up nested.c and vmx.c by using INVALID_GPA instead of "-1ull", to denote an invalid address in nested VMX. Affected addresses are the ones of VMXON region, current VMCS, VMCS link pointer, virtual- APIC page, ENCLS-exiting bitmap, and IO bitmap etc. Suggested-by: Sean Christopherson <seanjc@google.com> Signed-off-by: Yu Zhang <yu.c.zhang@linux.intel.com> Message-Id: <20210929175154.11396-2-yu.c.zhang@linux.intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-09-30KVM: x86: Swap order of CPUID entry "index" vs. "significant flag" checksSean Christopherson1-2/+2
Check whether a CPUID entry's index is significant before checking for a matching index to hack-a-fix an undefined behavior bug due to consuming uninitialized data. RESET/INIT emulation uses kvm_cpuid() to retrieve CPUID.0x1, which does _not_ have a significant index, and fails to initialize the dummy variable that doubles as EBX/ECX/EDX output _and_ ECX, a.k.a. index, input. Practically speaking, it's _extremely_ unlikely any compiler will yield code that causes problems, as the compiler would need to inline the kvm_cpuid() call to detect the uninitialized data, and intentionally hose the kernel, e.g. insert ud2, instead of simply ignoring the result of the index comparison. Although the sketchy "dummy" pattern was introduced in SVM by commit 66f7b72e1171 ("KVM: x86: Make register state after reset conform to specification"), it wasn't actually broken until commit 7ff6c0350315 ("KVM: x86: Remove stateful CPUID handling") arbitrarily swapped the order of operations such that "index" was checked before the significant flag. Avoid consuming uninitialized data by reverting to checking the flag before the index purely so that the fix can be easily backported; the offending RESET/INIT code has been refactored, moved, and consolidated from vendor code to common x86 since the bug was introduced. A future patch will directly address the bad RESET/INIT behavior. The undefined behavior was detected by syzbot + KernelMemorySanitizer. BUG: KMSAN: uninit-value in cpuid_entry2_find arch/x86/kvm/cpuid.c:68 BUG: KMSAN: uninit-value in kvm_find_cpuid_entry arch/x86/kvm/cpuid.c:1103 BUG: KMSAN: uninit-value in kvm_cpuid+0x456/0x28f0 arch/x86/kvm/cpuid.c:1183 cpuid_entry2_find arch/x86/kvm/cpuid.c:68 [inline] kvm_find_cpuid_entry arch/x86/kvm/cpuid.c:1103 [inline] kvm_cpuid+0x456/0x28f0 arch/x86/kvm/cpuid.c:1183 kvm_vcpu_reset+0x13fb/0x1c20 arch/x86/kvm/x86.c:10885 kvm_apic_accept_events+0x58f/0x8c0 arch/x86/kvm/lapic.c:2923 vcpu_enter_guest+0xfd2/0x6d80 arch/x86/kvm/x86.c:9534 vcpu_run+0x7f5/0x18d0 arch/x86/kvm/x86.c:9788 kvm_arch_vcpu_ioctl_run+0x245b/0x2d10 arch/x86/kvm/x86.c:10020 Local variable ----dummy@kvm_vcpu_reset created at: kvm_vcpu_reset+0x1fb/0x1c20 arch/x86/kvm/x86.c:10812 kvm_apic_accept_events+0x58f/0x8c0 arch/x86/kvm/lapic.c:2923 Reported-by: syzbot+f3985126b746b3d59c9d@syzkaller.appspotmail.com Reported-by: Alexander Potapenko <glider@google.com> Fixes: 2a24be79b6b7 ("KVM: VMX: Set EDX at INIT with CPUID.0x1, Family-Model-Stepping") Fixes: 7ff6c0350315 ("KVM: x86: Remove stateful CPUID handling") Cc: stable@vger.kernel.org Signed-off-by: Sean Christopherson <seanjc@google.com> Reviewed-by: Jim Mattson <jmattson@google.com> Message-Id: <20210929222426.1855730-2-seanjc@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-09-30x86/kvmclock: Move this_cpu_pvti into kvmclock.hZelin Deng2-11/+16
There're other modules might use hv_clock_per_cpu variable like ptp_kvm, so move it into kvmclock.h and export the symbol to make it visiable to other modules. Signed-off-by: Zelin Deng <zelin.deng@linux.alibaba.com> Cc: <stable@vger.kernel.org> Message-Id: <1632892429-101194-2-git-send-email-zelin.deng@linux.alibaba.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-09-30powerpc/iommu: Report the correct most efficient DMA mask for PCI devicesAlexey Kardashevskiy1-0/+9
According to dma-api.rst, the dma_get_required_mask() helper should return "the mask that the platform requires to operate efficiently". Which in the case of PPC64 means the bypass mask and not a mask from an IOMMU table which is shorter and slower to use due to map/unmap operations (especially expensive on "pseries"). However the existing implementation ignores the possibility of bypassing and returns the IOMMU table mask on the pseries platform which makes some drivers (mpt3sas is one example) choose 32bit DMA even though bypass is supported. The powernv platform sort of handles it by having a bigger default window with a mask >=40 but it only works as drivers choose 63/64bit if the required mask is >32 which is rather pointless. This reintroduces the bypass capability check to let drivers make a better choice of the DMA mask. Fixes: f1565c24b596 ("powerpc: use the generic dma_ops_bypass mode") Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20210930034454.95794-1-aik@ozlabs.ru
2021-09-29arm64: kasan: mte: move GCR_EL1 switch to task switch when KASAN disabledPeter Collingbourne2-5/+31
It is not necessary to write to GCR_EL1 on every kernel entry and exit when HW tag-based KASAN is disabled because the kernel will not execute any IRG instructions in that mode. Since accessing GCR_EL1 can be expensive on some microarchitectures, avoid doing so by moving the access to task switch when HW tag-based KASAN is disabled. Signed-off-by: Peter Collingbourne <pcc@google.com> Acked-by: Andrey Konovalov <andreyknvl@gmail.com> Link: https://linux-review.googlesource.com/id/I78e90d60612a94c24344526f476ac4ff216e10d2 Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Link: https://lore.kernel.org/r/20210924010655.2886918-1-pcc@google.com Signed-off-by: Will Deacon <will@kernel.org>
2021-09-29arm64: mm: update max_pfn after memory hotplugSudarshan Rajagopalan1-0/+5
After new memory blocks have been hotplugged, max_pfn and max_low_pfn needs updating to reflect on new PFNs being hot added to system. Without this patch, debug-related functions that use max_pfn such as get_max_dump_pfn() or read_page_owner() will not work with any page in memory that is hot-added after boot. Fixes: 4ab215061554 ("arm64: Add memory hotplug support") Signed-off-by: Sudarshan Rajagopalan <quic_sudaraja@quicinc.com> Signed-off-by: Chris Goldsworthy <quic_cgoldswo@quicinc.com> Acked-by: David Hildenbrand <david@redhat.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: Georgi Djakov <quic_c_gdjako@quicinc.com> Tested-by: Georgi Djakov <quic_c_gdjako@quicinc.com> Link: https://lore.kernel.org/r/a51a27ee7be66024b5ce626310d673f24107bcb8.1632853776.git.quic_cgoldswo@quicinc.com Signed-off-by: Will Deacon <will@kernel.org>
2021-09-29arm64/mm: Add pud_sect_supported()Anshuman Khandual3-13/+22
Section mapping at PUD level is supported only on 4K pages and currently it gets verified with explicit #ifdef or IS_ENABLED() constructs. This adds a new helper pud_sect_supported() for this purpose, which particularly cleans up the HugeTLB code path. It updates relevant switch statements with checks for __PAGETABLE_PMD_FOLDED in order to avoid build failures caused with two identical switch case values in those code blocks. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Suggested-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Link: https://lore.kernel.org/r/1632130171-472-1-git-send-email-anshuman.khandual@arm.com Signed-off-by: Will Deacon <will@kernel.org>
2021-09-29arm64/traps: Avoid unnecessary kernel/user pointer conversionAmit Daniel Kachhap1-2/+2
Annotating a pointer from kernel to __user and then back again requires an extra __force annotation to silent sparse warning. In call_undef_hook() this unnecessary complexity can be avoided by modifying the intermediate user pointer to unsigned long. This way there is no inter-changeable use of user and kernel pointers and the code is consistent. Note: This patch adds no functional changes to code. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Link: https://lore.kernel.org/r/20210917055811.22341-1-amit.kachhap@arm.com Signed-off-by: Will Deacon <will@kernel.org>
2021-09-29Merge branch 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6Linus Torvalds1-2/+3
Pull crypto fixes from Herbert Xu: "This contains fixes for a resource leak in ccp as well as stack corruption in x86/sm4" * 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: crypto: x86/sm4 - Fix frame pointer stack corruption crypto: ccp - fix resource leaks in ccp_run_aes_gcm_cmd()
2021-09-29bpf, arm: Fix register clobbering in div/mod implementationJohan Almbladh1-0/+19
On ARM CPUs that lack div/mod instructions, ALU32 BPF_DIV and BPF_MOD are implemented using a call to a helper function. Before, the emitted code for those function calls failed to preserve caller-saved ARM registers. Since some of those registers happen to be mapped to BPF registers, it resulted in eBPF register values being overwritten. This patch emits code to push and pop the remaining caller-saved ARM registers r2-r3 into the stack during the div/mod function call. ARM registers r0-r1 are used as arguments and return value, and those were already saved and restored correctly. Fixes: 39c13c204bb1 ("arm: eBPF JIT compiler") Signed-off-by: Johan Almbladh <johan.almbladh@anyfinetworks.com> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
2021-09-29arm64: exynos: don't have ARCH_EXYNOS select EXYNOS_CHIPIDWill McVicker1-1/+0
Now that EXYNOS_CHIPID can be a module and is enabled by default via ARCH_EXYNOS, we don't need to have ARCH_EXYNOS directly select it. So remove that. Signed-off-by: Will McVicker <willmcvicker@google.com> Link: https://lore.kernel.org/r/20210928235635.1348330-2-willmcvicker@google.com [krzysztof: the driver is not essential to boot and on ARMv7 it is also allowed to disable it] Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-09-29soc: samsung: exynos-chipid: do not enforce built-inKrzysztof Kozlowski1-1/+0
After converting the Exynos ChipID and ASV driver to a module, allow to actually choose it to be a module, while being a default built-in. The side effect is that driver could be now entirely disabled even for kernel with ARCH_EXYNOS, but this is not a critical issue because driver is not necessary for the proper platform boot. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Reviewed-by: Sylwester Nawrocki <snawrocki@kernel.org> Tested-by: Sylwester Nawrocki <snawrocki@kernel.org> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Tested-by: Alim Akhtar <alim.akhtar@samsung.com> Link: https://lore.kernel.org/r/20210919093114.35987-4-krzysztof.kozlowski@canonical.com
2021-09-29arm64: mm: Drop pointless call to set_max_mapnr()Will Deacon1-2/+0
set_max_mapnr() is an empty stub function if CONFIG_NUMA=y, otherwise it assigns to the 'max_mapnr' variable which is used to provide a generic pfn_valid() implementation if CONFIG_MMU=n. Since we don't support nommu on arm64, drop the pointless call to set_max_mapnr() from mem_init(). Link: https://lore.kernel.org/r/130a50d7-92fd-31fa-261e-f73dadcb4fcf@redhat.com Signed-off-by: Will Deacon <will@kernel.org>
2021-09-29arm64: zynqmp: Add support for Xilinx Kria SOM boardMichal Simek5-0/+936
There are couple of revisions of SOMs (k26) and associated carrier cards (kv260). SOM itself has two major versions: sm-k26 - SOM with EMMC smk-k26 - SOM without EMMC used on starter kit with preprogrammed firmware in QSPI. SOMs are describing only devices available on the SOM or connections which are described in specification (for example UART, fwuen). When SOM boots out of QSPI it uses limited number of peripherals defined by the specification and present in sm(k)-k26 dtses. Then a carrier card (CC) detection is happening and DT overlay is applied to brings new functionality. That's why DT overlays are used. The name is composed together with SOM name and CC name that's why DT overlays with these names are generated to make sure they can be used together. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/1ba32590670434b650bacf6410a65579dd30b38b.1632294439.git.michal.simek@xilinx.com
2021-09-29x86/boot: Fix make hdimage with older versions of mtoolsH. Peter Anvin (Intel)2-9/+11
Some versions of mtools (fixed somewhere between 4.0.31 and 4.0.35) generate bad output for mformat when used with the partition= option. Use the offset= option instead. An mtools.conf entry is *also* needed with partition= to support mpartition; combining them in one entry does not work either. Don't specify the -t option to mpartition; it is unnecessary and seems to confuse mpartition under some circumstances. Also do a few minor optimizations: Use a larger cluster size; there is no reason for the typical 4K clusters when we are dealing mainly with comparatively huge files. Start the partition at 32K. There is no reason to align it more than that, since the internal FAT filesystem structures will at best be cluster-aligned, and 32K is the maximum FAT cluster size. [ bp: Remove "we". ] Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20210911003906.2700218-1-hpa@zytor.com
2021-09-28Merge tag 'm68k-for-v5.15-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/linux-m68kLinus Torvalds24-353/+300
Pull more m68k updates from Geert Uytterhoeven: - signal handling fixes - removal of set_fs() [ The set_fs removal isn't strictly a fix, but it's been pending for a while and is very welcome. The signal handling fixes resolved an issue that was incorrectly attributed to the set_fs changes - Linus ] * tag 'm68k-for-v5.15-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/linux-m68k: m68k: Remove set_fs() m68k: Provide __{get,put}_kernel_nofault m68k: Factor the 8-byte lowlevel {get,put}_user code into helpers m68k: Use BUILD_BUG for passing invalid sizes to get_user/put_user m68k: Remove the 030 case in virt_to_phys_slow m68k: Document that access_ok is broken for !CONFIG_CPU_HAS_ADDRESS_SPACES m68k: Leave stack mangling to asm wrapper of sigreturn() m68k: Update ->thread.esp0 before calling syscall_trace() in ret_from_signal m68k: Handle arrivals of multiple signals correctly
2021-09-28Merge tag 'nios2_fixes_for_v5.15_part1' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linuxLinus Torvalds2-3/+2
Pull nios2 fixes from Dinh Nguyen: - Fix build warning for unmet dependency for EARLY_PRINTK - Remove unused dram_start() function * tag 'nios2_fixes_for_v5.15_part1' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: NIOS2: setup.c: drop unused variable 'dram_start' NIOS2: fix kconfig unmet dependency warning for SERIAL_CORE_CONSOLE
2021-09-28KVM: s390: Function documentation fixesJanosch Frank2-1/+15
The latest compile changes pointed us to a few instances where we use the kernel documentation style but don't explain all variables or don't adhere to it 100%. It's easy to fix so let's do that. Signed-off-by: Janosch Frank <frankja@linux.ibm.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
2021-09-28arm64: dts: qcom: sdm630-nile: Correct regulator label nameShawn Guo1-4/+4
29.5V (29p5) is obviously wrong for regulator l4 and l5. Correct them to be 2.95V (2p95). No functional change. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210926072215.27517-1-shawn.guo@linaro.org
2021-09-28arm64: dts: qcom: sm6125: Improve indentation of multiline propertiesMarijn Suijten1-23/+23
Some multiline properties (spread out over multiple lines to keep length in check) were not indented properly, leading to misalignment with the items above. The DT file is still small enough to address this early in the process. Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Martin Botka <martin.botka@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210925141841.407257-1-marijn.suijten@somainline.org
2021-09-28arm64: dts: qcom: msm8916-longcheer-l8150: Use &pm8916_usbin extconStephan Gerhold1-17/+6
At the moment, longcheer-l8150 is using a dummy extcon-usb-gpio device that permanently enables USB gadget mode. This workaround allows USB to work but is actually wrong and confusing. The "vbus-gpio" used there refers to an unused (floating) GPIO that is pulled up to make extcon-usb-gpio report USB gadget mode permanently. Replace this with the new &pm8916_usbin extcon device that actually reports if an USB cable is attached or not. This allows the USB PHY to be turned off when there is no USB cable attached and is much cleaner overall. Fixes: 16e8e8072108 ("arm64: dts: qcom: Add device tree for Longcheer L8150") Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210928112945.25310-3-stephan@gerhold.net
2021-09-28arm64: dts: qcom: pm8916: Add pm8941-misc extcon for USB detectionStephan Gerhold1-0/+8
At the moment, USB gadget mode on MSM8916 works only with an extcon device that reports the correct USB mode. This might be because the USB PHY needs to be configured appropriately. Unfortunately there is currently no simple approach to get such an extcon device during early bring-up. The extcon device for USB VBUS (i.e. gadget/peripheral mode) is typically provided by the charging driver which is almost always very complex to port. On pretty much all devices with PM8916, the USB VBUS is also connected to the PM8916 "USB_IN" pad, no matter if they use the linear charger integrated into PM8916 or not. The state of this pad can be checked with the "USBIN_VALID" interrupt of PM8916. The "qcom,pm8941-misc" binding exists to expose an "usb_vbus" and/or "usb_id" interrupt from the PMIC as an extcon device. Add a &pm8916_usbin node to pm8916.dtsi which can be used as simple extcon device for devices that are currently lacking a proper charger driver. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210928112945.25310-2-stephan@gerhold.net
2021-09-28arm64: dts: qcom: pm8916: Remove wrong reg-names for rtc@6000Stephan Gerhold1-1/+0
While removing the size from the "reg" properties in pm8916.dtsi, commit bd6429e81010 ("ARM64: dts: qcom: Remove size elements from pmic reg properties") mistakenly also removed the second register address for the rtc@6000 device. That one did not represent the size of the register region but actually the address of the second "alarm" register region of the rtc@6000 device. Now there are "reg-names" for two "reg" elements, but there is actually only one "reg" listed. Since the DT schema for "qcom,pm8941-rtc" only expects one "reg" element anyway, just drop the "reg-names" entirely to fix this. Fixes: bd6429e81010 ("ARM64: dts: qcom: Remove size elements from pmic reg properties") Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210928112945.25310-1-stephan@gerhold.net
2021-09-28Merge git://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpfDavid S. Miller2-32/+91
Daniel Borkmann says: ==================== pull-request: bpf 2021-09-28 The following pull-request contains BPF updates for your *net* tree. We've added 10 non-merge commits during the last 14 day(s) which contain a total of 11 files changed, 139 insertions(+), 53 deletions(-). The main changes are: 1) Fix MIPS JIT jump code emission for too large offsets, from Piotr Krysiuk. 2) Fix x86 JIT atomic/fetch emission when dst reg maps to rax, from Johan Almbladh. 3) Fix cgroup_sk_alloc corner case when called from interrupt, from Daniel Borkmann. 4) Fix segfault in libbpf's linker for objects without BTF, from Kumar Kartikeya Dwivedi. 5) Fix bpf_jit_charge_modmem for applications with CAP_BPF, from Lorenz Bauer. 6) Fix return value handling for struct_ops BPF programs, from Hou Tao. 7) Various fixes to BPF selftests, from Jiri Benc. ==================== Signed-off-by: David S. Miller <davem@davemloft.net> ,
2021-09-28bpf, x86: Fix bpf mapping of atomic fetch implementationJohan Almbladh1-5/+8
Fix the case where the dst register maps to %rax as otherwise this produces an incorrect mapping with the implementation in 981f94c3e921 ("bpf: Add bitwise atomic instructions") as %rax is clobbered given it's part of the cmpxchg as operand. The issue is similar to b29dd96b905f ("bpf, x86: Fix BPF_FETCH atomic and/or/ xor with r0 as src") just that the case of dst register was missed. Before, dst=r0 (%rax) src=r2 (%rsi): [...] c5: mov %rax,%r10 c8: mov 0x0(%rax),%rax <---+ (broken) cc: mov %rax,%r11 | cf: and %rsi,%r11 | d2: lock cmpxchg %r11,0x0(%rax) <---+ d8: jne 0x00000000000000c8 | da: mov %rax,%rsi | dd: mov %r10,%rax | [...] | | After, dst=r0 (%rax) src=r2 (%rsi): | | [...] | da: mov %rax,%r10 | dd: mov 0x0(%r10),%rax <---+ (fixed) e1: mov %rax,%r11 | e4: and %rsi,%r11 | e7: lock cmpxchg %r11,0x0(%r10) <---+ ed: jne 0x00000000000000dd ef: mov %rax,%rsi f2: mov %r10,%rax [...] The remaining combinations were fine as-is though: After, dst=r9 (%r15) src=r0 (%rax): [...] dc: mov %rax,%r10 df: mov 0x0(%r15),%rax e3: mov %rax,%r11 e6: and %r10,%r11 e9: lock cmpxchg %r11,0x0(%r15) ef: jne 0x00000000000000df _ f1: mov %rax,%r10 | (unneeded, but f4: mov %r10,%rax _| not a problem) [...] After, dst=r9 (%r15) src=r4 (%rcx): [...] de: mov %rax,%r10 e1: mov 0x0(%r15),%rax e5: mov %rax,%r11 e8: and %rcx,%r11 eb: lock cmpxchg %r11,0x0(%r15) f1: jne 0x00000000000000e1 f3: mov %rax,%rcx f6: mov %r10,%rax [...] The case of dst == src register is rejected by the verifier and therefore not supported, but x86 JIT also handles this case just fine. After, dst=r0 (%rax) src=r0 (%rax): [...] eb: mov %rax,%r10 ee: mov 0x0(%r10),%rax f2: mov %rax,%r11 f5: and %r10,%r11 f8: lock cmpxchg %r11,0x0(%r10) fe: jne 0x00000000000000ee 100: mov %rax,%r10 103: mov %r10,%rax [...] Fixes: 981f94c3e921 ("bpf: Add bitwise atomic instructions") Reported-by: Johan Almbladh <johan.almbladh@anyfinetworks.com> Signed-off-by: Johan Almbladh <johan.almbladh@anyfinetworks.com> Co-developed-by: Daniel Borkmann <daniel@iogearbox.net> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net> Reviewed-by: Brendan Jackman <jackmanb@google.com> Acked-by: Alexei Starovoitov <ast@kernel.org>
2021-09-28arm64: dts: renesas: rcar-gen3: Add missing Ethernet PHY resetsGeert Uytterhoeven5-0/+9
Describe all Ethernet PHY reset GPIOs on R-Car Gen3 boards, to avoid relying solely on boot loaders to bring PHYs out of reset. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/3e6fd765850e8ef0980d8e98bc5f2126538d626f.1631177442.git.geert+renesas@glider.be
2021-09-28ARM: dts: rzg1: Add missing Ethernet PHY resetsGeert Uytterhoeven2-0/+4
Describe all Ethernet PHY reset GPIOs on RZ/G1 boards, to avoid relying solely on boot loaders to bring PHYs out of reset. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/e20b3643b4dc5f6c2a9e19d9544495c06075d9ff.1631177442.git.geert+renesas@glider.be
2021-09-28ARM: dts: r-mobile: Add missing Ethernet PHY resetsGeert Uytterhoeven2-0/+2
Describe all Ethernet PHY reset GPIOs on R-Mobile boards, to avoid relying solely on boot loaders to bring PHYs out of reset. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/b41bf0098ff193fbff9fad04d00075ce1bea1986.1631177442.git.geert+renesas@glider.be
2021-09-28arm64: dts: renesas: Add compatible properties to RTL8211E Ethernet PHYsGeert Uytterhoeven2-0/+4
Add compatible values to Ethernet PHY subnodes representing Realtek RTL8211E PHYs on RZ/G2 boards. This allows software to identify the PHY model at any time, regardless of the state of the PHY reset line. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/3b366e3dddd4d3cd7e89b92d3a8f78f6dc18e244.1631174218.git.geert+renesas@glider.be
2021-09-28arm64: dts: renesas: Add compatible properties to KSZ9031 Ethernet PHYsGeert Uytterhoeven9-0/+18
Add compatible values to Ethernet PHY subnodes representing Micrel KSZ9031 PHYs on R-Car Gen3 boards. This allows software to identify the PHY model at any time, regardless of the state of the PHY reset line. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/07bd7e04dda9e84cde0664980f0b1a6d69e03109.1631174218.git.geert+renesas@glider.be
2021-09-28arm64: dts: renesas: Add compatible properties to AR8031 Ethernet PHYsGeert Uytterhoeven1-0/+2
Add compatible values to Ethernet PHY subnodes representing Atheros AR8031 PHYs on RZ/G2 boards. This allows software to identify the PHY model at any time, regardless of the state of the PHY reset line. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Adam Ford <aford173@gmail.com> Link: https://lore.kernel.org/r/3f1b58756f149f0c634c66abaecc88e699f4c3cc.1631174218.git.geert+renesas@glider.be
2021-09-28ARM: dts: renesas: Add compatible properties to uPD6061x Ethernet PHYsGeert Uytterhoeven2-0/+4
Add compatible values to Ethernet PHY subnodes representing Renesas uPD60610 or uPD60611 PHYs on RZ/A1 boards. This allows software to identify the PHY model at any time, regardless of the state of the PHY reset line. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/335a1dfea905369da683e122e41e08ca1c5f90f7.1631174218.git.geert+renesas@glider.be
2021-09-28ARM: dts: renesas: Add compatible properties to RTL8201FL Ethernet PHYsGeert Uytterhoeven1-0/+2
Add compatible values to Ethernet PHY subnodes representing Realtek RTL8201FL PHYs on RZ/A2 boards. This allows software to identify the PHY model at any time, regardless of the state of the PHY reset line. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/a23eca16869457684b0300379233e335b4e2047e.1631174218.git.geert+renesas@glider.be
2021-09-28ARM: dts: renesas: Add compatible properties to LAN8710A Ethernet PHYsGeert Uytterhoeven2-0/+4
Add compatible values to Ethernet PHY subnodes representing SMSC LAN8710A PHYs on RZ/A1 and R-Mobile A1 boards. This allows software to identify the PHY model at any time, regardless of the state of the PHY reset line. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/247dc2074dae149af07b6d014985ad30eb362eda.1631174218.git.geert+renesas@glider.be
2021-09-28ARM: dts: renesas: Add compatible properties to KSZ9031 Ethernet PHYsGeert Uytterhoeven4-0/+8
Add compatible values to Ethernet PHY subnodes representing Micrel KSZ9031 PHYs on RZ/G1 boards. This allows software to identify the PHY model at any time, regardless of the state of the PHY reset line. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/ce8ae6b199fa244315a008ae31891a808ca1948d.1631174218.git.geert+renesas@glider.be
2021-09-28ARM: dts: renesas: Add compatible properties to KSZ8081 Ethernet PHYsGeert Uytterhoeven1-0/+2
Add compatible values to Ethernet PHY subnodes representing Micrel KSZ8081 PHYs on RZ/G1 boards. This allows software to identify the PHY model at any time, regardless of the state of the PHY reset line. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/ec5c7dadf3c0fe5e47dfbae72fb435047203ad06.1631174218.git.geert+renesas@glider.be
2021-09-28ARM: dts: renesas: Add compatible properties to KSZ8041 Ethernet PHYsGeert Uytterhoeven9-0/+18
Add compatible values to Ethernet PHY subnodes representing Micrel KSZ8041 PHYs on RZ/G1 and R-Car Gen2 boards. This allows software to identify the PHY model at any time, regardless of the state of the PHY reset line. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/f9e26625924f90eff34fe6f6f02b15fa272c5d80.1631174218.git.geert+renesas@glider.be
2021-09-28arm64: dts: renesas: beacon: Fix Ethernet PHY modeGeert Uytterhoeven1-0/+1
While networking works fine in RGMII mode when using the Linux generic PHY driver, it fails when using the Atheros PHY driver. Fix this by correcting the Ethernet PHY mode to RGMII-RXID, which works fine with both drivers. Fixes: a5200e63af57d05e ("arm64: dts: renesas: rzg2: Convert EtherAVB to explicit delay handling") Reported-by: Adam Ford <aford173@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/2a4c15b2df23bb63f15abf9dfb88860477f4f523.1632465965.git.geert+renesas@glider.be
2021-09-28ARM: dts: renesas: Fix SMSC Ethernet compatible valuesGeert Uytterhoeven4-4/+4
According to schematics, and confirmed by ID_REV register contents, the Ethernet controllers on various development board are not SMSC LAN9220, but different variants: - KZM-A9-Dual and KZM-A9-GT: LAN9221, - Bock-W and Marzen: LAN89218AQ. Update the compatible values accordingly. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/59c142176f795b3541c935df43ab11cecd77cc61.1631173813.git.geert+renesas@glider.be
2021-09-28arm64: defconfig: Enable RZG2L_ADCLad Prabhakar1-0/+1
Enable ADC driver support for Renesas RZ/G2L based platforms. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210927193551.22422-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-09-28arm64: defconfig: Enable SND_SOC_WM8978Biju Das1-0/+1
WM8978 audio CODEC is supported on RZ/G2L SMARC EVK. Enable it on arm64 defconfig as module. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210920093905.10878-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-09-27arm64: dts: qcom: sc7280: Update Q6V5 MSS nodeSibi Sankar2-3/+23
Update MSS node to support MSA based modem boot on SC7280 SoCs. Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1631886935-14691-11-git-send-email-sibis@codeaurora.org
2021-09-27arm64: dts: qcom: sc7280: Add Q6V5 MSS nodeSibi Sankar1-0/+40
This patch adds Q6V5 MSS PAS remoteproc node for SC7280 SoCs. Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1631886935-14691-10-git-send-email-sibis@codeaurora.org
2021-09-27arm64: dts: qcom: sc7280: Add nodes to boot modemSibi Sankar1-0/+20
Add miscellaneous nodes to boot the modem and support post-mortem debug on SC7280 SoCs. Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1631886935-14691-9-git-send-email-sibis@codeaurora.org
2021-09-27arm64: dts: qcom: sc7280: Add/Delete/Update reserved memory nodesSibi Sankar1-0/+52
Add, delete and update platform specific reserved memory nodes. Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1631886935-14691-8-git-send-email-sibis@codeaurora.org
2021-09-27arm64: dts: qcom: sc7280: Update reserved memory mapSibi Sankar1-0/+34
Add missing reserved regions as described in v1 of SC7280 memory map. Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1631886935-14691-7-git-send-email-sibis@codeaurora.org