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2021-09-13x86/extable: Remove EX_TYPE_FAULT from MCE safe fixupsThomas Gleixner1-1/+0
Now that the MC safe copy and FPU have been converted to use the MCE safe fixup types remove EX_TYPE_FAULT from the list of types which MCE considers to be safe to be recovered in kernel. This removes the SGX exception handling of ENCLS from the #MC safe handling, but according to the SGX wizards the current SGX implementations cannot survive #MC on ENCLS: https://lore.kernel.org/r/YS+upEmTfpZub3s9@google.com The code relies on the trap number being stored if ENCLS raised an exception. That's still working, but it does no longer trick the MCE code into assuming that #MC is handled correctly for ENCLS. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20210908132525.445255957@linutronix.de
2021-09-13x86/fpu: Use EX_TYPE_FAULT_MCE_SAFE for exception fixupsThomas Gleixner1-2/+2
The macros used for restoring FPU state from a user space buffer can handle all exceptions including #MC. They need to return the trap number in the error case as the code which invokes them needs to distinguish the cause of the failure. It aborts the operation for anything except #PF. Use the new EX_TYPE_FAULT_MCE_SAFE exception table fixup type to document the nature of the fixup. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20210908132525.387464538@linutronix.de
2021-09-13x86/copy_mc: Use EX_TYPE_DEFAULT_MCE_SAFE for exception fixupsThomas Gleixner1-4/+4
Nothing in that code uses the trap number which was stored by the exception fixup which is instantiated via _ASM_EXTABLE_FAULT(). Use _ASM_EXTABLE(... EX_TYPE_DEFAULT_MCE_SAFE) instead which just handles the IP fixup and the type indicates to the #MC handler that the call site can handle the abort caused by #MC correctly. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20210908132525.328706042@linutronix.de
2021-09-13x86/extable: Provide EX_TYPE_DEFAULT_MCE_SAFE and EX_TYPE_FAULT_MCE_SAFEThomas Gleixner3-0/+7
Provide exception fixup types which can be used to identify fixups which allow in kernel #MC recovery and make them invoke the existing handlers. These will be used at places where #MC recovery is handled correctly by the caller. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20210908132525.269689153@linutronix.de
2021-09-13x86/extable: Rework the exception table mechanicsThomas Gleixner11-153/+131
The exception table entries contain the instruction address, the fixup address and the handler address. All addresses are relative. Storing the handler address has a few downsides: 1) Most handlers need to be exported 2) Handlers can be defined everywhere and there is no overview about the handler types 3) MCE needs to check the handler type to decide whether an in kernel #MC can be recovered. The functionality of the handler itself is not in any way special, but for these checks there need to be separate functions which in the worst case have to be exported. Some of these 'recoverable' exception fixups are pretty obscure and just reuse some other handler to spare code. That obfuscates e.g. the #MC safe copy functions. Cleaning that up would require more handlers and exports Rework the exception fixup mechanics by storing a fixup type number instead of the handler address and invoke the proper handler for each fixup type. Also teach the extable sort to leave the type field alone. This makes most handlers static except for special cases like the MCE MSR fixup and the BPF fixup. This allows to add more types for cleaning up the obscure places without adding more handler code and exports. There is a marginal code size reduction for a production config and it removes _eight_ exported symbols. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Borislav Petkov <bp@suse.de> Acked-by: Alexei Starovoitov <ast@kernel.org> Link: https://lkml.kernel.org/r/20210908132525.211958725@linutronix.de
2021-09-13x86/mce: Get rid of stray semicolonsThomas Gleixner1-2/+2
and the random number of tabs. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20210908132525.154428878@linutronix.de
2021-09-13ARM: dts: qcom: apq8064: Use 27MHz PXO clock as DSI PLL referenceMarijn Suijten1-2/+2
The 28NM DSI PLL driver for msm8960 calculates with a 27MHz reference clock and should hence use PXO, not CXO which runs at 19.2MHz. Note that none of the DSI PHY/PLL drivers currently use this "ref" clock; they all rely on (sometimes inexistant) global clock names and usually function normally without a parent clock. This discrepancy will be corrected in a future patch, for which this change needs to be in place first. Fixes: 6969d1d9c615 ("ARM: dts: qcom-apq8064: Set 'cxo_board' as ref clock of the DSI PHY") Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Link: https://lore.kernel.org/r/20210829203027.276143-2-marijn.suijten@somainline.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-09-13ARM: dts: qcom: apq8064: use compatible which contains chipidDavid Heidelberg1-2/+1
Also resolves these kernel warnings for APQ8064: adreno 4300000.adreno-3xx: Using legacy qcom,chipid binding! adreno 4300000.adreno-3xx: Use compatible qcom,adreno-320.2 instead. Tested on Nexus 7 2013, no functional changes. Cc: <stable@vger.kernel.org> Signed-off-by: David Heidelberg <david@ixit.cz> Link: https://lore.kernel.org/r/20210818065317.19822-1-david@ixit.cz Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-09-13arm64: dts: qcom: sdm845: Use RPMH_CE_CLK macro directlyBhupesh Sharma1-2/+2
In commit 3e482859f1ef ("dts: qcom: sdm845: Add dt entries to support crypto engine."), we decided to use the value indicated by constant RPMH_CE_CLK rather than using it directly. Now that the same RPMH clock value might be used for other SoCs (in addition to sdm845), let's use the constant RPMH_CE_CLK to make sure that this dtsi is compatible with the other qcom ones. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Reviewed-by: Thara Gopinath <thara.gopinath@linaro.org> Link: https://lore.kernel.org/r/20210519143700.27392-8-bhupesh.sharma@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-09-13x86/mce: Deduplicate exception handlingThomas Gleixner1-17/+17
Prepare code for further simplification. No functional change. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20210908132525.096452100@linutronix.de
2021-09-13powerpc/mce: Fix access error in mce handlerGanesh Goudar1-2/+15
We queue an irq work for deferred processing of mce event in realmode mce handler, where translation is disabled. Queuing of the work may result in accessing memory outside RMO region, such access needs the translation to be enabled for an LPAR running with hash mmu else the kernel crashes. After enabling translation in mce_handle_error() we used to leave it enabled to avoid crashing here, but now with the commit 74c3354bc1d89 ("powerpc/pseries/mce: restore msr before returning from handler") we are restoring the MSR to disable translation. Hence to fix this enable the translation before queuing the work. Without this change following trace is seen on injecting SLB multihit in an LPAR running with hash mmu. Oops: Kernel access of bad area, sig: 11 [#1] LE PAGE_SIZE=64K MMU=Hash SMP NR_CPUS=2048 NUMA pSeries CPU: 5 PID: 1883 Comm: insmod Tainted: G OE 5.14.0-mce+ #137 NIP: c000000000735d60 LR: c000000000318640 CTR: 0000000000000000 REGS: c00000001ebff9a0 TRAP: 0300 Tainted: G OE (5.14.0-mce+) MSR: 8000000000001003 <SF,ME,RI,LE> CR: 28008228 XER: 00000001 CFAR: c00000000031863c DAR: c00000027fa8fe08 DSISR: 40000000 IRQMASK: 0 ... NIP llist_add_batch+0x0/0x40 LR __irq_work_queue_local+0x70/0xc0 Call Trace: 0xc00000001ebffc0c (unreliable) irq_work_queue+0x40/0x70 machine_check_queue_event+0xbc/0xd0 machine_check_early_common+0x16c/0x1f4 Fixes: 74c3354bc1d89 ("powerpc/pseries/mce: restore msr before returning from handler") Signed-off-by: Ganesh Goudar <ganeshgr@linux.ibm.com> [mpe: Fix comment formatting, trim oops in change log for readability] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20210909064330.312432-1-ganeshgr@linux.ibm.com
2021-09-13KVM: PPC: Book3S HV: Tolerate treclaim. in fake-suspend mode changing registersNicholas Piggin1-2/+34
POWER9 DD2.2 and 2.3 hardware implements a "fake-suspend" mode where certain TM instructions executed in HV=0 mode cause softpatch interrupts so the hypervisor can emulate them and prevent problematic processor conditions. In this fake-suspend mode, the treclaim. instruction does not modify registers. Unfortunately the rfscv instruction executed by the guest do not generate softpatch interrupts, which can cause the hypervisor to lose track of the fake-suspend mode, and it can execute this treclaim. while not in fake-suspend mode. This modifies GPRs and crashes the hypervisor. It's not trivial to disable scv in the guest with HFSCR now, because they assume a POWER9 has scv available. So this fix saves and restores checkpointed registers across the treclaim. Fixes: 7854f7545bff ("KVM: PPC: Book3S: Rework TM save/restore code and make it C-callable") Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20210908101718.118522-2-npiggin@gmail.com
2021-09-13powerpc/64s: system call rfscv workaround for TM bugsNicholas Piggin1-0/+13
The rfscv instruction does not work correctly with the fake-suspend mode in POWER9, which can end up with the hypervisor restoring an incorrect checkpoint. Work around this by setting the _TIF_RESTOREALL flag if a system call returns to a transaction active state, causing rfid to be used instead of rfscv to return, which will do the right thing. The contents of the registers are irrelevant because they will be overwritten in this case anyway. Fixes: 7fa95f9adaee7 ("powerpc/64s: system call support for scv/rfscv instructions") Reported-by: Eirik Fuller <efuller@redhat.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20210908101718.118522-1-npiggin@gmail.com
2021-09-13powerpc/64s: system call scv tabort fix for corrupt irq soft-mask stateNicholas Piggin2-41/+30
If a system call is made with a transaction active, the kernel immediately aborts it and returns. scv system calls disable irqs even earlier in their interrupt handler, and tabort_syscall does not fix this up. This can result in irq soft-mask state being messed up on the next kernel entry, and crashing at BUG_ON(arch_irq_disabled_regs(regs)) in the kernel exit handlers, or possibly worse. This can't easily be fixed in asm because at this point an async irq may have hit, which is soft-masked and marked pending. The pending interrupt has to be replayed before returning to userspace. The fix is to move the tabort_syscall code to C in the main syscall handler, and just skip the system call but otherwise return as usual, which will take care of the pending irqs. This also does a bunch of other things including possible signal delivery to the process, but the doomed transaction should still be aborted when it is eventually returned to. The sc system call path is changed to use the new C function as well to reduce code and path differences. This slows down how quickly system calls are aborted when called while a transaction is active, which could potentially impact TM performance. But making any system call is already bad for performance, and TM is on the way out, so go with simpler over faster. Fixes: 7fa95f9adaee7 ("powerpc/64s: system call support for scv/rfscv instructions") Reported-by: Eirik Fuller <efuller@redhat.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> [mpe: Use #ifdef rather than IS_ENABLED() to fix build error on 32-bit] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20210903125707.1601269-1-npiggin@gmail.com
2021-09-13arm64: dts: fvp: Remove panel timingsRobin Murphy1-12/+0
The simple-panel driver already has hard-coded timings for "arm,rtsm-display", and as such screams at us for trying to override a fixed mode from DT. Since the exact values probably don't matter all that much anyway, just remove the DT node to keep boot quiet. Link: https://lore.kernel.org/r/2701c187cf8e0762df38f68cc069ec2c29a3b5a9.1626283322.git.robin.murphy@arm.com Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2021-09-13x86/extable: Get rid of redundant macrosThomas Gleixner1-24/+12
No point in defining the identical macros twice depending on C or assembly mode. They are still identical. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20210908132525.023659534@linutronix.de
2021-09-13x86/extable: Tidy up redundant handler functionsThomas Gleixner1-11/+5
No need to have the same code all over the place. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20210908132524.963232825@linutronix.de
2021-09-13m68k: mvme: Remove overdue #warnings in RTC handlingGeert Uytterhoeven2-2/+6
The warnings were introduced when converting the MVME147 and MVME16x RTC handling from gettod to hwclk. Replace the #warning by a comment, and return an error to inform the upper layer that writing to the RTC is not yet supported. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Link: https://lore.kernel.org/r/20210907124511.2723414-1-geert@linux-m68k.org
2021-09-13m68k: Double cast io functions to unsigned longGuenter Roeck1-10/+10
m68k builds fail widely with errors such as arch/m68k/include/asm/raw_io.h:20:19: error: cast to pointer from integer of different size arch/m68k/include/asm/raw_io.h:30:32: error: cast to pointer from integer of different size [-Werror=int-to-p On m68k, io functions are defined as macros. The problem is seen if the macro parameter variable size differs from the size of a pointer. Cast the parameter of all io macros to unsigned long before casting it to a pointer to fix the problem. Signed-off-by: Guenter Roeck <linux@roeck-us.net> Link: https://lore.kernel.org/r/20210907060729.2391992-1-linux@roeck-us.net Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2021-09-13arm64: dts: mt8183: add kukui platform audio nodeKansho Nishida21-4/+243
Set pin control for the SoC sound node. The compatibles are set by each model dts. The codecs that each models use are: burnet ts3a227_max98357 damu da7219_max98357 fennel da7219_rt1015p fennel14 da7219_rt1015p juniper ts3a227_max98357 kakadu da7219_rt1015p kappa ts3a227_max98357 kenzo ts3a227_max98357 kodama ts3a227_max98357 krane ts3a227_max98357 willow-sku0 da7219_max98357 willow-sku1 ts3a227_max98357 Signed-off-by: Kansho Nishida <kansho@chromium.org> Link: https://lore.kernel.org/r/20210706190111.v3.2.I6e9ce0f2a489f9a52299656cd966b38ae75e7552@changeid Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-09-13arm64: dts: mt8183: add audio nodeKansho Nishida1-1/+93
Add afe (audio front end) device node to the MT8183 dtsi. Signed-off-by: Kansho Nishida <kansho@chromium.org> Link: https://lore.kernel.org/r/20210706190111.v3.1.I88a52644e47e88b15f5db9841cb084dc53c5875c@changeid Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-09-13arm64: dts: mediatek: Add mt8192 clock controllersChun-Jie Chen1-0/+163
Add clock controller nodes for SoC mt8192 Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Ikjoon Jang <ikjn@chromium.org> Link: https://lore.kernel.org/r/20210727023205.20319-2-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-09-13arm64: dts: amlogic: add support for Radxa ZeroChristian Hewitt2-0/+406
Radxa Zero is a small form factor SBC based on the Amlogic S905Y2 chipset that ships in a number of RAM/eMMC configurations: Boards with 512MB/1GB LPDDR4 RAM have no eMMC storage and BCM43436 wireless (2.4GHz b/g/n) while 2GB/4GB boards have 8/16/32/64/128GB eMMC storage and BCM4345 wireless (2.4/5GHz a/b/g/n/ac). - Amlogic S905Y2 quad-core Cortex-A53 - Mali G31-MP2 GPU - HDMI 2.1 output (micro) - 1x USB 2.0 port - Type C (OTG) - 1x USB 3.0 port - Type C (Host) - 1x micro SD Card slot - 40 Pin GPIO header Signed-off-by: Christian Hewitt <christianshewitt@gmail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20210909102154.22710-3-christianshewitt@gmail.com
2021-09-13arm64: dts: meson: sm1: add Ethernet PHY reset line for ODROID-C4/HC4Dongjin Kim1-0/+4
This patch is to fix an issue that the ethernet link doesn't come up when using ip link set down/up: [ 11.428114] meson8b-dwmac ff3f0000.ethernet eth0: Link is Down [ 14.428595] meson8b-dwmac ff3f0000.ethernet eth0: PHY [0.0:00] driver [RTL8211F Gigabit Ethernet] (irq=31) [ 14.428610] meson8b-dwmac ff3f0000.ethernet: Failed to reset the dma [ 14.428974] meson8b-dwmac ff3f0000.ethernet eth0: stmmac_hw_setup: DMA engine initialization failed [ 14.711185] meson8b-dwmac ff3f0000.ethernet eth0: stmmac_open: Hw setup failed This fix refers to two commits applied for ODROID-N2 (G12B). commit 658e4129bb81 ("arm64: dts: meson: g12b: odroid-n2: add the Ethernet PHY reset line") commit 1c7412530d5d0 ("arm64: dts: meson: g12b: odroid-n2: fix PHY deassert timing requirements") Fixes: 88d537bc92ca ("arm64: dts: meson: convert meson-sm1-odroid-c4 to dtsi") Signed-off-by: Dongjin Kim <tobetter@gmail.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> [narmstrong: added fixes tag and typo in commit log] Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/YScKYFWlYymgGw3l@anyang-linuxfactory-or-kr
2021-09-13arm64: dts: allwinner: a64: Add GPU opp tableJernej Skrabec1-0/+17
GPU on A64 currently runs at default frequency, which is 297 MHz. This is a bit low in some cases and noticeable lag can be observed in GPU rendered UIs. GPU is capable to run at 432 MHz. Add GPU OPP table. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20210912095032.2397824-1-jernej.skrabec@gmail.com
2021-09-13ARM: dts: sun8i: r40: Add I2S nodesJernej Skrabec1-0/+39
Allwinner R40 has 3 I2S controllers, compatible to those in H3. First two are routed to pins, while third is used internally for HDMI audio. Add nodes for all 3 I2S controllers. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20210912072914.398419-3-jernej.skrabec@gmail.com
2021-09-13arm64: dts: allwinner: h5: NanoPI Neo 2: Fix ethernet nodeClément Bœsch1-1/+1
RX and TX delay are provided by ethernet PHY. Reflect that in ethernet node. Fixes: 44a94c7ef989 ("arm64: dts: allwinner: H5: Restore EMAC changes") Signed-off-by: Clément Bœsch <u@pkh.me> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20210905002027.171984-1-u@pkh.me
2021-09-13arm64: dts: allwinner: teres-i: Remove wakekup-source from the PMICMaxime Ripard1-1/+0
Neither the binding nor the driver make any use of the wakeup-source property for the AXP803. Remove it. Signed-off-by: Maxime Ripard <maxime@cerno.tech> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20210901091852.479202-53-maxime@cerno.tech
2021-09-13arm64: dts: allwinner: teres-i: Add missing regMaxime Ripard1-0/+2
The anx6345 bridge mandates that the input port is named port@0. Since we have a unit-address, this implies that we need a reg property with the same value, but it was found to be missing in the Teres-I device tree. Make sure it's there. Signed-off-by: Maxime Ripard <maxime@cerno.tech> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20210901091852.479202-52-maxime@cerno.tech
2021-09-13arm64: dts: allwinner: pinetab: Change regulator node name to avoid warningMaxime Ripard1-1/+1
The fixed regulator clock name has a unit address, but no reg property, which generates a warning in DTC. Change its name to remove its useless unit address. Signed-off-by: Maxime Ripard <maxime@cerno.tech> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20210901091852.479202-51-maxime@cerno.tech
2021-09-13arm64: dts: allwinner: a100: Fix thermal zone node nameMaxime Ripard1-3/+3
The thermal zones one the A100 are called $device-thermal-zone. However, the thermal zone binding explicitly requires that zones are called *-thermal. Let's fix it. Signed-off-by: Maxime Ripard <maxime@cerno.tech> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20210901091852.479202-50-maxime@cerno.tech
2021-09-13arm64: dts: allwinner: h6: Fix de3 parent clocks orderingMaxime Ripard1-4/+4
While it doesn't really matter from a functional point of view in this driver's case, it's usually a good practice to list the clocks in a driver in the same driver across all its users. The H6 is using the inverse order than all the other users, so let's make it consistent. Signed-off-by: Maxime Ripard <maxime@cerno.tech> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20210901091852.479202-49-maxime@cerno.tech
2021-09-13arm64: dts: allwinner: h5: Fix GPU thermal zone node nameMaxime Ripard1-1/+1
The GPU thermal zone is named gpu_thermal. However, the underscore is an invalid character for a node name and the thermal zone binding explicitly requires that zones are called *-thermal. Let's fix it. Signed-off-by: Maxime Ripard <maxime@cerno.tech> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20210901091852.479202-48-maxime@cerno.tech
2021-09-13ARM: dts: cubieboard4: Remove the dumb-vga-dac compatibleMaxime Ripard1-1/+1
The dumb-vga-dac and adi,adv7123 compatibles are not supposed to be used together according to the binding. Since the corpro gm7123 is a drop-in replacement for the adv7123, let's remove dumb-vga-dac from our compatible list. Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20210901091852.479202-47-maxime@cerno.tech
2021-09-13ARM: dts: tbs711: Fix touchscreen compatibleMaxime Ripard1-1/+1
The edt,edt-ft5x06 compatible has never been a valid compatible according to the binding. Let's change for one that is. Signed-off-by: Maxime Ripard <maxime@cerno.tech> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20210901091852.479202-46-maxime@cerno.tech
2021-09-13ARM: dts: sunxi: Fix the SPI NOR node namesMaxime Ripard3-3/+3
According to the SPI NOR bindings, the flash node names are supposed to be flash@<address>. Let's fix our users to use that new scheme. Signed-off-by: Maxime Ripard <maxime@cerno.tech> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20210901091852.479202-44-maxime@cerno.tech
2021-09-13ARM: dts: sunxi: Fix OPPs node nameMaxime Ripard6-9/+9
The operating-points-v2 nodes are named inconsistently, but mostly either opp_table0 or gpu-opp-table. However, the underscore is an invalid character for a node name and the thermal zone binding explicitly requires that zones are called opp-table-*. Let's fix it. Signed-off-by: Maxime Ripard <maxime@cerno.tech> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20210901091852.479202-43-maxime@cerno.tech
2021-09-13ARM: dts: sunxi: Fix OPP arraysMaxime Ripard6-71/+61
Even though it translates to the same thing down to the binary level, we should have an array of 2 number cells to describe each OPP, which in turns create a validation warning. Let's fix this. Signed-off-by: Maxime Ripard <maxime@cerno.tech> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20210901091852.479202-42-maxime@cerno.tech
2021-09-13ARM: dts: sunxi: Rename gpio pinctrl namesMaxime Ripard2-4/+4
We've had a pinctrl node name convention for a while now, let's follow it for the AXP pinctrl nodes as well. Signed-off-by: Maxime Ripard <maxime@cerno.tech> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20210901091852.479202-41-maxime@cerno.tech
2021-09-13ARM: dts: sunxi: Rename power-supply namesMaxime Ripard4-12/+12
The name of our PMIC power supply names conflict with the generic regulator supply check that matches anything called *-supply, including the nodes, and then makes sure it's a phandle. A node is obviously not a phandle, so let's change our power supplies names to avoid any conflict. Signed-off-by: Maxime Ripard <maxime@cerno.tech> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20210901091852.479202-40-maxime@cerno.tech
2021-09-13ARM: sunxi: Add a missing SPDX license headerJason Wang1-3/+1
Add the missing SPDX license header to arch/arm/mach-sunxi/platsmp.c. Signed-off-by: Jason Wang <wangborong@cdjrlc.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20210810133138.109309-1-wangborong@cdjrlc.com
2021-09-13ARM: sunxi: Add a missing SPDX license headerJason Wang1-3/+1
Add the missing SPDX license header to arch/arm/mach-sunxi/sunxi.c. Signed-off-by: Jason Wang <wangborong@cdjrlc.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20210810132954.107518-1-wangborong@cdjrlc.com
2021-09-13arm64: zynqmp: Wire psgtr for zc1751-xm013Michal Simek1-0/+26
Add psgtr description for SATA and USB. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/8c78625f08c16385a4798e0a62d20df7491ac00e.1628244860.git.michal.simek@xilinx.com
2021-09-13arm64: zynqmp: Enable xlnx,zynqmp-dwc3 driver for xilinx boardsMichal Simek10-21/+122
The commit 84770f028fab ("usb: dwc3: Add driver for Xilinx platforms") finally add proper support for Xilinx dwc3 driver. This patch is adding DT description for it. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Michael Tretter <m.tretter@pengutronix.de> Link: https://lore.kernel.org/r/640a3bc0dc3e32560d3e84c2f78b5ae561396eb0.1628244703.git.michal.simek@xilinx.com
2021-09-13arm64: zynqmp: Enable gpio and qspi for zc1275-revAMichal Simek1-1/+17
Add missing gpio and qspio for zc1275-revA board. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/839d833133318feeb2755c4431204b0ef4788cce.1628244299.git.michal.simek@xilinx.com
2021-09-13arm64: zynqmp: Fix serial compatible stringMichal Simek1-2/+2
Based on commit 65a2c14d4f00 ("dt-bindings: serial: convert Cadence UART bindings to YAML") compatible string should look like differently that's why fix it to be aligned with dt binding. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://lore.kernel.org/r/89b36e0a6187cc6b05b27a035efdf79173bd4486.1628240307.git.michal.simek@xilinx.com
2021-09-13arm64: zynqmp: Remove not documented is-dual propertyMichal Simek3-6/+3
Remove is-dual not documented property and also update comment about QSPI sizes to reflect dual configuration as 16MB + 16MB. Only single configuration is supported now. Reported-by: Quanyang Wang <quanyang.wang@windriver.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://lore.kernel.org/r/876c53b92f99623bae45d5c0c5ae79ee3e24f745.1628239345.git.michal.simek@xilinx.com
2021-09-13arm64: zynqmp: Add psgtr description to zc1751 dc1 boardMichal Simek1-0/+3
Wire psgtr for zc1751 dc1 board. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/51d9a5e0aa26b0ea79b8823bf3d15f4e2542f927.1623684253.git.michal.simek@xilinx.com
2021-09-13arm64: zynqmp: Add support for zcu102-rev1.1 boardMichal Simek2-0/+16
zcu102 rev1.1 compare to rev1.0 is using by default different DDR memory which requires different configuration. The reason for adding this file to Linux kernel is that U-Boot fdtfile variable is composed based on board revision (in eeprom) and dtb file should exist in standard distibutions for passing it to Linux kernel. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/38bbbeb885f4d9ba466c43ab9b4d25190a3552fb.1623684253.git.michal.simek@xilinx.com
2021-09-13arm64: zynqmp: Remove description for 8T49N287 and si5382 chipsMichal Simek3-9/+3
Based on commit 73d677e9f379 ("arm64: dts: zynqmp: Remove si5328 device nodes") also remove description for clock chips which don't have Linux driver yet. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/7557288230567fa136ba3edc004d5bfe4f4c6590.1623684253.git.michal.simek@xilinx.com
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