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2021-02-01arm64: dts: rockchip: Remove bogus "amba" bus nodesRobin Murphy5-120/+85
The "amba" bus nodes wrapping all the DMA-330 nodes serve no useful purpose, and certainly bear no relation at all to the actual underlying interconnect topology. They appear to be cargo-cult copying from a design misstep in the very early days of FDT adoption on ARM, which was righted with the "arm,primecell" compatible, and the last trace of the idea finally purged by commit 2ef7d5f342c1 ("ARM, ARM64: dts: drop "arm,amba-bus" in favor of "simple-bus""). As such, they can simply be removed and the DMA-330 nodes fitted into the normal sort order. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Link: https://lore.kernel.org/r/131e0ea065109760ea3b59c4bb90cf4fac7826f7.1611186142.git.robin.murphy@arm.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-02-01arm64: dts: rockchip: Light "sys" LED on NanoPi R2SRobin Murphy1-0/+1
Set NanoPi R2S's "sys" LED to be on by default. This matches the behaviour of the stock FriendlyWRT image, and makes it much easier to tell when the thing has finished booting. Suitable triggers for the two network LEDs cannot realistically be configured from DT, so leave them be. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Link: https://lore.kernel.org/r/f066be60aa99460a45d04113c5e507d6602186f1.1611187213.git.robin.murphy@arm.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-02-01arm64: dts: rockchip: fix ranges property format for rk3399 pcie nodeJohan Jonker1-2/+2
A test with the command below gives for example this error: /arch/arm64/boot/dts/rockchip/rk3399-evb.dt.yaml: pcie@f8000000: ranges: 'oneOf' conditional failed, one must be fixed: The pcie ranges property is an array. The dt-check expects that each array item is wrapped with angle brackets, so fix that ranges property format for the rk3399 pcie node. make ARCH=arm64 dtbs_check DT_SCHEMA_FILES=~/.local/lib/python3.5/site-packages/dtschema/ schemas/pci/pci-bus.yaml Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20210122171243.16138-1-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-02-01arm64: dts: rockchip: Rely on SoC external pull up on pmic-int-l on Helios64Uwe Kleine-König1-1/+1
According to the schematic there is an external pull up, so there is no need to enable the internal one additionally. Using no pull up matches the vendor device tree. Signed-off-by: Uwe Kleine-König <uwe@kleine-koenig.org> Link: https://lore.kernel.org/r/20210124210328.611707-2-uwe@kleine-koenig.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-02-01KVM: x86: Supplement __cr4_reserved_bits() with X86_FEATURE_PCID checkVitaly Kuznetsov1-0/+2
Commit 7a873e455567 ("KVM: selftests: Verify supported CR4 bits can be set before KVM_SET_CPUID2") reveals that KVM allows to set X86_CR4_PCIDE even when PCID support is missing: ==== Test Assertion Failure ==== x86_64/set_sregs_test.c:41: rc pid=6956 tid=6956 - Invalid argument 1 0x000000000040177d: test_cr4_feature_bit at set_sregs_test.c:41 2 0x00000000004014fc: main at set_sregs_test.c:119 3 0x00007f2d9346d041: ?? ??:0 4 0x000000000040164d: _start at ??:? KVM allowed unsupported CR4 bit (0x20000) Add X86_FEATURE_PCID feature check to __cr4_reserved_bits() to make kvm_is_valid_cr4() fail. Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com> Message-Id: <20210201142843.108190-1-vkuznets@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-02-01KVM/x86: assign hva with the right value to vm_munmap the pagesZheng Zhan Liang1-1/+1
Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Wanpeng Li <wanpengli@tencent.com> Cc: kvm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Zheng Zhan Liang <zhengzhanliang@huorong.cn> Message-Id: <20210201055310.267029-1-zhengzhanliang@huorong.cn> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-02-01KVM: x86: Allow guests to see MSR_IA32_TSX_CTRL even if tsx=offPaolo Bonzini2-13/+30
Userspace that does not know about KVM_GET_MSR_FEATURE_INDEX_LIST will generally use the default value for MSR_IA32_ARCH_CAPABILITIES. When this happens and the host has tsx=on, it is possible to end up with virtual machines that have HLE and RTM disabled, but TSX_CTRL available. If the fleet is then switched to tsx=off, kvm_get_arch_capabilities() will clear the ARCH_CAP_TSX_CTRL_MSR bit and it will not be possible to use the tsx=off hosts as migration destinations, even though the guests do not have TSX enabled. To allow this migration, allow guests to write to their TSX_CTRL MSR, while keeping the host MSR unchanged for the entire life of the guests. This ensures that TSX remains disabled and also saves MSR reads and writes, and it's okay to do because with tsx=off we know that guests will not have the HLE and RTM features in their CPUID. (If userspace sets bogus CPUID data, we do not expect HLE and RTM to work in guests anyway). Cc: stable@vger.kernel.org Fixes: cbbaa2727aa3 ("KVM: x86: fix presentation of TSX feature in ARCH_CAPABILITIES") Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-02-01arm64: hibernate: add __force attribute to gfp_t castingPavel Tatashin1-2/+2
Two new warnings are reported by sparse: "sparse warnings: (new ones prefixed by >>)" >> arch/arm64/kernel/hibernate.c:181:39: sparse: sparse: cast to restricted gfp_t >> arch/arm64/kernel/hibernate.c:202:44: sparse: sparse: cast from restricted gfp_t gfp_t has __bitwise type attribute and requires __force added to casting in order to avoid these warnings. Fixes: 50f53fb72181 ("arm64: trans_pgd: make trans_pgd_map_page generic") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Pavel Tatashin <pasha.tatashin@soleen.com> Link: https://lore.kernel.org/r/20210201150306.54099-2-pasha.tatashin@soleen.com Signed-off-by: Will Deacon <will@kernel.org>
2021-02-01x86/debug: Fix DR6 handlingPeter Zijlstra1-21/+18
Tom reported that one of the GDB test-cases failed, and Boris bisected it to commit: d53d9bc0cf78 ("x86/debug: Change thread.debugreg6 to thread.virtual_dr6") The debugging session led us to commit: 6c0aca288e72 ("x86: Ignore trap bits on single step exceptions") It turns out that TF and data breakpoints are both traps and will be merged, while instruction breakpoints are faults and will not be merged. This means 6c0aca288e72 is wrong, only TF and instruction breakpoints need to be excluded while TF and data breakpoints can be merged. [ bp: Massage commit message. ] Fixes: d53d9bc0cf78 ("x86/debug: Change thread.debugreg6 to thread.virtual_dr6") Fixes: 6c0aca288e72 ("x86: Ignore trap bits on single step exceptions") Reported-by: Tom de Vries <tdevries@suse.de> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Signed-off-by: Borislav Petkov <bp@suse.de> Cc: <stable@vger.kernel.org> Link: https://lkml.kernel.org/r/YBMAbQGACujjfz%2Bi@hirez.programming.kicks-ass.net Link: https://lkml.kernel.org/r/20210128211627.GB4348@worktop.programming.kicks-ass.net
2021-02-01perf/x86/intel: Support CPUID 10.ECX to disable fixed countersKan Liang3-11/+36
With Architectural Performance Monitoring Version 5, CPUID 10.ECX cpu leaf indicates the fixed counter enumeration. This extends the previous count to a bitmap which allows disabling even lower fixed counters. It could be used by a Hypervisor. The existing intel_ctrl variable is used to remember the bitmask of the counters. All code that reads all counters is fixed to check this extra bitmask. Suggested-by: Peter Zijlstra (Intel) <peterz@infradead.org> Originally-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lkml.kernel.org/r/1611873611-156687-6-git-send-email-kan.liang@linux.intel.com
2021-02-01perf/x86/intel: Add perf core PMU support for Sapphire RapidsKan Liang4-12/+433
Add perf core PMU support for the Intel Sapphire Rapids server, which is the successor of the Intel Ice Lake server. The enabling code is based on Ice Lake, but there are several new features introduced. The event encoding is changed and simplified, e.g., the event codes which are below 0x90 are restricted to counters 0-3. The event codes which above 0x90 are likely to have no restrictions. The event constraints, extra_regs(), and hardware cache events table are changed accordingly. A new Precise Distribution (PDist) facility is introduced, which further minimizes the skid when a precise event is programmed on the GP counter 0. Enable the Precise Distribution (PDist) facility with :ppp event. For this facility to work, the period must be initialized with a value larger than 127. Add spr_limit_period() to apply the limit for :ppp event. Two new data source fields, data block & address block, are added in the PEBS Memory Info Record for the load latency event. To enable the feature, - An auxiliary event has to be enabled together with the load latency event on Sapphire Rapids. A new flag PMU_FL_MEM_LOADS_AUX is introduced to indicate the case. A new event, mem-loads-aux, is exposed to sysfs for the user tool. Add a check in hw_config(). If the auxiliary event is not detected, return an unique error -ENODATA. - The union perf_mem_data_src is extended to support the new fields. - Ice Lake and earlier models do not support block information, but the fields may be set by HW on some machines. Add pebs_no_block to explicitly indicate the previous platforms which don't support the new block fields. Accessing the new block fields are ignored on those platforms. A new store Latency facility is introduced, which leverages the PEBS facility where it can provide additional information about sampled stores. The additional information includes the data address, memory auxiliary info (e.g. Data Source, STLB miss) and the latency of the store access. To enable the facility, the new event (0x02cd) has to be programed on the GP counter 0. A new flag PERF_X86_EVENT_PEBS_STLAT is introduced to indicate the event. The store_latency_data() is introduced to parse the memory auxiliary info. The layout of access latency field of PEBS Memory Info Record has been changed. Two latency, instruction latency (bit 15:0) and cache access latency (bit 47:32) are recorded. - The cache access latency is similar to previous memory access latency. For loads, the latency starts by the actual cache access until the data is returned by the memory subsystem. For stores, the latency starts when the demand write accesses the L1 data cache and lasts until the cacheline write is completed in the memory subsystem. The cache access latency is stored in low 32bits of the sample type PERF_SAMPLE_WEIGHT_STRUCT. - The instruction latency starts by the dispatch of the load operation for execution and lasts until completion of the instruction it belongs to. Add a new flag PMU_FL_INSTR_LATENCY to indicate the instruction latency support. The instruction latency is stored in the bit 47:32 of the sample type PERF_SAMPLE_WEIGHT_STRUCT. Extends the PERF_METRICS MSR to feature TMA method level 2 metrics. The lower half of the register is the TMA level 1 metrics (legacy). The upper half is also divided into four 8-bit fields for the new level 2 metrics. Expose all eight Topdown metrics events to user space. The full description for the SPR features can be found at Intel Architecture Instruction Set Extensions and Future Features Programming Reference, 319433-041. Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lkml.kernel.org/r/1611873611-156687-5-git-send-email-kan.liang@linux.intel.com
2021-02-01perf/x86/intel: Filter unsupported Topdown metrics eventKan Liang3-4/+22
Intel Sapphire Rapids server will introduce 8 metrics events. Intel Ice Lake only supports 4 metrics events. A perf tool user may mistakenly use the unsupported events via RAW format on Ice Lake. The user can still get a value from the unsupported Topdown metrics event once the following Sapphire Rapids enabling patch is applied. To enable the 8 metrics events on Intel Sapphire Rapids, the INTEL_TD_METRIC_MAX has to be updated, which impacts the is_metric_event(). The is_metric_event() is a generic function. On Ice Lake, the newly added SPR metrics events will be mistakenly accepted as metric events on creation. At runtime, the unsupported Topdown metrics events will be updated. Add a variable num_topdown_events in x86_pmu to indicate the available number of the Topdown metrics event on the platform. Apply the number into is_metric_event(). Only the supported Topdown metrics events should be created as metrics events. Apply the num_topdown_events in icl_update_topdown_event() as well. The function can be reused by the following patch. Suggested-by: Peter Zijlstra (Intel) <peterz@infradead.org> Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lkml.kernel.org/r/1611873611-156687-4-git-send-email-kan.liang@linux.intel.com
2021-02-01perf/x86/intel: Factor out intel_update_topdown_event()Kan Liang1-7/+13
Similar to Ice Lake, Intel Sapphire Rapids server also supports the topdown performance metrics feature. The difference is that Intel Sapphire Rapids server extends the PERF_METRICS MSR to feature TMA method level two metrics, which will introduce 8 metrics events. Current icl_update_topdown_event() only check 4 level one metrics events. Factor out intel_update_topdown_event() to facilitate the code sharing between Ice Lake and Sapphire Rapids. Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lkml.kernel.org/r/1611873611-156687-3-git-send-email-kan.liang@linux.intel.com
2021-02-01perf/core: Add PERF_SAMPLE_WEIGHT_STRUCTKan Liang2-9/+10
Current PERF_SAMPLE_WEIGHT sample type is very useful to expresses the cost of an action represented by the sample. This allows the profiler to scale the samples to be more informative to the programmer. It could also help to locate a hotspot, e.g., when profiling by memory latencies, the expensive load appear higher up in the histograms. But current PERF_SAMPLE_WEIGHT sample type is solely determined by one factor. This could be a problem, if users want two or more factors to contribute to the weight. For example, Golden Cove core PMU can provide both the instruction latency and the cache Latency information as factors for the memory profiling. For current X86 platforms, although meminfo::latency is defined as a u64, only the lower 32 bits include the valid data in practice (No memory access could last than 4G cycles). The higher 32 bits can be used to store new factors. Add a new sample type, PERF_SAMPLE_WEIGHT_STRUCT, to indicate the new sample weight structure. It shares the same space as the PERF_SAMPLE_WEIGHT sample type. Users can apply either the PERF_SAMPLE_WEIGHT sample type or the PERF_SAMPLE_WEIGHT_STRUCT sample type to retrieve the sample weight, but they cannot apply both sample types simultaneously. Currently, only X86 and PowerPC use the PERF_SAMPLE_WEIGHT sample type. - For PowerPC, there is nothing changed for the PERF_SAMPLE_WEIGHT sample type. There is no effect for the new PERF_SAMPLE_WEIGHT_STRUCT sample type. PowerPC can re-struct the weight field similarly later. - For X86, the same value will be dumped for the PERF_SAMPLE_WEIGHT sample type or the PERF_SAMPLE_WEIGHT_STRUCT sample type for now. The following patches will apply the new factors for the PERF_SAMPLE_WEIGHT_STRUCT sample type. The field in the union perf_sample_weight should be shared among different architectures. A generic name is required, but it's hard to abstract a name that applies to all architectures. For example, on X86, the fields are to store all kinds of latency. While on PowerPC, it stores MMCRA[TECX/TECM], which should not be latency. So a general name prefix 'var$NUM' is used here. Suggested-by: Peter Zijlstra (Intel) <peterz@infradead.org> Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lkml.kernel.org/r/1611873611-156687-2-git-send-email-kan.liang@linux.intel.com
2021-02-01KVM: arm64: Make gen-hyprel endianness agnosticMarc Zyngier2-16/+42
gen-hyprel is, for better or worse, a native-endian program: it assumes that the ELF data structures are in the host's endianness, and even assumes that the compiled kernel is little-endian in one particular case. None of these assumptions hold true though: people actually build (use?) BE arm64 kernels, and seem to avoid doing so on BE hosts. Madness! In order to solve this, wrap each access to the ELF data structures with the required byte-swapping magic. This requires to obtain the kernel data structure, and provide per-endianess wrappers. This result in a kernel that links and even boots in a model. Fixes: 8c49b5d43d4c ("KVM: arm64: Generate hyp relocation data") Reported-by: Guenter Roeck <linux@roeck-us.net> Tested-by: Guenter Roeck <linux@roeck-us.net> Acked-by: David Brazdil <dbrazdil@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org>
2021-02-01arm64: dts: zynqmp: Wire up the DisplayPort subsystemLaurent Pinchart6-0/+85
Enable the dpsub device and wire it up to the PS-GTR PHY lanes routed to the DisplayPort connector. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/9769d4d103b6eb75e3324825117f6832a746004e.1611232558.git.michal.simek@xilinx.com
2021-02-01arm64: dts: zynqmp: Add DisplayPort subsystemMichal Simek2-0/+28
Add a DT node for the DisplayPort subsystem, a hard IP present in the Zynq Ultrascale+ MPSoC. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/4d978aef852cacdfb35aa8e50d648a787e73b90c.1611232558.git.michal.simek@xilinx.com
2021-02-01arm64: dts: zynqmp: Add DPDMA nodeLaurent Pinchart2-0/+14
Add a DT node for the DisplayPort DMA engine (DPDMA). Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/3d11015512a085592f2aca76eeddc04178d38bbe.1611232558.git.michal.simek@xilinx.com
2021-02-01arm64: dts: zynqmp: Add description for zcu104 revCMichal Simek2-0/+283
Xilinx ZynqMP zcu104 revC and newer board revisions have different i2c structure compare to revA. The rest of the board is the same from software perspective. Also enable DMAs and QSPI. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/17f68c235ea1ce96c3293ca0cf3178951d6663f7.1611224800.git.michal.simek@xilinx.com
2021-02-01arm64: dts: zynqmp: Add missing iommu IDsMichal Simek1-0/+52
Add missing iommu IDs to all IPs which have IDs assigned. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/78afdafdc60c3182318894f2808f7f337a798278.1611224800.git.michal.simek@xilinx.com
2021-02-01arm64: dts: zynqmp: Add missing lpd watchdog nodeMichal Simek2-0/+13
Xilinx ZynqMP SoC has FPD (Full Power Domain) and LPD (Low Power Domain) watchdogs. There are cases where also LPD WDT should be used by Arm cores that's why list it with disabled status. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/0489a1d5528614f1d570ea153d38b813f0c1eb9f.1611224800.git.michal.simek@xilinx.com
2021-02-01arm64: dts: zynqmp: Wire zynqmp qspi controllerMichal Simek2-0/+18
Add missing ZynqMP qspi IP. It works in single mode only. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/5cebbc59a452f282c4ce0f0e1dffecadac8f126a.1611224800.git.michal.simek@xilinx.com
2021-02-01arm64: dts: zynqmp: Wire arasan nand controllerMichal Simek2-0/+16
Add missing arasan controller with clocks. Disable it by default. Every board can enable it with specifying others properties. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/05cc1ce7973ac5200aeca428c137b422c827c5e8.1611224800.git.michal.simek@xilinx.com
2021-02-01arm64: dts: zynqmp: Add missing mio-bank properties to sdhcisMichal Simek5-0/+6
Add missing xlnx,mio-bank property to sdhci nodes. Also add properties with 0 value to have it listed in case that files are copied to different projects where default case doesn't need to be handled in the same way. That's why explicitly list them too. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/dbdfcc1b25af8b28fc658a37ce18902978cb410d.1611224800.git.michal.simek@xilinx.com
2021-02-01arm64: dts: zynqmp: Add label for zynqmp_ipiMichal Simek1-1/+1
Add label which is used by bootloader for adding bootloader specific flag. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/3dc8416abdd3498e61edcd83830a12af295c5c6d.1611224800.git.michal.simek@xilinx.com
2021-02-01arm64: dts: zynqmp: Enable phy driver for Sata on zcu102/zcu104/zcu106Michal Simek4-0/+58
Enable psgtr driver and write clocks property to get sata to work. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/80b52ef97501968ee97fc152363bc4b9b7bb2cff.1611224800.git.michal.simek@xilinx.com
2021-02-01arm64: dts: zynqmp: Enable reset controller driverMichal Simek1-0/+5
Enable reset controller to be prepared for use. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/4fb62952f61e5046d750fff0e3e469c7abd1d0d0.1611224800.git.michal.simek@xilinx.com Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2021-02-01arm64: dts: zynqmp: Enable si5341 driver for zcu102/106/111Michal Simek3-2/+145
Enable si5341 driver is the main chip for providing preprogrammed clocks for the whole platform. # cat /sys/kernel/debug/clk/clk_summary ... refhdmi 1 1 0 114285000 0 0 50000 xtal_0 0 0 0 114285000 0 0 50000 pll_0 0 0 0 40731174000000 0 0 50000 clk1_0 0 0 0 27000000 0 0 50000 clk0_0 0 0 0 27000000 0 0 50000 ref48M 1 2 0 48000000 0 0 50000 si5341 0 4 0 14000000 0 0 50000 clock-generator.N4 0 0 0 0 0 0 50000 clock-generator.N3 0 1 0 733260000 0 0 50000 clock-generator.9 0 1 0 33330000 0 0 50000 clock-generator.N2 0 1 0 104000000 0 0 50000 clock-generator.2 0 1 0 26000000 0 0 50000 clock-generator.N1 0 2 0 594000000 0 0 50000 clock-generator.7 0 1 0 74250000 0 0 50000 clock-generator.0 0 1 0 27000000 0 0 50000 clock-generator.N0 0 4 0 1000000000 0 0 50000 clock-generator.8 0 0 0 0 0 0 50000 clock-generator.6 0 1 0 125000000 0 0 50000 clock-generator.5 0 1 0 100000000 0 0 50000 clock-generator.4 0 1 0 100000000 0 0 50000 clock-generator.3 0 1 0 125000000 0 0 50000 clock-generator.1 0 0 0 0 0 0 50000 ... Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/b93f13297684704a60e8d7274009a20aa98d14f7.1611224800.git.michal.simek@xilinx.com
2021-02-01arm64: dts: zynqmp: Add DT description for si5328 for zcu102/zcu106Michal Simek2-0/+39
Origin DT binding just specify driver but wasn't aligned with DT binding which came later. Extend description for zcu102 and zcu106 to cover latest binding. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/82b2b13006307f108ace81c50c213c3857078b57.1611224800.git.michal.simek@xilinx.com
2021-02-01arm64: dts: zynqmp: Fix u48 si5382 chip on zcu111Michal Simek1-1/+1
u48 chip on zcu111 is si5382 not si5328. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/cefda1a894fb54059aa1b018e4ecad0eb36fdc9d.1611224800.git.michal.simek@xilinx.com
2021-02-01arm64: configs: Support DEVAPC on MediaTek platformsNeal Liu1-0/+1
Support DEVAPC on MediaTek platforms by enabling CONFIG_MTK_DEVAPC. Signed-off-by: Neal Liu <neal.liu@mediatek.com> Link: https://lore.kernel.org/r/1608713092-26952-3-git-send-email-neal.liu@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-02-01arm64: dts: mt8183: Fix GCE include pathMatthias Brugger1-1/+1
The header file of GCE should be for MT8183 SoC instead of MT8173. Fixes: 91f9c963ce79 ("arm64: dts: mt8183: Add display nodes for MT8183") Reported-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: Matthias Brugger <mbrugger@suse.com> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> Link: https://lore.kernel.org/r/20210131101726.804-1-matthias.bgg@kernel.org Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-02-01kbuild: remove PYTHON variableMasahiro Yamada2-2/+2
Python retired in 2020, and some distributions do not provide the 'python' command any more. As in commit 51839e29cb59 ("scripts: switch explicitly to Python 3"), we need to use more specific 'python3' to invoke scripts even if they are written in a way compatible with both Python 2 and 3. This commit removes the variable 'PYTHON', and switches the existing users to 'PYTHON3'. BTW, PEP 394 (https://www.python.org/dev/peps/pep-0394/) is a helpful material. Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
2021-01-31Merge tag 'x86_entry_for_v5.11_rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tipLinus Torvalds1-10/+5
Pull x86 fix from Borislav Petkov: "A single fix for objtool to generate proper unwind info for newer toolchains which do not generate section symbols anymore. And a cleanup ontop. This was originally going to go during the next merge window but people can already trigger a build error with binutils-2.36 which doesn't emit section symbols - something which objtool relies on - so let's expedite it" * tag 'x86_entry_for_v5.11_rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/entry: Remove put_ret_addr_in_rdi THUNK macro argument x86/entry: Emit a symbol for register restoring thunk
2021-01-31Merge tag 'powerpc-5.11-6' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linuxLinus Torvalds1-12/+16
Pull powerpc fix from Michael Ellerman: "One fix for a bug in our soft interrupt masking, which could lead to interrupt replaying recursing, causing spurious interrupts. Thanks to Nicholas Piggin" * tag 'powerpc-5.11-6' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: powerpc/64s: prevent recursive replay_soft_interrupts causing superfluous interrupt
2021-01-31ARM: dts: sunxi: Rename nmi_intc to r_intcSamuel Holland15-15/+15
The R_INTC block controls more than just the NMI, and it is a different hardware block than the NMI INTC found in some other Allwinner SoCs, so the label "nmi_intc" is inaccurate. Name it "r_intc" to match the compatible and to match the few references in the vendor documentation. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20210118055040.21910-6-samuel@sholland.org
2021-01-31ARM: dts: sun8i: h2-plus: bananapi-m2-zero: Increase BT UART speedJernej Skrabec1-0/+1
Bluetooth module on BananaPi M2 Zero can also be used for streaming audio. However, for that case higher UART speed is required. Add a max-speed property. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20210116103710.245617-1-jernej.skrabec@siol.net
2021-01-31ARM: dts: sunxi: bananapi-m2-plus: Increase BT UART speedJernej Skrabec1-0/+1
Bluetooth module on BananaPi M2 Plus can also be used for streaming audio. However, for that case higher UART speed is required. Add a max-speed property. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20210116105228.847073-1-jernej.skrabec@siol.net
2021-01-31arm64: dts: allwinner: pine-h64: Fix typos in BT GPIOsMaxime Ripard1-2/+2
The commit 53441b8ef7de ("arm64: dts: allwinner: h6: PineH64 model B: Add bluetooth") introduced the Bluetooth chip for the PineH64 model B, but the GPIOs property didn't conform to the binding of the bluetooth chip. Let's fix this. Fixes: 53441b8ef7de ("arm64: dts: allwinner: h6: PineH64 model B: Add bluetooth") Signed-off-by: Maxime Ripard <maxime@cerno.tech> Acked-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Jernej Skrabec <jernej.skrabec@siol.net> Link: https://lore.kernel.org/r/20210114113538.1233933-19-maxime@cerno.tech
2021-01-31arm64: dts: allwinner: pinetab: Fix the panel compatibleMaxime Ripard1-1/+1
The commit 7fa40ca7ef61 ("arm64: allwinner: dts: a64: add DT for Early Adopter's PineTab") introduced an ili9881-based panel device node but didn't conform to the binding. Fix this. Fixes: 7fa40ca7ef61 ("arm64: allwinner: dts: a64: add DT for Early Adopter's PineTab") Signed-off-by: Maxime Ripard <maxime@cerno.tech> Acked-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Jernej Skrabec <jernej.skrabec@siol.net> Link: https://lore.kernel.org/r/20210114113538.1233933-18-maxime@cerno.tech
2021-01-31arm64: dts: allwinner: pinephone: Remove useless light sensor suppliesMaxime Ripard1-2/+0
The stk3311 binding don't expect a vdd or leda power supplies. Remove them. Signed-off-by: Maxime Ripard <maxime@cerno.tech> Acked-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Jernej Skrabec <jernej.skrabec@siol.net> Link: https://lore.kernel.org/r/20210114113538.1233933-17-maxime@cerno.tech
2021-01-31arm64: dts: allwinner: h6: Use - instead of @ for DT OPP entriesMaxime Ripard1-10/+10
DTC and the dt-validate tools report warnings for opp with the format opp@$frequency: dtc for a missing reg property, and dt-validate since the binding requires child nodes to have the format opp-$frequency. Change this to the latter format. Signed-off-by: Maxime Ripard <maxime@cerno.tech> Acked-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Jernej Skrabec <jernej.skrabec@siol.net> Link: https://lore.kernel.org/r/20210114113538.1233933-16-maxime@cerno.tech
2021-01-31ARM: dts: sun8i-a33: sina33: Add missing panel power supplyMaxime Ripard1-0/+1
The SinA33 panel is missing its power-supply property, even though the binding mandates it. Signed-off-by: Maxime Ripard <maxime@cerno.tech> Acked-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Jernej Skrabec <jernej.skrabec@siol.net> Link: https://lore.kernel.org/r/20210114113538.1233933-15-maxime@cerno.tech
2021-01-31ARM: dts: sun8i-a83t: Remove empty CSI portMaxime Ripard1-3/+0
The empty CSI port triggers a dt-validate warning. Let's align with the other DTSI and remove it entirely, expecting the DTS to fill it. Signed-off-by: Maxime Ripard <maxime@cerno.tech> Acked-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Jernej Skrabec <jernej.skrabec@siol.net> Link: https://lore.kernel.org/r/20210114113538.1233933-14-maxime@cerno.tech
2021-01-31ARM: dts: sun8i-s3: pinecube: Fix CSI DTC warningsMaxime Ripard1-3/+0
Our CSI endpoint trigger some DTC warnings due to the fact that we're having a single endpoint that doesn't need any reg property, and since we don't have a reg property, we don't need the address-cells and size-cells properties anymore. Fix those Signed-off-by: Maxime Ripard <maxime@cerno.tech> Acked-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Jernej Skrabec <jernej.skrabec@siol.net> Link: https://lore.kernel.org/r/20210114113538.1233933-13-maxime@cerno.tech
2021-01-31ARM: dts: sun8i-s3: impetus: Fix the USB PHY ID detect GPIO propertiesMaxime Ripard1-1/+1
While the USB PHY Device Tree mandates that the name of the ID detect pin should be usb0_id_det-gpios, a significant number of device tree use usb0_id_det-gpio instead. This was functional because the GPIO framework falls back to the gpio suffix that is legacy, but we should fix this. Signed-off-by: Maxime Ripard <maxime@cerno.tech> Acked-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Jernej Skrabec <jernej.skrabec@siol.net> Link: https://lore.kernel.org/r/20210114113538.1233933-12-maxime@cerno.tech
2021-01-31ARM: dts: sun8i: nanopi-r1: Fix GPIO regulator state arrayMaxime Ripard1-2/+2
Even though it translates to the same thing down to the binary level, we should have an array of 2 number cells to describe each voltage state, which in turns create a validation warning. Let's fix this. Signed-off-by: Maxime Ripard <maxime@cerno.tech> Acked-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Jernej Skrabec <jernej.skrabec@siol.net> Link: https://lore.kernel.org/r/20210114113538.1233933-11-maxime@cerno.tech
2021-01-31ARM: dts: sun6i: primo81: Remove useless io-channel-cellsMaxime Ripard1-1/+0
The mma8452 binding doesn't expect an io-channel-cells property, let's remove it. Signed-off-by: Maxime Ripard <maxime@cerno.tech> Acked-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Jernej Skrabec <jernej.skrabec@siol.net> Link: https://lore.kernel.org/r/20210114113538.1233933-10-maxime@cerno.tech
2021-01-31dts64: mt7622: fix slow sd card accessFrank Wunderlich1-0/+2
Fix extreme slow speed (200MB takes ~20 min) on writing sdcard on bananapi-r64 by adding reset-control for mmc1 like it's done for mmc0/emmc. Fixes: 2c002a3049f7 ("arm64: dts: mt7622: add mmc related device nodes") Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20210113180919.49523-1-linux@fw-web.de Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-01-31arm64: dts: mt8183: Add krane-sku0 board.Hsin-Yi Wang2-0/+24
Similar to krane-sku176 but using a different panel source. Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Link: https://lore.kernel.org/r/20210113110400.616319-2-hsinyi@chromium.org Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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