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2020-09-11crypto: arm/aes-neonbs - Use generic cbc encryption pathHerbert Xu1-18/+28
Since commit b56f5cbc7e08ec7d31c42fc41e5247677f20b143 ("crypto: arm/aes-neonbs - resolve fallback cipher at runtime") the CBC encryption path in aes-neonbs is now identical to that obtained through the cbc template. This means that it can simply call the generic cbc template instead of doing its own thing. This patch removes the custom encryption path and simply invokes the generic cbc template. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-09-11crypto: poly1305-x86_64 - Use XORL r32,32Uros Bizjak1-4/+4
x86_64 zero extends 32bit operations, so for 64bit operands, XORL r32,r32 is functionally equal to XORQ r64,r64, but avoids a REX prefix byte when legacy registers are used. Signed-off-by: Uros Bizjak <ubizjak@gmail.com> Cc: Herbert Xu <herbert@gondor.apana.org.au> Cc: "David S. Miller" <davem@davemloft.net> Acked-by: Jason A. Donenfeld <Jason@zx2c4.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-09-11crypto: curve25519-x86_64 - Use XORL r32,32Uros Bizjak1-34/+34
x86_64 zero extends 32bit operations, so for 64bit operands, XORL r32,r32 is functionally equal to XORL r64,r64, but avoids a REX prefix byte when legacy registers are used. Signed-off-by: Uros Bizjak <ubizjak@gmail.com> Cc: Herbert Xu <herbert@gondor.apana.org.au> Cc: "David S. Miller" <davem@davemloft.net> Acked-by: Jason A. Donenfeld <Jason@zx2c4.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-09-10arm64: dts: sc7180: add bus clock to mdp node for sc7180 targetKrishna Manikandan1-4/+4
Move the bus clock to mdp device node,in order to facilitate bus band width scaling on sc7180 target. The parent device MDSS will not vote for bus bw, instead the vote will be triggered by mdp device node. Since a minimum vote is required to turn on bus clock, move the clock node to mdp device from where the votes are requested. This patch has dependency on the below series https://patchwork.kernel.org/patch/11468783/ Reviewed-by: Rob Clark <robdclark@chromium.org> Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org> Link: https://lore.kernel.org/r/1594899334-19772-2-git-send-email-kalyan_t@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-10arm64: dts: qcom: sc7180: Add bandwidth votes for eMMC and SDcardPradeep P V K1-0/+15
Add the bandwidth domain supporting performance state and the corresponding OPP tables for the sdhc device on sc7180. Signed-off-by: Pradeep P V K <ppvk@codeaurora.org> Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org> Link: https://lore.kernel.org/r/1597646464-1863-1-git-send-email-sbhanu@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-10arm64: dts: exynos: Use newer S3FWRN5 GPIO properties in Exynos5433 TM2Krzysztof Kozlowski1-2/+2
Since "s3fwrn5" is not a valid vendor prefix, use new GPIO properties instead of the deprecated. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-09-10arm64: dts: qcom: sc7180: Add 'sustainable_power' for CPU thermal zonesMatthias Kaehlcke1-0/+10
The 'sustainable_power' attribute provides an estimate of the sustained power that can be dissipated at the desired control temperature. One could argue that this value is not necessarily the same for all devices with the same SoC, which may have different form factors or thermal designs. However there are reasons to specify a (default) value at SoC level for SC7180: most importantly, if no value is specified at all the power_allocator thermal governor (aka 'IPA') estimates a value, using the minimum power of all cooling devices of the zone, which can result in overly aggressive thermal throttling. For most devices an approximate conservative value should be more useful than the minimum guesstimate of power_allocator. Devices that need a different value can overwrite it in their <device>.dts. Also the thermal zones for SC7180 have a high level of granularity (essentially one for each function block), which makes it more likely that the default value just works for many devices. The values correspond to 1901 MHz for the big cores, and 1804 MHz for the small cores. The values were determined by limiting the CPU frequencies to different max values and launching a bunch of processes that cause high CPU load ('while true; do true; done &' is simple and does a good job). A frequency is deemed sustainable if the CPU temperatures don't rise (consistently) above the second trip point ('control temperature', 95 degC in this case). Once the highest sustainable frequency is found, the sustainable power can be calculated by multiplying the energy consumption per core at this frequency (which can be found in /sys/kernel/debug/energy_model/) with the number of cores that are specified as cooling devices. The sustainable frequencies were determined at room temperature on a device without heat sink or other passive cooling elements. Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Link: https://lore.kernel.org/r/20200813113030.1.I89c33c4119eaffb986b1e8c1bc6f0e30267089cd@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-10arm64: dts: qcom: sc7180: Add OPP tables and power-domains for venusRajendra Nayak1-2/+33
Add the OPP tables in order to be able to vote on the performance state of a power-domain Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Link: https://lore.kernel.org/r/1598970026-7199-6-git-send-email-rnayak@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-10arm64: dts: qcom: sdm845: Add OPP tables and power-domains for venusRajendra Nayak1-2/+38
Add the OPP tables in order to be able to vote on the performance state of a power-domain. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Link: https://lore.kernel.org/r/1598970026-7199-5-git-send-email-rnayak@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-10arm64: dts: qcom: sc7180: add interconnect bindings for displayKrishna Manikandan1-0/+3
This change adds the interconnect bindings to the MDSS node. This will establish Display to DDR path for bus bandwidth voting. Reviewed-by: Rob Clark <robdclark@chromium.org> Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org> Link: https://lore.kernel.org/r/1594899334-19772-1-git-send-email-kalyan_t@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-10Merge tag 'tags/bcm2835-dt-next-2020-09-08' into devicetree/nextFlorian Fainelli2-1/+169
Maxime Ripard enables vc4 on BCM2711 (RPi4), which among other things adds HDMI functionality (no 4K yet). Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2020-09-10ARM: dts: broadcom: Fix SP804 nodeAndre Przywara1-2/+2
The DT binding for SP804 requires to have an "arm,primecell" compatible string. Add this string so that the Linux primecell bus driver picks the device up and activates the clock. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Florian Fainelli <f.fainelli@gmail.com> [florian: added compatible to ccbtimer1] Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2020-09-10ARM: dts: NSP: Fix SP805 clock-namesAndre Przywara1-1/+1
The SP805 binding sets the name for the actual watchdog clock to "wdog_clk" (with an underscore). Change the name in the DTs for the Broadcom NSP platform to match that. The Linux and U-Boot driver use the *first* clock for this purpose anyway, so it does not break anything. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Ray Jui <ray.jui@broadcom.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2020-09-10ARM: dts: Cygnus: Fix SP805 clocksAndre Przywara1-2/+2
The SP805 DT binding requires two clocks to be specified, but the Broadcom Cygnus DT currently only specifies one clock. In practice, Linux would pick a clock named "apb_pclk" for the bus clock, and the Linux and U-Boot SP805 driver would use the first clock to derive the actual watchdog counter frequency. Since currently both are the very same clock, we can just double the clock reference, and add the correct clock-names, to match the binding. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Ray Jui <ray.jui@broadcom.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2020-09-10ARM: dts: NSP: replace status value "ok" by "okay"Adrian Schmutzler2-2/+2
While the DT parser recognizes "ok" as a valid value for the "status" property, it is actually mentioned nowhere. Use the proper value "okay" instead, as done in the majority of files already. Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2020-09-10ARM: BCM5301X: Add DT for Meraki MR32Christian Lamparter2-0/+198
add support for the Cisco Meraki MR32. This is a dual-band enterprise class 802.11ac access point. The unit was donated by Chris Blake. Thank you! SoC: Broadcom BCM53016A1 (1 GHz, 2 cores) RAM: 128 MiB NAND: 128 MiB Spansion S34ML01G2 (~114 MiB useable) ETH: 1GBit Ethernet Port - PoE WIFI1: Broadcom BCM43520 an+ac (2x2:2 - id: 0x4352) WIFI2: Broadcom BCM43520 bgn (2x2:2 - id: 0x4352) WIFI3: Broadcom BCM43428 abgn (1x1:1 - id: 43428) BLE: Broadcom BCM20732 (ttyS1) LEDS: 1 x Programmable RGB Status LED (driven by a PWM) 1 x White LED (GPIO) 1 x Orange LED Fault Indicator (GPIO) 2 x LAN Activity / Speed LEDs (On the RJ45 Port) BUTTON: one Reset button MISC: AT24C64 8KiB EEPROM (i2c - stores Ethernet MAC) ina219 hardware monitor (i2c) Kensington Lock SERIAL: WARNING: The serial port needs a TTL/RS-232 3V3 level converter! The Serial setting is 115200-8-N-1. The board has a populated right angle 1x4 0.1" pinheader. The pinout is: VCC, RX, TX, GND. Odd stuff: - uart0 clock frequency is 62.5 MHz. - The LEDs are labeled as SYS-LED1 through SYS-LED3 because of the silkscreen on the PCB. - the original u-boot has been compiled with most functions and commands disabled. The u-boot env isn't setup properly either and as a result, the bcm47xxpart probing is not working. Hence, the nand partitions are specified through a "fixed-partition" binding. - The "WICED SMART(TM)" Bluetooth LE 4.0 BCM20732 chip is connected to uart2 of the SoC. The BCM20732 does not provide a HCI. So the linux' bluetooth stack is useless. The mock-up node with the compatible binding and enable-gpios property is provided solely as documentation. Signed-off-by: Christian Lamparter <chunkeey@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2020-09-10x86/sev-es: Check required CPU features for SEV-ESMartin Radev5-6/+24
Make sure the machine supports RDRAND, otherwise there is no trusted source of randomness in the system. To also check this in the pre-decompression stage, make has_cpuflag() not depend on CONFIG_RANDOMIZE_BASE anymore. Signed-off-by: Martin Radev <martin.b.radev@gmail.com> Signed-off-by: Joerg Roedel <jroedel@suse.de> Signed-off-by: Borislav Petkov <bp@suse.de> Reviewed-by: Kees Cook <keescook@chromium.org> Link: https://lkml.kernel.org/r/20200907131613.12703-73-joro@8bytes.org
2020-09-10x86/efi: Add GHCB mappings when SEV-ES is activeTom Lendacky4-0/+43
Calling down to EFI runtime services can result in the firmware performing VMGEXIT calls. The firmware is likely to use the GHCB of the OS (e.g., for setting EFI variables), so each GHCB in the system needs to be identity-mapped in the EFI page tables, as unencrypted, to avoid page faults. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> [ jroedel@suse.de: Moved GHCB mapping loop to sev-es.c ] Signed-off-by: Joerg Roedel <jroedel@suse.de> Signed-off-by: Borislav Petkov <bp@suse.de> Acked-by: Ard Biesheuvel <ardb@kernel.org> Link: https://lkml.kernel.org/r/20200907131613.12703-72-joro@8bytes.org
2020-09-10net: dsa: microchip: look for phy-mode in port nodesHelmut Grohne1-1/+1
Documentation/devicetree/bindings/net/dsa/dsa.txt says that the phy-mode property should be specified on port nodes. However, the microchip drivers read it from the switch node. Let the driver use the per-port property and fall back to the old location with a warning. Fix in-tree users. Signed-off-by: Helmut Grohne <helmut.grohne@intenta.de> Link: https://lore.kernel.org/netdev/20200617082235.GA1523@laureti-dev/ Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-09-10arm64: dts: renesas: Add Renesas Falcon boards supportYoshihiro Shimoda3-0/+70
Initial support for the Renesas Falcon CPU and BreakOut boards support. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/1599739372-30669-5-git-send-email-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-09-10arm64: dts: renesas: Add Renesas R8A779A0 SoC supportYoshihiro Shimoda1-0/+133
Add initial support for the Renesas R8A77990 (R-Car V3U) support. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/1599739372-30669-4-git-send-email-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-09-10ARM: shmobile: rcar-gen2: Make rcar_gen2_{timer_init, reserve}() staticGeert Uytterhoeven2-4/+2
As of commit 1e90fea35b80cfe1 ("ARM: shmobile: r8a7791: Use common R-Car Gen2 machine definition"), there are no more users of rcar_gen2_timer_init() and rcar_gen2_reserve() outside arch/arm/mach-shmobile/setup-rcar-gen2.c. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20200908074403.4379-1-geert+renesas@glider.be
2020-09-10ARM: dts: r8a7742-iwg21d-q7: Enable SD2 LED indicationLad Prabhakar1-0/+10
Add support for LED trigger on SD2 interface. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com> Link: https://lore.kernel.org/r/20200907155541.2011-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-09-10ARM: dts: r8a7742-iwg21d-q7: Add can1 support to carrier boardLad Prabhakar1-0/+21
This patch enables CAN1 interface exposed through connector J20 on the carrier board. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com> Link: https://lore.kernel.org/r/20200907155541.2011-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-09-10ARM: dts: r8a7742-iwg21d-q7: Add SPI NOR supportLad Prabhakar1-0/+31
Add support for the SPI NOR device which is connected to MSIOF0 interface on the iWave RainboW-G21d-q7 board. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com> Link: https://lore.kernel.org/r/20200907155541.2011-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-09-10ARM: dts: r8a7742: Add VIN DT nodesLad Prabhakar1-0/+44
Add VIN[0123] instances found in the r8a7742 SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20200907144509.8861-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-09-10arm64: dts: renesas: r8a774e1-hihope-rzg2h-ex: Enable sataLad Prabhakar1-0/+5
Enable sata interface on HiHope RZ/G2H board. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20200907073214.13929-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-09-10arm64: dts: qcom: sc7180: Add LPASS clock controller nodesTaniya Das1-0/+24
Update the clock controller nodes for Low power audio subsystem functionality. Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/1596305615-5894-2-git-send-email-tdas@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-10arm64: dts: qcom: qrb5165-rb5: Add gpio-line-names for PM8150(B&L)Manivannan Sadhasivam1-0/+47
Add gpio-line-names for the GPIO pins exposed by PM8150, PM8150B and PM8150L PMIC nodes. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20200904063637.28632-7-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-10arm64: dts: qcom: qrb5165-rb5: Add gpio-line-names for TLMM blockManivannan Sadhasivam1-0/+181
Add gpio-line-names property for QRB5165 RB5 board for naming all GPIOs exposed by TLMM block. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20200904063637.28632-6-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-10arm64: dts: qcom: qrb5165-rb5: Add onboard LED supportManivannan Sadhasivam1-0/+26
Only User4, WLAN and BT LEDs are added for now. These GPIOs are coming from PM8150. Rest are coming from LPG block which is not supported yet! Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20200904063637.28632-5-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-10arm64: dts: qcom: Add basic devicetree support for QRB5165 RB5Manivannan Sadhasivam2-0/+433
Add basic devicetree support for Qualcomm Technologies, Inc. Robotics RB5 platform. This board is one of the 96Boards CE platform targeted for Robotics usecases from Qualcomm. This basic devicetree support includes regulators, onboard debug UART, I2C, SPI, and UFS support. Co-developed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20200904063637.28632-4-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-10arm64: dts: qcom: sm8250: Rename UART2 node to UART12Manivannan Sadhasivam2-3/+12
The UART12 node has been mistakenly mentioned as UART2. Let's fix that for both SM8250 SoC and MTP board and also add pinctrl definition for it. Fixes: 60378f1a171e ("arm64: dts: qcom: sm8250: Add sm8250 dts file") Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20200904063637.28632-3-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-10x86/fpu: Allow multiple bits in clearcpuid= parameterArvind Sankar1-8/+22
Commit 0c2a3913d6f5 ("x86/fpu: Parse clearcpuid= as early XSAVE argument") changed clearcpuid parsing from __setup() to cmdline_find_option(). While the __setup() function would have been called for each clearcpuid= parameter on the command line, cmdline_find_option() will only return the last one, so the change effectively made it impossible to disable more than one bit. Allow a comma-separated list of bit numbers as the argument for clearcpuid to allow multiple bits to be disabled again. Log the bits being disabled for informational purposes. Also fix the check on the return value of cmdline_find_option(). It returns -1 when the option is not found, so testing as a boolean is incorrect. Fixes: 0c2a3913d6f5 ("x86/fpu: Parse clearcpuid= as early XSAVE argument") Signed-off-by: Arvind Sankar <nivedita@alum.mit.edu> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20200907213919.2423441-1-nivedita@alum.mit.edu
2020-09-10arm64: defconfig: Enable Samsung S3FWRN5 NFC driverKrzysztof Kozlowski1-0/+3
Enable the Samsung S3FWRN5 NFC driver present in Exynos5433-based TM2/TM2E boards. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20200906153654.2925-10-krzk@kernel.org
2020-09-10objtool: Make unwind hint definitions available to other architecturesJulien Thierry3-84/+17
Unwind hints are useful to provide objtool with information about stack states in non-standard functions/code. While the type of information being provided might be very arch specific, the mechanism to provide the information can be useful for other architectures. Move the relevant unwint hint definitions for all architectures to see. [ jpoimboe: REGS_IRET -> REGS_PARTIAL ] Signed-off-by: Julien Thierry <jthierry@redhat.com> Signed-off-by: Josh Poimboeuf <jpoimboe@redhat.com>
2020-09-10objtool: Rename frame.h -> objtool.hJulien Thierry8-8/+8
Header frame.h is getting more code annotations to help objtool analyze object files. Rename the file to objtool.h. [ jpoimboe: add objtool.h to MAINTAINERS ] Signed-off-by: Julien Thierry <jthierry@redhat.com> Signed-off-by: Josh Poimboeuf <jpoimboe@redhat.com>
2020-09-10swiotlb: Declare swiotlb_late_init_with_default_size() in headerAndy Shevchenko1-1/+0
Compiler is not happy about one function prototype: CC kernel/dma/swiotlb.o kernel/dma/swiotlb.c:275:1: warning: no previous prototype for ‘swiotlb_late_init_with_default_size’ [-Wmissing-prototypes] 275 | swiotlb_late_init_with_default_size(size_t default_size) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Since it's used outside of the module, move its declaration to the header from the user. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
2020-09-10arm64: dts: mt8183: add scp nodeEddie Huang3-0/+53
Add scp node to mt8183 and mt8183-evb Signed-off-by: Erin Lo <erin.lo@mediatek.com> Signed-off-by: Pi-Hsun Shih <pihsun@chromium.org> Signed-off-by: Eddie Huang <eddie.huang@mediatek.com> Link: https://lore.kernel.org/r/20191112110330.179649-5-pihsun@chromium.org Link: https://lore.kernel.org/r/20200909081422.2412795-1-pihsun@chromium.org [mb: squashed both patches] Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-09-10ARM: omap2plus_defconfig: enable generic net optionsGrygorii Strashko1-0/+11
Enable set of generic, widely used, networking options: - basic QoS, filter and actions - VLAN support - Bridge support Use "M" build option where possible. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-09-10ARM: omap2plus_defconfig: enable twl4030_madc as a loadable moduleAndreas Kemnade1-0/+1
The ADC is used by twl4030_charger to read voltages. If a dtb contains the ADC but the module is not build, probing twl4030_charger will be endlessly deferred, so just enable CONFIG_TWL4030_MADC in the config. Signed-off-by: Andreas Kemnade <andreas@kemnade.info> Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-09-10ARM: dts: dra7: drop legacy cpsw dt nodeGrygorii Strashko2-56/+2
All dra7/am57 boards converted to use new driver, so drop legacy cpsw dt node. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-09-10ARM: dts: am57xx-cl-som-am57x: switch to new cpsw switch drvGrygorii Strashko1-7/+6
Switch CompuLab CL-SOM-AM57x board to use new cpsw switch driver. Those board configured in dual_mac mode by default. Hence, dual_mac mode has been preserved the same way between legacy and new driver it's safe to switch drivers. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-09-10ARM: dts: dra7x-evm: switch to new cpsw switch drvGrygorii Strashko6-37/+35
Switch all TI DRA7x boards to use new cpsw switch driver. Those boards configured in dual_mac mode by default. Hence, dual_mac mode has been preserved the same way between legacy and new driver it's safe to switch drivers. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-09-10ARM: dts: beagle-x15: switch to new cpsw switch drvGrygorii Strashko1-7/+6
Switch all TI AM5728 BeagleBoard-X15 boards to use new cpsw switch driver. Those boards have 2 Ext. port wired and configured in dual_mac mode by default. Hence, dual_mac mode has been preserved the same way between legacy and new driver it's safe to switch drivers. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-09-10ARM: dts: am57xx-idk: switch to new cpsw switch drvGrygorii Strashko4-42/+9
Switch all am571/2/4-idk boards to use new cpsw switch driver. Those boards have 2 Ext. port wired and configured in dual_mac mode by default. Hence, dual_mac mode has been preserved the same way between legacy and new driver it's safe to switch drivers. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-09-10ARM: dts: am5729: beagleboneai: switch to new cpsw switch drvGrygorii Strashko1-5/+9
Switch BeagleBone AI to use new cpsw switch driver. It has one Ext. port only and fits dual_mac mode with no issues. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-09-10ARM: dts: am43xx: replace status value "ok" by "okay"Adrian Schmutzler3-3/+3
While the DT parser recognizes "ok" as a valid value for the "status" property, it is actually mentioned nowhere. Use the proper value "okay" instead, as done in the majority of files already. Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de> Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-09-10ARM: dts: dra7xx: replace status value "ok" by "okay"Adrian Schmutzler5-11/+11
While the DT parser recognizes "ok" as a valid value for the "status" property, it is actually mentioned nowhere. Use the proper value "okay" instead, as done in the majority of files already. Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de> Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-09-10ARM: dts: omap: replace status value "ok" by "okay"Adrian Schmutzler29-51/+51
While the DT parser recognizes "ok" as a valid value for the "status" property, it is actually mentioned nowhere. Use the proper value "okay" instead, as done in the majority of files already. Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de> Signed-off-by: Tony Lindgren <tony@atomide.com>
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