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2020-07-28Merge branch 'kvm-arm64/misc-5.9' into kvmarm-master/next-WIPMarc Zyngier16-90/+85
Signed-off-by: Marc Zyngier <maz@kernel.org>
2020-07-28Merge branch 'kvm-arm64/target-table-no-more' into kvmarm-master/next-WIPMarc Zyngier4-227/+56
Signed-off-by: Marc Zyngier <maz@kernel.org>
2020-07-28Merge branch 'kvm-arm64/ptrauth-nvhe' into kvmarm-master/next-WIPMarc Zyngier4-35/+29
Signed-off-by: Marc Zyngier <maz@kernel.org>
2020-07-28Merge branch 'kvm-arm64/pre-nv-5.9' into kvmarm-master/next-WIPMarc Zyngier29-416/+690
Signed-off-by: Marc Zyngier <maz@kernel.org>
2020-07-28perf/x86/rapl: Add Hygon Fam18h RAPL supportPu Wen1-1/+2
Hygon Family 18h(Dhyana) support RAPL in bit 14 of CPUID 0x80000007 EDX, and has MSRs RAPL_PWR_UNIT/CORE_ENERGY_STAT/PKG_ENERGY_STAT. So add Hygon Dhyana Family 18h support for RAPL. The output is available via the energy-pkg pseudo event: $ perf stat -a -I 1000 --per-socket -e power/energy-pkg/ [ mingo: Tidied up the initializers. ] Signed-off-by: Pu Wen <puwen@hygon.cn> Signed-off-by: Ingo Molnar <mingo@kernel.org> Link: https://lore.kernel.org/r/20200720082205.1307-1-puwen@hygon.cn
2020-07-28Merge tag 'v5.8-rc7' into perf/core, to pick up fixesIngo Molnar136-444/+915
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2020-07-28ARM: mstar: Add reboot supportDaniel Palmer1-0/+7
MStar v7 SoCs support reset by writing a magic value to a register in the "pmsleep" area. This adds a node for using the syscon reboot driver to trigger a reset. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-28ARM: mstar: Add "pmsleep" node to base dtsiDaniel Palmer1-0/+5
This patch adds a node for the pmsleep area so that other drivers can access registers contained within it. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-28ARM: mstar: Add PMUDaniel Palmer1-0/+6
Adds the ARM PMU to the base MStar v7 dtsi. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-28ARM: mstar: Adjust IMI size for infinity3Daniel Palmer1-0/+4
infinity3 has 128KB of SRAM at the IMI region. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-28ARM: mstar: Adjust IMI size for mercury5Daniel Palmer1-0/+4
mercury5 family chips have 128KB of SRAM in the IMI region. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-28ARM: mstar: Adjust IMI size of infinityDaniel Palmer1-0/+4
infinity has 88KB of SRAM at the IMI region. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-28ARM: mstar: Add IMI SRAM regionDaniel Palmer1-1/+7
All MStar v7 SoCs have an internal SRAM region that is between 64KB (infinity2m) and 128KB(infinity3, mercury5). The region is always at the same base address and is used for the second stage loader (MStar IPL or u-boot SPL) and will be used for the DDR self-refresh entry code within the kernel eventually. This patch adds a 128KB region to the SoC and the minimum 64KB SRAM region to the base dtsi. Families with more SRAM will override the size in their family level dtsi. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-28ARM: 8995/1: drop Thumb-2 workaround for ancient binutilsArd Biesheuvel2-35/+0
The CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11 workaround addresses an issue which was fixed before the oldest supported binutils (2.23 at this time) were released. So we can remove it now. Acked-by: Dave Martin <Dave.Martin@arm.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2020-07-28ARM: 8994/1: mm: drop kimage_voffset which was only used by KVMArd Biesheuvel1-5/+0
Now that KVM support has been removed from the 32-bit ARM port, drop the export kimage_voffset symbol, which no longer has any users. Acked-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2020-07-28KVM: arm64: Substitute RANDOMIZE_BASE for HARDEN_EL2_VECTORSDavid Brazdil4-23/+5
The HARDEN_EL2_VECTORS config maps vectors at a fixed location on cores which are susceptible to Spector variant 3a (A57, A72) to prevent defeating hyp layout randomization by leaking the value of VBAR_EL2. Since this feature is only applicable when EL2 layout randomization is enabled, unify both behind the same RANDOMIZE_BASE Kconfig. Majority of code remains conditional on a capability selected for the affected cores. Signed-off-by: David Brazdil <dbrazdil@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200721094445.82184-3-dbrazdil@google.com
2020-07-28KVM: arm64: Make nVHE ASLR conditional on RANDOMIZE_BASEDavid Brazdil1-1/+1
If there are spare bits in non-VHE hyp VA, KVM unconditionally replaces them with a random tag chosen at init. Disable this if the kernel is built without RANDOMIZE_BASE to align with kernel behavior. Signed-off-by: David Brazdil <dbrazdil@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200721094445.82184-2-dbrazdil@google.com
2020-07-28parisc: Replace HTTP links with HTTPS onesAlexander A. Klimov1-1/+1
Reduces attack surface on kernel devs opening the links for MITM as HTTPS traffic is much harder to manipulate. Signed-off-by: Alexander A. Klimov <grandmaster@al2klimov.de> Signed-off-by: Helge Deller <deller@gmx.de>
2020-07-28parisc: elf.h: delete a duplicated wordRandy Dunlap1-1/+1
Drop the repeated word "the". Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Cc: "James E.J. Bottomley" <James.Bottomley@HansenPartnership.com> Cc: Helge Deller <deller@gmx.de> Cc: linux-parisc@vger.kernel.org Signed-off-by: Helge Deller <deller@gmx.de>
2020-07-28parisc: Report bad pages as HardwareCorruptedHelge Deller1-0/+3
The /proc/meminfo file reports physically broken memory pages in the HardwareCorrupted field. When the parisc kernel boots report physically bad pages which were recorded in the page deallocation table (PDT) as HardwareCorrupted too. Signed-off-by: Helge Deller <deller@gmx.de>
2020-07-28ARM: mstar: Fix dts filename for 70mai midrive d08Daniel Palmer1-1/+1
Fixes the filename for the 70mai midrive d08 dts. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-28ARM: mstar: Add dts for 70mai midrive d08Daniel Palmer2-1/+27
Adds initial support for the 70mai midrive d08 dash camera. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-28ARM: mstar: Add dts for msc313(e) based BreadBee boardsDaniel Palmer3-0/+53
BreadBee is an opensource development board based on the MStar msc313(e) SoC. Hardware details, schematics and so on can be found at: https://github.com/breadbee/breadbee Signed-off-by: Daniel Palmer <daniel@0x0f.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-28ARM: mstar: Add mercury5 series dtsisDaniel Palmer2-0/+21
This adds a family level dtsi for the mercury5 and then a chip level dtsi for the ssc8336n chip. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-28ARM: mstar: Add infinity/infinity3 family dtsisDaniel Palmer4-0/+42
This adds two family level dtsis for the infinity and infinity3 and then adds a chip level dtsi each for a chip in those families. infinity3.dtsi includes infinity.dtsi as these SoCs share most of their memory map and we would have a lot of duplication otherwise. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-28ARM: mstar: Add Armv7 base dtsiDaniel Palmer1-0/+83
Adds initial dtsi for the base MStar/Sigmastar Armv7 SoCs. These SoCs have very similar memory maps and this will avoid duplicating nodes across multiple dtsis. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-28ARM: mstar: Add machine for MStar/Sigmastar Armv7 SoCsDaniel Palmer5-0/+110
Initial support for the MStar/Sigmastar Armv7 based IP camera and dashcam SoCs. These chips are interesting in that they contain a Cortex-A7, peripherals and system memory in a single tiny QFN package that can be hand soldered allowing almost anyone to embed Linux in their projects. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-28arm64: dts: sparx5: Add i2c devices, i2c muxesLars Povlsen5-0/+360
This patch adds i2c devices and muxes to the Sparx5 reference boards. Link: https://lore.kernel.org/r/20200615133242.24911-11-lars.povlsen@microchip.com Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-28arm64: dts: sparx5: Add Sparx5 SoC DPLL clockLars Povlsen1-16/+23
This adds a DPLL clock to the Sparx5 SoC. It is used to generate clock to misc peripherals, specifically the SDHCI/eMMC controller. Link: https://lore.kernel.org/r/20200615133242.24911-10-lars.povlsen@microchip.com Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-28MIPS: qi_lb60: Fix routing to audio amplifierPaul Cercueil1-1/+1
The ROUT (right channel output of audio codec) was connected to INL (left channel of audio amplifier) instead of INR (right channel of audio amplifier). Fixes: 8ddebad15e9b ("MIPS: qi_lb60: Migrate to devicetree") Cc: stable@vger.kernel.org # v5.3 Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-07-28MIPS: Remove legacy MIPS_MACHINE optionPaul Cercueil4-112/+0
The CONFIG_MIPS_MACHINE option is dead code that hasn't been used in years. The Kconfig option is not selected anywhere, and the <asm/mips_machine.h> is not included anywhere either. To make things worse, for years it co-existed with a separate MIPS machine implementation as <asm/machine.h>. The two defined the 'mips_machine' structure with different fields, and the 'MIPS_MACHINE' macro with different parameters. The two used the same memory area (defined by the linker script) to store data, and you could totally use the two at the same time for all kinds of funny results. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-07-28MIPS: ath79: Remove unused include <asm/mips_machine.h>Paul Cercueil1-1/+0
Since commit 3a77e0d75eed ("MIPS: ath79: drop machfiles"), this header is not used anymore. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-07-28MIPS: cpu-feature-overrides: Remove not needed overridesThomas Bogendoerfer4-8/+0
Clean up cpu-feature-overrides, which only repeat the default. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-07-28KVM: arm64: Don't inherit exec permission across page-table levelsWill Deacon1-5/+6
If a stage-2 page-table contains an executable, read-only mapping at the pte level (e.g. due to dirty logging being enabled), a subsequent write fault to the same page which tries to install a larger block mapping (e.g. due to dirty logging having been disabled) will erroneously inherit the exec permission and consequently skip I-cache invalidation for the rest of the block. Ensure that exec permission is only inherited by write faults when the new mapping is of the same size as the existing one. A subsequent instruction abort will result in I-cache invalidation for the entire block mapping. Signed-off-by: Will Deacon <will@kernel.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Tested-by: Quentin Perret <qperret@google.com> Reviewed-by: Quentin Perret <qperret@google.com> Cc: Marc Zyngier <maz@kernel.org> Cc: <stable@vger.kernel.org> Link: https://lore.kernel.org/r/20200723101714.15873-1-will@kernel.org
2020-07-28KVM: arm64: Prevent vcpu_has_ptrauth from generating OOL functionsMarc Zyngier1-3/+8
So far, vcpu_has_ptrauth() is implemented in terms of system_supports_*_auth() calls, which are declared "inline". In some specific conditions (clang and SCS), the "inline" very much turns into an "out of line", which leads to a fireworks when this predicate is evaluated on a non-VHE system (right at the beginning of __hyp_handle_ptrauth). Instead, make sure vcpu_has_ptrauth gets expanded inline by directly using the cpus_have_final_cap() helpers, which are __always_inline, generate much better code, and are the only thing that make sense when running at EL2 on a nVHE system. Fixes: 29eb5a3c57f7 ("KVM: arm64: Handle PtrAuth traps early") Reported-by: Nathan Chancellor <natechancellor@gmail.com> Reported-by: Nick Desaulniers <ndesaulniers@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Tested-by: Nathan Chancellor <natechancellor@gmail.com> Reviewed-by: Nathan Chancellor <natechancellor@gmail.com> Link: https://lore.kernel.org/r/20200722162231.3689767-1-maz@kernel.org
2020-07-28xtensa: add boot subdirectories build artifacts to 'targets'Masahiro Yamada2-0/+2
Xtensa always rebuilds the following even if nothing in the source code has been changed. Passing V=2 shows the reason. AS arch/xtensa/boot/boot-elf/bootstrap.o - due to bootstrap.o not in $(targets) LDS arch/xtensa/boot/boot-elf/boot.lds - due to boot.lds not in $(targets) They are built by if_changed(_dep). Add them to 'targets' so .*.cmd files are included. Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> Message-Id: <20200722004707.779601-1-masahiroy@kernel.org> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2020-07-28xtensa: add uImage and xipImage to targetsMax Filippov1-0/+1
uImage and xipImage are always rebuilt in the xtensa kernel build process. Add them to 'targets' to avoid that. Reviewed-by: Masahiro Yamada <masahiroy@kernel.org> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2020-07-28xtensa: move vmlinux.bin[.gz] to boot subdirectoryMax Filippov3-9/+10
vmlinux.bin and vmlinux.bin.gz are always rebuilt in the kernel build process. Add them to 'targets' and move them to the boot subdirectory where their rules are. Update make rules that refer to them. Reviewed-by: Masahiro Yamada <masahiroy@kernel.org> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2020-07-28xtensa: initialize_mmu.h: fix a duplicated wordRandy Dunlap1-1/+1
Change "The the" to "For the". Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Cc: Chris Zankel <chris@zankel.net> Cc: Max Filippov <jcmvbkbc@gmail.com> Cc: linux-xtensa@linux-xtensa.org Message-Id: <20200721210044.15458-1-rdunlap@infradead.org> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2020-07-28xtensa: add seccomp supportMax Filippov4-2/+23
Add SECCOMP to xtensa Kconfig, select HAVE_ARCH_SECCOMP_FILTER, add TIF_SECCOMP and call secure_computing from do_syscall_trace_enter. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2020-07-28xtensa: expose syscall through user_pt_regsMax Filippov2-1/+6
Use one of the reserved slots in struct user_pt_regs to return syscall number in the GPR regset. Update syscall number from the GPR regset only when it's non-zero. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2020-07-28xtensa: add audit supportMax Filippov3-1/+10
All bits needed for syscall audit are present on xtensa. Add audit_syscall_entry and audit_syscall_exit calls and select HAVE_ARCH_AUDITSYSCALL in Kconfig. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2020-07-28ARM: dts: berlin: Align L2 cache-controller nodename with dtschemaKrzysztof Kozlowski3-3/+3
Fix dtschema validator warnings like: l2-cache-controller@ac0000: $nodename:0: 'l2-cache-controller@ac0000' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$' Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Link: https://lore.kernel.org/r/20200626080642.4244-1-krzk@kernel.org' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-28Merge tag 'aspeed-5.9-devicetree' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/aspeed into arm/dtArnd Bergmann10-100/+2121
ASPEED device tree updates for 5.9 There is one new machine; AMD's EthanolX reference platform with an AST2600 BMC. Misc updates for Rainier, Tacoma, Wedge and Mihawk machines. * tag 'aspeed-5.9-devicetree' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/aspeed: (26 commits) ARM: dts: Aspeed: tacoma: Enable EHCI controller ARM: dts: aspeed: rainier: Enable EHCI controller ARM: dts: aspeed: rainier: Switch OCCs to P10 ARM: dts: aspeed: rainier: Add FSI I2C masters ARM: dts: aspeed: rainier: Add CFAM SPI controllers ARM: dts: aspeed: rainier: Add I2C buses for NVMe use ARM: dts: aspeed: Initial device tree for AMD EthanolX ARM: dts: rainier: Describe GPIO mux on I2C3 ARM: dts: aspeed: wedge40: Enable pwm_tacho device ARM: dts: aspeed: wedge40: Enable ADC device ARM: dts: aspeed: wedge40: Disable unused i2c controllers ARM: dts: aspeed: cmm: Fixup I2C tree ARM: dts: aspeed: tacoma: Add CFAM reset GPIO ARM: dts: aspeed: rainier: Add CFAM reset GPIO ARM: dts: aspeed: tacoma: Fix gpio-key definitions ARM: dts: rainier: Configure ball Y23 as GPIOP7 for MCLR_VPP ARM: dts: aspeed: rainier: Add second cfam on the hub ARM: dts: aspeed: rainier: Add line-name checkstop ARM: dts: aspeed: tacoma: Remove checkstop gpio-key ARM: dts: aspeed: tacoma: Enable XDMA engine ... Link: https://lore.kernel.org/r/CACPK8Xf_Np7LtcDFhywi6Uk1EgUpb0pVVa+Lr9YEwBRjbjOKCQ@mail.gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-27arm64: dts: qcom: Add Microsoft Lumia 950 (Talkman) device treeKonrad Dybcio2-0/+40
Add device tree support for the Microsoft Lumia 950 smartphone. It is based on msm8992 and supports booting Linux via a custom EDK2 port. Currently it supports: * Screen console via EFIFB * Booting via EFI_STUB * SDHCI * I2C * PSCI core bringup Please note that there is an implementation of EL2 startup on this board, but it requires the user to resign from PSCI and use spin-table instead. This revision sticks with PSCI. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200625182118.131476-14-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-07-27arm64: dts: qcom: Add Xiaomi Libra (Mi 4C) device treeKonrad Dybcio2-0/+365
This commit adds support for the Xiaomi Libra (Mi 4C) smartphone. It's based on the Qualcomm msm8992 SoC. It currently supports: * Screen console from bootloader * SDHCI * Regulator configuration * Serial console * I2C Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200625182118.131476-13-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-07-27arm64: dts: qcom: msm8992: Add RPMCC nodeKonrad Dybcio1-0/+5
This lets us use clocks provided by RPM. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200625182118.131476-12-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-07-27arm64: dts: qcom: msm8992: Add PSCI support.Konrad Dybcio1-0/+5
This SoC's firmware does not fully support the PSCI spec, but it's good enough to bring the cores up. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200625182118.131476-11-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-07-27arm64: dts: qcom: msm8992: Add PMU nodeKonrad Dybcio1-0/+5
Add the PMU so we can get proper perf event support on this SoC. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200625182118.131476-10-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-07-27arm64: dts: qcom: msm8992: Add BLSP2_UART2 and I2C nodesKonrad Dybcio1-0/+153
Add support for I2C to enable support for peripherals such as touchscreens or sensors. Also add BLSP_UART2 interface. Please note that the naming scheme follows downstream and as abominable as it is, that's what we get. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200625182118.131476-9-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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