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2020-07-27arm64: dts: qcom: msm8992: Add SPMI PMIC arbiter deviceKonrad Dybcio1-0/+16
Add SPMI PMIC arbiter device to communicate with PMICs attached to SPMI bus. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200625182118.131476-8-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-07-27arm64: dts: qcom: msm8992: Add a SCM nodeKonrad Dybcio1-0/+6
Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200625182118.131476-7-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-07-27arm64: dts: qcom: msm8992: Add a proper CPU mapKonrad Dybcio1-7/+75
This commit adds cpu nodes for all 6 cores present on this SoC and the cpu-map. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200625182118.131476-6-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-07-27arm64: dts: qcom: bullhead: Move UART pinctrl to SoCKonrad Dybcio1-9/+4
This pinout is common for every 8992-based device and should therefore reside in the SoC device tree. Also convert addresses into phandles. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200625182118.131476-5-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-07-27arm64: dts: qcom: bullhead: Add qcom,msm-idKonrad Dybcio1-0/+1
Add the property required for the bootloader to select the correct device tree blob. It has been removed from the SoC device tree as it should be set on a per-device basis. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200625182118.131476-4-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-07-27arm64: dts: qcom: msm8992: Fix SDHCI1Konrad Dybcio2-7/+15
This commit ensures the correct IRQ type is set and disables the device by default. The mmc-hs400-1_8v property is also moved to Bullhead as it might not be present on all boards. The node has been renamed to sdhci@ instead of mmc@ and the phandle was changed to sdhc_1 to comply with the newer DTS style. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200625182118.131476-3-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-07-27arm64: dts: qcom: msm8992: Modernize the DTS styleKonrad Dybcio2-168/+168
Following changes have been made: - remove name, compatible and msm-id - wrap clocks in clocks{} - order nodes by name and by address - clock_gcc -> gcc - msmgpio -> tlmm - retire msm8992-pins.dtsi - add some of the missing pins - make comments C-style - make apcs a mailbox Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200625182118.131476-2-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-07-27arm64: dts: qcom: Add support for Sony Xperia Z5 (SoMC Sumire-RoW)Konrad Dybcio3-0/+249
Add device tree support for the Sony Xperia Z5 smartphone. It's based on Sony Kitakami platform (msm8994) and hence a Kitakami-common DTSI has been created so as to reduce clutter when remaining devices are added. The board currently supports * Serial * SDHCI * I2C * Regulator configuration * pstore log dump * GPIO keys Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200624150107.76234-9-konradybcio@gmail.com [bjorn: Changed vendor identifier in board compatible from somc to sony] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-07-27arm64: dts: qcom: Move msm8994-smd-rpm contents to lg-bullhead.Konrad Dybcio3-315/+224
This was the only device using that dtsi, so no point keeping it separate AND with a confusing name (bullhead is based on msm8992 and the file contains regulator values for that specific board). Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200624150107.76234-8-konradybcio@gmail.com [bjorn: Squashed with change that remove regulators from msm8992.dtsi] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-07-27arm64: dts: qcom: msm8994: Add support for SMD RPMKonrad Dybcio1-0/+43
Add support for SMD RPM, including pm8994 and pmi8994 regulators. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200624150107.76234-7-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-07-27arm64: dts: qcom: msm8992: Add a label to rpm-requestsKonrad Dybcio1-1/+1
This enables the node to be referenced directly from other DTs. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200624150107.76234-4-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-07-27arm64: dts: qcom: msm8994: Add SCM nodeKonrad Dybcio1-0/+6
Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200624150107.76234-3-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-07-27arm64: dts: qcom: sdm845-db845c: Add hdmi bridge nodesBjorn Andersson1-0/+118
Enable MDSS and DSI and add the LT9611 HDMI bridge. Also add the HDMI audio nodes. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Co-developed-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20200727075532.1932134-1-vkoul@kernel.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-07-27arm64: dts: qcom: add sm8250 GPU nodesJonathan Marek1-0/+142
This brings up the GPU. Tested on HDK865 by running vulkan CTS. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Link: https://lore.kernel.org/r/20200709135251.643-15-jonathan@marek.ca Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-07-27arm64: dts: qcom: add sm8150 GPU nodesJonathan Marek1-0/+135
This brings up the GPU. Tested on HDK855 by running vulkan CTS. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Link: https://lore.kernel.org/r/20200709135251.643-14-jonathan@marek.ca Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-07-27arm64: dts: qcom: sc7180: Add opp-peak-kBps to GPU oppSharat Masetty1-0/+7
Add opp-peak-kBps bindings to the GPU opp table, listing the peak GPU -> DDR bandwidth requirement for each opp level. This will be used to scale the DDR bandwidth along with the GPU frequency dynamically. Signed-off-by: Sharat Masetty <smasetty@codeaurora.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org> Link: https://lore.kernel.org/r/1594992579-20662-7-git-send-email-akhilpo@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-07-27arm64: dts: qcom: sc7180: Add interconnects property for GPUSharat Masetty1-0/+3
This patch adds the interconnects property to the GPU node. This enables the GPU->DDR path bandwidth voting. Signed-off-by: Sharat Masetty <smasetty@codeaurora.org> Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org> Link: https://lore.kernel.org/r/1594992579-20662-6-git-send-email-akhilpo@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-07-27arm64: dts: qcom: SDM845: Enable GPU DDR bw scalingSharat Masetty1-0/+10
This patch adds the interconnects property for the gpu node and the opp-peak-kBps property to the opps of the gpu opp table. This should help enable DDR bandwidth scaling dynamically and proportionally to the GPU frequency. Signed-off-by: Sharat Masetty <smasetty@codeaurora.org> Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org> Link: https://lore.kernel.org/r/1594992579-20662-5-git-send-email-akhilpo@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-07-27arm64: dts: qcom: sc7180: Add support for context losing replicatorSai Prakash Ranjan1-0/+1
Add "qcom,replicator-loses-context" property to the replicator in Always-on domain in SC7180 SoC to enable coresight replicator driver to handle this variation of replicator designs. Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Link: https://lore.kernel.org/r/5072d94849cfaee46748d26ac997212fb2d783c2.1591708204.git.saiprakash.ranjan@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-07-28KVM: PPC: Book3S HV: Rework secure mem slot droppingLaurent Dufour1-17/+35
When a secure memslot is dropped, all the pages backed in the secure device (aka really backed by secure memory by the Ultravisor) should be paged out to a normal page. Previously, this was achieved by triggering the page fault mechanism which is calling kvmppc_svm_page_out() on each pages. This can't work when hot unplugging a memory slot because the memory slot is flagged as invalid and gfn_to_pfn() is then not trying to access the page, so the page fault mechanism is not triggered. Since the final goal is to make a call to kvmppc_svm_page_out() it seems simpler to call directly instead of triggering such a mechanism. This way kvmppc_uvmem_drop_pages() can be called even when hot unplugging a memslot. Since kvmppc_uvmem_drop_pages() is already holding kvm->arch.uvmem_lock, the call to __kvmppc_svm_page_out() is made. As __kvmppc_svm_page_out needs the vma pointer to migrate the pages, the VMA is fetched in a lazy way, to not trigger find_vma() all the time. In addition, the mmap_sem is held in read mode during that time, not in write mode since the virual memory layout is not impacted, and kvm->arch.uvmem_lock prevents concurrent operation on the secure device. Reviewed-by: Bharata B Rao <bharata@linux.ibm.com> Signed-off-by: Laurent Dufour <ldufour@linux.ibm.com> [modified check on the VMA in kvmppc_uvmem_drop_pages] Signed-off-by: Ram Pai <linuxram@us.ibm.com> [modified the changelog description] Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2020-07-28KVM: PPC: Book3S HV: Move kvmppc_svm_page_out upLaurent Dufour1-76/+90
kvmppc_svm_page_out() will need to be called by kvmppc_uvmem_drop_pages() so move it up earlier in this file. Furthermore it will be interesting to call this function when already holding the kvm->arch.uvmem_lock, so prefix the original function with __ and remove the locking in it, and introduce a wrapper which call that function with the lock held. There is no functional change. Reviewed-by: Bharata B Rao <bharata@linux.ibm.com> Signed-off-by: Laurent Dufour <ldufour@linux.ibm.com> Signed-off-by: Ram Pai <linuxram@us.ibm.com> Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2020-07-28KVM: PPC: Book3S HV: Migrate hot plugged memoryLaurent Dufour3-12/+39
When a memory slot is hot plugged to a SVM, PFNs associated with the GFNs in that slot must be migrated to the secure-PFNs, aka device-PFNs. Call kvmppc_uv_migrate_mem_slot() to accomplish this. Disable page-merge for all pages in the memory slot. Reviewed-by: Bharata B Rao <bharata@linux.ibm.com> Signed-off-by: Ram Pai <linuxram@us.ibm.com> [rearranged the code, and modified the commit log] Signed-off-by: Laurent Dufour <ldufour@linux.ibm.com> Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2020-07-28KVM: PPC: Book3S HV: In H_SVM_INIT_DONE, migrate remaining normal-GFNs to secure-GFNsRam Pai1-22/+132
The Ultravisor is expected to explicitly call H_SVM_PAGE_IN for all the pages of the SVM before calling H_SVM_INIT_DONE. This causes a huge delay in tranistioning the VM to SVM. The Ultravisor is only interested in the pages that contain the kernel, initrd and other important data structures. The rest contain throw-away content. However if not all pages are requested by the Ultravisor, the Hypervisor continues to consider the GFNs corresponding to the non-requested pages as normal GFNs. This can lead to data-corruption and undefined behavior. In H_SVM_INIT_DONE handler, move all the PFNs associated with the SVM's GFNs to secure-PFNs. Skip the GFNs that are already Paged-in or Shared or Paged-in followed by a Paged-out. Reviewed-by: Bharata B Rao <bharata@linux.ibm.com> Signed-off-by: Ram Pai <linuxram@us.ibm.com> Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2020-07-28KVM: PPC: Book3S HV: Track the state GFNs associated with secure VMsRam Pai1-19/+172
During the life of SVM, its GFNs transition through normal, secure and shared states. Since the kernel does not track GFNs that are shared, it is not possible to disambiguate a shared GFN from a GFN whose PFN has not yet been migrated to a secure-PFN. Also it is not possible to disambiguate a secure-GFN from a GFN whose GFN has been pagedout from the ultravisor. The ability to identify the state of a GFN is needed to skip migration of its PFN to secure-PFN during ESM transition. The code is re-organized to track the states of a GFN as explained below. ************************************************************************ 1. States of a GFN --------------- The GFN can be in one of the following states. (a) Secure - The GFN is secure. The GFN is associated with a Secure VM, the contents of the GFN is not accessible to the Hypervisor. This GFN can be backed by a secure-PFN, or can be backed by a normal-PFN with contents encrypted. The former is true when the GFN is paged-in into the ultravisor. The latter is true when the GFN is paged-out of the ultravisor. (b) Shared - The GFN is shared. The GFN is associated with a a secure VM. The contents of the GFN is accessible to Hypervisor. This GFN is backed by a normal-PFN and its content is un-encrypted. (c) Normal - The GFN is a normal. The GFN is associated with a normal VM. The contents of the GFN is accesible to the Hypervisor. Its content is never encrypted. 2. States of a VM. --------------- (a) Normal VM: A VM whose contents are always accessible to the hypervisor. All its GFNs are normal-GFNs. (b) Secure VM: A VM whose contents are not accessible to the hypervisor without the VM's consent. Its GFNs are either Shared-GFN or Secure-GFNs. (c) Transient VM: A Normal VM that is transitioning to secure VM. The transition starts on successful return of H_SVM_INIT_START, and ends on successful return of H_SVM_INIT_DONE. This transient VM, can have GFNs in any of the three states; i.e Secure-GFN, Shared-GFN, and Normal-GFN. The VM never executes in this state in supervisor-mode. 3. Memory slot State. ------------------ The state of a memory slot mirrors the state of the VM the memory slot is associated with. 4. VM State transition. -------------------- A VM always starts in Normal Mode. H_SVM_INIT_START moves the VM into transient state. During this time the Ultravisor may request some of its GFNs to be shared or secured. So its GFNs can be in one of the three GFN states. H_SVM_INIT_DONE moves the VM entirely from transient state to secure-state. At this point any left-over normal-GFNs are transitioned to Secure-GFN. H_SVM_INIT_ABORT moves the transient VM back to normal VM. All its GFNs are moved to Normal-GFNs. UV_TERMINATE transitions the secure-VM back to normal-VM. All the secure-GFN and shared-GFNs are tranistioned to normal-GFN Note: The contents of the normal-GFN is undefined at this point. 5. GFN state implementation: ------------------------- Secure GFN is associated with a secure-PFN; also called uvmem_pfn, when the GFN is paged-in. Its pfn[] has KVMPPC_GFN_UVMEM_PFN flag set, and contains the value of the secure-PFN. It is associated with a normal-PFN; also called mem_pfn, when the GFN is pagedout. Its pfn[] has KVMPPC_GFN_MEM_PFN flag set. The value of the normal-PFN is not tracked. Shared GFN is associated with a normal-PFN. Its pfn[] has KVMPPC_UVMEM_SHARED_PFN flag set. The value of the normal-PFN is not tracked. Normal GFN is associated with normal-PFN. Its pfn[] has no flag set. The value of the normal-PFN is not tracked. 6. Life cycle of a GFN -------------------- -------------------------------------------------------------- | | Share | Unshare | SVM |H_SVM_INIT_DONE| | |operation |operation | abort/ | | | | | | terminate | | ------------------------------------------------------------- | | | | | | | Secure | Shared | Secure |Normal |Secure | | | | | | | | Shared | Shared | Secure |Normal |Shared | | | | | | | | Normal | Shared | Secure |Normal |Secure | -------------------------------------------------------------- 7. Life cycle of a VM -------------------- -------------------------------------------------------------------- | | start | H_SVM_ |H_SVM_ |H_SVM_ |UV_SVM_ | | | VM |INIT_START|INIT_DONE|INIT_ABORT |TERMINATE | | | | | | | | --------- ---------------------------------------------------------- | | | | | | | | Normal | Normal | Transient|Error |Error |Normal | | | | | | | | | Secure | Error | Error |Error |Error |Normal | | | | | | | | |Transient| N/A | Error |Secure |Normal |Normal | -------------------------------------------------------------------- ************************************************************************ Reviewed-by: Bharata B Rao <bharata@linux.ibm.com> Reviewed-by: Thiago Jung Bauermann <bauerman@linux.ibm.com> Signed-off-by: Ram Pai <linuxram@us.ibm.com> Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2020-07-28KVM: PPC: Book3S HV: Disable page merging in H_SVM_INIT_STARTRam Pai1-35/+88
Page-merging of pages in memory-slots associated with a Secure VM is disabled in H_SVM_PAGE_IN handler. This operation should have been done the much earlier; the moment the VM is initiated for secure-transition. Delaying this operation increases the probability for those pages to acquire new references, making it impossible to migrate those pages in H_SVM_PAGE_IN handler. Disable page-migration in H_SVM_INIT_START handling. Reviewed-by: Bharata B Rao <bharata@linux.ibm.com> Signed-off-by: Ram Pai <linuxram@us.ibm.com> Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2020-07-28KVM: PPC: Book3S HV: Fix function definition in book3s_hv_uvmem.cRam Pai1-11/+10
Without this fix, git is confused. It generates wrong function context for code changes in subsequent patches. Weird, but true. Signed-off-by: Ram Pai <linuxram@us.ibm.com> Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2020-07-28ARM: dts: Aspeed: tacoma: Enable EHCI controllerEddie James1-1/+5
Enable the second EHCI controller on the AST2600. Also add a line-name for the GPIO that controls power to the USB port. The power control is in place to allow the port to be disabled, for those that are worried about rogue USB sticks. Signed-off-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-28ARM: dts: aspeed: rainier: Enable EHCI controllerEddie James1-1/+5
Enable the second EHCI controller on the AST2600. Also add a line-name for the GPIO that controls power to the USB port. The power control is in place to allow the port to be disabled, for those that are worried about rogue USB sticks. Signed-off-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-28ARM: dts: aspeed: rainier: Switch OCCs to P10Eddie James1-3/+3
Rainier uses the P10 processor so the OCC binding should reflect that. Signed-off-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-28ARM: dts: aspeed: rainier: Add FSI I2C mastersJoel Stanley1-0/+21
The host processor contains i2c masters on each cfam. Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-28ARM: dts: aspeed: rainier: Add CFAM SPI controllersEddie James1-0/+226
Add the four SPI masters on each CFAM. Each master has four 128KB EEPROM devices attached to it. Signed-off-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-28ARM: dts: aspeed: rainier: Add I2C buses for NVMe useJet Li1-0/+105
Adding pca9552 exposes the presence detect lines for the cards and tca9554 exposes the presence details for the cards. Signed-off-by: Jet Li <Jet.Li@ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-28ARM: dts: aspeed: Initial device tree for AMD EthanolXSupreeth Venkatesh2-0/+220
Initial introduction of AMD EthanolX platform equipped with an Aspeed ast2500 BMC manufactured by AMD. AMD EthanolX platform is an AMD customer reference board with an Aspeed ast2500 BMC manufactured by AMD. This adds AMD EthanolX device tree file including the flash layout used by EthanolX BMC machines. Signed-off-by: Supreeth Venkatesh <supreeth.venkatesh@amd.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-28ARM: dts: rainier: Describe GPIO mux on I2C3Andrew Jeffery1-0/+46
We have a 4-bus mux whose output is selected by two GPIO inputs. Wire it up in the devicetree and ensure the output is enabled by hogging the appropriate line. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-27arm64: dts: qcom: sc7180: Add iommus property to ETRSai Prakash Ranjan1-0/+1
Define iommus property for Coresight ETR component in SC7180 SoC with the SID and mask to enable SMMU translation for this master. Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Link: https://lore.kernel.org/r/2312c9a10e7251d69e31e4f51c0f1d70e6f2f2f5.1591708204.git.saiprakash.ranjan@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-07-27arm64: dts: qcom: sc7180: Add support to skip powering up of ETMSai Prakash Ranjan1-0/+8
Add "qcom,skip-power-up" property to skip powering up ETM on SC7180 SoC to workaround a hardware errata where CPU watchdog counter is stopped when ETM power up bit is set (i.e., when TRCPDCR.PU = 1). Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Link: https://lore.kernel.org/r/8c5ff297d8c89d9d451352f189baf26c8938842a.1591708204.git.saiprakash.ranjan@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-07-27arm64: dts: qcom: sc7180: Add properties to qfprom for fuse blowingRavi Kumar Bokka2-2/+12
This patch adds properties to the qfprom node to enable fuse blowing. Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20200710073439.v5.4.I70c17309f8b433e900656d7c53a2e6b61888bb68@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-07-27sh: Fix validation of system call numberMichael Karcher1-3/+3
The slow path for traced system call entries accessed a wrong memory location to get the number of the maximum allowed system call number. Renumber the numbered "local" label for the correct location to avoid collisions with actual local labels. Signed-off-by: Michael Karcher <kernel@mkarcher.dialup.fu-berlin.de> Tested-by: John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de> Fixes: f3a8308864f920d2 ("sh: Add a few missing irqflags tracing markers.") Signed-off-by: Rich Felker <dalias@libc.org>
2020-07-27sh/tlb: Fix PGTABLE_LEVELS > 2Peter Zijlstra1-9/+1
Geert reported that his SH7722-based Migo-R board failed to boot after commit: c5b27a889da9 ("sh/tlb: Convert SH to generic mmu_gather") That commit fell victim to copying the wrong pattern -- __pmd_free_tlb() used to be implemented with pmd_free(). Fixes: c5b27a889da9 ("sh/tlb: Convert SH to generic mmu_gather") Reported-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Rich Felker <dalias@libc.org>
2020-07-27arm64: dts: meson: fix mmc0 tuning error on Khadas VIM3Christian Hewitt2-1/+4
Similar to other G12B devices using the W400 dtsi, I see reports of mmc0 tuning errors on VIM3 after a few hours uptime: [12483.917391] mmc0: tuning execution failed: -5 [30535.551221] mmc0: tuning execution failed: -5 [35359.953671] mmc0: tuning execution failed: -5 [35561.875332] mmc0: tuning execution failed: -5 [61733.348709] mmc0: tuning execution failed: -5 I do not see the same on VIM3L, so remove sd-uhs-sdr50 from the common dtsi to silence the error, then (re)add it to the VIM3L dts. Fixes: 4f26cc1c96c9 ("arm64: dts: khadas-vim3: move common nodes into meson-khadas-vim3.dtsi") Fixes: 700ab8d83927 ("arm64: dts: khadas-vim3: add support for the SM1 based VIM3L") Signed-off-by: Christian Hewitt <christianshewitt@gmail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20200721015950.11816-1-christianshewitt@gmail.com
2020-07-27arm64: dts: meson: misc fixups for w400 dtsiChristian Hewitt1-2/+4
Current devices using the W400 dtsi show mmc tuning errors: [12483.917391] mmc0: tuning execution failed: -5 [30535.551221] mmc0: tuning execution failed: -5 [35359.953671] mmc0: tuning execution failed: -5 [35561.875332] mmc0: tuning execution failed: -5 [61733.348709] mmc0: tuning execution failed: -5 Removing "sd-uhs-sdr50" from the SDIO node prevents this. We also add keep-power-in-suspend to the SDIO node and fix an indentation. Fixes: 3cb74db9b256 ("arm64: dts: meson: convert ugoos-am6 to common w400 dtsi") Signed-off-by: Christian Hewitt <christianshewitt@gmail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20200721013952.11635-1-christianshewitt@gmail.com
2020-07-27kill unused dump_fpu() instancesAl Viro14-257/+1
dump_fpu() is used only on the architectures that support elf and have neither CORE_DUMP_USE_REGSET nor ELF_CORE_COPY_FPREGS defined. Currently that's csky, m68k, microblaze, nds32 and unicore32. The rest of the instances are dead code. NB: THIS MUST GO AFTER ELF_FDPIC CONVERSION Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2020-07-27Merge branch 'work.fdpic' into regset.followupAl Viro3-6/+0
2020-07-27regset(): kill ->get_size()Al Viro1-13/+0
not used anymore Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2020-07-27csky: switch to ->regset_get()Al Viro1-14/+10
NB: WTF is fpregs_get() playing at??? Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2020-07-27xtensa: switch to ->regset_get()Al Viro1-10/+6
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2020-07-27parisc: switch to ->regset_get()Al Viro1-68/+16
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2020-07-27nds32: switch to ->regset_get()Al Viro1-5/+4
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2020-07-27nios2: switch to ->regset_get()Al Viro1-36/+15
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2020-07-27hexagon: switch to ->regset_get()Al Viro1-41/+21
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>