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2020-07-08kvm: x86: Set last_vmentry_cpu in vcpu_enter_guestJim Mattson3-2/+1
2020-07-08kvm: x86: Move last_cpu into kvm_vcpu_arch as last_vmentry_cpuJim Mattson6-16/+13
2020-07-08kvm: x86: Add "last CPU" to some KVM_EXIT informationJim Mattson3-3/+12
2020-07-08kvm: vmx: Add last_cpu to struct vcpu_vmxJim Mattson2-0/+4
2020-07-08kvm: svm: Always set svm->last_cpu on VMRUNJim Mattson2-1/+1
2020-07-08kvm: svm: Prefer vcpu->cpu to raw_smp_processor_id()Jim Mattson1-6/+3
2020-07-08KVM: x86: report sev_pin_memory errors with PTR_ERRPaolo Bonzini1-10/+12
2020-07-08KVM: SVM: convert get_user_pages() --> pin_user_pages()John Hubbard1-3/+3
2020-07-08KVM: SVM: fix svn_pin_memory()'s use of get_user_pages_fast()John Hubbard1-1/+5
2020-07-08KVM: nSVM: Check that DR6[63:32] and DR7[64:32] are not set on vmrun of nested guestsKrish Sadhukhan1-0/+3
2020-07-08KVM: x86: Move the check for upper 32 reserved bits of DR6 to separate functionKrish Sadhukhan2-1/+6
2020-07-08KVM: X86: Do the same ignore_msrs check for feature msrsPeter Xu3-4/+10
2020-07-08KVM: X86: Move ignore_msrs handling upper the stackPeter Xu2-26/+56
2020-07-08KVM: x86/mmu: Make .write_log_dirty a nested operationSean Christopherson4-40/+40
2020-07-08KVM: nVMX: WARN if PML emulation helper is invoked outside of nested guestSean Christopherson1-21/+22
2020-07-08KVM: x86/mmu: Drop kvm_arch_write_log_dirty() wrapperSean Christopherson3-17/+1
2020-07-08KVM: async_pf: change kvm_setup_async_pf()/kvm_arch_setup_async_pf() return type to boolVitaly Kuznetsov2-13/+11
2020-07-08KVM: x86: drop KVM_PV_REASON_PAGE_READY case from kvm_handle_page_fault()Vitaly Kuznetsov1-11/+6
2020-07-08Merge branch 'kvm-master' into HEADPaolo Bonzini14-34/+64
2020-07-08Merge branch 'kvm-async-pf-int' into HEADPaolo Bonzini4-13/+40
2020-07-08KVM: MIPS: fix spelling mistake "Exteneded" -> "Extended"Colin Ian King1-2/+2
2020-07-08arm64: dts: qcom: sc7180: Drop the unused non-MSA SIDSibi Sankar2-2/+2
2020-07-08Raise gcc version requirement to 4.9Linus Torvalds2-13/+3
2020-07-08powerpc/64s/exception: Fix 0x1500 interrupt handler crashNicholas Piggin1-1/+1
2020-07-08Merge branch 'sched/urgent'Peter Zijlstra204-902/+1627
2020-07-08perf/x86/intel/lbr: Support XSAVES for arch LBR readKan Liang3-1/+47
2020-07-08perf/x86/intel/lbr: Support XSAVES/XRSTORS for LBR context switchKan Liang6-10/+119
2020-07-08x86/fpu/xstate: Add helpers for LBR dynamic supervisor featureKan Liang2-0/+75
2020-07-08x86/fpu/xstate: Support dynamic supervisor feature for LBRKan Liang3-5/+47
2020-07-08x86/fpu: Use proper mask to replace full instruction maskKan Liang2-40/+46
2020-07-08perf/x86: Remove task_ctx_sizeKan Liang2-2/+0
2020-07-08perf/x86/intel/lbr: Create kmem_cache for the LBR context dataKan Liang1-2/+19
2020-07-08perf/x86/intel/lbr: Support Architectural LBRKan Liang3-11/+253
2020-07-08perf/x86/intel/lbr: Factor out intel_pmu_store_lbrKan Liang1-26/+56
2020-07-08perf/x86/intel/lbr: Factor out rdlbr_all() and wrlbr_all()Kan Liang2-17/+51
2020-07-08perf/x86/intel/lbr: Mark the {rd,wr}lbr_{to,from} wrappers __always_inlineKan Liang1-4/+4
2020-07-08perf/x86/intel/lbr: Unify the stored format of LBR informationKan Liang4-22/+16
2020-07-08perf/x86/intel/lbr: Support LBR_CTLKan Liang2-3/+55
2020-07-08perf/x86: Expose CPUID enumeration bits for arch LBRKan Liang2-0/+53
2020-07-08x86/msr-index: Add bunch of MSRs for Arch LBRKan Liang1-0/+16
2020-07-08perf/x86/intel/lbr: Use dynamic data structure for task_ctxKan Liang2-34/+32
2020-07-08perf/x86/intel/lbr: Factor out a new struct for generic optimizationKan Liang2-20/+28
2020-07-08perf/x86/intel/lbr: Add the function pointers for LBR save and restoreKan Liang3-30/+59
2020-07-08perf/x86/intel/lbr: Add a function pointer for LBR readKan Liang3-7/+13
2020-07-08perf/x86/intel/lbr: Add a function pointer for LBR resetKan Liang3-17/+27
2020-07-08x86/cpufeatures: Add Architectural LBRs feature bitKan Liang1-0/+1
2020-07-08MIPS: Loongson: Update dts file for RS780EHuacai Chen1-2/+2
2020-07-08MIPS: Loongson: Rename CPU device-tree bindingHuacai Chen6-7/+7
2020-07-08MIPS: Loongson64: Adjust IRQ layoutHuacai Chen1-1/+5
2020-07-08MIPS: Unify naming style of vendor CP0.Config6 bitsHuacai Chen5-27/+27
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