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2020-05-05ARM: dts: aspeed: witherspoon: Add gpio line namesAndrew Geissler1-0/+34
Name the GPIOs to help userspace work with them. The names describe the functionality the lines provide, not the net or ball name. This makes it easier to share userspace code across different systems and makes the use of the lines more obvious. Signed-off-by: Andrew Geissler <geissonator@yahoo.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-05-05ARM: dts: aspeed: ast2600: Set arch timer always-onEddie James1-0/+2
According to ASPEED, FTTMR010 is not intended to be used in the AST2600. The arch timer should be used, but Linux doesn't enable high-res timers without being assured that the arch timer is always on, so set that property in the devicetree. The FTTMR010 device is described by set to disabled. This fixes highres timer support for AST2600. Fixes: 2ca5646b5c2f ("ARM: dts: aspeed: Add AST2600 and EVB") Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-05-05ARM: dts: aspeed: tacoma: Add GPIOs for FSIJoel Stanley1-6/+3
GPIO Q7 is no longer used for air/water. It is repurposed on Tacoma to indicate internal FSI (low) vs cabled (high). GPIO B0 controls the muxing of FSI to the cable (low) or internal pins (high). Acked-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-05-05ARM: dts: aspeed: mihawk: Change the name of ledsBen Pai1-14/+3
Change the name of power, fault and rear-id. Remove the two leds. Signed-off-by: Ben Pai <Ben_Pai@wistron.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-05-05ARM: dts: aspeed: rainier: Remove regulatorsMatthew Barth1-60/+0
Regulators will be dynamically configured and monitored from userspace. Signed-off-by: Matthew Barth <msbarth@linux.ibm.com> Reviewed-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Jim Wright <wrightj@linux.vnet.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-05-05ARM: dts: aspeed: rainier: Add host FSI descriptionJoel Stanley1-0/+82
This adds the description of the Power CPUs that are attached to the BMC. Without this userspace will see the '/dev/scom66' style layout. Reviewed-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-05-05ARM: dts: aspeed: ast2600evb: Enable FSI masterJoel Stanley1-0/+4
Use the first FSI master. Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-05-05ARM: dts: aspeed: tacoma: Add gpio-key definitionsEddie James1-0/+59
Add gpio-keys for various signals on Tacoma. Signed-off-by: Eddie James <eajames@linux.ibm.com> Acked-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-05-05ARM: dts: aspeed: rainier: Set PCA9552 pin typesMatthew Barth1-0/+17
All 16 pins of the PCA9552 at 7-bit address 0x61 should be set as type GPIO. Signed-off-by: Matthew Barth <msbarth@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-05-05ARM: dts: aspeed: rainier: Enable VUART2Andrew Jeffery1-0/+4
The second VUART is used to expose multiplexed, non-hypervisor consoles. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-05-05ARM: dts: aspeed: ast2400: Add video engine supportAlexander Filippov1-0/+10
Add a node to describe the video engine on AST2400. These changes were copied from aspeed-g5.dtsi Signed-off-by: Alexander Filippov <a.filippov@yadro.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-05-05ARM: dts: aspeed: tacoma: Enable eMMC controllerGuenter Roeck1-0/+4
Enabling emmc without enabling its controller doesn't do any good. Enable its controller as well to make it work. Cc: Andrew Jeffery <andrew@aj.id.au> Cc: Joel Stanley <joel@jms.id.au> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-05-05ARM: dts: aspeed: tiogapass: Add gpio line namesVijay Khemka1-0/+63
Added GPIO line names for all gpio used in tiogapass platform, these line names will be used by libgpiod to control GPIOs Signed-off-by: Vijay Khemka <vijaykhemka@fb.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-05-05ARM: dts: aspeed: tiogapass: Add IPMB deviceVijay Khemka1-0/+11
Adding IPMB devices for facebook tiogapass platform. Signed-off-by: Vijay Khemka <vijaykhemka@fb.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-05-05ARM: dts: aspeed: ast2600: Add Video Engine nodeJae Hyun Yoo1-0/+10
The AST2600 has Video Engine so add it. Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Acked-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-05-05ARM: dts: aspeed: ast2600: Add SCU interrupt controllersEddie James1-0/+16
Add nodes for the interrupt controllers provided by the SCU. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-05-05ARM: dts: aspeed: ast2500: Add SCU interrupt controllerEddie James1-0/+8
Add a node for the interrupt controller provided by the SCU. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-05-04riscv: force __cpu_up_ variables to put in data sectionZong Li1-2/+2
Put __cpu_up_stack_pointer and __cpu_up_task_pointer in data section. Currently, these two variables are put in bss section, there is a potential risk that secondary harts get the uninitialized value before main hart finishing the bss clearing. In this case, all secondary harts would pass the waiting loop and enable the MMU before main hart set up the page table. This issue happens on random booting of multiple harts, which means it will manifest for BBL and OpenSBI v0.6 (or older version). In OpenSBI v0.7 (or higher version), we have HSM extension so all the secondary harts are brought-up by Linux kernel in an orderly fashion. This means we don't need this change for OpenSBI v0.7 (or higher version). Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Greentime Hu <greentime.hu@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-05-04riscv: add Linux note to vdsoAndreas Schwab2-1/+13
The Linux note in the vdso allows glibc to check the running kernel version without having to issue the uname syscall. Signed-off-by: Andreas Schwab <schwab@suse.de> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-05-04riscv: set max_pfn to the PFN of the last pageVincent Chen1-1/+2
The current max_pfn equals to zero. In this case, I found it caused users cannot get some page information through /proc such as kpagecount in v5.6 kernel because of new sanity checks. The following message is displayed by stress-ng test suite with the command "stress-ng --verbose --physpage 1 -t 1" on HiFive unleashed board. # stress-ng --verbose --physpage 1 -t 1 stress-ng: debug: [109] 4 processors online, 4 processors configured stress-ng: info: [109] dispatching hogs: 1 physpage stress-ng: debug: [109] cache allocate: reducing cache level from L3 (too high) to L0 stress-ng: debug: [109] get_cpu_cache: invalid cache_level: 0 stress-ng: info: [109] cache allocate: using built-in defaults as no suitable cache found stress-ng: debug: [109] cache allocate: default cache size: 2048K stress-ng: debug: [109] starting stressors stress-ng: debug: [109] 1 stressor spawned stress-ng: debug: [110] stress-ng-physpage: started [110] (instance 0) stress-ng: error: [110] stress-ng-physpage: cannot read page count for address 0x3fd34de000 in /proc/kpagecount, errno=0 (Success) stress-ng: error: [110] stress-ng-physpage: cannot read page count for address 0x3fd32db078 in /proc/kpagecount, errno=0 (Success) ... stress-ng: error: [110] stress-ng-physpage: cannot read page count for address 0x3fd32db078 in /proc/kpagecount, errno=0 (Success) stress-ng: debug: [110] stress-ng-physpage: exited [110] (instance 0) stress-ng: debug: [109] process [110] terminated stress-ng: info: [109] successful run completed in 1.00s # After applying this patch, the kernel can pass the test. # stress-ng --verbose --physpage 1 -t 1 stress-ng: debug: [104] 4 processors online, 4 processors configured stress-ng: info: [104] dispatching hogs: 1 physpage stress-ng: info: [104] cache allocate: using defaults, can't determine cache details from sysfs stress-ng: debug: [104] cache allocate: default cache size: 2048K stress-ng: debug: [104] starting stressors stress-ng: debug: [104] 1 stressor spawned stress-ng: debug: [105] stress-ng-physpage: started [105] (instance 0) stress-ng: debug: [105] stress-ng-physpage: exited [105] (instance 0) stress-ng: debug: [104] process [105] terminated stress-ng: info: [104] successful run completed in 1.01s # Cc: stable@vger.kernel.org Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Yash Shah <yash.shah@sifive.com> Tested-by: Yash Shah <yash.shah@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-05-04RISC-V: Remove N-extension related definesAnup Patel1-3/+0
The RISC-V N-extension is still in draft state hence remove N-extension related defines from asm/csr.h. Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-05-04RISC-V: Add bitmap reprensenting ISA features common across CPUsAnup Patel2-3/+102
This patch adds riscv_isa bitmap which represents Host ISA features common across all Host CPUs. The riscv_isa is not same as elf_hwcap because elf_hwcap will only have ISA features relevant for user-space apps whereas riscv_isa will have ISA features relevant to both kernel and user-space apps. One of the use-case for riscv_isa bitmap is in KVM hypervisor where we will use it to do following operations: 1. Check whether hypervisor extension is available 2. Find ISA features that need to be virtualized (e.g. floating point support, vector extension, etc.) Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Alexander Graf <graf@amazon.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-05-04RISC-V: Export riscv_cpuid_to_hartid_mask() APIAnup Patel1-0/+2
The riscv_cpuid_to_hartid_mask() API should be exported to allow building KVM RISC-V as loadable module. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-05-04ARM: dts: socfpga: Add fpga2hps and fpga2sdram bridgesSteffen Trumtrar1-0/+14
Add the remaining two bridges on the Cyclone-V SoCFPGA SoCs. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2020-05-04ARM: dts: socfgpa: set bridges status to disabledSteffen Trumtrar1-0/+2
The hps-to-fpga bridges can't be used, when the FPGA is not programmed. Set the default state to disabled and leave enabling them to the board-specific dts files. Although this changes behavior, there are no in-tree users of the bridges, so this won't break anything. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2020-05-04arm64: dts: ti: j721e-main: add main navss cpts nodeGrygorii Strashko1-0/+12
Add DT node for Main NAVSS CPTS module. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-05-04arm64: dts: ti: k3-j721e-mcu: add mcu cpsw cpts nodeGrygorii Strashko1-0/+9
Add DT node for The TI J721E MCU CPSW CPTS which is part of MCU CPSW NUSS. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-05-04arm64: dts: ti: k3-am65-main: add main navss cpts nodeGrygorii Strashko1-0/+22
Add DT node for Main NAVSS CPTS module. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-05-04arm64: dts: ti: k3-am65-mcu: add cpsw cpts nodeGrygorii Strashko1-0/+19
Add DT node for the TI AM65x SoC Common Platform Time Sync (CPTS). Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-05-04arm64: dts: sdm845: add IPA iommus propertyAlex Elder1-0/+2
Add an "iommus" property to the IPA node in "sdm845.dtsi". It is required because there are two regions of memory the IPA accesses through an SMMU. The next few patches define and map those regions. Signed-off-by: Alex Elder <elder@linaro.org> Link: https://lore.kernel.org/r/20200504181350.22822-1-elder@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-05-04x86/boot/compressed/64: Switch to __KERNEL_CS after GDT is loadedJoerg Roedel1-0/+8
When the pre-decompression code loads its first GDT in startup_64(), it is still running on the CS value of the previous GDT. In the case of SEV-ES, this is the EFI GDT but it can be anything depending on what has loaded the kernel (boot loader, container runtime, etc.) To make exception handling work (especially IRET) the CPU needs to switch to a CS value in the current GDT, so jump to __KERNEL_CS after the first GDT is loaded. This is prudent also as a general sanitization of CS to a known good value. [ bp: Massage commit message. ] Signed-off-by: Joerg Roedel <jroedel@suse.de> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20200428151725.31091-13-joro@8bytes.org
2020-05-04arm64/cpuinfo: Move device_initcall() near cpuinfo_regs_init()Anshuman Khandual1-2/+2
This moves device_initcall() near cpuinfo_regs_init() making the calling sequence clear. Besides it is a standard practice to have device_initcall() (any __initcall for that matter) just after the function it actually calls. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Mark Brown <broonie@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Suzuki Poulose <suzuki.poulose@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Link: https://lore.kernel.org/r/1588595377-4503-1-git-send-email-anshuman.khandual@arm.com Signed-off-by: Will Deacon <will@kernel.org>
2020-05-04arm64: dts: allwinner: sun50i-a64: Add missing address/size-cellsOndrej Jirman1-0/+2
The binding specifies #address-cells and #size-cells should be present. Without them present, dtc issues a warning because default for #address-cells seems to be <2>: arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi:1108.4-52: Warning (dma_ranges_format): /soc/dram-controller@1c62000:dma-ranges: "dma-ranges" property has invalid length (12 bytes) (parent #address-cells == 1, child #address-cells == 2, #size-cells == 1) mbus #address-cells should be 1. Signed-off-by: Ondrej Jirman <megous@megous.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2020-05-04arm64: dts: allwinner: h6: Enable CPU opp tables for Pine H64Clément Péron1-1/+8
Enable CPU and GPU opp tables for Pine H64. This needs to change the CPU regulator max voltage to fit the OPP table. Also add the ramp-delay information to avoid any out of spec running as the regulator is slower at reaching the voltage requested compare to the PLL reaching the frequency. There is no such information for AXP805 but similar PMIC (AXP813) has a DVM (Dynamic Voltage scaling Management) ramp rate equal to 2500uV/us. Signed-off-by: Clément Péron <peron.clem@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2020-05-04arm64: dts: allwinner: Sort Pine H64 device-tree nodesClément Péron1-17/+17
Pine H64 device-tree have some nodes not properly sorted. Fix this. Signed-off-by: Clément Péron <peron.clem@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2020-05-04kvm: ioapic: Restrict lazy EOI update to edge-triggered interruptsPaolo Bonzini1-5/+5
Commit f458d039db7e ("kvm: ioapic: Lazy update IOAPIC EOI") introduces the following infinite loop: BUG: stack guard page was hit at 000000008f595917 \ (stack is 00000000bdefe5a4..00000000ae2b06f5) kernel stack overflow (double-fault): 0000 [#1] SMP NOPTI RIP: 0010:kvm_set_irq+0x51/0x160 [kvm] Call Trace: irqfd_resampler_ack+0x32/0x90 [kvm] kvm_notify_acked_irq+0x62/0xd0 [kvm] kvm_ioapic_update_eoi_one.isra.0+0x30/0x120 [kvm] ioapic_set_irq+0x20e/0x240 [kvm] kvm_ioapic_set_irq+0x5c/0x80 [kvm] kvm_set_irq+0xbb/0x160 [kvm] ? kvm_hv_set_sint+0x20/0x20 [kvm] irqfd_resampler_ack+0x32/0x90 [kvm] kvm_notify_acked_irq+0x62/0xd0 [kvm] kvm_ioapic_update_eoi_one.isra.0+0x30/0x120 [kvm] ioapic_set_irq+0x20e/0x240 [kvm] kvm_ioapic_set_irq+0x5c/0x80 [kvm] kvm_set_irq+0xbb/0x160 [kvm] ? kvm_hv_set_sint+0x20/0x20 [kvm] .... The re-entrancy happens because the irq state is the OR of the interrupt state and the resamplefd state. That is, we don't want to show the state as 0 until we've had a chance to set the resamplefd. But if the interrupt has _not_ gone low then ioapic_set_irq is invoked again, causing an infinite loop. This can only happen for a level-triggered interrupt, otherwise irqfd_inject would immediately set the KVM_USERSPACE_IRQ_SOURCE_ID high and then low. Fortunately, in the case of level-triggered interrupts the VMEXIT already happens because TMR is set. Thus, fix the bug by restricting the lazy invocation of the ack notifier to edge-triggered interrupts, the only ones that need it. Tested-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Reported-by: borisvk@bstnet.org Suggested-by: Paolo Bonzini <pbonzini@redhat.com> Link: https://www.spinics.net/lists/kvm/msg213512.html Fixes: f458d039db7e ("kvm: ioapic: Lazy update IOAPIC EOI") Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=207489 Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-05-04KVM: x86: Fixes posted interrupt check for IRQs delivery modesSuravee Suthikulpanit1-2/+2
Current logic incorrectly uses the enum ioapic_irq_destination_types to check the posted interrupt destination types. However, the value was set using APIC_DM_XXX macros, which are left-shifted by 8 bits. Fixes by using the APIC_DM_FIXED and APIC_DM_LOWEST instead. Fixes: (fdcf75621375 'KVM: x86: Disable posted interrupts for non-standard IRQs delivery modes') Cc: Alexander Graf <graf@amazon.com> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Message-Id: <1586239989-58305-1-git-send-email-suravee.suthikulpanit@amd.com> Reviewed-by: Maxim Levitsky <mlevitsk@redhat.com> Tested-by: Maxim Levitsky <mlevitsk@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-05-04Merge tag 'kvmarm-fixes-5.7-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into kvm-masterPaolo Bonzini4-15/+33
KVM/arm fixes for Linux 5.7, take #2 - Fix compilation with Clang - Correctly initialize GICv4.1 in the absence of a virtual ITS - Move SP_EL0 save/restore to the guest entry/exit code - Handle PC wrap around on 32bit guests, and narrow all 32bit registers on userspace access
2020-05-04KVM: SVM: fill in kvm_run->debug.arch.dr[67]Paolo Bonzini1-0/+2
The corresponding code was added for VMX in commit 42dbaa5a057 ("KVM: x86: Virtualize debug registers, 2008-12-15) but never for AMD. Fix this. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-05-04KVM: nVMX: Replace a BUG_ON(1) with BUG() to squash clang warningSean Christopherson1-1/+1
Use BUG() in the impossible-to-hit default case when switching on the scope of INVEPT to squash a warning with clang 11 due to clang treating the BUG_ON() as conditional. >> arch/x86/kvm/vmx/nested.c:5246:3: warning: variable 'roots_to_free' is used uninitialized whenever 'if' condition is false [-Wsometimes-uninitialized] BUG_ON(1); Reported-by: kbuild test robot <lkp@intel.com> Fixes: ce8fe7b77bd8 ("KVM: nVMX: Free only the affected contexts when emulating INVEPT") Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com> Message-Id: <20200504153506.28898-1-sean.j.christopherson@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-05-04ARM: dts: s5pv210: Set MAX8998 GPIO pulls on Aries boardsJonathan Bakker1-0/+18
Make sure that the GPIOs are configured correctly for the interrupt (otherwise it won't fire) and disable the pulls on the DVS GPIOs which are outputs. Signed-off-by: Jonathan Bakker <xc-racer2@live.ca> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-05-04ARM: dts: s5pv210: Correct FIMC definitionsJonathan Bakker1-4/+7
The extended mainscaler is only available on FIMC1 and there are minimum pixel alignments that differ from the default. Additionally, the cam-if interface is available on all three while FIMC2 has no rotators. The lcd-wb interface is supported on FIMC1. Signed-off-by: Jonathan Bakker <xc-racer2@live.ca> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-05-04ARM: dts: s5pv210: Assign clocks to MMC devices on Aries boardsJonathan Bakker2-0/+12
The SHDCI controller on Aries devices is a little bit peculiar about the clocks and with a slightly off clock can run into errors such as: mmc2: ADMA error: 0x02000000 mmc2: sdhci: ============ SDHCI REGISTER DUMP =========== mmc2: sdhci: Sys addr: 0x347e4cc4 | Version: 0x00002401 mmc2: sdhci: Blk size: 0x00007004 | Blk cnt: 0x0000fffc mmc2: sdhci: Argument: 0x00000000 | Trn mode: 0x00000013 mmc2: sdhci: Present: 0x01fa0000 | Host ctl: 0x00000012 mmc2: sdhci: Power: 0x00000000 | Blk gap: 0x00000000 mmc2: sdhci: Wake-up: 0x00000000 | Clock: 0x0000010f mmc2: sdhci: Timeout: 0x0000000a | Int stat: 0x00000003 mmc2: sdhci: Int enab: 0x03ff004b | Sig enab: 0x03ff004b mmc2: sdhci: ACmd stat: 0x00000000 | Slot int: 0x00000001 mmc2: sdhci: Caps: 0x05e80080 | Caps_1: 0x00000000 mmc2: sdhci: Cmd: 0x0000163a | Max curr: 0x00000000 mmc2: sdhci: Resp[0]: 0x00000920 | Resp[1]: 0x00000000 mmc2: sdhci: Resp[2]: 0x00000000 | Resp[3]: 0x00000000 mmc2: sdhci: Host ctl2: 0x00000000 mmc2: sdhci: ADMA Err: 0x00000000 | ADMA Ptr: 0x349a3208 mmc2: sdhci: ============================================ mmc2: sdhci: 349a3200: DMA 0x347e4cc0, LEN 0x0004, Attr=0x23 Specifically assign the MMC sclks to be parented from MPLL with specific rates that match the vendor kernel. Signed-off-by: Jonathan Bakker <xc-racer2@live.ca> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-05-04ARM: dts: s5pv210: Enable ADC on Aries boardsJonathan Bakker1-1/+6
On Aries boards, the ADC is used for things such as jack detection and battery temperature monitoring. It is supplied by LDO4 of max8998, so only enable that regulator when we are actually using the ADC. Signed-off-by: Jonathan Bakker <xc-racer2@live.ca> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-05-04ARM: dts: s5pv210: Add an ADC nodeJonathan Bakker1-0/+12
The exynos-adc driver now supports the S5PV210, so add the DT node so that devices can use it. Signed-off-by: Jonathan Bakker <xc-racer2@live.ca> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-05-04ARM: dts: s5pv210: Disable pull for vibrator enable GPIO on Aries boardsJonathan Bakker1-0/+9
The enable GPIO for the fixed vibrator regulator shouldn't be pulled in one direction or the other. Signed-off-by: Jonathan Bakker <xc-racer2@live.ca> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-05-04ARM: dts: s5pv210: Add si470x FM radio to Galaxy SPaweł Chmiel2-1/+48
Add support for the Silicon Labs si4709 FM radio, which can be found on Galaxy S GT-i9000 (but not on most of other Aries variants). Signed-off-by: Paweł Chmiel <pawel.mikolaj.chmiel@gmail.com> Signed-off-by: Jonathan Bakker <xc-racer2@live.ca> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-05-04ARM: dts: s5pv210: Add remaining i2c-gpio adapters to Aries boardsJonathan Bakker1-0/+69
The remaining i2c-gpio adapters that are common to all Aries boards have devices without mainline bindings attachted to them. Add them here for documentation. Signed-off-by: Jonathan Bakker <xc-racer2@live.ca> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-05-04ARM: dts: s5pv210: Add panel support to Aries boardsJonathan Bakker1-16/+52
Aries boards have an s6e63m0 AMOLED panel connected over i2c-spi. Signed-off-by: Jonathan Bakker <xc-racer2@live.ca> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-05-04ARM: dts: s5pv210: Add touchkey support to Aries boardsJonathan Bakker1-0/+58
Aries boards have soft touchkeys, manufactured by Cypress, attached over i2c-gpio. Signed-off-by: Jonathan Bakker <xc-racer2@live.ca> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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