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2022-07-06arm64: dts: qcom: msm8996: clean up PCIe PHY nodeJohan Hovold1-10/+17
Clean up the PCIe PHY node by renaming the wrapper node and grouping the child node properties. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220705114032.22787-15-johan+linaro@kernel.org
2022-07-06arm64: dts: qcom: msm8996: use non-empty ranges for PCIe PHYsJohan Hovold1-13/+13
Clean up the PCIe PHY nodes by using a non-empty ranges property. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220705114032.22787-14-johan+linaro@kernel.org
2022-07-06arm64: dts: qcom: sm8450: drop UFS PHY clock-cellsJohan Hovold1-1/+0
The QMP UFS PHY provides more than one symbol clock and would need an index to differentiate the clocks, but none of this is described by the binding currently. Drop the incorrect '#clock-cells' property for now. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220705114032.22787-12-johan+linaro@kernel.org
2022-07-06arm64: dts: qcom: sm8250: drop UFS PHY clock-cellsJohan Hovold1-1/+0
The QMP UFS PHY provides more than one symbol clock and would need an index to differentiate the clocks, but none of this is described by the binding currently. Drop the incorrect '#clock-cells' property for now. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220705114032.22787-11-johan+linaro@kernel.org
2022-07-06arm64: dts: qcom: sc8280xp: drop UFS PHY clock-cellsJohan Hovold1-2/+0
The QMP UFS PHY provides more than one symbol clock and would need an index to differentiate the clocks, but none of this is described by the binding currently. Drop the incorrect '#clock-cells' property for now. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220705114032.22787-10-johan+linaro@kernel.org
2022-07-06arm64: dts: qcom: sm8450: drop USB PHY clock indexJohan Hovold1-1/+1
The QMP USB PHY provides a single clock so drop the redundant clock index. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220705114032.22787-9-johan+linaro@kernel.org
2022-07-06arm64: dts: qcom: sm8350: drop USB PHY clock indexJohan Hovold1-2/+2
The QMP USB PHY provides a single clock so drop the redundant clock index. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220705114032.22787-8-johan+linaro@kernel.org
2022-07-06arm64: dts: qcom: msm8998: drop USB PHY clock indexJohan Hovold1-1/+1
The QMP USB PHY provides a single clock so drop the redundant clock index. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220705114032.22787-7-johan+linaro@kernel.org
2022-07-06arm64: dts: qcom: ipq8074: drop USB PHY clock indexJohan Hovold1-2/+2
The QMP USB PHY provides a single clock so drop the redundant clock index. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220705114032.22787-5-johan+linaro@kernel.org
2022-07-06arm64: dts: qcom: ipq6018: drop USB PHY clock indexJohan Hovold1-1/+1
The QMP USB PHY provides a single clock so drop the redundant clock index. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220705114032.22787-4-johan+linaro@kernel.org
2022-07-06arm64: dts: qcom: sm8250: add missing PCIe PHY clock-cellsJohan Hovold1-0/+6
Add the missing '#clock-cells' properties to the PCIe QMP PHY nodes. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Fixes: e53bdfc00977 ("arm64: dts: qcom: sm8250: Add PCIe support") Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220705114032.22787-3-johan+linaro@kernel.org
2022-07-06arm64: dts: qcom: sc7280: drop PCIe PHY clock indexJohan Hovold1-2/+2
The QMP PCIe PHY provides a single clock so drop the redundant clock index. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Fixes: bd7d507935ca ("arm64: dts: qcom: sc7280: Add pcie clock support") Fixes: 92e0ee9f83b3 ("arm64: dts: qcom: sc7280: Add PCIe and PHY related nodes") Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220705114032.22787-2-johan+linaro@kernel.org
2022-07-06Revert "arm64: dts: qcom: Fix 'reg-names' for sdhci nodes"Douglas Anderson6-8/+8
This reverts commit afcbe252e9c19161e4d4c95f33faaf592f1de086. The commit in question caused my sc7280-herobrine-herobrine-r1 board not to boot anymore. This shouldn't be too surprising since the driver is relying on the name "cqhci". The issue seems to be that someone decided to change the names of things when the binding moved from .txt to .yaml. We should go back to the names that the bindings have historically specified. For some history, see commit d3392339cae9 ("mmc: cqhci: Update cqhci memory ioresource name") and commit d79100c91ae5 ("dt-bindings: mmc: sdhci-msm: Add CQE reg map"). Fixes: afcbe252e9c1 ("arm64: dts: qcom: Fix 'reg-names' for sdhci nodes") Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220706144706.1.I48f35820bf3670d54940110462555c2d0a6d5eb2@changeid
2022-07-06arm64: dts: qcom: sc7180-idp: add vdds supply to the DSI PHYDmitry Baryshkov1-0/+1
Add the (required) vdss-supply property to the DSI PHY node. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220706145412.1566011-3-dmitry.baryshkov@linaro.org
2022-07-06arm64: dts: qcom: sc7280: use constants for gpucc clocks and power-domainsDmitry Baryshkov1-16/+16
To ease merging of bindings and dts files, the constants were replaced with numeric values. Change them back to defined constants. While we are at it, fix the indentation of these clocks properties to follow established guidelines. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220706145412.1566011-2-dmitry.baryshkov@linaro.org
2022-07-06arm64: dts: qcom: msm8996: add missing DSI clock assignmentsDmitry Baryshkov1-0/+4
Add missing DSI clock assignments to properly use DSI PHY clocks as DSI byte and pixel clock parents. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220706145412.1566011-1-dmitry.baryshkov@linaro.org
2022-07-06arm64: dts: qcom: ipq8074: add reset to SDHCIRobert Marko1-0/+1
Add reset to SDHCI controller so it can be reset to avoid timeout issues after software reset due to bootloader set configuration. Signed-off-by: Robert Marko <robimarko@gmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220704143554.1180927-2-robimarko@gmail.com
2022-07-06arm64: dts: qcom: sdm845: Add CPU BWMONKrzysztof Kozlowski1-0/+37
Add device node for CPU-memory BWMON device (bandwidth monitoring) on SDM845 measuring bandwidth between CPU (gladiator_noc) and Last Level Cache (memnoc). Usage of this BWMON allows to remove fixed bandwidth votes from cpufreq (CPU nodes) thus achieve high memory throughput even with lower CPU frequencies. Co-developed-by: Thara Gopinath <thara.gopinath@gmail.com> Signed-off-by: Thara Gopinath <thara.gopinath@gmail.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220704121730.127925-5-krzysztof.kozlowski@linaro.org
2022-07-06arm64: dts: qcom: ipq8074: move ARMv8 timer out of SoC nodeRobert Marko1-8/+8
The ARM timer is usually considered not part of SoC node, just like other ARM designed blocks (PMU, PSCI). This fixes dtbs_check warning: arch/arm64/boot/dts/qcom/ipq8072-ax9000.dtb: soc: timer: {'compatible': ['arm,armv8-timer'], 'interrupts': [[1, 2, 3848], [1, 3, 3848], [1, 4, 3848], [1, 1, 3848]]} should not be valid under {'type': 'object'} From schema: dtschema/schemas/simple-bus.yaml Signed-off-by: Robert Marko <robimarko@gmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> [bjorn: Moved node after "soc" for alphabetical ordering] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220704113318.623102-1-robimarko@gmail.com
2022-07-06arm64: dta: qcom: sc7180: delete vdda-1p2 and vdda-0p9 from mdss_dpKuogee Hsieh1-2/+0
Both vdda-1p2-supply and vdda-0p9-supply regulators are controlled by dp combo phy. Therefore remove them from dp controller. Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1656690436-15221-1-git-send-email-quic_khsieh@quicinc.com
2022-07-06arm64: dts: qcom: sdm845: Switch PSCI cpu idle states from PC to OSIAbel Vesa2-54/+213
Switch from the flat PC idle states of sdm845 to OSI hierarchical idle states. The exceptions are the cheza plaftorms, which need to remain with PC idle states. So in order allow all the other platforms to switch, while cheza platforms to remain the same, replace the PC idle states with the OSI ones in the main SDM845 dtsi, and then override the inherited OSI states with PC ones, delete inherited psci cpus nodes, domain idle states and power domain properties. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Tested-by: Steev Klimaszewski <steev@kali.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220630101403.1888541-1-abel.vesa@linaro.org
2022-07-06arm64: dts: qcom: extend scm compatible stringsDavid Heidelberg4-4/+4
First device specific compatible, then general one. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: David Heidelberg <david@ixit.cz> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220626183247.142776-2-david@ixit.cz
2022-07-06arm64: dts: qcom: add device tree for LG G7 and LG V35Anton Bambura4-0/+728
Adds initial support for the LG G7 (judyln) and LG V35 (judyp) phones. Currently supported features: - Display via simplefb (panel driver is WIP) - Keys - Micro SD card - Modem (not tested much, but initialises) - UFS (crashes during intensive workloads, may need quirks) - USB in peripheral mode Notable missing features: - Enabling WiFi causes a remoteproc crash, so it's disabled here. Needs to be debugged - ideas welcome! Signed-off-by: Anton Bambura <jenneron@protonmail.com> Signed-off-by: Stefan Hansson <newbie13xd@gmail.com> Tested-by: Gregari Ivanov <llamashere@posteo.de> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220626164536.16011-2-newbie13xd@gmail.com
2022-07-06arm64: dts: qcom: msm8996: add xo clock source to rpmccDmitry Baryshkov1-0/+2
Add XO clock source to the RPM clock controller. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220620071936.1558906-5-dmitry.baryshkov@linaro.org
2022-07-06arm64: dts: qcom: msm8996: add GCC's optional clock sourcesDmitry Baryshkov1-2/+16
Add missing GCC clock sources. This includes PCIe and USB PIPE and UFS symbol clocks. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220620071936.1558906-4-dmitry.baryshkov@linaro.org
2022-07-06arm64: dts: qcom: msm8996: correct #clock-cells for QMP PHY nodesDmitry Baryshkov1-2/+4
The commit 82d61e19fccb ("arm64: dts: qcom: msm8996: Move '#clock-cells' to QMP PHY child node") moved the '#clock-cells' properties to the child nodes. However it missed the fact that the property must have been set to <0> (as all pipe clocks use of_clk_hw_simple_get as the xlate function. Also the mentioned commit didn't add '#clock-cells' properties to second and third PCIe PHY nodes. Correct both these mistakes: - Set '#clock-cells' to <0>, - Add the property to pciephy_1 and pciephy_2 nodes. Fixes: 82d61e19fccb ("arm64: dts: qcom: msm8996: Move '#clock-cells' to QMP PHY child node") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220620071936.1558906-3-dmitry.baryshkov@linaro.org
2022-07-06arm64: dts: qcom: sdm845-shift-axolotl: Enable pmi9889 LPG LEDDylan Van Assche1-0/+29
Enables the RGB notification LED on the SHIFT 6mq (sdm845-shift-axolotl) with the Qualcomm Light Pulse Generator bindings by Bjorn Andersson [1]. Patches are merged in for-next branch of linux-leds. Tested these changes on the SHIFT 6mq. [1] https://git.kernel.org/pub/scm/linux/kernel/git/pavel/linux-leds.git/commit/?h=for-next&id=a8e53db46f19f67be6a26488aafb7d10c78e33bd Signed-off-by: Dylan Van Assche <me@dylanvanassche.be> Reviewed-by: Alexander Martinz <amartinz@shiftphones.com> Tested-by: Alexander Martinz <amartinz@shiftphones.com> Tested-by: Caleb Connolly <caleb@connolly.tech> Reviewed-by: Caleb Connolly <caleb@connolly.tech> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220512054439.13971-1-me@dylanvanassche.be
2022-07-06arm64: dts: ti: k3-am62-main: Enable crypto acceleratorJayesh Choudhary1-0/+13
Add the node for sa3ul crypto accelerator. Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20220624043905.129207-1-j-choudhary@ti.com
2022-07-06arm64: dts: ti: k3-am625-sk: Enable ramoopsGuillaume La Roque1-0/+9
Enable ramoops features to easily debug some issues. Signed-off-by: Guillaume La Roque <glaroque@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20220517122828.2985179-1-glaroque@baylibre.com
2022-07-06arm64: dts: ti: k3-am642-sk: Add pinmux corresponding to main_uart0Aswath Govindraju1-0/+14
Add pinmux details required for the zeroth instance of main UART. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20220516113417.3516-1-a-govindraju@ti.com
2022-07-06ARM: 9214/1: alignment: advance IT state after emulating Thumb instructionArd Biesheuvel3-25/+30
After emulating a misaligned load or store issued in Thumb mode, we have to advance the IT state by hand, or it will get out of sync with the actual instruction stream, which means we'll end up applying the wrong condition code to subsequent instructions. This might corrupt the program state rather catastrophically. So borrow the it_advance() helper from the probing code, and use it on CPSR if the emulated instruction is Thumb. Cc: <stable@vger.kernel.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
2022-07-06ARM: 9213/1: Print message about disabled Spectre workarounds only onceDmitry Osipenko1-2/+1
Print the message about disabled Spectre workarounds only once. The message is printed each time CPU goes out from idling state on NVIDIA Tegra boards, causing storm in KMSG that makes system unusable. Cc: stable@vger.kernel.org Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
2022-07-06ARM: 9212/1: domain: Modify Kconfig help textLinus Walleij1-1/+5
After the removal of set_fs() the reference to set_fs() is stale. Alter the helptext to reflect what the config option really does. Fixes: 8ac6f5d7f84b ("ARM: 9113/1: uaccess: remove set_fs() implementation") Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
2022-07-06ARM: 9211/1: domain: drop modify_domain()Linus Walleij1-13/+0
This function/macro isn't used anywhere in the kernel. The only user was set_fs() and was deleted in the set_fs() removal patch set. Fixes: 8ac6f5d7f84b ("ARM: 9113/1: uaccess: remove set_fs() implementation") Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
2022-07-06ARM: 9210/1: Mark the FDT_FIXED sections as shareableZhen Lei2-1/+15
commit 7a1be318f579 ("ARM: 9012/1: move device tree mapping out of linear region") use FDT_FIXED_BASE to map the whole FDT_FIXED_SIZE memory area which contains fdt. But it only reserves the exact physical memory that fdt occupied. Unfortunately, this mapping is non-shareable. An illegal or speculative read access can bring the RAM content from non-fdt zone into cache, PIPT makes it to be hit by subsequently read access through shareable mapping(such as linear mapping), and the cache consistency between cores is lost due to non-shareable property. |<---------FDT_FIXED_SIZE------>| | | ------------------------------- | <non-fdt> | <fdt> | <non-fdt> | ------------------------------- 1. CoreA read <non-fdt> through MT_ROM mapping, the old data is loaded into the cache. 2. CoreB write <non-fdt> to update data through linear mapping. CoreA received the notification to invalid the corresponding cachelines, but the property non-shareable makes it to be ignored. 3. CoreA read <non-fdt> through linear mapping, cache hit, the old data is read. To eliminate this risk, add a new memory type MT_MEMORY_RO. Compared to MT_ROM, it is shareable and non-executable. Here's an example: list_del corruption. prev->next should be c0ecbf74, but was c08410dc kernel BUG at lib/list_debug.c:53! ... ... PC is at __list_del_entry_valid+0x58/0x98 LR is at __list_del_entry_valid+0x58/0x98 psr: 60000093 sp : c0ecbf30 ip : 00000000 fp : 00000001 r10: c08410d0 r9 : 00000001 r8 : c0825e0c r7 : 20000013 r6 : c08410d0 r5 : c0ecbf74 r4 : c0ecbf74 r3 : c0825d08 r2 : 00000000 r1 : df7ce6f4 r0 : 00000044 ... ... Stack: (0xc0ecbf30 to 0xc0ecc000) bf20: c0ecbf74 c0164fd0 c0ecbf70 c0165170 bf40: c0eca000 c0840c00 c0840c00 c0824500 c0825e0c c0189bbc c088f404 60000013 bf60: 60000013 c0e85100 000004ec 00000000 c0ebcdc0 c0ecbf74 c0ecbf74 c0825d08 ... ... < next prev > (__list_del_entry_valid) from (__list_del_entry+0xc/0x20) (__list_del_entry) from (finish_swait+0x60/0x7c) (finish_swait) from (rcu_gp_kthread+0x560/0xa20) (rcu_gp_kthread) from (kthread+0x14c/0x15c) (kthread) from (ret_from_fork+0x14/0x24) The faulty list node to be deleted is a local variable, its address is c0ecbf74. The dumped stack shows that 'prev' = c0ecbf74, but its value before lib/list_debug.c:53 is c08410dc. A large amount of printing results in swapping out the cacheline containing the old data(MT_ROM mapping is read only, so the cacheline cannot be dirty), and the subsequent dump operation obtains new data from the DDR. Fixes: 7a1be318f579 ("ARM: 9012/1: move device tree mapping out of linear region") Suggested-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Kefeng Wang <wangkefeng.wang@huawei.com> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
2022-07-06ARM: 9209/1: Spectre-BHB: avoid pr_info() every time a CPU comes out of idleArd Biesheuvel1-3/+3
Jon reports that the Spectre-BHB init code is filling up the kernel log with spurious notifications about which mitigation has been enabled, every time any CPU comes out of a low power state. Given that Spectre-BHB mitigations are system wide, only a single mitigation can be enabled, and we already print an error if two types of CPUs coexist in a single system that require different Spectre-BHB mitigations. This means that the pr_info() that describes the selected mitigation does not need to be emitted for each CPU anyway, and so we can simply emit it only once. In order to clarify the above in the log message, update it to describe that the selected mitigation will be enabled on all CPUs, including ones that are unaffected. If another CPU comes up later that is affected and requires a different mitigation, we report an error as before. Fixes: b9baf5c8c5c3 ("ARM: Spectre-BHB workaround") Tested-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
2022-07-06ARM: dts: qcom: msm8974: rename GPU's OPP table nodeDmitry Baryshkov1-1/+1
Rename the GPU's opp table node to make it follow the display/msm/gpu.yaml schema. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220706145412.1566011-6-dmitry.baryshkov@linaro.org
2022-07-06ARM: dts: qcom: apq8064: disable DSI and DSI PHY by defaultDmitry Baryshkov1-0/+3
Disable DSI and DSI PHY devices by default. The only actual user, Nexus 7, already contains `status = "okay"` property in the respective devices nodes. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220706145412.1566011-5-dmitry.baryshkov@linaro.org
2022-07-06ARM: dts: qcom: apq8064: rename DSI PHY iface clockDmitry Baryshkov1-1/+1
Follow the usual scheme and use name 'iface' rather than 'iface_clk' for the interface clock. The DSI PHY driver can cope with both of them, so there is no breakage. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220706145412.1566011-4-dmitry.baryshkov@linaro.org
2022-07-06arm64: defconfig: enable Qualcomm Bandwidth MonitorKrzysztof Kozlowski1-0/+1
Enable the Qualcomm Bandwidth Monitor to allow scaling interconnects depending on bandwidth usage between CPU and memory. This is used already on Qualcomm SDM845 SoC. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220704121730.127925-4-krzysztof.kozlowski@linaro.org
2022-07-06ARM: dts: qcom: extend scm compatible to match dt-schemaDavid Heidelberg4-4/+4
First device specific compatible, then general one. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: David Heidelberg <david@ixit.cz> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220626183247.142776-1-david@ixit.cz
2022-07-06Merge tag 'dt-cleanup-5.20-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dtArnd Bergmann91-348/+301
Cleanup of ARM DTS for v5.20, part two Series of cleanups for ARM DTS - white-spaces, gpio-key subnode names and gpio-key properties for more boards: TI, Marvell, AT91 and Aspeed. * tag 'dt-cleanup-5.20-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: ARM: dts: aspeed: correct gpio-keys properties ARM: dts: aspeed: align gpio-key node names with dtschema ARM: dts: at91: drop unneeded status from gpio-keys ARM: dts: at91: correct gpio-keys properties ARM: dts: at91: align gpio-key node names with dtschema ARM: dts: omap: correct gpio-keys properties ARM: dts: omap: align gpio-key node names with dtschema ARM: dts: marvell: correct gpio-keys properties ARM: dts: marvell: align gpio-key node names with dtschema ARM: dts: omap: adjust whitespace around '=' ARM: dts: ti: adjust whitespace around '=' Link: https://lore.kernel.org/r/20220706163754.33064-2-krzysztof.kozlowski@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-07-06Merge tag 'dt64-cleanup-5.20-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dtArnd Bergmann2-4/+4
Cleanup of ARM64 DTS for v5.20, part two Remaining cleanups for ARM64 DTS: gpio-keys and led node names on Marvel platforms. * tag 'dt64-cleanup-5.20-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: arm64: dts: marvell: armada-3720: align lednode names with dtschema arm64: dts: marvell: align gpio-key node names with dtschema Link: https://lore.kernel.org/r/20220706163754.33064-1-krzysztof.kozlowski@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-07-06arm64: dts: qcom: sm6125: Add DLL/DDR configuration on SDHCI 1/2Marijn Suijten1-0/+6
These config values have been extracted from CodeLinaro's most recent trinket/sm6125 tag: https://git.codelinaro.org/clo/la/kernel/msm-4.14/-/blob/LA.UM.9.11.r1-05600-NICOBAR.QSSI12.0/arch/arm64/boot/dts/qcom/trinket.dtsi Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220508100336.127176-3-marijn.suijten@somainline.org
2022-07-06arm64: dts: qcom: sm6125: Append -state suffix to pinctrl nodesMarijn Suijten2-6/+6
According to qcom,sm6125-pinctrl.yaml all nodes inside the tlmm must be suffixed by -state: qcom/sm6125-sony-xperia-seine-pdx201.dtb: pinctrl@500000: 'sdc2-off', 'sdc2-on' do not match any of the regexes: '-state$', 'pinctrl-[0-9]+' The label names have been updated to match, going from sdc2_state_X to sdc2_X_state. Fixes: cff4bbaf2a2d ("arm64: dts: qcom: Add support for SM6125") Fixes: 82e1783890b7 ("arm64: dts: qcom: sm6125: Add support for Sony Xperia 10II") Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220508100336.127176-2-marijn.suijten@somainline.org
2022-07-06arm64: dts: qcom: sm6125: Move sdc2 pinctrl from seine-pdx201 to sm6125Marijn Suijten2-28/+30
Both the sdc2-on and sdc2-off pinctrl nodes are used by the sdhci@4784000 node in sm6125.dtsi. Surprisingly sdc2-off is defined in sm6125, yet its sdc2-on counterpart is only defined in board-specific DT for the Sony Seine PDX201 board/device resulting in an "undefined label &sdc2_state_on" error if sm6125.dtsi were included elsewhere. This sm6125 base dtsi should not rely on externally defined labels; the properties referencing it should then also be written externally. Since the sdc2-on pin configuration is board-independent just like sdc2-off, move it from seine-pdx201.dts into sm6125.dtsi. The SDCard-detect pin (gpio98) is however board-specific, and remains as an overwrite in seine-pdx201.dts for both the on and off state. As a drive-by cleanup, reorder bias- and drive-strength properties. Fixes: cff4bbaf2a2d ("arm64: dts: qcom: Add support for SM6125") Fixes: 82e1783890b7 ("arm64: dts: qcom: sm6125: Add support for Sony Xperia 10II") Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220508100336.127176-1-marijn.suijten@somainline.org
2022-07-06arm64: dts: qcom: db820c: Add user LEDsBjorn Andersson1-0/+56
The db820c has 4 "user LEDs", all connected to the PMI8994. The first three are connected to the three current sinks provided by the TRILED and the fourth is connected to MPP2. By utilizing the DTEST bus the MPP is fed the control signal from the fourth LPG block, providing a consistent interface to the user. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Dylan Van Assche <me@dylanvanassche.be> Link: https://lore.kernel.org/r/20220505022706.1692554-5-bjorn.andersson@linaro.org
2022-07-06arm64: dts: qcom: pmi8994: Define MPP blockBjorn Andersson1-0/+10
The pmi8994 has 4 multi-purpose-pins, add these to the definition. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Dylan Van Assche <me@dylanvanassche.be> Link: https://lore.kernel.org/r/20220505022706.1692554-4-bjorn.andersson@linaro.org
2022-07-06arm64: dts: qcom: sdm845: Enable user LEDs on DB845cBjorn Andersson1-0/+30
The DB845c has 4 "user LEDs", the last one is already supported as it's just wired to a gpio. Now that the LPG binding is in place we can wire up the other 3 LEDs as well. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Caleb Connolly <caleb@connolly.tech> Reviewed-by: Dylan Van Assche <me@dylanvanassche.be> Link: https://lore.kernel.org/r/20220505022706.1692554-3-bjorn.andersson@linaro.org
2022-07-06arm64: dts: qcom: Add LPG to pm8916, pm8994, pmi8994 and pmi8998Bjorn Andersson4-1/+38
Add PWM/LPG nodes to the PMICs currently supported by the binding. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Caleb Connolly <caleb@connolly.tech> Reviewed-by: Dylan Van Assche <me@dylanvanassche.be> Link: https://lore.kernel.org/r/20220505022706.1692554-2-bjorn.andersson@linaro.org
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