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2022-07-06arm64: dts: qcom: sm8350: Replace integers with rpmpd definesRobert Foss1-8/+8
Replace &rpmhpd power domain integers with their respective defines in order to improve legibility. Signed-off-by: Robert Foss <robert.foss@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220706152830.2021197-1-robert.foss@linaro.org
2022-07-06arm64: dts: qcom: sm8350: Add DISPCC nodeRobert Foss1-0/+26
Add the dispcc clock-controller DT node for sm8350. Signed-off-by: Robert Foss <robert.foss@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220706154337.2026269-6-robert.foss@linaro.org
2022-07-06arm64: dts: qcom: sm8450: Add description of camera clock controllerVladimir Zapolskiy1-0/+16
The change adds description of Qualcomm SM8450 camera clock controller. Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220701062622.2757831-3-vladimir.zapolskiy@linaro.org
2022-07-06Merge tag 'for-linus' of https://github.com/openrisc/linuxLinus Torvalds1-1/+1
Pull OpenRISC fixes from Stafford Horne: "Fixups for OpenRISC found during recent testing: - An OpenRISC irqchip fix to stop acking level interrupts which was causing issues on SMP platforms - A comment typo fix in our unwinder code" * tag 'for-linus' of https://github.com/openrisc/linux: openrisc: unwinder: Fix grammar issue in comment irqchip: or1k-pic: Undefine mask_ack for level triggered hardware
2022-07-06m68k: virt: Fix missing platform_device_unregister() on error in virt_platform_init()Yang Yingliang1-25/+33
Add the missing platform_device_unregister() before return from virt_platform_init() in the error handling case. Fixes: 05d51e42df06 ("m68k: Introduce a virtual m68k machine") Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Link: https://lore.kernel.org/r/20220628084903.3147123-1-yangyingliang@huawei.com Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2022-07-06m68k: virt: Use RNG seed from bootinfo blockJason A. Donenfeld2-0/+19
Other virt VMs can pass RNG seeds via the "rng-seed" device tree property or via UEFI, but m68k doesn't have either. Instead it has its own bootinfo protocol. So this commit adds support for receiving a RNG seed from it, which will be used at the earliest possible time in boot, just like device tree. Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com> Link: https://lore.kernel.org/r/20220626111509.330159-1-Jason@zx2c4.com Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2022-07-06m68k: bitops: Change __fls to return and accept unsigned longAmadeusz Sławiński1-1/+1
As per asm-generic definition and other architectures __fls should return and accept unsigned long as its parameter. No functional change is expected as return value should fit in unsigned long. Reviewed-by: Cezary Rojewski <cezary.rojewski@intel.com> Signed-off-by: Amadeusz Sławiński <amadeuszx.slawinski@linux.intel.com> Link: https://lore.kernel.org/r/20220527115345.2588775-3-amadeuszx.slawinski@linux.intel.com Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2022-07-06m68k: Kconfig.machine: Add endif commentJuerg Haefliger1-1/+1
Add missing trailing endif comment. Signed-off-by: Juerg Haefliger <juergh@canonical.com> Link: https://lore.kernel.org/r/20220524075848.21684-4-juergh@canonical.com Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2022-07-06m68k: Kconfig.debug: Replace single quotesJuerg Haefliger1-3/+3
Replace single quotes in strings with double quotes to match the majority of the rest of the kernel's Kconfig files. Signed-off-by: Juerg Haefliger <juergh@canonical.com> Link: https://lore.kernel.org/r/20220524075848.21684-3-juergh@canonical.com Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2022-07-06m68k: Kconfig.cpu: Fix indentation and add endif commentsJuerg Haefliger1-4/+3
The convention for indentation seems to be a single tab. Help text is further indented by an additional two whitespaces. Fix the lines that violate these rules. While at it, add missing trailing endif comments and squeeze multiple empty lines. Signed-off-by: Juerg Haefliger <juergh@canonical.com> Link: https://lore.kernel.org/r/20220524075848.21684-2-juergh@canonical.com Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2022-07-06Merge tag 'juno-updates-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into arm/dtArnd Bergmann7-32/+37
Armv8 Juno/FVP updates for v5.20 Just a small bunch of miscellaneous updates: addition of missing cache-level property to L2 caches on Juno, whitespace adjustments and removal of erroneous 'mbox-name' and 'panel-dpi' compatible in the device tree nodes. * tag 'juno-updates-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux: arm64: dts: juno: Add cache-level property to L2 caches arm64: dts: arm: adjust whitespace around '=' arm64: dts: arm/juno: Drop erroneous 'mbox-name' property arm64: dts: arm/fvp-base-revc: Remove 'panel-dpi' compatible Link: https://lore.kernel.org/r/20220706115026.2272643-1-sudeep.holla@arm.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-07-06Merge tag 'stm32-dt-for-v5.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into arm/dtArnd Bergmann24-109/+772
STM32 DT for v5.20, round 1 Highlights: ---------- - MCU: -Fix whitespace coding style. No functional changes. - MPU: - General: - Remove specific IPCC wakeup interrupt on STM32MP15. - Enable OPTEE firmware and scmi support (clock/reset) on STM32MP13. It allows to enable RCC clock driver. - Add new pins configurations groups. - DH boards: - Add DHCOR based DRC Compact board. It embeds: 2xETH, 1xCAN, uSD, USB, eMMC and SDIO wifi. - Add ST MIPID02 bindings to AV96 (not enabled by default) - OSD32: - Correct vcc-supply for eeprom. - fix missing internally connected voltage regulator (ldo3 supplied by vdd_ddr). * tag 'stm32-dt-for-v5.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: (25 commits) ARM: dts: stm32: Add ST MIPID02 bindings to AV96 ARM: dts: stm32: Add alternate pinmux for RCC pin ARM: dts: stm32: Add alternate pinmux for DCMI pins ARM: dts: stm32: Add DHCOR based DRC Compact board ARM: dts: stm32: Add alternate pinmux for UART5 pins ARM: dts: stm32: Add alternate pinmux for UART4 pins ARM: dts: stm32: Add alternate pinmux for UART3 pins ARM: dts: stm32: Add alternate pinmux for SPI2 pins ARM: dts: stm32: Add alternate pinmux for CAN1 pins dt-bindings: arm: stm32: Add compatible string for DH electronics DHCOR DRC Compact ARM: dts: stm32: Fix SPI2 pinmux pin comments on stm32mp15 ARM: dts: stm32: add optee reserved memory on stm32mp135f-dk ARM: dts: stm32: add RCC on STM32MP13x SoC family ARM: dts: stm32: enable optee firmware and SCMI support on STM32MP13 dt-bindings: rcc: stm32: select the "secure" path for stm32mp13 ARM: dts: stm32: correct vcc-supply for eeprom on stm32mp15xx-osd32 ARM: dts: stm32: fix missing internally connected voltage regulator for OSD32MP1 ARM: dts: stm32: adjust whitespace around '=' on MCU boards ARM: dts: stm32: Move DHCOR BUCK3 VDD 2V9 adjustment to 1V8 DTSI ARM: dts: stm32: remove the IPCC "wakeup" IRQ on stm32mp151 ... Link: https://lore.kernel.org/r/a250f32b-f67c-2922-0748-e39dc791e95c@foss.st.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-07-06Merge tag 'at91-dt-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/dtArnd Bergmann18-37/+66
AT91 DT for v5.20 It contains: - compilation warning fixes for SAMA5D2 - updates for all AT91 device tree to use generic name for reset controller - reset controller node for SAMA7G5 - MCAN1 and UDPHS nodes for LAN966 SoCs - Flexcom3 bindings were updated for lan966x-pcb8291.dts board to cope with reality * tag 'at91-dt-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: ARM: dts: lan966x: Add UDPHS support dt-bindings: usb: atmel: Add Microchip LAN9662 compatible string ARM: dts: lan966x: Cleanup flexcom3 usart pinctrl settings. ARM: dts: lan966x: Add mcan1 node. ARM: dts: at91: sama7g5: add reset-controller node ARM: dts: at91: use generic name for reset controller ARM: dts: at91: sama5d2: fix compilation warning ARM: dts: at91: sama5d2: fix compilation warning Link: https://lore.kernel.org/r/20220705084637.818216-1-claudiu.beznea@microchip.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-07-06Merge tag 'ux500-dts-v5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik into arm/dtArnd Bergmann4-11/+6
Ux500 DTS updates for the v5.20 kernel: - Fix orientation matrices on a few U8500 mobile phones. - Drop unused i2c power supply handled by the power domain. * tag 'ux500-dts-v5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik: ARM: dts: ux500: Drop unused i2c power domain supply ARM: dts: ux500: Fix Gavini accelerometer mounting matrix ARM: dts: ux500: Fix Codina accelerometer mounting matrix ARM: dts: ux500: Fix Janice accelerometer mounting matrix Link: https://lore.kernel.org/r/CACRpkdY1MG=HG+tOCmD1_LEAStV1-ycCLkwShMRD4R=4jGDYHQ@mail.gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-07-06Merge tag 'v5.20-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dtArnd Bergmann23-44/+60
NFC flash node on rk3066a-mk808 and some dts styling fixes (alignment and node names). * tag 'v5.20-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: ARM: dts: rockchip: correct gpio-keys properties on rk3288-tinker ARM: dts: rockchip: align gpio-key node names with dtschema ARM: dts: rockchip: adjust whitespace around '=' ARM: dts: rockchip: enable nfc node in rk3066a-mk808.dts Link: https://lore.kernel.org/r/14795241.VsHLxoZxqI@phil Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-07-06Merge tag 'v5.20-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dtArnd Bergmann36-51/+854
New board the Radxa Rock Pi S, enablement of graphics support and hdmi-audio on rk356x in general plus necessary board-specific changes on Rock-3A, Quartz64-A, rk3568-evb, BPI-R2-Pro. A number of additional peripherals on BPI-R2-Pro (gpu, thermal, rtc) and PCIe2x1 support on rk3568 and enablement on Quart64-A as well as a number of additional peripherals to this board (sfc node, sdr-104 support, fan). And finally touch panel support for rockpro64 and some misc dt cleanups (node names for dtschema and styling). * tag 'v5.20-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (27 commits) arm64: dts: rockchip: enable hdmi tx audio on rock-3a arm64: dts: rockchip: enable hdmi tx audio on rk3568-evb1-v10 arm64: dts: rockchip: align gpio-key node names with dtschema arm64: dts: rockchip: rock-pi-s add more peripherals arm64: dts: rockchip: add ROCK Pi S DTS support dt-bindings: arm: rockchip: Add Radxa ROCK Pi S arm64: dts: rockchip: Add missing space around regulator-name on rk3368-orion-r68 arm64: dts: rockchip: enable the gpu on BPI-R2-Pro arm64: dts: rockchip: configure thermal shutdown for BPI-R2-Pro arm64: dts: rockchip: Enable HDMI audio on BPI R2 Pro arm64: dts: rockchip: enable vop2 and hdmi tx on BPI-R2-Pro arm64: dts: rockchip: set display regulators to always-on on BPI-R2-Pro arm64: dts: rockchip: add RTC to BPI-R2 Pro arm64: dts: rockchip: Enable HDMI audio on Quartz64 A arm64: dts: rockchip: Add HDMI audio nodes to rk356x arm64: dts: rockchip: adjust whitespace around '=' arm64: dts: rockchip: enable vop2 and hdmi tx on rock-3a arm64: dts: rockchip: enable vop2 and hdmi tx on quartz64a arm64: dts: rockchip: rk3568-evb: Enable VOP2 and hdmi arm64: dts: rockchip: rk356x: Add HDMI nodes ... Link: https://lore.kernel.org/r/40088956.J2Yia2DhmK@phil Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-07-06Merge tag 'v5.19-rockchip-socfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/fixesArnd Bergmann1-2/+5
Add a missing of_node_put in suspend code error path. * tag 'v5.19-rockchip-socfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: ARM: rockchip: Add missing of_node_put() in rockchip_suspend_init() Link: https://lore.kernel.org/r/7527945.6fTUFtlzNn@phil Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-07-06Merge tag 'v5.19-rockchip-dtsfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/fixesArnd Bergmann4-4/+9
rk3399 vdu clock-rate fix, otg port fix on Quartz64-A and ethernet fix on Quartz64-B (actual production model) * tag 'v5.19-rockchip-dtsfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: arm64: dts: rockchip: Assign RK3399 VDU clock rate arm64: dts: rockchip: Fix Quartz64-A dwc3 otg port behavior arm64: dts: rockchip: Fix ethernet on production Quartz64-B Link: https://lore.kernel.org/r/7723415.29KlJPOoH8@phil Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-07-06x86/compressed/64: Add identity mappings for setup_data entriesMichael Roth1-0/+13
The decompressed kernel initially relies on the identity map set up by the boot/compressed kernel for accessing things like boot_params. With the recent introduction of SEV-SNP support, the decompressed kernel also needs to access the setup_data entries pointed to by boot_params->hdr.setup_data. This can lead to a crash in the kexec kernel during early boot due to these entries not currently being included in the initial identity map, see thread at Link below. Include mappings for the setup_data entries in the initial identity map. [ bp: Massage commit message and use a helper var for better readability. ] Fixes: b190a043c49a ("x86/sev: Add SEV-SNP feature detection/setup") Reported-by: Jun'ichi Nomura <junichi.nomura@nec.com> Signed-off-by: Michael Roth <michael.roth@amd.com> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lore.kernel.org/r/TYCPR01MB694815CD815E98945F63C99183B49@TYCPR01MB6948.jpnprd01.prod.outlook.com
2022-07-06KVM: arm64: Don't return from void functionQuentin Perret2-2/+2
Although harmless, the return statement in kvm_unexpected_el2_exception is rather confusing as the function itself has a void return type. The C standard is also pretty clear that "A return statement with an expression shall not appear in a function whose return type is void". Given that this return statement does not seem to add any actual value, let's not pointlessly violate the standard. Build-tested with GCC 10 and CLANG 13 for good measure, the disassembled code is identical with or without the return statement. Fixes: e9ee186bb735 ("KVM: arm64: Add kvm_extable for vaxorcism code") Signed-off-by: Quentin Perret <qperret@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220705142310.3847918-1-qperret@google.com
2022-07-05context_tracking: Take NMI eqs entrypoints over RCUFrederic Weisbecker2-5/+5
The RCU dynticks counter is going to be merged into the context tracking subsystem. Prepare with moving the NMI extended quiescent states entrypoints to context tracking. For now those are dumb redirection to existing RCU calls. Acked-by: Paul E. McKenney <paulmck@kernel.org> Signed-off-by: Frederic Weisbecker <frederic@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Neeraj Upadhyay <quic_neeraju@quicinc.com> Cc: Uladzislau Rezki <uladzislau.rezki@sony.com> Cc: Joel Fernandes <joel@joelfernandes.org> Cc: Boqun Feng <boqun.feng@gmail.com> Cc: Nicolas Saenz Julienne <nsaenz@kernel.org> Cc: Marcelo Tosatti <mtosatti@redhat.com> Cc: Xiongfeng Wang <wangxiongfeng2@huawei.com> Cc: Yu Liao <liaoyu15@huawei.com> Cc: Phil Auld <pauld@redhat.com> Cc: Paul Gortmaker<paul.gortmaker@windriver.com> Cc: Alex Belits <abelits@marvell.com> Signed-off-by: Paul E. McKenney <paulmck@kernel.org> Reviewed-by: Nicolas Saenz Julienne <nsaenzju@redhat.com> Tested-by: Nicolas Saenz Julienne <nsaenzju@redhat.com>
2022-07-05context_tracking: Take IRQ eqs entrypoints over RCUFrederic Weisbecker3-5/+5
The RCU dynticks counter is going to be merged into the context tracking subsystem. Prepare with moving the IRQ extended quiescent states entrypoints to context tracking. For now those are dumb redirection to existing RCU calls. [ paulmck: Apply Stephen Rothwell feedback from -next. ] [ paulmck: Apply Nathan Chancellor feedback. ] Acked-by: Paul E. McKenney <paulmck@kernel.org> Signed-off-by: Frederic Weisbecker <frederic@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Neeraj Upadhyay <quic_neeraju@quicinc.com> Cc: Uladzislau Rezki <uladzislau.rezki@sony.com> Cc: Joel Fernandes <joel@joelfernandes.org> Cc: Boqun Feng <boqun.feng@gmail.com> Cc: Nicolas Saenz Julienne <nsaenz@kernel.org> Cc: Marcelo Tosatti <mtosatti@redhat.com> Cc: Xiongfeng Wang <wangxiongfeng2@huawei.com> Cc: Yu Liao <liaoyu15@huawei.com> Cc: Phil Auld <pauld@redhat.com> Cc: Paul Gortmaker<paul.gortmaker@windriver.com> Cc: Alex Belits <abelits@marvell.com> Signed-off-by: Paul E. McKenney <paulmck@kernel.org> Reviewed-by: Nicolas Saenz Julienne <nsaenzju@redhat.com> Tested-by: Nicolas Saenz Julienne <nsaenzju@redhat.com>
2022-07-05context_tracking: Take idle eqs entrypoints over RCUFrederic Weisbecker1-2/+3
The RCU dynticks counter is going to be merged into the context tracking subsystem. Start with moving the idle extended quiescent states entrypoints to context tracking. For now those are dumb redirections to existing RCU calls. [ paulmck: Apply kernel test robot feedback. ] Signed-off-by: Frederic Weisbecker <frederic@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Neeraj Upadhyay <quic_neeraju@quicinc.com> Cc: Uladzislau Rezki <uladzislau.rezki@sony.com> Cc: Joel Fernandes <joel@joelfernandes.org> Cc: Boqun Feng <boqun.feng@gmail.com> Cc: Nicolas Saenz Julienne <nsaenz@kernel.org> Cc: Marcelo Tosatti <mtosatti@redhat.com> Cc: Xiongfeng Wang <wangxiongfeng2@huawei.com> Cc: Yu Liao <liaoyu15@huawei.com> Cc: Phil Auld <pauld@redhat.com> Cc: Paul Gortmaker<paul.gortmaker@windriver.com> Cc: Alex Belits <abelits@marvell.com> Signed-off-by: Paul E. McKenney <paulmck@kernel.org> Reviewed-by: Nicolas Saenz Julienne <nsaenzju@redhat.com> Tested-by: Nicolas Saenz Julienne <nsaenzju@redhat.com>
2022-07-05arm64: dts: allwinner: a100: Update I2C controller fallbackSamuel Holland1-0/+6
The I2C controllers in the A100 SoC are newer-generation hardware which includes an offload engine. Signify that by including the allwinner,sun8i-v536-i2c fallback compatible, as V536 is the first SoC with this generation of I2C controller. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20220702052544.31443-2-samuel@sholland.org
2022-07-05ARM: dts: sun8i-r40: Add thermal trip points/cooling mapsqianfan Zhao1-0/+28
For the trip points, I used values from the BSP code. The critical trip point value is 30°C above the maximum recommended ambient temperature (85°C) for the SoC from the datasheet, so there's some headroom even at such a high ambient temperature. Signed-off-by: qianfan Zhao <qianfanguijin@163.com> Reviewed-by: Samuel Holland <samuel@sholland.org> Tested-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20220517013607.2252-4-qianfanguijin@163.com
2022-07-05ARM: dts: sun8i-r40: add opp table for cpuqianfan Zhao6-0/+64
OPP table value is get from allwinner lichee linux-3.10 kernel driver Signed-off-by: qianfan Zhao <qianfanguijin@163.com> Reviewed-by: Samuel Holland <samuel@sholland.org> Tested-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20220517013607.2252-3-qianfanguijin@163.com
2022-07-05ARM: dts: sun8i-r40: Add "cpu-supply" node for sun8i-r40 based boardqianfan Zhao4-0/+16
The CPU of sun8i-r40 is powered by PMIC, let's add "cpu-supply" node. Signed-off-by: qianfan Zhao <qianfanguijin@163.com> Reviewed-by: Samuel Holland <samuel@sholland.org> Tested-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20220517013607.2252-2-qianfanguijin@163.com
2022-07-05ACPI: CPPC: Don't require _OSC if X86_FEATURE_CPPC is supportedMario Limonciello1-0/+10
commit 72f2ecb7ece7 ("ACPI: bus: Set CPPC _OSC bits for all and when CPPC_LIB is supported") added support for claiming to support CPPC in _OSC on non-Intel platforms. This unfortunately caused a regression on a vartiety of AMD platforms in the field because a number of AMD platforms don't set the `_OSC` bit 5 or 6 to indicate CPPC or CPPC v2 support. As these AMD platforms already claim CPPC support via a dedicated MSR from `X86_FEATURE_CPPC`, use this enable this feature rather than requiring the `_OSC` on platforms with a dedicated MSR. If there is additional breakage on the shared memory designs also missing this _OSC, additional follow up changes may be needed. Fixes: 72f2ecb7ece7 ("Set CPPC _OSC bits for all and when CPPC_LIB is supported") Reported-by: Perry Yuan <perry.yuan@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2022-07-05Merge tag 'xsa-5.19-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/xen/tipLinus Torvalds1-2/+4
Pull xen security fixes from Juergen Gross: - XSA-403 (4 patches for blkfront and netfront drivers): Linux Block and Network PV device frontends don't zero memory regions before sharing them with the backend (CVE-2022-26365, CVE-2022-33740). Additionally the granularity of the grant table doesn't allow sharing less than a 4K page, leading to unrelated data residing in the same 4K page as data shared with a backend being accessible by such backend (CVE-2022-33741, CVE-2022-33742). - XSA-405 (1 patch for netfront driver, only 5.10 and newer): While adding logic to support XDP (eXpress Data Path), a code label was moved in a way allowing for SKBs having references (pointers) retained for further processing to nevertheless be freed. - XSA-406 (1 patch for Arm specific dom0 code): When mapping pages of guests on Arm, dom0 is using an rbtree to keep track of the foreign mappings. Updating of that rbtree is not always done completely with the related lock held, resulting in a small race window, which can be used by unprivileged guests via PV devices to cause inconsistencies of the rbtree. These inconsistencies can lead to Denial of Service (DoS) of dom0, e.g. by causing crashes or the inability to perform further mappings of other guests' memory pages. * tag 'xsa-5.19-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/xen/tip: xen/arm: Fix race in RB-tree based P2M accounting xen-netfront: restore __skb_queue_tail() positioning in xennet_get_responses() xen/blkfront: force data bouncing when backend is untrusted xen/netfront: force data bouncing when backend is untrusted xen/netfront: fix leaking data in shared pages xen/blkfront: fix leaking data in shared pages
2022-07-05riscv: dts: microchip: hook up the mpfs' l2cacheConor Dooley1-0/+4
The initial PolarFire SoC devicetree must have been forked off from the fu540 one prior to the addition of l2cache controller support being added there. When the controller node was added to mpfs.dtsi, it was not hooked up to the CPUs & thus sysfs reports an incorrect cache configuration. Hook it up. Fixes: 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board") Reviewed-by: Sudeep Holla <sudeep.holla@arm.com> Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-07-05arm64: mm: Remove assembly DMA cache maintenance wrappersWill Deacon3-53/+14
Remove the __dma_{flush,map,unmap}_area assembly wrappers and call the appropriate cache maintenance functions directly from the DMA mapping callbacks. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Link: https://lore.kernel.org/r/20220610151228.4562-3-will@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05Merge branch 'for-v5.20/aspeed-dts-cleanup' into for-v5.20/dts-cleanupKrzysztof Kozlowski15-123/+118
2022-07-05ARM: dts: aspeed: correct gpio-keys propertiesKrzysztof Kozlowski3-6/+0
gpio-keys children do not use unit addresses. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220616005333.18491-37-krzysztof.kozlowski@linaro.org
2022-07-05ARM: dts: aspeed: align gpio-key node names with dtschemaKrzysztof Kozlowski15-117/+118
The node names should be generic and DT schema expects certain pattern (e.g. with key/button/switch). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220616005333.18491-36-krzysztof.kozlowski@linaro.org
2022-07-05arm64: errata: Add Cortex-A510 to the repeat tlbi listJames Morse2-1/+24
Cortex-A510 is affected by an erratum where in rare circumstances the CPUs may not handle a race between a break-before-make sequence on one CPU, and another CPU accessing the same page. This could allow a store to a page that has been unmapped. Work around this by adding the affected CPUs to the list that needs TLB sequences to be done twice. Signed-off-by: James Morse <james.morse@arm.com> Link: https://lore.kernel.org/r/20220704155732.21216-1-james.morse@arm.com Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/sysreg: Convert ID_AA64ZFR0_EL1 to automatic generationMark Brown2-23/+46
Convert ID_AA64ZFR0_EL1 to automatic register generation as per DDI0487H.a, no functional changes. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-29-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/sysreg: Convert ID_AA64SMFR0_EL1 to automatic generationMark Brown2-18/+37
Convert ID_AA64SMFR0_EL1 to automatic register generation as per DDI0487H.a, no functional change. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-28-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/sysreg: Convert LORID_EL1 to automatic generationMark Brown2-2/+7
Convert LORID_EL1 to automatic register generation as per DDI0487H.a, no functional changes. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-27-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/sysreg: Convert LORC_EL1 to automatic generationMark Brown2-1/+7
Convert LORC_EL1 to automatic register generation as per DDI0487H.a, no functional changes. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-26-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/sysreg: Convert LORN_EL1 to automatic generationMark Brown2-1/+5
Convert LORN_EL1 to automatic register generation as per DDI0487H.a, no functional changes. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-25-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/sysreg: Convert LOREA_EL1 to automatic generationMark Brown2-1/+6
Convert LOREA_EL1 to automatic register generation as per DDI0487H.a, no functional changes. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-24-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/sysreg: Convert LORSA_EL1 to automatic generationMark Brown2-1/+8
Convert LORSA_EL1 to automatic register generation as per DDI0487H.a, no functional changes. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-23-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/sysreg: Convert ID_AA64ISAR2_EL1 to automatic generationMark Brown2-27/+33
Automatically generate defines for ID_AA64ISAR2_EL1, using the definitions in DDI0487H.a. No functional changes. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-22-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/sysreg: Convert ID_AA64ISAR1_EL1 to automatic generationMark Brown2-34/+83
Automatically generate defines for ID_AA64ISAR1_EL1, using the definitions in DDI0487H.a. No functional changes. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-21-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/sysreg: Convert GMID to automatic generationMark Brown2-1/+5
Automatically generate the register definitions for GMID as per DDI0487H.a, no functional change. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-20-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/sysreg: Convert DCZID_EL0 to automatic generationMark Brown2-5/+6
Convert DCZID_EL0 to automatic register generation as per DDI0487H.a, no functional change. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-19-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/sysreg: Convert CTR_EL0 to automatic generationMark Brown2-16/+21
Convert CTR_EL0 to automatic register generation as per DDI0487H.a, no functional change. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-18-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/sysreg: Add _EL1 into ID_AA64ISAR2_EL1 definition namesMark Brown8-43/+43
Normally we include the full register name in the defines for fields within registers but this has not been followed for ID registers. In preparation for automatic generation of defines add the _EL1s into the defines for ID_AA64ISAR2_EL1 to follow the convention. No functional changes. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-17-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/sysreg: Add _EL1 into ID_AA64ISAR1_EL1 definition namesMark Brown7-102/+102
Normally we include the full register name in the defines for fields within registers but this has not been followed for ID registers. In preparation for automatic generation of defines add the _EL1s into the defines for ID_AA64ISAR1_EL1 to follow the convention. No functional changes. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-16-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/sysreg: Remove defines for RPRES enumerationMark Brown1-2/+0
We have defines for the RPRES enumeration in ID_AA64ISAR2 which do not follow our normal conventions. Since these defines are never used just remove them. No functional changes. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-15-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
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