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2020-03-26arm64: dts: k3-am654-base-board: add mcu cpsw nuss pinmux and phy defsGrygorii Strashko1-0/+42
AM654 EVM base board has TI DP83867 PHY connected to external CPSW NUSS Port 1 in rgmii-rxid mode. Hence, add pinmux and Ethernet PHY configuration for TI am654 SoC Gigabit Ethernet two ports Switch subsystem (CPSW NUSS). Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Tested-by: Murali Karicheri <m-karicheri2@ti.com> Tested-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-03-26arm64: dts: ti: k3-am65-mcu: add cpsw nuss nodeGrygorii Strashko2-0/+50
Add DT node for the TI AM65x SoC Gigabit Ethernet two ports Switch subsystem (CPSW NUSS). Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Tested-by: Murali Karicheri <m-karicheri2@ti.com> Tested-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-03-26RISC-V: Move all address space definition macros to one placeAtish Patra1-37/+41
We get the following compilation error if CONFIG_SPARSEMEM_VMEMMAP is set. --------------------------------------------------------------- ./arch/riscv/include/asm/pgtable-64.h: In function ‘pud_page’: ./include/asm-generic/memory_model.h:54:29: error: ‘vmemmap’ undeclared (first use in this function); did you mean ‘mem_map’? #define __pfn_to_page(pfn) (vmemmap + (pfn)) ^~~~~~~ ./include/asm-generic/memory_model.h:82:21: note: in expansion of macro ‘__pfn_to_page’ #define pfn_to_page __pfn_to_page ^~~~~~~~~~~~~ ./arch/riscv/include/asm/pgtable-64.h:70:9: note: in expansion of macro ‘pfn_to_page’ return pfn_to_page(pud_val(pud) >> _PAGE_PFN_SHIFT); --------------------------------------------------------------- Fix the compliation errors by moving all the address space definition macros before including pgtable-64.h. Fixes: 8ad8b72721d0 (riscv: Add KASAN support) Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-03-26Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds4-12/+29
Pull KVM fixes from Paolo Bonzini: "x86 bug fixes" * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: KVM: X86: Narrow down the IPI fastpath to single target IPI KVM: LAPIC: Also cancel preemption timer when disarm LAPIC timer KVM: VMX: don't allow memory operands for inline asm that modifies SP KVM: LAPIC: Mark hrtimer for period or oneshot mode to expire in hard interrupt context KVM: SVM: Issue WBINVD after deactivating an SEV guest KVM: SVM: document KVM_MEM_ENCRYPT_OP, let userspace detect if SEV is available KVM: x86: remove bogus user-triggerable WARN_ON
2020-03-26ARM: integrator: impd1: Use GPIO_LOOKUP() helper macroGeert Uytterhoeven1-7/+4
impd1_probe() fills in the GPIO lookup table by manually populating an array of gpiod_lookup structures. Use the existing GPIO_LOOKUP() helper macro instead, to relax a dependency on the gpiod_lookup structure's member names. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20200324135653.6676-1-geert+renesas@glider.be Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-03-26RISC-V: Only select essential drivers for SOC_VIRT configAnup Patel3-16/+30
The kconfig select causes build failues for SOC_VIRT config becaus we are selecting lot of VIRTIO drivers without selecting all required dependencies. Better approach is to only select essential drivers from SOC_VIRT config option and enable required VIRTIO drivers using defconfigs. Fixes: 759bdc168181 ("RISC-V: Add kconfig option for QEMU virt machine") Signed-off-by: Anup Patel <anup.patel@wdc.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-03-26kill uaccess_try()Al Viro4-84/+0
finally Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2020-03-26x86: unsafe_put-style macro for sigmaskAl Viro1-4/+8
regularizes things a bit Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2020-03-26x86: x32_setup_rt_frame(): consolidate uaccess areasAl Viro1-12/+5
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2020-03-26x86: __setup_rt_frame(): consolidate uaccess areasAl Viro1-17/+9
reorder copy_siginfo_to_user() calls a bit Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2020-03-26x86: __setup_frame(): consolidate uaccess areasAl Viro1-17/+6
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2020-03-26x86: setup_sigcontext(): list user_access_{begin,end}() into callersAl Viro1-21/+24
Similar to ia32_setup_sigcontext() change several commits ago, make it __always_inline. In cases when there is a user_access_{begin,end}() section nearby, just move the call over there. Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2020-03-26x86: get rid of put_user_try in __setup_rt_frame() (both 32bit and 64bit)Al Viro1-42/+47
Straightforward, except for save_altstack_ex() stuck in those. Replace that thing with an analogue that would use unsafe_put_user() instead of put_user_ex() (called compat_save_altstack()) and be done with that. Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2020-03-26x86: ia32_setup_rt_frame(): consolidate uaccess areasAl Viro1-10/+3
__copy_siginfo_to_user32() call reordered a bit. The rest folds nicely. Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2020-03-26x86: ia32_setup_frame(): consolidate uaccess areasAl Viro1-27/+12
Currently we have user_access block, followed by __put_user(), deciding what the restorer will be and finally a put_user_try block. Moving the calculation of restorer first allows the rest (actual copyout work) to coalesce into a single user_access block. Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2020-03-26x86: ia32_setup_sigcontext(): lift user_access_{begin,end}() into the callersAl Viro1-16/+28
What's left is just a sequence of stores to userland addresses, with all error handling, etc. done out of line. Calling that from user_access block is safe, but rather than teaching objtool to recognize it as such we can just make it always_inline - it is small enough and has few enough callers, for the space savings not to be an issue. Rename the sucker to __unsafe_setup_sigcontext32() and provide unsafe_put_sigcontext32() with usual kind of semantics. Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2020-03-26mm: handle multiple owners of device private pages in migrate_vmaChristoph Hellwig1-0/+1
Add a new src_owner field to struct migrate_vma. If the field is set, only device private pages with page->pgmap->owner equal to that field are migrated. If the field is not set only "normal" pages are migrated. Fixes: df6ad69838fc ("mm/device-public-memory: device memory cache coherent with CPU") Link: https://lore.kernel.org/r/20200316193216.920734-3-hch@lst.de Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Ralph Campbell <rcampbell@nvidia.com> Tested-by: Bharata B Rao <bharata@linux.ibm.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
2020-03-26memremap: add an owner field to struct dev_pagemapChristoph Hellwig1-0/+2
Add a new opaque owner field to struct dev_pagemap, which will allow the hmm and migrate_vma code to identify who owns ZONE_DEVICE memory, and refuse to work on mappings not owned by the calling entity. Link: https://lore.kernel.org/r/20200316193216.920734-2-hch@lst.de Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Ralph Campbell <rcampbell@nvidia.com> Tested-by: Bharata B Rao <bharata@linux.ibm.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
2020-03-26ARM: dts: OMAP3: disable RNG on N950/N9Aaro Koskinen1-0/+5
Like on N900, we cannot access RNG directly on N950/N9. Mark it disabled in the DTS to allow kernel to boot. Fixes: 308607e5545f ("ARM: dts: Configure omap3 rng") Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-03-26riscv: Use macro definition instead of magic numberZong Li1-1/+1
The KERN_VIRT_START defines the start virtual address of kernel space. Use this macro instead of magic number. Signed-off-by: Zong Li <zong.li@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-03-26riscv: Add support to dump the kernel page tablesZong Li5-0/+340
In a similar manner to arm64, x86, powerpc, etc., it can traverse all page tables, and dump the page table layout with the memory types and permissions. Add a debugfs file at /sys/kernel/debug/kernel_page_tables to export the page table layout to userspace. Signed-off-by: Zong Li <zong.li@sifive.com> Tested-by: Alexandre Ghiti <alex@ghiti.fr> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-03-26riscv: patch code by fixmap mappingZong Li1-9/+4
On strict kernel memory permission, the ftrace have to change the permission of text for dynamic patching the intructions. Use riscv_patch_text_nosync() to patch code instead of probe_kernel_write. Signed-off-by: Zong Li <zong.li@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-03-26riscv: introduce interfaces to patch kernel codeZong Li4-1/+137
On strict kernel memory permission, we couldn't patch code without writable permission. Preserve two holes in fixmap area, so we can map the kernel code temporarily to fixmap area, then patch the instructions. We need two pages here because we support the compressed instruction, so the instruction might be align to 2 bytes. When patching the 32-bit length instruction which is 2 bytes alignment, it will across two pages. Introduce two interfaces to patch kernel code: riscv_patch_text_nosync: - patch code without synchronization, it's caller's responsibility to synchronize all CPUs if needed. riscv_patch_text: - patch code and always synchronize with stop_machine() Signed-off-by: Zong Li <zong.li@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-03-26riscv: add macro to get instruction lengthZong Li2-1/+10
Extract the calculation of instruction length for common use. Signed-off-by: Zong Li <zong.li@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-03-26riscv: add STRICT_KERNEL_RWX supportZong Li3-0/+53
The commit contains that make text section as non-writable, rodata section as read-only, and data section as non-executable. The init section should be changed to non-executable. Signed-off-by: Zong Li <zong.li@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-03-26riscv: add alignment for text, rodata and data sectionsZong Li2-1/+17
The kernel mapping will tried to optimize its mapping by using bigger size. In rv64, it tries to use PMD_SIZE, and tryies to use PGDIR_SIZE in rv32. To ensure that the start address of these sections could fit the mapping entry size, make them align to the biggest alignment. Define a macro SECTION_ALIGN because the HPAGE_SIZE or PMD_SIZE, etc., are invisible in linker script. This patch is prepared for STRICT_KERNEL_RWX support. Signed-off-by: Zong Li <zong.li@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-03-26riscv: move exception table immediately after RO_DATAZong Li1-2/+4
Move EXCEPTION_TABLE immediately after RO_DATA. Make it easy to set the attribution of the sections which should be read-only at a time. Add _data to specify the start of data section with write permission. This patch is prepared for STRICT_KERNEL_RWX support. Signed-off-by: Zong Li <zong.li@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-03-26riscv: add ARCH_SUPPORTS_DEBUG_PAGEALLOC supportZong Li2-0/+16
ARCH_SUPPORTS_DEBUG_PAGEALLOC provides a hook to map and unmap pages for debugging purposes. Implement the __kernel_map_pages functions to fill the poison pattern. Signed-off-by: Zong Li <zong.li@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-03-26riscv: add ARCH_HAS_SET_DIRECT_MAP supportZong Li3-0/+28
Add set_direct_map_*() functions for setting the direct map alias for the page to its default permissions and to an invalid state that cannot be cached in a TLB. (See d253ca0c ("x86/mm/cpa: Add set_direct_map_*() functions")) Add a similar implementation for RISC-V. Signed-off-by: Zong Li <zong.li@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-03-26riscv: add ARCH_HAS_SET_MEMORY supportZong Li4-1/+176
Add set_memory_ro/rw/x/nx architecture hooks to change the page attribution. Use own set_memory.h rather than generic set_memory.h (i.e. include/asm-generic/set_memory.h), because we want to add other function prototypes here. Signed-off-by: Zong Li <zong.li@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-03-26Merge tag 'qcom-arm64-for-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/lateArnd Bergmann26-69/+2860
Qualcomm ARM64 DT updates for v5.7 This brings initial support for the SM8250 and IPQ6018 platforms. SDM845 gets audio, PCIe and IP-accelerator support, and the interconnect providers are refactored. The Lenovo Yoga C630 has audio enabled and the DB845c has PCIe, analog audio and low-speed interfaces enabled. The SDM845 MTP has its display enabled and firmware location updated to match linux-firmware. SC7180 gains CPU topology and power properties. Interconnect providers, eMMC, SD-card, multimedia clocks, display, Bluetooth, Venus are added. Critical trip points are added as well as various fixes. For MSM8916 FastRPC support is added, ETM power management and reserved memory for Samsung A2015 are corrected. MSM8996 switches to generic QMP phy driver for its UFS support. MSM8998 temporarily disables part of Coresight to boot without clk_ignore_unused. CEQ for eMMC on QCS404 is enabled. Fixes throughout the platforms to fix binding compliance, correct compatibles for SDHCI nodes and add gpio-ranges. * tag 'qcom-arm64-for-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (56 commits) arm64: dts: qcom: sdm845-mtp: Relocate remoteproc firmware arm64: dts: sdm845: add IPA information arm64: dts: qcom: db845c: add analog audio support arm64: dts: qcom: sdm845: add pinctrl nodes for quat i2s arm64: dts: qcom: c630: Enable audio support arm64: dts: qcom: sdm845: add apr nodes arm64: dts: qcom: sdm845: add slimbus nodes arm64: dts: qcom: sc7180: Update reg names for SDHC arm64: dts: qcom: qcs404: Enable CQE support for eMMC arm64: dts: msm8916: Add fastrpc node arm64: dts: qcom: sm8250: Add sm8250 dts file arm64: dts: qcom: msm8998-mtp: Disable funnel 4 and 5 arm64: dts: qcom: db845c: add Low speed expansion i2c and spi nodes arm64: dts: qcom: apq8016-sbc: Remove wrong regulator supply arm64: dts: qcom: sc7180: Added critical trip point Thermal-zones node arm64: dts: qcom: msm8998: Fix cpu compatible arm64: dts: qcom: sc7180: Add OSM L3 interconnect provider arm64: dts: qcom: sdm845: Add OSM L3 interconnect provider arm64: dts: sc7180: Add interconnect provider DT nodes arm64: dts: qcom: msm8996: Use generic QMP driver for UFS ... Link: https://lore.kernel.org/r/20200318043823.GA470201@yoga Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-03-26Merge tag 'omap-for-v5.7/ti-sysc-drop-pdata-ti81xx-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/lateArnd Bergmann5-335/+318
Drop remaining legacy platform data for cpsw and edma With a non-critical clock fix for dm814x ethernet, we can update ti81xx for cpsw ethernet and edma to probe them with ti-sysc interconnect target module driver and device tree data. And we can drop the related remaining platform data for cpsw and edma. * tag 'omap-for-v5.7/ti-sysc-drop-pdata-ti81xx-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: OMAP2+: Drop legacy platform data for ti81xx edma ARM: dts: Configure interconnect target module for ti816x edma ARM: dts: Configure interconnect target module for dm814x tptc3 ARM: dts: Configure interconnect target module for dm814x tptc2 ARM: dts: Configure interconnect target module for dm814x tptc1 ARM: dts: Configure interconnect target module for dm814x tptc0 ARM: dts: Configure interconnect target module for dm814x tpcc ARM: OMAP2+: Drop legacy platform data for dm814x cpsw ARM: dts: Configure interconnect target module for dm814x cpsw clk: ti: Fix dm814x clkctrl for ethernet Link: https://lore.kernel.org/r/pull-1584575307-189595@atomide.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-03-26Merge tag 'omap-for-v5.7/ti-sysc-drop-pdata-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/lateArnd Bergmann23-1672/+876
Drop legacy platform data for omaps for v5.7 This series of changes continues dropping legacy platform data for omaps by updating devices to probe with ti-sysc interconnect target module driver: - Update omap4, omap5, am437x, and dra7 display subsystem (DSS) to probe with device tree data only - Update am335x, am437x and dra7 to probe EDMA to probe with device tree data only - Drop legacy platform data for am335x and am437x PRUSS as the current code just keeps the devices in reset - Drop legacy platform data for omap4 DSP and IPU as the current code just keeps the devices in reset - Configure am437x and dra7 PRU-ICSS to probe with device tree data For the dropped omap4 DSP and IPU platform data, there will be patches coming later on to configure the accelerators using the omap remoteproc bindings so hopefully folks can actually use these devices eventually. * tag 'omap-for-v5.7/ti-sysc-drop-pdata-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (56 commits) ARM: OMAP2+: Drop legacy platform data for dra7 edma ARM: OMAP2+: Drop legacy platform data for am3 and am4 edma ARM: dts: Configure interconnect target module for dra7 tptc1 ARM: dts: Configure interconnect target module for dra7 tptc0 ARM: dts: Configure interconnect target module for dra7 tpcc ARM: dts: Configure interconnect target module for am4 tptc2 ARM: dts: Configure interconnect target module for am4 tptc1 ARM: dts: Configure interconnect target module for am4 tptc0 ARM: dts: Configure interconnect target module for am4 tpcc ARM: dts: Configure interconnect target module for am3 tptc2 ARM: dts: Configure interconnect target module for am3 tptc1 ARM: dts: Configure interconnect target module for am3 tptc0 ARM: dts: Configure interconnect target module for am3 tpcc ARM: dts: dra7: Add PRU-ICSS interconnect target-module nodes ARM: dts: AM4372: Add the PRU-ICSS interconnect target-module node ARM: dts: AM33xx-l4: Update PRUSS interconnect target-module node ARM: OMAP2+: Drop legacy platform data for am437x DSS ARM: OMAP2+: Drop legacy platform data for dra7 DSS ARM: OMAP2+: Drop legacy platform data for omap5 DSS ARM: OMAP2+: Drop legacy platform data for omap4 dss ... Link: https://lore.kernel.org/r/pull-1583858385-416921@atomide.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-03-27powerpc/smp: Use IS_ENABLED() to avoid #ifdefMichael Ellerman1-3/+2
We can avoid the #ifdef by using IS_ENABLED() in the existing condition check. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Reviewed-by: Srikar Dronamraju <srikar@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20200313112020.28235-2-mpe@ellerman.id.au
2020-03-27powerpc/smp: Drop superfluous NULL checkMichael Ellerman1-5/+2
We don't need the NULL check of np, the result is the same because the OF helpers cope with NULL, of_node_to_nid(NULL) == NUMA_NO_NODE (-1). Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Reviewed-by: Srikar Dronamraju <srikar@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20200313112020.28235-1-mpe@ellerman.id.au
2020-03-27powerpc/xmon: Add ASCII dump to d1,d2,d4,d8 commands.Douglas Miller1-1/+6
The reason debuggers add an ASCII dump to other types of memory dumps is to give the user visual reference points in the case that ASCII strings are adjacent to other structures or element. For example, when examining the task_struct structure one can look for the comm[] string and use it to locate other important elements. ASCII strings do not have endianess, they exist in memory in the same order regardless of CPU endianess. ASCII strings are, by definition, human readable and so should be presented in a human readable format. For these reasons, the supplemental ASCII dump does not re-order the strings from memory to match the endianess of the corresponding 16, 32, or 64 bit words. That would make the ASCII dump much less useful. Signed-off-by: Douglas Miller <dougmill@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/1488205694-13337-1-git-send-email-dougmill@linux.vnet.ibm.com
2020-03-27powerpc/xive: Add a debugfs file to dump internal XIVE stateCédric Le Goater4-0/+129
As does XMON, the debugfs file /sys/kernel/debug/powerpc/xive exposes the XIVE internal state of the machine CPUs and interrupts. Available on the PowerNV and sPAPR platforms. Signed-off-by: Cédric Le Goater <clg@kaod.org> [mpe: Make the debugfs file 0400] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20200306150143.5551-5-clg@kaod.org
2020-03-27powerpc/xmon: Add source flags to output of XIVE interruptsCédric Le Goater1-1/+4
Some firmwares or hypervisors can advertise different source characteristics. Track their value under XMON. What we are mostly interested in is the StoreEOI flag. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20200306150143.5551-4-clg@kaod.org
2020-03-27powerpc/xive: Fix xmon support on the PowerNV platformCédric Le Goater1-0/+4
The PowerNV platform has multiple IRQ chips and the xmon command dumping the state of the XIVE interrupt should only operate on the XIVE IRQ chip. Fixes: 5896163f7f91 ("powerpc/xmon: Improve output of XIVE interrupts") Cc: stable@vger.kernel.org # v5.4+ Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20200306150143.5551-3-clg@kaod.org
2020-03-27powerpc/xive: Use XIVE_BAD_IRQ instead of zero to catch non configured IPIsCédric Le Goater4-13/+14
When a CPU is brought up, an IPI number is allocated and recorded under the XIVE CPU structure. Invalid IPI numbers are tracked with interrupt number 0x0. On the PowerNV platform, the interrupt number space starts at 0x10 and this works fine. However, on the sPAPR platform, it is possible to allocate the interrupt number 0x0 and this raises an issue when CPU 0 is unplugged. The XIVE spapr driver tracks allocated interrupt numbers in a bitmask and it is not correctly updated when interrupt number 0x0 is freed. It stays allocated and it is then impossible to reallocate. Fix by using the XIVE_BAD_IRQ value instead of zero on both platforms. Reported-by: David Gibson <david@gibson.dropbear.id.au> Fixes: eac1e731b59e ("powerpc/xive: guest exploitation of the XIVE interrupt controller") Cc: stable@vger.kernel.org # v4.14+ Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Tested-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20200306150143.5551-2-clg@kaod.org
2020-03-27powerpc: Prefer __section and __printf from compiler_attributes.hNick Desaulniers2-2/+2
Reported-by: Sedat Dilek <sedat.dilek@gmail.com> Suggested-by: Josh Poimboeuf <jpoimboe@redhat.com> Signed-off-by: Nick Desaulniers <ndesaulniers@google.com> [mpe: Drop changes to a/p/boot which doesn't use linux headers] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20190812215052.71840-10-ndesaulniers@google.com
2020-03-26arm64: dts: Revert "specify console via command line"Arnd Bergmann1-1/+1
I accidentally merged this after requesting a different solution, reverting now. Link: https://patchwork.kernel.org/patch/11431397/ Fixes: 2cedfe1247c0 ("arm64: dts: specify console via command line") Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-03-26x86/insn: Add Control-flow Enforcement (CET) instructions to the opcode mapYu-cheng Yu1-6/+11
Add the following CET instructions to the opcode map: INCSSP: Increment Shadow Stack pointer (SSP). RDSSP: Read SSP into a GPR. SAVEPREVSSP: Use "previous ssp" token at top of current Shadow Stack (SHSTK) to create a "restore token" on the previous (outgoing) SHSTK. RSTORSSP: Restore from a "restore token" to SSP. WRSS: Write to kernel-mode SHSTK (kernel-mode instruction). WRUSS: Write to user-mode SHSTK (kernel-mode instruction). SETSSBSY: Verify the "supervisor token" pointed by MSR_IA32_PL0_SSP, set the token busy, and set then Shadow Stack pointer(SSP) to the value of MSR_IA32_PL0_SSP. CLRSSBSY: Verify the "supervisor token" and clear its busy bit. ENDBR64/ENDBR32: Mark a valid 64/32 bit control transfer endpoint. Detailed information of CET instructions can be found in Intel Software Developer's Manual. Signed-off-by: Yu-cheng Yu <yu-cheng.yu@intel.com> Signed-off-by: Borislav Petkov <bp@suse.de> Reviewed-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Tony Luck <tony.luck@intel.com> Acked-by: Masami Hiramatsu <mhiramat@kernel.org> Link: https://lkml.kernel.org/r/20200204171425.28073-2-yu-cheng.yu@intel.com
2020-03-26Merge tag 'kvm-s390-next-5.7-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kvms390/linux into HEADPaolo Bonzini5-17/+20
KVM: s390: cleanups for 5.7 - mark sie control block as 512 byte aligned - use fallthrough;
2020-03-26KVM: Fix out of range accesses to memslotsSean Christopherson1-0/+3
Reset the LRU slot if it becomes invalid when deleting a memslot to fix an out-of-bounds/use-after-free access when searching through memslots. Explicitly check for there being no used slots in search_memslots(), and in the caller of s390's approximation variant. Fixes: 36947254e5f9 ("KVM: Dynamically size memslot array based on number of used slots") Reported-by: Qian Cai <cai@lca.pw> Cc: Peter Xu <peterx@redhat.com> Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com> Message-Id: <20200320205546.2396-2-sean.j.christopherson@intel.com> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-03-26KVM: X86: Micro-optimize IPI fastpath delayWanpeng Li3-3/+8
This patch optimizes the virtual IPI fastpath emulation sequence: write ICR2 send virtual IPI read ICR2 write ICR2 send virtual IPI ==> write ICR write ICR We can observe ~0.67% performance improvement for IPI microbenchmark (https://lore.kernel.org/kvm/20171219085010.4081-1-ynorov@caviumnetworks.com/) on Skylake server. Signed-off-by: Wanpeng Li <wanpengli@tencent.com> Message-Id: <1585189202-1708-4-git-send-email-wanpengli@tencent.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-03-26KVM: X86: Delay read msr data iff writes ICR MSRWanpeng Li1-1/+2
Delay read msr data until we identify guest accesses ICR MSR to avoid to penalize all other MSR writes. Signed-off-by: Wanpeng Li <wanpengli@tencent.com> Message-Id: <1585189202-1708-2-git-send-email-wanpengli@tencent.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-03-26arm: dts: calxeda: Group port-phys and sgpio-gpio itemsAndre Przywara1-4/+5
For proper bindings checks we need to properly group the port-phys and sgpio-gpio items, so that they match the expected number of items. Link: https://lore.kernel.org/r/20200228135106.220620-5-andre.przywara@arm.com Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-03-26arm: dts: calxeda: Fix interrupt groupingAndre Przywara3-5/+5
Currently multiple interrupts for some devices are written as one array instead of using the DT grouping notation (<0 42 4>, <0 23 4>). This ends up in the same binary representation in the .dtb, but is semantically not equivalent. The yaml schema checks will stumble over this, so lets fix that first. I refrained from using the symbolic names for GIC_SPI/GIC_PPI and IRQ_TYPE_LEVEL_HIGH, mostly because it increases the delta between the original DTS files and the mainline versions, so it's just additional churn. Link: https://lore.kernel.org/r/20200228135106.220620-4-andre.przywara@arm.com Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-03-26arm: dts: calxeda: Provide UART clockAndre Przywara1-2/+2
The PL011 UART binding requires two clocks to be named in a node. Add the second clock, which is the bus gate, that just gets enabled. Since this is a fixed clock anyway, it doesn't make any difference. Link: https://lore.kernel.org/r/20200228135106.220620-3-andre.przywara@arm.com Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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