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2019-12-10x86/mm/pat: Rename <asm/pat.h> => <asm/memtype.h>Ingo Molnar17-19/+19
pat.h is a file whose main purpose is to provide the memtype_*() APIs. PAT is the low level hardware mechanism - but the high level abstraction is memtype. So name the header <memtype.h> as well - this goes hand in hand with memtype.c and memtype_interval.c. Signed-off-by: Ingo Molnar <mingo@kernel.org>
2019-12-10x86/mm/pat: Standardize on memtype_*() prefix for APIsIngo Molnar5-42/+42
Half of our memtype APIs are memtype_ prefixed, the other half are _memtype suffixed: reserve_memtype() free_memtype() kernel_map_sync_memtype() io_reserve_memtype() io_free_memtype() memtype_check_insert() memtype_erase() memtype_lookup() memtype_copy_nth_element() Use prefixes consistently, like most other modern kernel APIs: reserve_memtype() => memtype_reserve() free_memtype() => memtype_free() kernel_map_sync_memtype() => memtype_kernel_map_sync() io_reserve_memtype() => memtype_reserve_io() io_free_memtype() => memtype_free_io() memtype_check_insert() => memtype_check_insert() memtype_erase() => memtype_erase() memtype_lookup() => memtype_lookup() memtype_copy_nth_element() => memtype_copy_nth_element() Signed-off-by: Ingo Molnar <mingo@kernel.org>
2019-12-10x86/mm/pat: Move the memtype related files to arch/x86/mm/pat/Ingo Molnar7-12/+17
- pat.c offers, dominantly, the memtype APIs - so rename it to memtype.c. - pageattr.c is offering, primarily, the set_memory*() page attribute APIs, which is offered via the <asm/set_memory.h> header: name the .c file along the same pattern. I.e. perform these renames, and move them all next to each other in arch/x86/mm/pat/: pat.c => memtype.c pat_internal.h => memtype.h pat_interval.c => memtype_interval.c pageattr.c => set_memory.c pageattr-test.c => cpa-test.c Signed-off-by: Ingo Molnar <mingo@kernel.org>
2019-12-10x86/mm/pat: Clean up PAT initialization flagsIngo Molnar1-12/+14
Right now we have these variables that impact the PAT initialization sequence: pat_disabled boot_cpu_done pat_initialized init_cm_done Some have a pat_ prefix, some not, and the naming is random, which makes their purpose rather opaque. Name them consistently and according to their role: pat_disabled pat_bp_initialized pat_bp_enabled pat_cm_initialized Also rename pat_bsp_init() => pat_bp_init(), to use the canonical abbreviation. Also add a warning for double calls of init_cache_modes(), the call chains leading to this are complex and I couldn't convince myself that we never call this function twice - so utilize the flag for a debug check. No change in functionality intended. Signed-off-by: Ingo Molnar <mingo@kernel.org>
2019-12-10x86/mm/pat: Harmonize 'struct memtype *' local variable and function parameter useIngo Molnar3-73/+75
We have quite a zoo of 'struct memtype' variable nomenclature: new entry print_entry data match out memtype Beyond the randomness, some of these are outright confusing, especially when used in larger functions. Standardize them: entry entry_new entry_old entry_print entry_match entry_out Signed-off-by: Ingo Molnar <mingo@kernel.org>
2019-12-10x86/mm/pat: Simplify the free_memtype() control flowIngo Molnar1-8/+3
Simplify/streamline the quirky handling of the pat_pagerange_is_ram() logic, and get rid of the 'err' local variable. Signed-off-by: Ingo Molnar <mingo@kernel.org>
2019-12-10x86/mm/pat: Create fixed width output in /sys/kernel/debug/x86/pat_memtype_list, similar to the E820 debug printoutsIngo Molnar1-3/+3
Before: write-back @ 0xbdfa9000-0xbdfaa000 write-back @ 0xbdfaa000-0xbdfab000 write-back @ 0xbdfab000-0xbdfac000 uncached-minus @ 0xc0000000-0xd0000000 uncached-minus @ 0xd0900000-0xd0920000 uncached-minus @ 0xd0920000-0xd0940000 uncached-minus @ 0xd0940000-0xd0960000 uncached-minus @ 0xd0960000-0xd0980000 uncached-minus @ 0xd0980000-0xd0981000 uncached-minus @ 0xd0990000-0xd0991000 uncached-minus @ 0xd09a0000-0xd09a1000 uncached-minus @ 0xd09b0000-0xd09b1000 uncached-minus @ 0xd0d00000-0xd0d01000 uncached-minus @ 0xd0d10000-0xd0d11000 uncached-minus @ 0xd0d20000-0xd0d21000 uncached-minus @ 0xd0d40000-0xd0d41000 uncached-minus @ 0xfed00000-0xfed01000 uncached-minus @ 0xfed1f000-0xfed20000 uncached-minus @ 0xfed40000-0xfed41000 After: PAT: [mem 0x00000000bdf8e000-0x00000000bdfa8000] write-back PAT: [mem 0x00000000bdfa9000-0x00000000bdfaa000] write-back PAT: [mem 0x00000000bdfaa000-0x00000000bdfab000] write-back PAT: [mem 0x00000000bdfab000-0x00000000bdfac000] write-back PAT: [mem 0x00000000c0000000-0x00000000d0000000] uncached-minus PAT: [mem 0x00000000d0900000-0x00000000d0920000] uncached-minus PAT: [mem 0x00000000d0920000-0x00000000d0940000] uncached-minus PAT: [mem 0x00000000d0940000-0x00000000d0960000] uncached-minus PAT: [mem 0x00000000d0960000-0x00000000d0980000] uncached-minus PAT: [mem 0x00000000d0980000-0x00000000d0981000] uncached-minus PAT: [mem 0x00000000d0990000-0x00000000d0991000] uncached-minus PAT: [mem 0x00000000d09a0000-0x00000000d09a1000] uncached-minus PAT: [mem 0x00000000d09b0000-0x00000000d09b1000] uncached-minus PAT: [mem 0x00000000fed1f000-0x00000000fed20000] uncached-minus PAT: [mem 0x00000000fed40000-0x00000000fed41000] uncached-minus The advantage is that it's easier to parse at a glance - and the tree is ordered by start address, which is now reflected in putting the start address in the first column. This is also now similar to how we print e820 entries: BIOS-e820: [mem 0x00000000bafda000-0x00000000bb3d3fff] usable BIOS-e820: [mem 0x00000000bb3d4000-0x00000000bdd2efff] reserved BIOS-e820: [mem 0x00000000bdd2f000-0x00000000bddccfff] ACPI NVS BIOS-e820: [mem 0x00000000bddcd000-0x00000000bdea0fff] ACPI data BIOS-e820: [mem 0x00000000bdea1000-0x00000000bdf2efff] ACPI NVS Since this is a debugfs file not used by tools there's no known ABI dependencies. Signed-off-by: Ingo Molnar <mingo@kernel.org>
2019-12-10x86/mm/pat: Disambiguate PAT-disabled boot messagesIngo Molnar2-7/+15
Right now we have these four types of PAT-disabled boot messages: x86/PAT: PAT support disabled. x86/PAT: PAT MSR is 0, disabled. x86/PAT: MTRRs disabled, skipping PAT initialization too. x86/PAT: PAT not supported by CPU. The first message is ambiguous in that it doesn't signal that PAT is off due to a boot option. The second message doesn't really make it clear that this is the MSR value during early bootup and it's the firmware environment that disabled PAT support. The fourth message doesn't really make it clear that we disable PAT support because CONFIG_MTRR is off in the kernel. Clarify, harmonize and fix the spelling in these user-visible messages: x86/PAT: PAT support disabled via boot option. x86/PAT: PAT support disabled by the firmware. x86/PAT: PAT support disabled because CONFIG_MTRR is disabled in the kernel. x86/PAT: PAT not supported by the CPU. Also add a fifth message, in case PAT support is disabled at build time: x86/PAT: PAT support disabled because CONFIG_X86_PAT is disabled in the kernel. Previously we'd just silently return from pat_init() without giving any indication that PAT support is off. Finally, clarify/extend some of the comments related to PAT initialization. Signed-off-by: Ingo Molnar <mingo@kernel.org>
2019-12-10x86/mm/pat: Update the comments in pat.c and pat_interval.c and refresh the code a bitIngo Molnar2-35/+72
Tidy up the code: - add comments explaining the PAT code, the role of the functions and the logic - fix various typos and grammar while at it - simplify the file-scope memtype_interval_*() namespace to interval_*() - simplify stylistic complications such as unnecessary linebreaks or convoluted control flow - use the simpler '#ifdef CONFIG_*' pattern instead of '#if defined(CONFIG_*)' pattern - remove the non-idiomatic newline between late_initcall() and its function definition Signed-off-by: Ingo Molnar <mingo@kernel.org>
2019-12-10Merge tag 'v5.5-rc1' into core/kprobes, to resolve conflictsIngo Molnar1392-18331/+47583
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2019-12-10x86/setup: Enhance the commentsIngo Molnar1-16/+25
Update various comments, fix outright mistakes and meaningless descriptions. Also harmonize the style across the file, both in form and in language. Cc: linux-kernel@vger.kernel.org Cc: Borislav Petkov <bp@alien8.de> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@kernel.org>
2019-12-10x86/setup: Clean up the header portion of setup.cIngo Molnar1-100/+22
In 20 years we accumulated 89 #include lines in setup.c, but we only need 30 of them (!) ... Get rid of the excessive ones, and while at it, sort the remaining ones alphabetically. Also get rid of the incomplete changelogs at the header of the file, and explain better what this file does. Cc: linux-kernel@vger.kernel.org Cc: Borislav Petkov <bp@alien8.de> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@kernel.org>
2019-12-09arm64: dts: meson-gxbb: add support for Videostrong KII ProMohammad Rasim2-0/+79
This patch adds support for the Videostrong KII Pro tv box which is based on the gxbb-p201 reference design Device specifications: - SOC: Amlogic S905 - RAM: 2GB DDR3 - Storage: 16GB - Connectivity: - 10/100M Ethernet (IC Plus IP101GR) - 802.11 b/g/n/ac Wi-Fi (Ampak AP6335 BT/WIFI combo) - Bluetooth 4.0 (Ampak AP6335 BT/WIFI combo) - Video out: HDMI 2.0 up to 4K @ 60Hz, and 3.5mm AV (composite video) jack - Audio out: HDMI, AV (stereo audio) and optical S/PDIF - Tuner: AVL6862 DVB-C/T/T2 + DVB-S/S2 demod and Rafael Micro R848 tuner - Ports: - x1 micro SD card slot up to 32GB - 4x USB 2.0 host ports - Misc: - Power button and LED, IR receiver Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Mohammad Rasim <mohammad.rasim96@gmail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-12-10ARM: debug-ll: select DEBUG_AT91_RM9200_DBGU for sam9x60Claudiu Beznea1-3/+3
Select DEBUG_AT91_RM9200_DBGU for SAM9X60 SoC. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1575035505-6310-8-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2019-12-10ARM: at91: pm: move SAM9X60's PM under its own SoC config flagClaudiu Beznea4-19/+36
Move SAM9X60's PM part under SoC config flag. This allows the building of SAM9X60 platform withouth depending on CONFIG_SOC_AT91SAM9 flag, allowing us to select only necessary config flags for SAM9X60. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1575035505-6310-4-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2019-12-10ARM: at91: Kconfig: add config flag for SAM9X60 SoCClaudiu Beznea1-2/+19
Add config flag for SAM9X60 SoC. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/1575035505-6310-3-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2019-12-10ARM: at91: Kconfig: add sam9x60 pll config flagClaudiu Beznea1-0/+3
Add SAM9X60's pll config flag. It was first used in commit a436c2a447e5 ("clk: at91: add sam9x60 PLL driver"). Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1575035505-6310-2-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2019-12-10ARM: dts: at91: sama5d2: set the sdmmc gclk frequencyLudovic Desroches1-0/+4
Set the frequency of the generated clock used by sdmmc devices in order to not rely on the configuration done by previous components. Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com> Link: https://lore.kernel.org/r/20191128074522.69706-3-ludovic.desroches@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2019-12-09arm64: dts: meson: a1: add pinctrl controller supportQianggui Song1-0/+19
add peripheral pinctrl controller to a1 SoC Signed-off-by: Qianggui Song <qianggui.song@amlogic.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-12-09arm64: dts: meson: add reset controller for Meson-A1 SoCXingyu Chen1-0/+6
Add the reset controller device of Meson-A1 SoC family Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-12-09arm64: dts: meson-sm1-sei610: add gpio bluetooth interruptGuillaume La Roque1-0/+2
add gpio irq to support interrupt trigger mode. Signed-off-by: Guillaume La Roque <glaroque@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-12-09ARM: dts: meson8: fix the size of the PMU registersMartin Blumenstingl1-1/+1
The PMU registers are at least 0x18 bytes wide. Meson8b already uses a size of 0x18. The structure of the PMU registers on Meson8 and Meson8b is similar but not identical. Meson8 and Meson8b have the following registers in common (starting at AOBUS + 0xe0): #define AO_RTI_PWR_A9_CNTL0 0xe0 (0x38 << 2) #define AO_RTI_PWR_A9_CNTL1 0xe4 (0x39 << 2) #define AO_RTI_GEN_PWR_SLEEP0 0xe8 (0x3a << 2) #define AO_RTI_GEN_PWR_ISO0 0x4c (0x3b << 2) Meson8b additionally has these three registers: #define AO_RTI_GEN_PWR_ACK0 0xf0 (0x3c << 2) #define AO_RTI_PWR_A9_MEM_PD0 0xf4 (0x3d << 2) #define AO_RTI_PWR_A9_MEM_PD1 0xf8 (0x3e << 2) Thus we can assume that the register size of the PMU IP blocks is identical on both SoCs (and Meson8 just contains some reserved registers in that area) because the CEC registers start right after the PMU (AO_RTI_*) registers at AOBUS + 0x100 (0x40 << 2). The upcoming power domain driver will need to read and write the AO_RTI_GEN_PWR_SLEEP0 and AO_RTI_GEN_PWR_ISO0 registers, so the updated size is needed for that driver to work. Fixes: 4a5a27116b447d ("ARM: dts: meson8: add support for booting the secondary CPU cores") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-12-09arm64: dts: meson-sm1-sei610: gpio-keys: switch to IRQsKevin Hilman1-2/+24
Switch the GPIO buttons/switches to use interrupts instead of polling. While at it, add the mic mute switch and the power button. Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-12-09soc: fsl: move cpm.h from powerpc/include/asm to include/soc/fslRasmus Villemoes1-171/+1
Some drivers, e.g. ucc_uart, need definitions from cpm.h. In order to allow building those drivers for non-ppc based SOCs, move the header to include/soc/fsl. For now, leave a trivial wrapper at the old location so drivers can be updated one by one. Reviewed-by: Timur Tabi <timur@kernel.org> Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk> Signed-off-by: Li Yang <leoyang.li@nxp.com>
2019-12-09powerpc/83xx: remove mpc83xx_ipic_and_qe_init_IRQRasmus Villemoes7-17/+5
This is now exactly the same as mpc83xx_ipic_init_IRQ, so just use that directly. Acked-by: Scott Wood <oss@buserror.net> Reviewed-by: Timur Tabi <timur@kernel.org> Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk> Signed-off-by: Li Yang <leoyang.li@nxp.com>
2019-12-09soc: fsl: qe: move calls of qe_ic_init out of arch/powerpc/Rasmus Villemoes11-92/+0
Having to call qe_ic_init() from platform-specific code makes it awkward to allow building the QE drivers for ARM. It's also a needless duplication of code, and slightly error-prone: Instead of the caller needing to know the details of whether the QUICC Engine High and QUICC Engine Low are actually the same interrupt (see e.g. the machine_is() in mpc85xx_mds_qeic_init), just let the init function choose the appropriate handlers after it has parsed the DT and figured it out. If the two interrupts are distinct, use separate handlers, otherwise use the handler which first checks the CHIVEC register (for the high priority interrupts), then the CIVEC. All existing callers pass 0 for flags, so continue to do that from the new single caller. Later cleanups will remove that argument from qe_ic_init and simplify the body, as well as make qe_ic_init into a proper init function for an IRQCHIP_DECLARE, eliminating the need to manually look up the fsl,qe-ic node. Reviewed-by: Timur Tabi <timur@kernel.org> Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk> Signed-off-by: Li Yang <leoyang.li@nxp.com>
2019-12-09soc: fsl: qe: use qe_ic_cascade_{low, high}_mpic also on 83xxRasmus Villemoes1-1/+1
The *_ipic and *_mpic handlers are almost identical - the only difference is that the latter end with an unconditional chip->irq_eoi() call. Since IPIC does not have ->irq_eoi, we can reduce some code duplication by calling irq_eoi conditionally. This is similar to what is already done in mpc8xxx_gpio_irq_cascade(). This leaves the functions slightly misnamed, but that will be fixed in a subsequent patch. Reviewed-by: Timur Tabi <timur@kernel.org> Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk> Signed-off-by: Li Yang <leoyang.li@nxp.com>
2019-12-09ARM: dts: at91: sama5d27_som1_ek: add i2c filters propertiesEugen Hristev1-0/+6
Add properties for i2c filters for i2c0 and i2c1 on sama5d27_som1_ek. Noise is affecting communication on i2c for example when connecting i2c camera sensors. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Link: https://lore.kernel.org/r/1575531818-21332-1-git-send-email-eugen.hristev@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2019-12-09ARM: dts: at91: sama5d27_wlsom1: add SAMA5D27 wlsom1 and wlsom1-ekEugen Hristev3-0/+575
This is the addition of a new Evaluation Kit the SAMA5D27-WLSOM1-EK. It's based on the Microchip WireLess SoM which contains the SAMA5D27 LPDDR2 2Gbits SiP. [nicolas.ferre@microchip.com]: initial implementation Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> [eugen.hristev@microchip.com]: ported to new kernel version, [eugen.hristev@microchip.com]: addition of peripherals (adc, pmic, qspi, uart) Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Link: https://lore.kernel.org/r/1573543139-8533-4-git-send-email-eugen.hristev@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2019-12-09ARM: dts: at91: sama5d2: mark secumod as a GPIO controllerAndrei Stefanescu1-1/+4
The Security Module exposes the PIOBU pins which an be used as regular GPIOs. The PIOBU pins are special because they do not lose their voltage during suspend-to-mem. This patch marks the secumod as a GPIO controller. Signed-off-by: Andrei Stefanescu <andrei.stefanescu@microchip.com> [razvan.stefanescu@microchip.com Updated title] Signed-off-by: Razvan Stefanescu <razvan.stefanescu@microchip.com> Link: https://lore.kernel.org/r/1573543139-8533-2-git-send-email-eugen.hristev@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2019-12-09ARM: dts: at91: sama5d2: disable pwm0 by defaultRazvan Stefanescu1-0/+1
It will be enabled as needed by each board. Signed-off-by: Razvan Stefanescu <razvan.stefanescu@microchip.com> Link: https://lore.kernel.org/r/1573543139-8533-1-git-send-email-eugen.hristev@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2019-12-09ARC: mm: drop stale define of __ARCH_USE_5LEVEL_HACKMike Rapoport1-1/+0
Commit 6aae3425aa9c ("ARC: mm: remove __ARCH_USE_5LEVEL_HACK") make ARC paging code 5-level compliant but left behind a stale define of __ARCH_USE_5LEVEL_HACK in arch/arc/include/asm/hugepage.h. Remove it. Signed-off-by: Mike Rapoport <rppt@linux.ibm.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2019-12-09arc: eznps: fix allmodconfig kconfig warningRandy Dunlap1-1/+1
Fix kconfig warning for arch/arc/plat-eznps/Kconfig allmodconfig: WARNING: unmet direct dependencies detected for CLKSRC_NPS Depends on [n]: GENERIC_CLOCKEVENTS [=y] && !PHYS_ADDR_T_64BIT [=y] Selected by [y]: - ARC_PLAT_EZNPS [=y] Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Cc: Vineet Gupta <vgupta@synopsys.com> Cc: Ofer Levi <oferle@mellanox.com> Cc: linux-snps-arc@lists.infradead.org Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2019-12-09treewide: Use sizeof_field() macroPankaj Bharadiya5-18/+18
Replace all the occurrences of FIELD_SIZEOF() with sizeof_field() except at places where these are defined. Later patches will remove the unused definition of FIELD_SIZEOF(). This patch is generated using following script: EXCLUDE_FILES="include/linux/stddef.h|include/linux/kernel.h" git grep -l -e "\bFIELD_SIZEOF\b" | while read file; do if [[ "$file" =~ $EXCLUDE_FILES ]]; then continue fi sed -i -e 's/\bFIELD_SIZEOF\b/sizeof_field/g' $file; done Signed-off-by: Pankaj Bharadiya <pankaj.laxminarayan.bharadiya@intel.com> Link: https://lore.kernel.org/r/20190924105839.110713-3-pankaj.laxminarayan.bharadiya@intel.com Co-developed-by: Kees Cook <keescook@chromium.org> Signed-off-by: Kees Cook <keescook@chromium.org> Acked-by: David Miller <davem@davemloft.net> # for net
2019-12-09MIPS: OCTEON: Replace SIZEOF_FIELD() macroPankaj Bharadiya1-8/+1
Switch to the standard sizeof_field() macro to find the size of a member of a struct and remove the custom SIZEOF_FIELD() macro. Signed-off-by: Pankaj Bharadiya <pankaj.laxminarayan.bharadiya@intel.com> Link: https://lore.kernel.org/r/20190924105839.110713-4-pankaj.laxminarayan.bharadiya@intel.com Co-developed-by: Kees Cook <keescook@chromium.org> Signed-off-by: Kees Cook <keescook@chromium.org>
2019-12-09ARM: dts: Cygnus: Fix MDIO node address/size cellsFlorian Fainelli1-2/+2
The MDIO node on Cygnus had an reversed #address-cells and #size-cells properties, correct those. Fixes: 40c26d3af60a ("ARM: dts: Cygnus: Add the ethernet switch and ethernet PHY") Reported-by: Simon Horman <simon.horman@netronome.com> Reviewed-by: Ray Jui <ray.jui@broadcom.com> Reviewed-by: Simon Horman <simon.horman@netronome.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2019-12-09ARM: dts: bcm2711: fix soc's node dma-rangesNicolas Saenz Julienne1-1/+1
Raspberry Pi's firmware has a feature to select how much memory to reserve for its GPU called 'gpu_mem'. The possible values go from 16MB to 944MB, with a default of 64MB. This memory resides in the topmost part of the lower 1GB memory area and grows bigger expanding towards the begging of memory. It turns out that with low 'gpu_mem' values (16MB and 32MB) the size of the memory available to the system in the lower 1GB area can outgrow the interconnect's dma-range as its size was selected based on the maximum system memory available given the default gpu_mem configuration. This makes that memory slice unavailable for DMA. And may cause nasty kernel warnings if CMA happens to include it. Change soc's dma-ranges to really reflect it's HW limitation, which is being able to only DMA to the lower 1GB area. Fixes: 7dbe8c62ceeb ("ARM: dts: Add minimal Raspberry Pi 4 support") Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Reviewed-by: Phil Elwell <phil@raspberrypi.org> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2019-12-09ARM: exynos_defconfig: Restore debugfs supportMarek Szyprowski1-0/+1
Commit 9f532d26c75c ("ARM: exynos_defconfig: Trim and reorganize with savedefconfig") removed explicit enable line for CONFIG_DEBUG_FS, because that feature has been selected by other enabled options: CONFIG_TRACING, which in turn had been selected by CONFIG_PERF_EVENTS and CONFIG_PROVE_LOCKING. In meantime, commit 0e4a459f56c3 ("tracing: Remove unnecessary DEBUG_FS dependency") removed the dependency between CONFIG_DEBUG_FS and CONFIG_TRACING, so CONFIG_DEBUG_FS is no longer enabled in default builds. Enable it again explicitly, as debugfs support is essential for various automated testing tools. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2019-12-09ARM: dts: BCM5301X: Fix MDIO node address/size cellsFlorian Fainelli1-2/+2
The MDIO node on BCM5301X had an reversed #address-cells and #size-cells properties, correct those, silencing checker warnings: .../linux/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dt.yaml: mdio@18003000: #address-cells:0:0: 1 was expected Reported-by: Simon Horman <simon.horman@netronome.com> Fixes: 23f1eca6d59b ("ARM: dts: BCM5301X: Specify MDIO bus in the DT") Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2019-12-09Merge tag 'socfpga_dts_updates_for_v5.5_part2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/dtOlof Johansson5-3/+437
SoCFPGA DTS updates for v5.5, part 2 - Add NAND support for both Agilex and Stratix10 boards - Agilex - Add FPGA manager and Service Layer support - Add EDAC support - Add System manager - Add System manager property to ethernet nodes * tag 'socfpga_dts_updates_for_v5.5_part2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: arm64: dts: agilex: Add SysMgr to Ethernet nodes arm64: dts: agilex: Add SysMgr compatible arm64: dts: agilex: Add EDAC Device Tree arm64: dts: add NAND board files for Stratix10 and Agilex arm64: dts: agilex: add NAND IP to base dts Link: https://lore.kernel.org/r/20191118220559.16623-1-dinguyen@kernel.org Signed-off-by: Olof Johansson <olof@lixom.net>
2019-12-09Merge tag 'samsung-dt-5.5-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dtOlof Johansson11-14/+107
Samsung DTS ARM changes for v5.5, part 2 1. Cleanup by adjusting DTS to bindings, 2. Add touch-sensitive buttons to Midas (Galaxy S III family phones), 3. Add GPU/Mali to Exynos542x and Odroid XU3/XU4 family. * tag 'samsung-dt-5.5-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: ARM: dts: exynos: Add Mali/GPU node on Exynos5420 and enable it on Odroid XU3/4 ARM: dts: exynos: Add support for the touch-sensitive buttons on Midas family ARM: dts: exynos: Rename children of SysRAM node to "sram" Link: https://lore.kernel.org/r/20191119142026.7190-1-krzk@kernel.org Signed-off-by: Olof Johansson <olof@lixom.net>
2019-12-09arm64: dts: uDPU: SFP cages support 3W modulesRussell King1-0/+2
The SFP cages are designed to support up to 3W modules, such as G.hn, G.fast and MoCA modules. Although there is no way for such modules to declare to software that they consume 3W, we document in DT that this is the designed power level for these cages. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-12-09arm64: dts: uDPU: remove i2c-fast-modeRussell King1-0/+2
The I2C bus violates the timing specifications when run in fast mode on the uDPU, so switch to 100kHz mode. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-12-09arm64: dts: uDPU: fix broken ethernetRussell King1-0/+4
The uDPU uses both ethernet controllers, which ties up COMPHY 0 for eth1 and COMPHY 1 for eth0, with no USB3 comphy. The addition of COMPHY support made the kernel override the setup by the boot loader breaking this platform by assuming that COMPHY 0 was always used for USB3. Delete the USB3 COMPHY definition at platform level, and add phy specifications for the ethernet channels. Fixes: bd3d25b07342 ("arm64: dts: marvell: armada-37xx: link USB hosts with their PHYs") Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-12-09ARM: dts: stm32: remove useless clock-names from RTC node on stm32f746Benjamin Gaignard1-1/+0
On stm32f7 family RTC node doesn't need clock-names property. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-12-09ARM: dts: stm32: remove useless clock-names from RTC node on stm32f429Benjamin Gaignard1-1/+0
On stm32f4 family RTC node doesn't need clock-names property. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-12-09ARM: dts: stm32: Enable MAC TX clock gating during TX low-power mode on stm32mp15Christophe Roullier1-0/+1
When there is no activity on ethernet phy link, the ETH_GTX_CLK is cut. Signed-off-by: Christophe Roullier <christophe.roullier@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-12-09ARM: dts: stm32: adjust slew rate for Ethernet on stm32mp15Christophe Roullier1-2/+7
ETH_MDIO slew-rate should be set to "0" instead of "2". Signed-off-by: Christophe Roullier <christophe.roullier@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-12-09ARM: dts: ux500: Add devicetree for HREF520Linus Walleij3-1/+39
This reference design is very similar to the others just that it has a different display mounted on the user interface board, and some GPIOs where shuffled around. As this is the first board that uses DB8520 we create the DB8520-specific DTSI file here. Cc: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20191126124738.77690-3-linus.walleij@linaro.org
2019-12-09ARM: dts: ux500: Split TVK DTSI files in twoLinus Walleij5-71/+141
The TVK1281618 was made in R1, R2 and R3 variants. The most commonly used variants are R2 and R3 so split out these to their own files. The R3 version has a totally different display than R1 and R2 and a different set of sensors. Cc: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20191126124738.77690-2-linus.walleij@linaro.org
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